UNIVERSIDAD NACIONAL MAYOR DE SAN MARCOS

Universidad del Perú, DECANA DE AMÉRICA

FACULTAD DE INGENIERÍA ELECTRÓNICA Y ELÉCTRICA

PROYECTO FINAL

 Curso: Circuitos Digitales I

 Docente: DR. RUBEN ALARCON M.

 Alumno: Fabrizio David Apaestegui Centurion

 Código: 16190093

 Turno: Miércoles 6-8 pm

 Ciclo académico: 2018-I

A) INFORME 1:

Pregunta 5:

Tabla de Verdad:
A B C Z
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

Funcion Booleana:
𝒁 = ̅̅̅̅̅̅̅̅̅̅̅̅
(𝑨𝑩 + 𝑪)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pregunta5 is

port(
A: in std_logic;
B: in std_logic;
C: in std_logic;
F: out std_logic);

end pregunta5;

architecture FuncLogic of pregunta5 is

signal aux1 : std_logic;

begin

aux1 <= B and A;

F <= not (aux1 or C);

end FuncLogic;
Pregunta 6:

Tabla de Verdad:

A B C D E Z
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 1
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 1 0 1
0 0 1 1 1 1
0 1 0 0 0 1
0 1 0 0 1 1
 0 1 0 1 0 1
0 1 0 1 1 1
0 1 1 0 0 1
0 1 1 0 1 1
0 1 1 1 0 1
0 1 1 1 1 1
1 0 0 0 0 1
1 0 0 0 1 1
1 0 0 1 0 1
1 0 0 1 1 1
1 0 1 0 0 1
1 0 1 0 1 1
1 0 1 1 0 1
1 0 1 1 1 1
1 1 0 0 0 1
1 1 0 0 1 1
1 1 0 1 0 1
1 1 0 1 1 1
1 1 1 0 0 1
1 1 1 0 1 1
1 1 1 1 0 1
1 1 1 1 1 1

Funcion Booleana:

̅)
𝒁 = (𝑨𝑩) + (𝑪 + 𝑫) + (𝑬

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe1_pregunta6 is

port(
A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
E: in std_logic;
F: out std_logic);

end informe1_pregunta6;

architecture FuncLogic of informe1_pregunta6 is

signal aux1 : std_logic;

signal aux2 : std_logic;

begin

aux1 <= A or B;
aux2 <= C and D;
F<= aux1 or aux2 (not E);

end FuncLogic;
B) INFORME 2

Pregunta A.3(3.13):

Complete la tabla de verdad para el circuito de la figura 3-15(b) y

determinar los valores para las 32 posibles combinaciones de entrada.

A B C D E ̅̅̅̅̅̅̅̅̅̅̅̅
𝑿 = ((𝑨 + 𝑩)𝑪 + 𝑫)𝑬
0 0 0 0 0 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 1 1
 0 1 0 0 0 0
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 1 0
0 1 1 1 0 0
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 1 1
1 0 0 1 0 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 1 0
1 0 1 1 0 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 1 1
1 1 0 1 0 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 1 0
1 1 1 1 0 0
1 1 1 1 1 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe2_pregunta3_13 is

port(
A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
E: in std_logic;
X: out std_logic);

end informe2_pregunta3_13;

architecture FuncLogic of informe2_pregunta3_13 is

signal aux1 : std_logic;

signal aux2 : std_logic;
signal aux3 : std_logic;

begin

aux1 <= A or B;
aux2 <= aux1 and C;
aux3 <= D or (not aux2);
X<= aux3 and E;

end FuncLogic;
Pregunta A.3(3.15):

Complete la tabla de verdad para el circuito de la figura 3-16 y

determinar los valores para las 32 posibles combinaciones de entrada.

A B C D ̅ ∗ 𝑩 ∗ 𝑪) ∗ (𝑨
(𝑨 ̅̅̅̅̅̅̅̅
+ 𝑫)
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
 0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe2_pregunta3_15 is

port(
A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
X: out std_logic);

end informe2_pregunta3_15;

architecture FuncLogic of informe2_pregunta3_15 is

signal aux1 : std_logic;

signal aux2 : std_logic;

begin

aux1 <= (not A) and B and C;

aux2 <= A or D;
X<= (not aux2) and aux1;

end FuncLogic;
C) INFORME 3

Pregunta 4-27:

A B C D E-O N-S
0 0 0 0 1 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 1 0

𝑭=𝑨 ̅𝑫
̅ 𝑩𝑪 ̅ + 𝑨𝑩 ̅𝑫
̅𝑪 ̅ + 𝑨𝑩𝑪 ̅𝑫̅ + 𝑨𝑩𝑪̅ 𝑫 + 𝑨𝑩𝑪𝑫̅
𝑭=𝑪̅𝑫
̅ (𝑨
̅ 𝑩 + 𝑨𝑩̅ ) + 𝑨𝑩𝑪 ̅ (𝑫 + 𝑫
̅ ) + 𝑨𝑩𝑪𝑫
̅
𝑭 = 𝑨𝑩(𝑪̅+𝑫 ̅) + 𝑪̅𝑫̅ (𝑨⨁𝑩)
̅̅̅̅ + (𝑪
𝑭 = 𝑨𝑩𝑪𝑫 ̅̅̅̅̅̅̅̅
+ 𝑫)(𝑨⨁𝑩)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe3_pregunta4_27 is

port(
A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
NS: out std_logic;
EO: out std_logic);

end informe3_pregunta4_27;

architecture FuncLogic of informe3_pregunta4_27 is

signal aux1 : std_logic;

signal aux2 : std_logic;
signal aux3 : std_logic;
signal aux4 : std_logic;
signal aux5 : std_logic;

begin

aux1 <= A xor B;

aux2 <= C nand D;
aux3 <= A and B and aux2;
aux4 <= C nor D;
aux5 <= aux1 and aux4;

NS <= aux5 or aux3;

EO <= aux5 nor aux3;

end FuncLogic;
Pregunta 4-6:

A B C D X
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
𝑋 = 𝐴𝐵𝐶̅ 𝐷
̅ + 𝐴𝐵𝐶̅ 𝐷 + 𝐴𝐵𝐶𝐷
̅ + 𝐴𝐵𝐶𝐷 + 𝐴̅𝐵𝐶𝐷

𝑋 = 𝐴𝐵𝐶̅ + 𝐴𝐵𝐶 + 𝐴̅𝐵𝐶𝐷

𝑋 = 𝐴𝐵 + 𝐴̅𝐵𝐶𝐷
𝑋 = 𝐵(𝐴 + 𝐶𝐷)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe3_pregunta4_6 is
port(
A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
X: out std_logic);

end informe3_pregunta4_6;

architecture FuncLogic of informe3_pregunta4_6 is

signal aux1 : std_logic;

signal aux2 : std_logic;

begin

aux1 <= C and D;

aux2 <= aux1 or A;

X <= aux1 and aux2;

end FuncLogic;

D) INFORME 4

PREGUNTA F:
Convertir de BCD(2-4-2-1) conocido como AIKEN a
BCD natural. Usar un FA de 4 bits
AIKEN BCD NATURAL
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 1
0 1 0 0 0 1 0 0
1 0 1 1 0 1 0 1
1 1 0 0 0 1 1 0
1 1 0 1 0 1 1 1
1 1 1 0 1 0 0 0
1 1 1 1 1 0 0 1

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
port(
Cin,x,y: in std_logic;
s,Cout: out std_logic);
end fulladder;

architecture FuncLogic of fulladder is

begin

s <= x xor y xor Cin;

Cout <= (x and y) or (Cin and x) or (Cin and y);

end FuncLogic;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe4_preguntaf is

port(
Cin: in std_logic;
X: in std_logic_vector (3 downto 0);
Y: in std_logic_vector (3 downto 0);
S: out std_logic_vector (3 downto 0);
Cout: out std_logic);
end informe4_preguntaf;

architecture FuncLogic of informe4_preguntaf is

signal c1,c2,c3: std_logic;

component fulladder
port(
Cin,x,y: in std_logic;
s,Cout: out std_logic);
end component;

begin

stage0: fulladder port map (Cin=>Cin,x=>X(0),y=>Y(0),s=>S(0),Cout=>c1);

stage1: fulladder port map (Cin=>c1,x=>X(1),y=>X(3),s=>S(1),Cout=>c2);
stage2: fulladder port map (Cin=>c2,x=>X(2),y=>Y(2),s=>S(2),Cout=>c3);
stage3: fulladder port map (Cin=>c3,x=>X(3),y=>X(3),s=>S(3),Cout=>Cout);

end FuncLogic;
 PREGUNTA C:
Diseñar un circuito que convierta un numero
binario natural (0-19) en el correspondiente
numero en código BCD natural (2 digitos: unidades
y decenas). Usar un bloque Full Adder de 4 bits
como base del diseño y puertas simples de ser
necesario

BINARIO BCD NATURAL

0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 0 0 0 0 1 0
0 0 0 1 1 0 0 0 0 0 0 1 1
0 0 1 0 0 0 0 0 0 0 1 0 0
0 0 1 0 1 0 0 0 0 0 1 0 1
0 0 1 1 0 0 0 0 0 0 1 1 0
0 0 1 1 1 0 0 0 0 0 1 1 1
0 1 0 0 0 0 0 0 0 1 0 0 0
0 1 0 0 1 0 0 0 0 1 0 0 1
0 1 0 1 0 0 0 0 1 0 0 0 0
0 1 0 1 1 0 0 0 1 0 0 0 1
0 1 1 0 0 0 0 0 1 0 0 1 0
0 1 1 0 1 0 0 0 1 0 0 1 1
0 1 1 1 0 0 0 0 1 0 1 0 0
0 1 1 1 1 0 0 0 1 0 1 0 1
1 0 0 0 0 0 0 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 1 1 1
1 0 0 1 0 0 0 0 1 1 0 0 0
1 0 0 1 1 0 0 0 1 1 0 0 1

El numero binario y el BCD son iguales hasta el numero 9, por lo cual se necesita un circuito que
sume 6 (00110) al numero cuando este sea 9 o mayor para obtener su representación en BCD.
El circuito va a comprobar si los 4 primeros bits suman mas de 9.
 𝐹 = 𝐵𝐷 + 𝐵𝐶

La salida de esta función deberá entrar a una compuerta OR que tendrá de entradas A y la
función. Esto hará que cuando el numero sea mayor que 9, se le sume 6 al numero binario
introducido.

También el acarreo de salida deberá entrar a una compuerta OR junto con A ,ya que al evaluar
los primeros cuatro bits, no se esta tomando en cuenta que cuando solo A esta prendido el
numero seria 16 pero al tener las 4 entradas del full adder como 0, lo que pasaría es que el circuito
solo sumaria 6 a 0.

Entonces el circuito quedaría de la siguiente manera

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
port(
Cin,x,y: in std_logic;
s,Cout: out std_logic);
end fulladder;

architecture FuncLogic of fulladder is

begin
s <= x xor y xor Cin;
Cout <= (x and y) or (Cin and x) or (Cin and y);

end FuncLogic;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe4_preguntac is

port(
Cin: in std_logic;
X: in std_logic_vector (4 downto 0);
Y: in std_logic_vector (3 downto 0);
S: out std_logic_vector (4 downto 0));

end informe4_preguntac;

architecture FuncLogic of informe4_preguntac is

signal c1,c2,c3,c4: std_logic;

signal aux1: std_logic;
component fulladder
port(
Cin,x,y: in std_logic;
s,Cout: out std_logic);
end component;

begin

aux1 <= X(4) or (X(3) and X(2)) or (X(3) and X(1));

stage0: fulladder port map (Cin=>Cin,x=>X(0),y=>Y(0),s=>S(0),Cout=>c1);
stage1: fulladder port map (Cin=>c1,x=>X(1),y=>aux1,s=>S(1),Cout=>c2);
stage2: fulladder port map (Cin=>c2,x=>X(2),y=>aux1,s=>S(2),Cout=>c3);
stage3: fulladder port map (Cin=>c3,x=>X(3),y=>Y(3),s=>S(3),Cout=>c4);

S(4) <= c4 or X(4);

end FuncLogic;
E) INFORME 5

PREGUNTA A:
 S3 S2 S1 S0 F
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7
1 0 0 0 D8
1 0 0 1 D9
1 0 1 0 D10
1 0 1 1 D11
1 1 0 0 D12
1 1 0 1 D13
1 1 1 0 D14
1 1 1 1 D15

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe5_preguntaa is

port(
D0: in std_logic;
D1: in std_logic;
D2: in std_logic;
D3: in std_logic;
D4: in std_logic;
D5: in std_logic;
D6: in std_logic;
D7: in std_logic;
D8: in std_logic;
D9: in std_logic;
D10: in std_logic;
D11: in std_logic;
D12: in std_logic;
D13: in std_logic;
D14: in std_logic;
D15: in std_logic;

S: in std_logic_vector (3 downto 0);

X: out std_logic);

end informe5_preguntaa;

architecture FuncLogic of informe5_preguntaa is

begin
process (D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15,S) begin
case S is
when "0000" => X <= D0;
when "0001" => X <= D1;
when "0010" => X <= D2;
when "0011" => X <= D3;
when "0100" => X <= D4;
when "0101" => X <= D5;
when "0110" => X <= D6;
when "0111" => X <= D7;
when "1000" => X <= D8;
when "1001" => X <= D9;
when "1010" => X <= D10;
when "1011" => X <= D11;
when "1100" => X <= D12;
when "1101" => X <= D13;
when "1110" => X <= D14;
when "1111" => X <= D15;
when others => X <= '-';
end case;
end process;

end FuncLogic;
PREGUNTA G:

Analizar el circuito dado y hallar la expresión

booleana de la salida F en función de las entradas
(x,y,z1,z0)

Tabla de funcionamiento del multiplexor 4 a 1:

S1 S0 Z
0 0 I0
0 1 I1
1 0 I2
1 1 I3
 𝐹 = 𝑆̅0 𝑆̅1 𝐼0 + 𝑆̅0 𝑆1 𝐼1 + 𝑆0 𝑆̅1 𝐼2 + 𝑆0 𝑆1 𝐼3

𝑆0 𝑆1 X Y F
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

𝐹 = 𝑆̅0 𝑋̅𝑌 + 𝑆0 𝑆̅1 𝑌 + 𝑋𝑌̅ + 𝑆1 𝑌̅

 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe5_preguntag is

port(
S0: in std_logic;
S1: in std_logic;
X: in std_logic;
Y: in std_logic;
F: out std_logic);

end informe5_preguntag;

architecture FuncLogic of informe5_preguntag is

begin

F<= ((not S0) and (not X) and Y) or (S0 and (not S1) and Y) or (X and (not Y)) or (S1 and (not Y));

end FuncLogic;

F) INFORME 6

Pregunta 4:

Sin reloj:
 M N B(n) B(n+1)
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

̅𝑁
𝐵 (𝑛 + 1) = 𝑀 ̅+𝑀
̅𝐵
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity electrobomba_sinreloj is

port(
M: in std_logic;
N: in std_logic;
B: out std_logic);

end electrobomba_sinreloj;

architecture FuncLogic of electrobomba_sinreloj is

signal aux1 : std_logic;

signal aux2 : std_logic;
signal aux3 : std_logic;

begin

aux1 <= (not M) and (not N);

aux2 <= (not M) and aux3;
aux3 <= aux1 or aux2;
B <= aux3;

end FuncLogic;
Con reloj:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity electrobomba_conreloj is

port(
M: in std_logic;
N: in std_logic;
CLK: in std_logic;
B: out std_logic);

end electrobomba_conreloj;

architecture FuncLogic of electrobomba_conreloj is

signal aux1 : std_logic;

signal aux2 : std_logic;
signal aux3 : std_logic;
signal aux4 : std_logic;

begin
aux1 <= (not M) and (not N);
aux2 <= (not M) and aux4;
aux3 <= aux1 or aux2;

process (CLK)
begin
if (CLK='1')and(CLK'EVENT) then

aux4 <= aux3;

B <= aux3;

end if;
end process;
end FuncLogic;

PREGUNTA 2:
 Data Clock Q nQ
0 0 Q nQ
0 1 0 1
1 0 Q nQ
1 1 1 0

La salida del Latch D va a tomar el valor de D cuando el Clock cambia de 0 a 1. Mientras que
cuando el Clock cambia de 1 a 0, la salida va a mantener su estado previo.

Ecuacion de Estado:

𝑄 = ̅̅̅̅̅̅̅̅̅̅̅
̅ . 𝐶 + 𝑄̅
𝐷
𝑄 = ̅̅̅̅̅
𝐷̅. 𝐶. 𝑄

𝑛𝑄 = ̅̅̅̅̅̅̅̅̅̅
𝐷𝐶 + 𝑄
𝑛𝑄 = ̅̅̅̅̅
𝐷. 𝐶 . 𝑄̅
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity informe6_pregunta2 is

port(
D: in std_logic;
CLK: in std_logic;
Q: out std_logic;
nQ: out std_logic);

end informe6_pregunta2;

architecture FuncLogic of informe6_pregunta2 is

signal aux1 : std_logic;

signal aux2 : std_logic;
signal aux3 : std_logic;
signal aux4 : std_logic;
begin
aux1 <= (not D) and CLK;
aux2 <= D and CLK;
aux3 <= not(aux1 or aux4);
aux4 <= not(aux2 or aux3);
Q <= aux3;
nQ <= aux4;

end FuncLogic;