INTEGRATED ELECTRONICS 2016-EE-105

LAB # 01
TASK# 01: To implement AND-gate using gate level modeling in Verilog HDL

CIRCUIT DIAGRAM: TRUTH TABLE:

Table 1 AND-gate truth table

Figure 1 AND-gate

CODING:
// design module module SAROSH; a=1'b0; b=1'b1; #20
module andgate(out,a,b); reg a,b; a=1'b1; b=1'b0; #20
input a,b; wire out; a=1'b1; b=1'b1; #20
output out; andgate g1(out,a,b); $finish;
and a1(out,a,b); initial end
endmodule begin endmodule
//stimulus module a=1'b0; b=1'b0; #20

TIMING DIAGRAM:

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TASK# 02: To implement NAND-gate using gate level modeling in Verilog HDL

CIRCUIT DIAGRAM: TRUTH TABLE:

CODING:
// design module //stimulus module a=1'b0; b=1'b0; #20
module nandgate(out,a,b); module SAROSH; a=1'b0; b=1'b1; #20
input a,b; reg a,b; a=1'b1; b=1'b0; #20
output out; wire out; a=1'b1; b=1'b1; #20
nand a1(out,a,b); nandgate g1(out,a,b); $finish;
endmodule initial end
begin endmodule

TIMING DIAGRAM:

TASK# 03: To implement OR-gate using gate level modeling in Verilog HDL

CIRCUIT DIAGRAM: TRUTH TABLE:

Table 2 OR-gate truth table

A+B

CODING:

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// design module //stimulus module a=1'b0; b=1'b0; #20

module orgate(out,a,b); module SAROSH; a=1'b0; b=1'b1; #20
input a,b; reg a,b; a=1'b1; b=1'b0; #20
output out; wire out; a=1'b1; b=1'b1; #20
or a1(out,a,b); orgate g1(out,a,b); $finish;
endmodule initial end
begin endmodule

TIMING DIAGRAM:

TASK# 04: To implement NOR -gate using gate level modeling in Verilog HDL

CIRCUIT DIAGRAM:

A+B
TRUTH TABLE:
Table 3 NOR-gate truth table

CODING:
//design module
module norgate(out,a,b);
input a,b;
output out;
nor a1(out,a,b);
endmodule
//stimulus module
module SAROSH;
reg a,b;
wire out;

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norgate a2(out,a,b);
initial
begin
a=1'b0; b=1'b0;
#20
a=1'b0; b=1'b1;
#20
a=1'b1; b=1'b0;
#20
a=1'b1; b=1'b1;
#20
$finish;
end
endmodule

Timing Diagram:

TASK# 05: To implement XOR-gate using gate level modeling in Verilog HDL

CIRCUIT DIAGRAM:

TRUTH TABLE:

module xorgate(out,a,b);
input a,b;
output out;
wire x,y,c,d;

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not n1(c,b);
not n2(d,a);
and a1(x,a,c);
and a2(y,b,d);
or o1(out,x,y);
endmodule

//stimulus

module SAROSH;
reg a,b;
wire out;

xorgate b1(out,a,b);
initial
begin

a=1'b0;b=1'b0;#20
a=1'b0;b=1'b1;#20
a=1'b1;b=1'b0;#20
a=1'b1;b=1'b1;#20

$finish;
end
endmodule

TIMING DIAGRAM:

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TASK# 06: To implement Not-gate using gate level modeling in Verilog HDL

Ciruit diagram :

Coding
//Design Module
module gate(c,a);
input a;
output c;
not a1(c,a);
endmodule

//Stimulus Module
module SAROSH;
reg a;
wire c;
gate g1(c,a);
initial
begin
a=1'b0;
#20
a=1'b1;
#20
$finish;
end
endmodule

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