ENC O U NT E R P O WE R S YS T E M
DATASHEET
Encounter Power
System
Encounter Power System offers designers
a complete and accurate view of gate
and grid power, IR drop, electromigration,
and statistical and thermal analysis – for
all technology nodes – delivering the
utmost in productivity, precision, and
performance for the most complex
advanced node designs.
Encounter Power System and its native
production-proven VoltageStorm®
signoff engines have been in use for
more than a decade with thousands of
successful tapeouts for both analysis
and in-design optimization. It is used
across the implementation flow, spanning
floorplanning, power planning, design
optimization, and signoff, to provide
consistent, converging results at every
step of the flow. Encounter Power System
helps front-end logic designers looking
for high-quality early rail analysis and
ease of use, as well as back-end physical
designers looking for comprehensive
signoff analysis and silicon correlation.
As geometries shrink and clock frequencies increase, timing-clean
designs could fail on silicon due to lowered operating voltage
caused by static and instantaneous IR drop, increased leakage,
and temperature variation. Cadence® Encounter® Power System
enables designers to analyze and debug power and IR drop across
multimillion-gate designs with significant gains in productivity. It
provides a complete signoff solution in combination with Encounter
Timing System and Encounter Library Characterizer, delivering
comprehensive timing, signal integrity, thermal, power, power grid,
and statistical characterization and analysis with a common user
interface, constraints, commands, debug, and reporting.
Complete power integrity and vector-based dynamic analysis,
analysis Encounter Power System helps designers
identify areas of high dynamic current
Encounter Power System provides a
caused by simultaneously switching
comprehensive static and dynamic power,
logic. Encounter Power System identifies
IR drop, and electromigration analysis
the amount of de-coupling capacitance
solution with advanced debugging
needed to fix such dynamic IR drop
capabilities, easy Power Grid View
violations. It also allows de-coupling
(PGV) library generation, and input
capacitance and power-switch
data validation. Designed for optimal
optimization, rush-current and turn-on-
usability, accuracy, and runtime, it enables
time analysis for shut-off blocks, clock
designers to rapidly check that the power
jitter and skew analysis, and package/die
rails can supply the amount of power
co-design.
needed by the design. Designers can
use it for accurate power estimation, An essential part of any deep sub-
optimal I/O placement, study of package micron design, Encounter Power System
impact on IR drop, power stripe size, and is available in L and XL configurations.
pitch correction, and via and connection An Encounter Power System Advanced
problem identification. Analysis Option is also available.
The Encounter Power System power
estimation engine enables Verilog®-based
early gate-level power estimation, as well
as DEF-based signoff power calculation.
It leverages the Encounter Timing System
signoff timing engine for accurate slew
and arrival windows needed during power
estimation. With hierarchical vectorless
Benefits
• Delivers consistent, integrated power
and IR drop analysis across the
implementation flow, from
floorplanning through optimization and
signoff

– Early rail analysis (ERA) at floor/power

planning stages allows correct-by-
construct power-grid design

– Consistent Encounter-integrated
and standalone use model improves
productivity

– Integration with Encounter platform

technologies allows access to physical
database and on-the-fly engineering
change orders (ECOs)

• Provides a unified signoff analysis

solution

– Integration with Encounter Timing

System enables analysis of IR drop-
induced delay variability across data
and clock networks, such as clock
jitter and skew analysis
– Provides consistent engines, interface,
and commands across the flow
• Performs comprehensive full-chip and
package IR drop analysis
– Power grid views of analog, mixed-
signal, custom-digital, or full digital
blocks allow true full-chip IR drop
analysis
– Supports chip/package co-design
through package and die model
exchange with Allegro® Package
Designer
• Boosts productivity and shaves weeks
off tapeout schedules
– Multi-CPU support ensures high
performance
– Pipelined methodology ensures high
capacity and throughput
– Performs incremental and what-if
analysis and exploration
– Supports the Common Power Format
(CPF)
– Provides a GUI-driven and interactive
Tcl command interface
Figure 1: Power and IR drop cross probing and waveforms
• Allows easy debugging
– Global Power Debug speeds up root
cause analysis
– Integrated waveform and layout viewers
enable fast power and IR debugging
• Offers advanced node analysis capabilities
– Performs manufacturing-aware
extraction for advanced nodes
– Performs thermal and statistical
leakage power analysis
– Supports Blech Length for accurate
electromigration analysis
• Supported by major foundries, ASIC
and IP vendors, and integrated device
manufactures
Features
Comprehensive power and
power grid verification
• Flexible, consistent power engine used
for power estimation across the
implementation flow
• Gate-level power estimation using
Verilog as input for early power
estimation, with full RTL and gate-level
VCD and SAIF support
• Accurate post-placement and routing
power estimation for power grid
optimization and signoff
Easy library generation
• Detailed Power Grid View (PGV))
generation using easily available Spice
sub-circuits
• Detailed PGV generation using industry-
standard LVS rule decks
• On-the-fly device and coupling
capacitance characterization using the
embedded Spectre® SIMI
• Pass/Fail report capabilities to analyze
contents of PGVs with guidance on
causes of failure
• Layout-aware Power System Viewer
(PSViewer) for graphically viewing and
debugging PGVs
• Automatic spawning of library generation
jobs for macros and memories
Seamless data import and
input data sanity checking
• Flexible design imports using Encounter
database, OpenAccess, or third-party
designs

www.ca de nce .com EN C O U N TER PO WER SYSTEM 2


Figure 2: Global Power Debug
• Embedded design sanity checks such as
completeness of LEF library data, timing
library data, physical and logical netlist
annotation, and SPEF annotation
• Fast structural power grid verification to
identify missing vias and disconnected
power pins
• Access to the Encounter Timing System
signoff timing engine, enabling fast
timing database queries for slews and
arrival times
Powerful GUI
• Command console with full Tcl support,
command completion, history, and
context highlighting
• Script editor to evaluate scripts with
ability to crosslink and expand Tcl
procedures
Easy debugging
• Global Power Debug for analyzing
power consumption at different levels
of hierarchy, cell type, power net,
power domain, clock domain, etc., with
pie charts and histograms
www.ca de nce .com
• Integrated full-featured waveform
viewer enables study of dynamic power
and IR drop waveforms, with composite
waveform creation capabilities across
design hierarchies and clock domains
• Embedded Encounter layout viewer
with ability to cross-probe power and IR
drop information
• Instance-based effective resistance plots
with automatic least-resistive path
highlighting
Figure 3: Effective resistance plots with automatic least-resistive path highlighting
• HTML reporting for easy result
navigation
• Fast what-if analysis enabling quick
experimentation
Early rail analysis (ERA)
Floorplanning and power planning
designers can use Encounter Power
System engines to rapidly prototype their
I/O placement, macro placement, and
power grid structure early in the design.
Consistency of the engines between early
rail analysis and Encounter Power System
removes correlation risks, improves
productivity, and speeds design closure.
Vector profiling
Encounter Power System includes
multiple vector profiling options to help
designers study VCD profiles textually and
graphically. Activity-based vector profiling
enables fast identification of high activity
regions of VCDs. A fast vector power-
profiling option calculates switching
power of the design over time. The
accurate vector power-profiling option
allows full power estimation of a VCD,
with activity propagation capabilities for
non-annotated nodes.
Effective Resistance Plots
highlighting weak connections
Automatic least resistive
path highlighting
EN C O U N TER PO WER SYSTEM 3

Figure 4: HTML reports
Automatic de-coupling
capacitance optimization
Encounter Power System can calculate
and recommend the amount of additional
de-coupling capacitance necessary to
limit the dynamic IR drop to user-specified
limits. This recommended additional
de-coupling capacitance can then drive an
automated optimization flow throughout
the Encounter Platform, where filler
cells are swapped with de-coupling
capacitance cells. For low-power designs,
this flow can be used to remove extra
de-coupling capacitance cells in the
design, improving leakage and yield.
Package/die co-design
Encounter Power System integration with
Allegro Package Designer enables easy
hand-off of package and die models.
Encounter Power System enables chip
designers to create an abstract parasitics
and dynamic current profile of the die for
package designers. It also takes in 2 or
n-port package models to enable accurate
IR drop analysis, taking into account the
package effects.
Analysis of IR drop impact on
timing and signal integrity
Encounter Power System calculates
instance operating voltages based on
the switching windows associated with
each instance. It then provides this
www.ca de nce .com
information to Encounter Timing System,
which calculates the impact of IR drop
on delay- and signal integrity-generated
noise. Encounter Power System can also
generate dynamic IR drop and ground-
bounce waveforms for critical paths,
allowing Encounter Timing System to
accurately trace and analyze such paths.
Analysis of IR drop-induced
delay variability on clock
and data networks
The delay variation introduced by
instantaneous rail voltage changes on the
clock network can cause set-up and hold
violations in a design. The different delays
seen on the clock and data networks
could introduce further set-up and hold
violations. By monitoring the effective
operating voltage of the clock and data
network elements, Encounter Power
System enables Encounter Timing System
to more accurately analyze clock jitter,
skew, and delay variability across clock
and data networks. This analysis allows
Encounter Timing System to identify
problematic clock network elements
and to create and run a complete jitter-
sensitized Spice trace.
Power-switch optimization
Today, many low-power designs include
switched blocks through the use of power
switches. These blocks are only turned
on when needed, saving leakage power
while the blocks are not in use. Encounter
Power System analyzes power-on and
power-off scenarios of these blocks,
creating engineering change orders
(ECOs) to optimize power switch size and
location. This ensures the block’s rush
current during power-up will not impact
the neighboring logic, and that the static
and dynamic IR drop within the block is
within expected budgets.
Comprehensive IR drop
analysis solution
Encounter Power System uses Power
Grid Views (PGVs) as the building blocks
for hierarchical power grid analysis. The
VoltageStorm family of products, such
as VoltageStorm Transistor and Virtuoso®
Analog VoltageStorm Option, analyze IR
drop across custom-digital and analog/
mixed-signal blocks accordingly. After this
analysis, both products create PGVs for
use in Encounter Power System during
full-chip static and dynamic runs. This
allows study of IR drop across the entire
chip, taking into account digital, custom
block, and analog domains’ power grid
interactions.
Thermal and statistical
analysis
Designed for advanced nodes, Encounter
Power System allows designers advanced
analysis features such as thermal and
statistical leakage power analysis (SLPA).
Worst-case leakage has a very low
probability of occurring across the entire
chip, and leakage distributions have long
tails that make worst-corner analysis very
pessimistic. Using SLPA, designers can
capture a more realistic picture of their
design’s leakage power distribution. SLPA
accounts for global, within-the-die, and
random variation. It enables designers to
spend less time fixing leakage problems
that are very unlikely to occur. Thermal
analysis allows users to study the impact
of power on temperature variations across
the die, which in turn impact leakage and
power consumption, and hence IR drop. It
also helps designers ensure proper cooling
of the die to avoid thermal runaways.
EN C O U N TER PO WER SYSTEM 4
Standard Interface
Support Timing
DEF Verilog LEF
• Mandatory design data Libraries

– Timing libraries
SPEF GDS Spice
– Verilog Subckts
– SDC

– LEF SDC Power

Pads
– DEF
Encounter
– SPEF Power
VCD Package
– Spice Subckts and GDS for design
System
components

– Power pad location Power IRdrop/EM

Reports Reports
– Extraction tech file for QRC or
process file Power IRdrop/EM
Plots Plots
• Optional design data Power IRdrop
Waveforms Waveforms
– Common Power Format (CPF) file

– Package model

– VCD = Required Input = Optional Input

= Input for Library Generation = Output
Specifications
Figure 5: Encounter Power System inputs and outputs
Platforms
• Sun Solaris 8 or 9 (32-bit, 64-bit) CADENCE SERVICES AND • Cadence-certified instructors teach more
SUPPORT than 80 courses and bring their real-
• HP-UX 11.0 (32-bit, 64-bit)
world experience into the classroom
• Cadence application engineers can
• Opteron Linux RHEL 3.0 (64-bit)
answer your technical questions by • More than 25 Internet Learning Series
• Red Hat Linux RHEL 2.1 (32-bit) telephone, email, or internet — they (iLS) online courses allow you the
can also provide technical assistance flexibility of training at your own
• IBM AIX 5.1 (32-bit, 64-bit) computer via the Internet
and custom training

• SourceLink® online customer support

gives you answers to your technical
questions — 24 hours a day, 7 days a
week — including the latest in quarterly
software rollups, product release
information, technical documentation,
software updates, and more

For more information,

contact Cadence sales at:
1.800.746.6223
Email us at:
info@cadence.com
or log on to:
www.cadence.com

© 2008 Cadence Design Systems, Inc. All rights reserved. Cadence, Allegro, Encounter, SourceLink, Verilog, Virtuoso, and VoltageStorm are registered
trademarks, and the Cadence logo is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders.
20718 08/08 MK/MVC/CS/PDF