Acer Aspire 4553 4553g 5553 5553g 4625 4625g 5625 5625g Quanta zq2 Rev 1a SCH PDF

1 2 3 4 5 6 7 8
PCB STACK UP ZQ2 SYSTEM DIAGRAM 01

LAYER 1 : TOP DDR3 channel A
DDR3-SODIMM1
LAYER 2 : GND AMD Champlain CPU THERMAL
LAYER 3 : IN1 PAGE 5,6 SENSOR
35mm X 35mm
A LAYER 4 : IN2 S1G4 Processor PAGE 4
A
DDR3-SODIMM2 DDR3 channel B

LAYER 5 : VCC
638P (PGA)45W/35W
LAYER 6 : IN3 PAGE 5,6 PAGE 2,3,4 CPU_CLK
LAYER 7 : GND NBGFX_CLK From SB
LAYER 8 : BOT NBGPP_CLK CLOCK GEN
SBLINK_CLK
IV@ -----> iGPU
HT3
SW@ -----> dGPU
SP@ -----> option notice PCI-Express 8X ATI 800MHz
PCI-E
SIDE@ -----> sideport Side port
Park XT
VRAM DDR3
NORTH BRIDGE 128-bit M2 Pkg
X1 X2 64MX16X4,64 bit
29mm X 29mm
sideport-L75,L76,R583,R392,C832,R455,R550,R502 64MX16X8,128 bit
NB A11-R105,R108 LAN Mini PCI-E RS880 DDR3 RAM PAGE 16,17,18
PAGE 22
Atheros Card 19,20,21
SB A12-R267,R271 PAGE 7
JV/JM-CN16,R450,R456 PCIE-LAN A12 VGA Park
AR8151 (Wireless LAN)
B EC-D8,D27 21mm X 21mm, 528pin BGA HDMI B
(10/100/1000) PAGE 24
UMA-R461 HDMI
VRAM-R358,R359,R360,R363,R365,R72 PAGE 25 PAGE 26 CRT CRT PAGE 23
PAGE 7,8,9,10 LVDS
LVDS PAGE 23
RJ45
ALINK X4
PAGE 25
SATA - HDD1
SATA0 150MB BT
PAGE 27 SOUTH BRIDGE PAGE 32
SATA1 150MB 9
SATA - CD-ROM SB820
PAGE 27 21mm X 21mm, 528pin BGA USB1.1
AMD CPU CORE (ISL6265)
CPU 4.5W(Ext)
PAGE 36 A11
C 4.3W(Int) USB2.0 C
NB_CORE (UP6111AQDD) PAGE 12,13,14,15,16 0 8 5 4

PAGE 38 NB USB2.0 Ports Webcam WLAN conn
CardReader
X1 PAGE 30 PAGE 23 PAGE 26
AU6437
+VGPU_CORE (MAX8792ETD)
PAGE 29 10,11,12
PAGE 40 LPC Azalia
USB BOARD
+1V/+1.5_GPU/+1.8_GPU USB2.0 Ports x3
Winbond KBC Codec
PAGE 41 RTL ALC271X
PAGE 30
NPCE781L
0.9V/DDR 1.5V(RT8207) PAGE 28 Power BOARD
PAGE 33
PAGE 39 PAGE 30
SYSTEM 5V/3V (RT8206) Switch BOARD

D
PAGE 35 PAGE 30
D
1.1V(UP6111AQDD) SPI Digital MIC AUDIO CONN Speaker

PAGE 37 PAGE 32 CPU FAN (Phone/ MIC)
Keyboard
PAGE 32 PAGE 32 PAGE 33 PAGE 28 PAGE 28 PAGE 28
PROJECT : ZQ2
Touch Pad
Discharge /Thermal protec Quanta Computer Inc.
Size Document Number Rev
PAGE 42 1A
Block Diagram
Date: Wednesday, May 27, 2009 Sheet 1 of 46
1 2 3 4 5 6 7 8
5 4 3 2 1
W/S= 15 mil/20mil+CPUVDDA
02
BLM21PG221SN1D(220,100M,2A)_8
S1G4 +2.5V +CPUVDDA CPU_LDT_RST# 300/F_4 R416
L35 CPU CLK CPU_PWRGD 300/F_4 R415 +1.5V
2.5V@250mA CPU_LDT_REQ#_CPU *300/F_4 R412
+1.1V 1.1V@1.5A +1.1V_VLDT C385 LS0805-100M-N
4.7U/6.3V_6
C387
4.7U/6.3V_6
C379
0.22U/6.3V_4
C380
3300P/50V_4
C386
11 CLK_CPU_BCLKP_PR
CLK_CPU_BCLKP_PR
CLK_CPU_BCLKN_PR CPU_LDT_STOP# 300/F_4 R206
*10U/6.3V_8 11 CLK_CPU_BCLKN_PR
R194 *Short_6
Keep trace from resisor to CPU within 0.6"
R195 *Short_6 +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U24D
U24A W/S= 15 mil/20mil
+CPUVDDA F8 M11
C596 10U/6.3V_8 +1.1V_VLDT +1.1V_VLDT 10U/6.3V_8 C353 CLK_CPU_BCLKP_C R417 169/F_4 CLK_CPU_BCLKN_C +CPUVDDA VDDA1 VSS
D1
VLDT_A0
HT LINK VLDT_B0
AE2 F9
VDDA2 RSVD11
W18
C352 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT 0.22U/6.3V_4 C598
D C354 0.22U/6.3V_4 +1.1V_VLDT VLDT_A1 VLDT_B1 +1.1V_VLDT 180P/50V_4 C597 CLK_CPU_BCLKP_PR C608 3900P/25V_4 CLK_CPU_BCLKP_C CPU_SVC_R D
D3 AE4 A9 A6
C599 180P/50V_4 +1.1V_VLDT VLDT_A2 VLDT_B2 +1.1V_VLDT CLK_CPU_BCLKN_PR C609 3900P/25V_4 CLK_CPU_BCLKN_C CLKIN_H SVC CPU_SVD_R
D4 AE5 A8 A4
VLDT_A3 VLDT_B3 CLKIN_L SVD
HT_CADINP0 E3 AD1 HT_CADOUTP0 CPU_LDT_RST# B7
L0_CADIN_H0 L0_CADOUT_H0 11 CPU_LDT_RST# RESET_L
HT_CADINN0 E2 AC1 HT_CADOUTN0 CPU_PWRGD A7
L0_CADIN_L0 L0_CADOUT_L0 11 CPU_PWRGD PWROK
HT_CADINP1 E1 AC2 HT_CADOUTP1 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L#
L0_CADIN_H1 L0_CADOUT_H1 9,11 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
SI Change from AMD request HT_CADINN1 F1 AC3 HT_CADOUTN1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_CADINP2 L0_CADIN_L1 L0_CADOUT_L1 HT_CADOUTP2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 AB1 AA8
HT_CADINN2 L0_CADIN_H2 L0_CADOUT_H2 HT_CADOUTN2 MEMHOT_L
G2
L0_CADIN_L2 L0_CADOUT_L2
AA1 SideBand Temp sense I2C 4 CPU_SIC AF4
SIC
HT_CADINP[15..0] HT_CADINP3 G1 AA2 HT_CADOUTP3 AF5
7 HT_CADINP[15..0] L0_CADIN_H3 L0_CADOUT_H3 4 CPU_SID SID
HT_CADINN3 H1 AA3 HT_CADOUTN3 AE6 W7
HT_CADINN[15..0] L0_CADIN_L3 L0_CADOUT_L3 4 CPU_ALERT ALERT_L THERMDC H_THRMDC 4
HT_CADINP4 J1 W2 HT_CADOUTP4 W8
7 HT_CADINN[15..0] L0_CADIN_H4 L0_CADOUT_H4 THERMDA H_THRMDA 4
HT_CADINN4 K1 W3 HT_CADOUTN4 R162 44.2/F_4 CPU_HTREF0 R6
HT_CLKINP[1..0] HT_CADINP5 L0_CADIN_L4 L0_CADOUT_L4 HT_CADOUTP5 R158 44.2/F_4 CPU_HTREF1 HT_REF0
7 HT_CLKINP[1..0]
L3 V1 +1.1V_VLDT P6
HT_CADINN5 L0_CADIN_H5 L0_CADOUT_H5 HT_CADOUTN5 place them to CPU within 1.5" HT_REF1
L2 U1
HT_CLKINN[1..0] HT_CADINP6 L0_CADIN_L5 L0_CADOUT_L5 HT_CADOUTP6 VDDIO_FB_H
7 HT_CLKINN[1..0] L1 U2 36 CPU_VDD0_FB_H F6 W9 VDDIO_FB_H 39
HT_CADINN6 L0_CADIN_H6 L0_CADOUT_H6 HT_CADOUTN6 VDD0_FB_H VDDIO_FB_H VDDIO_FB_L
M1 U3 36 CPU_VDD0_FB_L E6 Y9 VDDIO_FB_L 39
HT_CTLINP[1..0] HT_CADINP7 L0_CADIN_L6 L0_CADOUT_L6 HT_CADOUTP7 VDD0_FB_L VDDIO_FB_L
7 HT_CTLINP[1..0]
N3 T1
HT_CADINN7 L0_CADIN_H7 L0_CADOUT_H7 HT_CADOUTN7
N2 R1 36 CPU_VDD1_FB_H Y6 H6 CPU_VDDNB_FB_H 36
HT_CTLINN[1..0] HT_CADINP8 L0_CADIN_L7 L0_CADOUT_L7 HT_CADOUTP8 VDD1_FB_H VDDNB_FB_H
7 HT_CTLINN[1..0] E5 AD4 36 CPU_VDD1_FB_L AB6 G6 CPU_VDDNB_FB_L 36
HT_CADINN8 L0_CADIN_H8 L0_CADOUT_H8 HT_CADOUTN8 VDD1_FB_L VDDNB_FB_L
F5 AD3
HT_CADOUTP[15..0] HT_CADINP9 L0_CADIN_L8 L0_CADOUT_L8 HT_CADOUTP9 CPU_DBRDY
7 HT_CADOUTP[15..0] F3 AD5 G10
HT_CADINN9 L0_CADIN_H9 L0_CADOUT_H9 HT_CADOUTN9 CPU_TMS DBRDY
F4 AC5 AA9 E10 CPU_DBREQ# R212 *300/F_4 +1.5V
HT_CADOUTN[15..0] HT_CADINP10 L0_CADIN_L9 L0_CADOUT_L9 HT_CADOUTP10 CPU_TCK TMS DBREQ_L R204 300/F_4
G5 AB4 AC9 +1.5VSUS
7 HT_CADOUTN[15..0] HT_CADINN10 L0_CADIN_H10 L0_CADOUT_H10 HT_CADOUTN10 CPU_TRST# TCK
H5 AB3 AD9 AE9 CPU_TDO
HT_CLKOUTP[1..0] HT_CADINP11 L0_CADIN_L10 L0_CADOUT_L10 HT_CADOUTP11 CPU_TDI TRST_L TDO PV stage:add
7 HT_CLKOUTP[1..0] H3 AB5 AF9
HT_CADINN11 L0_CADIN_H11 L0_CADOUT_H11 HT_CADOUTN11 TDI +1.5VSUS
H4 AA5
HT_CLKOUTN[1..0] HT_CADINP12 L0_CADIN_L11 L0_CADOUT_L11 HT_CADOUTP12 CPUTEST23 option R204
7 HT_CLKOUTN[1..0]
K3 Y5 AD7 J7
HT_CADINN12 L0_CADIN_H12 L0_CADOUT_H12 HT_CADOUTN12 TEST23 TEST28_H for Caspian
K4 W5 H8
HT_CTLOUTP[1..0] HT_CADINP13 L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUTP13 CPUTEST18 TEST28_L CPU power
7 HT_CTLOUTP[1..0] L5 V4 H10
C HT_CADINN13 L0_CADIN_H13 L0_CADOUT_H13 HT_CADOUTN13 CPUTEST19 TEST18 CPUTEST17 leakage issue C
M5 V3 G9 D7 T32
HT_CTLOUTN[1..0] HT_CADINP14 L0_CADIN_L13 L0_CADOUT_L13 HT_CADOUTP14 TEST19 TEST17 CPUTEST16
7 HT_CTLOUTN[1..0] M3 V5 E7 T31
HT_CADINN14 L0_CADIN_H14 L0_CADOUT_H14 HT_CADOUTN14 R205 510/F_4 CPUTEST25H TEST16 CPUTEST15
M4 U5 +1.5VSUS E9 F7 T38
HT_CADINP15 L0_CADIN_L14 L0_CADOUT_L14 HT_CADOUTP15 R211 510/F_4 CPUTEST25L TEST25_H TEST15 CPUTEST14
N5 T4 E8 C7 T39
HT_CADINN15 L0_CADIN_H15 L0_CADOUT_H15 HT_CADOUTN15 place them to CPU within 1.5" TEST25_L TEST14
P5 T3
L0_CADIN_L15 L0_CADOUT_L15 CPUTEST21 AB8 C3
HT_CLKINP0 HT_CLKOUTP0 CPUTEST20 TEST21 TEST7
J3 Y1 AF7 K8
HT_CLKINN0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CLKOUTN0 CPUTEST24 TEST20 TEST10
J2 W1 AE7
HT_CLKINP1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUTP1 CPUTEST22 TEST24
J5 Y4 AE8 C4
HT_CLKINN1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CLKOUTN1 CPUTEST12 TEST22 TEST8
K5 Y3 AC8
L0_CLKIN_L1 L0_CLKOUT_L1 R384 1K/F_4 CPUTEST27 TEST12
+1.5VSUS AF8
HT_CTLINP0 HT_CTLOUTP0 TEST27 CPUTEST29H
N1 R2 C9 T40
HT_CTLINN0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CTLOUTN0 R383 *300/F_4 R401 *Short_4 TEST9 TEST29_H
P1 R3 C2 C8
HT_CTLINP1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CTLOUTP1 TEST9 TEST29_L
P3 T5 AA6
HT_CTLINN1 L0_CTLIN_H1 L0_CTLOUT_H1 HT_CTLOUTN1 TEST6 R208
P4 R5
L0_CTLIN_L1 L0_CTLOUT_L1
A3 H18 80.6/F_4
FOX PZ63826-284R-41F RSVD1 RSVD10
A5 H19
SOCKET_638_PIN RSVD2 RSVD9 CPUTEST29L
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) B3 AA7 T41
RSVD3 RSVD8
MLX 47296-4131 B5 D5
RSVD4 RSVD7
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2) 3..6,36,39,41 +1.5VSUS C1 C5
RSVD5 RSVD6
TYC 4-1903401-2 7,10,26,39,42 +1.5V
7..10,14,37 +1.1V
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) 42 +2.5V
SOCKET_638_PIN
4,5,9..15,19,23,24,26,28..33,35..42 +3V
CNTR_VREF 4 +3V
PV stage:add +1.5VSUS option
C578 0.1U/10V_4
Serial VID R540 R541 for Caspian CPU VFIX MODE VID Override Circuit
+3V R92 20K/F_4 R371 34.8K/F_4 SI Change from AMD request power leakge issue
B R91 B
CNTR_VREF
SVC SVD Voltage Output
4.7K/J_4
0 0 1.1V
2
Q29 *BSS138_NL/SOT23
0 1 1.0V
2
CPU_LDT_REQ#_CPU 1 3 +1.5VSUS R405 1K/F_4

CPU_LDT_REQ# 9
R406 *1K/F_4
CPU_LDT_RST# 1 3 CPU_LDT_RST_HTPA#
+1.5V 1 0 0.9V
Q5 D05
R368 *0_4 BSS138_NL/SOT23 +1.5VSUS R409 *1K/F_4 1 1 0.8V
1
G2 +1.5V R413 1K/F_4

The RS880 family does not support CLMC architecture *SHORT_ PAD1
The LDTREQ# connection from the CPU to ALLOW_LDTSTOP CPU_SVC_R R411 *Short_4
CPU_SVC 36
CPU_SVD_R R408 *Short_4
of the Northbridge is no longer required.
2
CPU_SVD 36
CPU_PWRGD R414 *Short_4
CPU_PWRGD_SVID_REG 36
for debug only
R410 *220/J_4
R407 *220/J_4
+1.5VSUS R95 *10K/F_4 S1g4 does not support MEMHOT# R418 *220/J_4
2
+1.5VSUS R90 *1K/F_4 Q4

*MMBT3904 CPUTEST24 R381 1K/F_4
CPU_MEMHOT_L# 3
R152
1
*0_4
CPU_MEMHOT# 5,11 HDT Connector CPUTEST23
CPUTEST20
CPUTEST22
R379
R380
R382
1K/F_4
1K/F_4
1K/F_4
C01 CPUTEST12 R120 1K/F_4
+1.5VSUS 3 1 R373 1K_4 R428 100K_6 CPUTEST15 R209 *300/F_4
1 2 CPUTEST14 R210 *300/F_4
Q43 BSS138_NL/SOT23 3 4 CPUTEST19 R183 1K/F_4
A 5 6 CPUTEST18 R184 1K/F_4 A
2
15,33,36 CPU_COREPG CPU_DBREQ# 7 8 CPUTEST21 R121 1K/F_4

2
Q31 CPU_DBRDY 9 10
CPU_THERMTRIP_L# MMBT3904 CPU_TCK 11 12 S1G4
+1.5VSUS R378 1K/F_4 1 3 R236 *0_4 CPU_TMS 13 14
CPU_THERMTRIP# 12
CPU_TDI 15 16
+1.5VSUS R113 *10K/F_4 R424 *Short_4
SYS_SHDN# 4,35,42
CPU_TRST#
CPU_TDO
17
19
18
20
PROJECT : ZQ2
R377 300/F_4 B12 21 22
+1.5VSUS +1.5VSUS
Quanta Computer Inc.
2
Q8 D11 C530 *0.1U/10V_4 23 24 CPU_LDT_RST_HTPA#

KEY 25
CPU_PROCHOT_L# 1 3 Size Document Number Rev
PM_THERM# 4,12,32
*MMBT3904 *HDT CONN S1G4 HT,CTL I/F 1/3 1A
R104 0_4 CN5
CPU_PROCHOT# 11
5 4 3 2 1
A B C D E
03
35W CPU support 0.9V VDDR=> 0.9V support 1066 / 800 DDR
45W CPU support 1.05V VDDR= >1.05V support 1333 / 1066 / 800 DDR
VDDR=>1.75A CPU_VDDR D01

5 M_B_DQ[0..63]
Processor Memory Interface
+1.5VSUS CPU_VDDR U24B CPU_VDDR
PLACE THEM CLOSE TO D10 W10 +SMDDR_VREF

VDDR1 MEM:CMD/CTRL/CLKVDDR5 U24C
CPU WITHIN 1" C10 AC10 M_A_DQ[0..63] 5
R374 VDDR2 VDDR6 MEM:DATA
B10 AB10
0/J_4 VDDR3 VDDR7 M_B_DQ0 M_A_DQ0
AD10 AA10 C11 G12
VDDR4 VDDR8 R124 M_B_DQ1 MB_DATA0 MA_DATA0 M_A_DQ1
A10 A11 F12
R386 39.2/F_4 M_ZP VDDR9 M_B_DQ2 MB_DATA1 MA_DATA1 M_A_DQ2
AF10 *0/J_4 A14 H14
R385 39.2/F_4 M_ZN MEMZP MB_DATA2 MA_DATA2
AE10 Y10 CPU_VTT_SENSE R479 M_B_DQ3 B14 G14 M_A_DQ3
4 MEMZN VDDR_SENSE *0/J_4 M_B_DQ4 MB_DATA3 MA_DATA3 M_A_DQ4 4
G11 H11
MB_DATA4 MA_DATA4
5 M_A_RST# H16 W17 MEMVREF_CPU M_B_DQ5 E11 H12 M_A_DQ5
C595 C536 MA_RESET_L MEMVREF M_B_DQ6 MB_DATA5 MA_DATA5 M_A_DQ6
D12 C13
4.7U/6.3V_6 4.7U/6.3V_6 M_B_DQ7 MB_DATA6 MA_DATA6 M_A_DQ7
5 M_A_ODT0 T19 B18 M_B_RST# 5 A13 E13
MA0_ODT0 MB_RESET_L M_B_DQ8 MB_DATA7 MA_DATA7 M_A_DQ8
EC-D 5 M_A_ODT1 V22
MA0_ODT1
A15
MB_DATA8 MA_DATA8
H15
U21 W26 M_B_DQ9 A16 E15 M_A_DQ9
MA1_ODT0 MB0_ODT0 M_B_ODT0 5 MB_DATA9 MA_DATA9
V19 W23 C227 C226 M_B_DQ10 A19 E17 M_A_DQ10
MA1_ODT1 MB0_ODT1 M_B_ODT1 5 MB_DATA10 MA_DATA10
Y26 0.1U/10V_4 1000P/50V_4 M_B_DQ11 A20 H17 M_A_DQ11
MB1_ODT0 M_B_DQ12 MB_DATA11 MA_DATA11 M_A_DQ12
5 M_A_CS#0 T20 C14 E14
MA0_CS_L0 M_B_DQ13 MB_DATA12 MA_DATA12 M_A_DQ13
5 M_A_CS#1 U19 V26 M_B_CS#0 5 D14 F14
MA0_CS_L1 MB0_CS_L0 M_B_DQ14 MB_DATA13 MA_DATA13 M_A_DQ14
U20 W25 M_B_CS#1 5 C18 C17
V20 U22 D18 G17
D20 G18
M_B_DQ17 MB_DATA16 MA_DATA16 M_A_DQ17
5 M_A_CKE0 J22 J25 M_B_CKE0 5 A21 C19
MA_CKE0 MB_CKE0 M_B_DQ18 MB_DATA17 MA_DATA17 M_A_DQ18
5 M_A_CKE1 J20 H26 M_B_CKE1 5 D24 D22
MA_CKE1 MB_CKE1 M_B_DQ19 MB_DATA18 MA_DATA18 M_A_DQ19
C25 E20
5 M_A_CLKP1 N19 P22 M_B_CLKP1 5 B20 E18
MA_CLK_H5 MB_CLK_H5 M_B_DQ21 MB_DATA20 MA_DATA20 M_A_DQ21
5 M_A_CLKN1 N20 R22 M_B_CLKN1 5 C20 F18
MA_CLK_L5 MB_CLK_L5 M_B_DQ22 MB_DATA21 MA_DATA21 M_A_DQ22
E16 A17 B24 B22
F16 A18 C24 C23
Y16 AF18 E23 F20
AA16 AF17 E24 F22
5 M_A_CLKP2 P19 R26 M_B_CLKP2 5 G25 H24
5 M_A_CLKN2 P20 R25 M_B_CLKN2 5 G26 J19
C26 E21
M_A_A0 M_B_A0 M_B_DQ29 MB_DATA28 MA_DATA28 M_A_DQ29
N21 P24 D26 E22
M_A_A1 MA_ADD0 MB_ADD0 M_B_A1 M_B_DQ30 MB_DATA29 MA_DATA29 M_A_DQ30
M20 N24 G23 H20
N22 P26 G24 H22
M19 N23 AA24 Y24
3 M22 N26 AA23 AB24 3
L20 L23 AD24 AB22
M24 N25 AE24 AA21
L21 L24 AA26 W22
L19 M26 AA25 W21
K22 K26 AD26 Y22
R21 T26 AE25 AA22
L22 L26 AC22 Y20
K20 L25 AD22 AA20
V24 W24 AE20 AA18
K24 J23 AF20 AB18
5 M_A_A[0..15] K19 J24 M_B_A[0..15] 5 AF24 AB21
MA_ADD15 MB_ADD15 M_B_DQ45 MB_DATA44 MA_DATA44 M_A_DQ45
AF23 AD21
5 M_A_BANK0 R20 R24 M_B_BANK0 5 AC20 AD19
MA_BANK0 MB_BANK0 M_B_DQ47 MB_DATA46 MA_DATA46 M_A_DQ47
5 M_A_BANK1 R23 U26 M_B_BANK1 5 AD20 Y18
5 M_A_BANK2 J21 J26 M_B_BANK2 5 AD18 AD17
AE18 W16
5 M_A_RAS# R19 U25 M_B_RAS# 5 AC14 W14
MA_RAS_L MB_RAS_L M_B_DQ51 MB_DATA50 MA_DATA50 M_A_DQ51
5 M_A_CAS# T22 U24 M_B_CAS# 5 AD14 Y14
MA_CAS_L MB_CAS_L M_B_DQ52 MB_DATA51 MA_DATA51 M_A_DQ52
5 M_A_WE# T24 U23 M_B_WE# 5 AF19 Y17
MA_WE_L MB_WE_L M_B_DQ53 MB_DATA52 MA_DATA52 M_A_DQ53
AC18 AB17
AF16 AB15
SOCKET_638_PIN M_B_DQ55 MB_DATA54 MA_DATA54 M_A_DQ55
AF15 AD15
AF13 AB13
CPU_VDDR M_B_DQ57 MB_DATA56 MA_DATA56 M_A_DQ57
AC12 AD13
Place close to socket M_B_DQ58 AB11
MB_DATA57 MA_DATA57
Y12 M_A_DQ58
Y11 W11
AE14 AB14
AF14 AA14
C371 C210 C218 C370 C363 C364 C223 C224 M_B_DQ62 MB_DATA61 MA_DATA61 M_A_DQ62
AF11 AB12
2
4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 M_B_DQ63 MB_DATA62 MA_DATA62 M_A_DQ63 2
5 M_B_DM[0..7] AD11 AA12 M_A_DM[0..7] 5
MB_DATA63 MA_DATA63
CPU_VDDR M_B_DM0 A12 E12 M_A_DM0
M_B_DM1 MB_DM0 MA_DM0 M_A_DM1
B16 C15
A22 E19
E25 F24
AB26 AC24
C362 C365 C282 C230 C367 C217 C360 C229 M_B_DM5 MB_DM4 MA_DM4 M_A_DM5
AE22 Y19
1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 M_B_DM6 MB_DM5 MA_DM5 M_A_DM6
AC16 AB16
AD12 Y13
MB_DM7 MA_DM7
5 M_B_DQSP0 C12 G13 M_A_DQSP0 5

MB_DQS_H0 MA_DQS_H0
5 M_B_DQSN0 B12 H13 M_A_DQSN0 5
+1.5VSUS MB_DQS_L0 MA_DQS_L0
D16 G16
Reserved for AMD suggest 5 M_B_DQSP1
C16
MB_DQS_H1 MA_DQS_H1
G15
M_A_DQSP1 5
5 M_B_DQSN1 MB_DQS_L1 MA_DQS_L1 M_A_DQSN1 5
5 M_B_DQSP2 A24 C22 M_A_DQSP2 5
MB_DQS_H2 MA_DQS_H2
5 M_B_DQSN2 A23 C21 M_A_DQSN2 5
R112 0/J_4 MB_DQS_L2 MA_DQS_L2
5 M_B_DQSP3 F26 G22 M_A_DQSP3 5
MB_DQS_H3 MA_DQS_H3
5 M_B_DQSN3 E26 G21 M_A_DQSN3 5
+3VPCU MB_DQS_L3 MA_DQS_L3
5 M_B_DQSP4 AC25 AD23 M_A_DQSP4 5
MB_DQS_H4 MA_DQS_H4
C203 5 M_B_DQSN4 AC26 AC23 M_A_DQSN4 5
R103 MB_DQS_L4 MA_DQS_L4
5 M_B_DQSP5 AF21 AB19 M_A_DQSP5 5
MB_DQS_H5 MA_DQS_H5
5 M_B_DQSN5 AF22 AB20 M_A_DQSN5 5
1K/F_4 MB_DQS_L5 MA_DQS_L5
5 M_B_DQSP6 AE16 Y15 M_A_DQSP6 5
MB_DQS_H6 MA_DQS_H6
5 M_B_DQSN6 AD16 W15 M_A_DQSN6 5
5
U6 *.1U/10V_4 MB_DQS_L6 MA_DQS_L6

5 M_B_DQSP7 AF12 W12 M_A_DQSP7 5
R110 *10_4 MB_DQS_H7 MA_DQS_H7
3 + 5 M_B_DQSN7 AE12 W13 M_A_DQSN7 5
MEMVREF_CPU MB_DQS_L7 MA_DQS_L7
1 1 2
4 -
2
1 R100 *OPA343NA/3K SOCKET_638_PIN 1

C207
2
1K/F_4 *0.47U/10V_4 R111

1
*10K/F_4
R102 *0/J_4
R109 *0/J_4 PROJECT : ZQ2

5,39 +0.75V_DDR_VTT Quanta Computer Inc.
5,39 +SMDDR_VREF
39 CPU_VDDR Size Document Number Rev
2,4..6,36,39,41 +1.5VSUS S1G4 DDRIII MEMORY I/F 2/3 1A
11,27,30..35,39,42 +3VPCU
A B C D E
5 4 3 2 1
36 +VCORE
04
31,36 CPU_VDDNB_CORE
2,3,5,6,36,39,41 +1.5VSUS
2,5,9..15,19,23,24,26,28..33,35..42 +3V U24F
AA4 VSS1 VSS66 J6
AA11 J8
+VCORE U24E +VCORE VSS2 VSS67 +VCORE
AA13 J10
G4 P8
AA15
AA17
VSS3
VSS4
VSS68
VSS69
J12
J14
BOTTOM SIDE DECOUPLING
VDD_1 VDD_24 VSS5 VSS70
H2 VDD_2 VDD_25 P10 AA19 VSS6 VSS71 J16
J9 VDD_3 VDD_26 R4 AB2 VSS7 VSS72 J18
J11 R7 AB7 K2 C284 C310 C299 C291 C286 C285 C321
VDD_4 VDD_27 VSS8 VSS73 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 0.22U/6.3V_4 0.01u/16V_4 180P/50V_4
J13 R9 AB9 K7
D
J15 VDD_6 VDD_29 R11 AB23 VSS10 VSS75 K9 D
K6 T2 AB25 K11
K10 T6 AC11 K13
K12 T8 AC13 K15
VDD_9 VDD_32 VSS13 VSS78 +VCORE
K14 T10 AC15 K17
L4 VDD_11 VDD_34 T12 AC17 VSS15 VSS80 L6
L7 T14 AC19 L8
L9 U7 AC21 L10
L11 VDD_14 VDD_37 U9 AD6 VSS18 VSS83 L12
L13 U11 AD8 L14 C292 C311 C330 C319 C331 C327 C332 C334
VDD_15 VDD_38 VSS19 VSS84 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 0.22U/6.3V_4 0.01u/16V_4 180P/50V_4 0.01u/16V_4
L15 U13 AD25 L16
M2 U15 AE11 L18
M6 V6 AE13 M7
M8 VDD_19 VDD_42 V8 AE15 VSS23 VSS88 M9
M10 VDD_20 VDD_43 V10 AE17 VSS24 VSS89 AC6
N7 V12 AE19 M17 CPU_VDDNB_CORE +1.5VSUS
CPU_VDDNB_CORE VDD_21 VDD_44 VSS25 VSS90
N9 V14 AE21 N4
N11 VDD_23 VDD_46 W4 AE23 VSS27 VSS92 N8
Y2 B4 N10
3A K16
VDDNB_1
VDD_47
VDD_48
AC4
+1.5VSUS
B6
VSS28
VSS29
VSS93
VSS94
N16
M16 AD2 B8 N18 C300 C320 C312 C347 C348 C295 C322 C296 C318
VDDNB_2 VDD_49 VSS30 VSS95 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 0.22U/6.3V_4 0.22U/6.3V_4 180P/50V_4 180P/50V_4
P16 VDDNB_3 B9 VSS31 VSS96 P2
+1.5VSUS T16 Y25 B11 P7
VDDNB_4 VDDIO27 VSS32 VSS97
V16 V25 B13 P9
H25
VDDNB_5 VDDIO26
VDDIO25
V23
V21
1.5V@2A B15
B17
VSS33
VSS34
VSS98
VSS99
P11
P17
VDDIO1 VDDIO24 VSS35 VSS100
J17 VDDIO2 VDDIO23 V18 B19 VSS36 VSS101 R8
K18 U17 B21 R10
K21 T25 B23 R16
K23 T23 B25 R18
C K25 VDDIO6 VDDIO19 T21 D6 VSS40 VSS105 T7 C
L17 T18 D8 T9
M18
M21
VDDIO7
VDDIO8
VDDIO18
VDDIO17 R17
P25
D9
D11
VSS41
VSS42
VSS106
VSS107 T11
T13
DECOUPLING BETWEEN PROCESSOR AND DIMMs
M23 P23 D13 T15
M25
N17
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21
P18
D15
D17
VSS44
VSS45
VSS109
VSS110 T17
U4
PLACE CLOSE TO PROCESSOR AS POSSIBLE
D19 U6
VSS47 VSS112 +1.5VSUS
D21 U8
SOCKET_638_PIN VSS48 VSS113
D23 U10
VSS49 VSS114
D25 VSS50 VSS115 U12
+1.5VSUS E4 U14
VSS51 VSS116
F2 U16
VSS52 VSS117 C302 C338 C304 C303 C283 C301
F11 VSS53 VSS118 U18
F13 V2 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 0.22U/6.3V_4
VSS54 VSS119
F15 V7
R375 R369 R376 VSS55 VSS120
F17 VSS56 VSS121 V9
1K/F_4 1K/F_4 1K/F_4 F19 V11 +1.5VSUS
2 CNTR_VREF VSS57 VSS122
F21 V13
VSS58 VSS123
F23 VSS59 VSS124 V15
2
F25 V17
Q30 VSS60 VSS125
H7 W6
CPU_SMBCLK VSS61 VSS126 C309 C290 C328 C349 C314
3 1 CPU_SIC 2 H9 Y21
VSS62 VSS127 0.22U/6.3V_4 0.22U/6.3V_4 0.01u/16V_4 0.01u/16V_4 180P/50V_4
H21 Y23
VSS63 VSS128
2
BSS138_NL/SOT23 H23 N6
Q28 VSS64 VSS129
J4 VSS65
CPU_SMBDATA 3 1 CPU_SID 2
SOCKET_638_PIN
2
BSS138_NL/SOT23
Q3
B B
PM_THERM# 3 1 CPU_ALERT 2
D11
BSS138_NL/SOT23
+3V PROCESSOR POWER AND GROUND

+3V R403
*200/F_6
SYS_SHDN#_3904 R185 *Short_4
SYS_SHDN# 2,35,42
reserve for
1
R404
power shutdown D5
C606 ( if can )
*10K/F_4 *CH500H
*0.1U/10V_4
2
U25
33 CPU_SMBCLK CPU_SMBCLK 8 1
SCLK VCC H_THRMDA 2
R191 *Short_4
33 CPU_SMBDATA CPU_SMBDATA 7 2 C607 Q16
SDA DXP *1000P/50V_4
3
6 3 *MMBT3904 D6
ALERT# DXN
H_THRMDC 2 2 PWROK_EC_39042 1 PWROK_EC 15,33
2,12,32 PM_THERM# R432 *0_4 4 5 *CH501H-40PT
OVERT# GND
1
A MSOP R187 *10K/F_4 A

+3V
*G786P8 SMBALERT#
3
Adress ID: 9A R402 *10K/F_4
Q15 2 TEMP_FAIL 17
PROJECT : ZQ2
*2N7002E-G Quanta Computer Inc.
ADD VGA TEMP_ FAIL function
M93 is active Hi Size Document Number Rev
1
S1G4 PWR & GND 3/3 1A

5 4 3 2 1
5 4 3 2 1
3 M_A_A[0..15] +1.5VSUS M_A_DQ[0..63] 3 3 M_B_A[0..15] +1.5VSUS M_B_DQ[0..63] 3
05
100
105
106
111
112
117
118
123
124
100
105
106
111
112
117
118
123
124
75
76
81
82
87
88
93
94
99
75
76
81
82
87
88
93
94
99
CN18 CN19
M_A_A0 98 5 M_A_DQ1 M_B_A0 98 5 M_B_DQ5
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
M_A_A1 A0 DQ0 M_A_DQ0 M_B_A1 A0 DQ0 M_B_DQ4
97 7 97 7
M_A_A2 A1 DQ1 M_A_DQ7 +1.5VSUS M_B_A2 A1 DQ1 M_B_DQ7
96 15 96 15
95 17 95 17
M_A_A4 A3/A4 DQ3 M_A_DQ5 M_B_A4 A3/A4 DQ3 M_B_DQ0
92 4 92 4
M_A_A5 A4/A3 DQ4 M_A_DQ4 +SMDDR_VREF +VREF_CA_B M_B_A5 A4/A3 DQ4 M_B_DQ1
91 6 91 6
M_A_A6 A5/A6 DQ5 M_A_DQ2 R153 M_B_A6 A5/A6 DQ5 M_B_DQ3
90 16 90 16
M_A_A7 A6/A5 DQ6 M_A_DQ3 *2K/F_4 M_B_A7 A6/A5 DQ6 M_B_DQ2
86 18 86 18
89 21 89 21
85 23 85 23
D M_A_A10 A9 DQ9 M_A_DQ15 R151 *Short_4 M_B_A10 A9 DQ9 M_B_DQ14 D
107 33 107 33
M_A_A11 A10/AP DQ10 M_A_DQ11 M_B_A11 A10/AP DQ10 M_B_DQ15
84 35 84 35
83 22 83 22
M_A_A13 A12_BC# DQ12 M_A_DQ12 C293 C288 R160 M_B_A13 A12_BC# DQ12 M_B_DQ9
119 24 119 24
80 34 80 34
M_A_A15 A14 DQ14 M_A_DQ10 0.1U/10V_4 2.2u/6.3V_6 M_B_A15 A14 DQ14 M_B_DQ11
78 36 78 36
A15/BA3 DQ15 M_A_DQ16 *2K/F_4 A15/BA3 DQ15 M_B_DQ20
39 39
M_A_BANK0 DQ16 M_A_DQ21 M_B_BANK0 DQ16 M_B_DQ21
109 41 109 41
M_A_BANK1 BA0/BA1 DQ17 M_A_DQ18 M_B_BANK1 BA0/BA1 DQ17 M_B_DQ23
108 51 108 51
M_A_BANK2 BA1/BA0 DQ18 M_A_DQ23 M_B_BANK2 BA1/BA0 DQ18 M_B_DQ22
3 M_A_BANK[0..2] 79 53 3 M_B_BANK[0..2] 79 53
BA2 DQ19 M_A_DQ17 BA2 DQ19 M_B_DQ17
40 40
M_A_DM0 DQ20 M_A_DQ20 M_B_DM0 DQ20 M_B_DQ16
11 42 11 42
M_A_DM1 DM0 DQ21 M_A_DQ22 M_B_DM1 DM0 DQ21 M_B_DQ19
28 50 28 50
46 52 46 52
63 57 63 57
136 59 136 59
DM4 DQ25 DM4 DQ25
M_A_DM5 153
DM5 DQ26
67 M_A_DQ30 M_B_DM5 153
DM5 DQ26
67 M_B_DQ30 Standard
M_A_DM6 170
DM6 DQ27
69 M_A_DQ27 Standard M_B_DM6 170
DM6 DQ27
69 M_B_DQ31
3 M_A_DM[0..7]
M_A_DM7 187
DM7 DQ28
56 M_A_DQ28
3 M_B_DM[0..7]
M_B_DM7 187
DM7 DQ28
56 M_B_DQ29 Connector
DQ29
58 M_A_DQ29 Connector DQ29
58 M_B_DQ25
3 M_A_DQSP0 12
DQS0 DQ30
68 M_A_DQ31
3 M_B_DQSP0 12
DQS0 DQ30
68 M_B_DQ27 1
3 M_A_DQSP1 29
DQS1 DQ31
70 M_A_DQ26 1 3 M_B_DQSP1 29
DQS1 DQ31
70 M_B_DQ26
47 129 M_A_DQ37 47 129 M_B_DQ33
3 M_A_DQSP2 3 M_B_DQSP2
1
DQS2 DQ32 M_A_DQ36 DQS2 DQ32 M_B_DQ32

5
7
4
6
64 131 64 131
8
9
10
DDR3 SO-DIMM
DDR3 SO-DIMM
DQS3 DQ33 DQS3 DQ33 2
2 13
3 14
5 4 15
6 16
M_A_DQ35 M_B_DQ34
7 17
137 141 137 141

8 18
11 21
12 22
DQS4 DQ34 2 DQS4 DQ34

13 23 24
14 25
15 26
16 27
M_A_DQ39 M_B_DQ35
17 28
3 M_A_DQSP5 154 143 21

20
22
3 M_B_DQSP5 154 143 31
33
32
CON_SODIMM200_STD_V1
DQS5 DQ35 DQS5 DQ35
23 24 34
25 35
26 36
M_A_DQ38 M_B_DQ37
29 39
171 130 171 130

30 40
31
32
33
CON_SODIMM200_STD_V1
DQS6 DQ36 DQS6 DQ36
34
37
M_A_DQ32 M_B_DQ36
38
188 132 188 132

39
40
41
42
DQS7 DQ37 M_A_DQ33 DQS7 DQ37 M_B_DQ38

45
47
46
48
140 140
49
50
51
DQ38 DQ38
43 54
44 55
45 56
46 57
M_A_DQ34 M_B_DQ39
47 48 58
10 142 10 142
49 59
52 62
3 M_A_DQSN0 3 M_B_DQSN0
53 63
DQS0# DQ39 DQS0# DQ39

54 64
55 65
56 67 66
57 68
C M_A_DQ40 M_B_DQ40 C
58 69
3 M_A_DQSN1 27 147 61
63
62
3 M_B_DQSN1 27 147 73
72
74
(Standard )
(Standard )
64 75
65 76
67 66 77
M_A_DQ41 M_B_DQ45
70 80
45 149 45 149
71 81
72 82
73 83 84
74 85

75 86
78 89
M_A_DQ46 M_B_DQ46
79 90
62 157 62 157
80 91
81 92
82 93
83 84 94
85 95
DQS3# DQ42 M_A_DQ47

89
88
90
DQS3# DQ42 M_B_DQ47

99
98
100
135 159 135 159

91 101
92 103 102
93 104
3 M_A_DQSN4 DQS4# DQ43 3 M_B_DQSN4 DQS4# DQ43

96 107
97 108
98 109
99 110
M_A_DQ44 M_B_DQ44
100 111
152 146 152 146

101 112
105 115
106 116

107 117
108 118
109 119 120
110 121
M_A_DQ45 M_B_DQ41
111 122
3 M_A_DQSN6 169 148 115

114
116
3 M_B_DQSN6 169 148 125
127
126

117 128
118 129
119 120 130
M_A_DQ42 M_B_DQ43
123 133
186 158 186 158

124 134
125 135
126 136
127 137

128 139 138
131 142
M_A_DQ43 M_B_DQ42
132 143
160 160
133 144
134 145
135 146
136 147
137 148
DQ47 M_A_DQ52
141
143
142
DQ47 M_B_DQ53
151
153
152
163 163
144 154
145 155
146 157 156
DQ48 DQ48
149 160
150 161
151 162
152 163
M_A_DQ49 M_B_DQ52
153 164
101 165 101 165

154 165
199 200
158 168
3 M_A_CLKP1 3 M_B_CLKP1
159 169
CK0 DQ49 CK0 DQ49

160 170
161 171
162 172
163 173
M_A_DQ54 M_B_DQ54
164 175 174
103 175 103 175

200
167 178
199
168 179
3 M_A_CLKN1 3 M_B_CLKN1
169 180
CK0# DQ50 CK0# DQ50

170 181
171 182
172 183
M_A_DQ51 M_B_DQ50
176 186
102 177 102 177

177 187
178 188
179 189
3 M_A_CLKP2 3 M_B_CLKP2
180 190
CK1 DQ51 CK1 DQ51

181 191
184 195
M_A_DQ53 M_B_DQ48
185 196
104 164 104 164

186 197
187 198
188 199
189 200
3 M_A_CLKN2 3 M_B_CLKN2
190
CK1# DQ52 M_A_DQ48

193
195
194
196
CK1# DQ52 M_B_DQ49

166 166
197
198
199
DQ53 M_A_DQ50 DQ53 M_B_DQ55

3 M_A_CKE0 73 174 3 M_B_CKE0 73 174
CKE0 DQ54 M_A_DQ55 CKE0 DQ54 M_B_DQ51
3 M_A_CKE1 74 176 3 M_B_CKE1 74 176
CKE1 DQ55 M_A_DQ61 CKE1 DQ55 M_B_DQ60
181 181
DQ56 M_A_DQ60 DQ56 M_B_DQ61
3 M_A_RAS# 110 183 3 M_B_RAS# 110 183
RAS# DQ57 M_A_DQ59 RAS# DQ57 M_B_DQ59
3 M_A_CAS# 115 191 3 M_B_CAS# 115 191
CAS# DQ58 M_A_DQ58 CAS# DQ58 M_B_DQ58 +1.5VSUS
3 M_A_WE# 113 193 3 M_B_WE# 113 193
WE# DQ59 M_A_DQ57 WE# DQ59 M_B_DQ57
3 M_A_CS#0 114 180 3 M_B_CS#0 114 180
S0# DQ60 M_A_DQ56 S0# DQ60 M_B_DQ56
3 M_A_CS#1 121 182 3 M_B_CS#1 121 182
S1# DQ61 M_A_DQ62 S1# DQ61 M_B_DQ62
192 192
DQ62 M_A_DQ63 DQ62 M_B_DQ63 R234
3 M_A_ODT0 116 194 3 M_B_ODT0 116 194
ODT0 DQ63 ODT0 DQ63
3 M_A_ODT1 120 3 M_B_ODT1 120 1K/F_4
ODT1 +1.5VSUS ODT1 +0.75VSMVREF_SUSB
DIM1_SA0 197 77 DIM2_SA0 197 77
DIM1_SA1 SA0 NC1 DIM2_SA1 SA0 NC1
201 122 201 122
SA1 NC2 MEM_MA_TEST SA1 NC2 MEM_MB_TEST
125 T29 125 T30
TEST R440 PDAT_SMB TEST
12,25,26 PDAT_SMB 200 200
B SDA PCLK_SMB SDA B
12,25,26 PCLK_SMB 202 1K/F_4 202
C225 SCL +0.75VSMVREF_SUSA C592 SCL
+3V 0.1U/10V_4 199 196 +3V 0.1U/10V_4 199 196
VDDspd VSS51 VDDspd VSS51
195 195
VSS50 VSS50
3 M_A_RST# 30 190 3 M_B_RST# 30 190
RST# VSS49 RST# VSS49 C395 C397 R232
189 189
MEMHOT_MA# VSS48 MEMHOT_MB# VSS48
198 185 198 185 1K/F_4
EVENT# VSS47 EVENT# VSS47 0.1U/10V_4
184 184
VSS46 VSS46
+0.75VSMVREF_SUSA 1 179 +0.75VSMVREF_SUSB 1 179
VREF VSS45 oVREF VSS45 2.2u/6.3V_6
178 178
VSS44 C627 C631 VSS44
+VREF_CA_A 126 173 +VREF_CA_B 126 173
VrefCA VSS43 R431 VrefCA VSS43
172 172
VSS42 0.1U/10V_4 VSS42
+0.75V_DDR_VTT 203 168 1K/F_4 +0.75V_DDR_VTT 203 168
VTT1 VSS41 VTT1 VSS41
204 167 204 167
VTT2 VSS40 2.2u/6.3V_6 C265 VTT2 VSS40
162 162
C205 C589 C211 VSS39 C251 C258 VSS39
2 161 2 161
VSS0 VSS38 0.1u/10V_4 1000P/50V_4 VSS0 VSS38
3 156 3 156
VSS1 VSS37 *10u/6.3V_6 VSS1 VSS37
8 155 8 155
*10u/6.3V_6 0.1U/10V_4 1000P/50V_4 VSS2 VSS36 VSS2 VSS36
9 151 9 151
VSS3 VSS35 VSS3 VSS35
13 150 13 150
VSS4 VSS34 R97 2.2K/J_4 VSS4 VSS34
14 145 +1.5VSUS 14 145
19 144 19 144
20 139 20 139
2
VSS7 VSS31 R94 2.2K/J_4 Q6 VSS7 VSS31

25 138 +1.5VSUS 25 138
VSS8 VSS30 MMBT3904 VSS8 VSS30
26 134 26 134
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS9 VSS29 MEMHOT_MA# VSS9 VSS29
31 133 1 3 31 133
32 128 32 128
+1.5VSUS
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
A DDR3_SO-DIMM_H=8_1.5V_Standard
H=4 A
+SMDDR_VREF +VREF_CA_A
R161 DDR3_SO-DIMM_H=4_1.5V_Standard
*2K/F_4 R99 2.2K/J_4
H=8 +1.5VSUS
DIM2_SA0 R122 10K/F_4
+3V
2
R154 *Short_4
R370 10K/F_4 DIM1_SA0
+1.5VSUS R98 2.2K/J_4 Q7
MMBT3904
DIM2_SA1 R119 10K/F_4
PROJECT : ZQ2
C294 C289 R165 R372 10K/F_4 DIM1_SA1 MEMHOT_MB# 1 3 SMbus address A2
CPU_MEMHOT# 2,11
0.1U/10V_4 2.2u/6.3V_6 SMbus address A0 3,39 +SMDDR_VREF
*2K/F_4 Size Document Number Rev
2..4,6,36,39,41 +1.5VSUS
DDR2 SODIMMS: A/B CHANNEL 1A
2,4,9..15,19,23,24,26,28..33,35..42 +3V
39 +0.75V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
07
D D
Place these Caps near So-Dimm H=8.
+1.5VSUS
C326 C333 C344 C297 C317

10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1U/10V_4 0.1U/10V_4
C342
10u/6.3V_6
C313 C307 C337 C306 C345

10u/6.3V_6 10u/6.3V_6 *.1u/16V_4 *.1u/16V_4 *.1u/16V_4
Place these Caps near So-Dimm H=4.

C +1.5VSUS C
C340 C339 C341 C329 C325

10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1U/10V_4 0.1U/10V_4
C323
10u/6.3V_6
C315 C305 C324 C308 C346

10u/6.3V_6 10u/6.3V_6 *.1u/16V_4 *.1u/16V_4 *.1u/16V_4
B B
A A
PROJECT : ZQ2
DDR3 SODIMMS TERMINATIONS 1A

5 4 3 2 1
5 4 3 2 1
07
U22A
SIDE PORT HT_CADOUTP0 Y25 HT_RXCAD0P HT_TXCAD0P D24 HT_CADINP0 HT_CADOUTP[15..0]
HT_CADOUTP[15..0] 2
HT_CADOUTN0 Y24 PART 1 OF 6 D25 HT_CADINN0
HT_CADOUTP1 HT_RXCAD0N HT_TXCAD0N HT_CADINP1 HT_CADOUTN[15..0]
11/4 V22
HT_RXCAD1P HT_TXCAD1P
E24
HT_CADOUTN[15..0] 2
HT_CADOUTN1 V23 E25 HT_CADINN1
HT_CADOUTP2 HT_RXCAD1N HT_TXCAD1N HT_CADINP2 HT_CLKOUTP[1..0]
V25 F24
HT_CADOUTN2 HT_RXCAD2P HT_TXCAD2P HT_CADINN2 HT_CLKOUTP[1..0] 2
V24 F25
HT_CADOUTP3 HT_RXCAD2N HT_TXCAD2N HT_CADINP3 HT_CLKOUTN[1..0]
U24 F23
HT_CADOUTN3 HT_RXCAD3P HT_TXCAD3P HT_CADINN3 HT_CLKOUTN[1..0] 2
U25 F22
HT_CADOUTP4 HT_RXCAD3N HT_TXCAD3N HT_CADINP4 HT_CTLOUTP[1..0]
T25 HT_RXCAD4P HT_TXCAD4P H23 HT_CTLOUTP[1..0] 2
HT_CADOUTN4 T24 H22 HT_CADINN4
HT_CADOUTP5 HT_RXCAD4N HT_TXCAD4N HT_CADINP5 HT_CTLOUTN[1..0]
P22 J25
+1.5V_MEM_VDDQ +1.5V_MEM_VDDQ HT_CADOUTN5 HT_RXCAD5P HT_TXCAD5P HT_CADINN5 HT_CTLOUTN[1..0] 2
P23
HYPER TRANSPORT CPU I/F

J24
HT_CADOUTP6 HT_RXCAD5N HT_TXCAD5N HT_CADINP6 HT_CADINP[15..0]
P25 HT_RXCAD6P HT_TXCAD6P K24
D
HT_CADOUTN6 HT_CADINN6 HT_CADINP[15..0] 2 D
P24 K25
HT_CADOUTP7 HT_RXCAD6N HT_TXCAD6N HT_CADINP7 HT_CADINN[15..0]
N24 K23
HT_CADOUTN7 HT_RXCAD7P HT_TXCAD7P HT_CADINN7 HT_CADINN[15..0] 2
N25 K22
HT_RXCAD7N HT_TXCAD7N HT_CLKINP[1..0]
C823 R587 C821 R585 HT_CADOUTP8 HT_CADINP8 HT_CLKINP[1..0] 2
AC24 HT_RXCAD8P HT_TXCAD8P F21
SIDE@1K/F_4 SIDE@1K/F_4 HT_CADOUTN8 AC25 G21 HT_CADINN8 HT_CLKINN[1..0]
SIDE@0.1u/10V_4 SIDE@0.1u/10V_4 HT_CADOUTP9 HT_RXCAD8N HT_TXCAD8N HT_CADINP9 HT_CLKINN[1..0] 2
AB25 G20
HT_CADOUTN9 HT_RXCAD9P HT_TXCAD9P HT_CADINN9 HT_CTLINP[1..0]
AB24 HT_RXCAD9N HT_TXCAD9N H21
HT_CADOUTP10 HT_CADINP10 HT_CTLINP[1..0] 2
AA24 HT_RXCAD10P HT_TXCAD10P J20
SPM_VREFDQ SPM_VREFCA HT_CADOUTN10 AA25 J21 HT_CADINN10 HT_CTLINN[1..0]
HT_CADOUTP11 HT_RXCAD10N HT_TXCAD10N HT_CADINP11 HT_CTLINN[1..0] 2
Y22 J18
HT_CADOUTN11 HT_RXCAD11P HT_TXCAD11P HT_CADINN11
Y23 K17
C824 R588 C822 R586 HT_CADOUTP12 HT_RXCAD11N HT_TXCAD11N HT_CADINP12
W21 HT_RXCAD12P HT_TXCAD12P L19
SIDE@1K/F_4 SIDE@1K/F_4 HT_CADOUTN12 W20 J19 HT_CADINN12
HT_CADOUTP13 HT_RXCAD12N HT_TXCAD12N HT_CADINP13
SIDE@0.1u/10V_4 SIDE@0.1u/10V_4 V21 M19 signals RS880 RX880
HT_CADOUTN13 HT_RXCAD13P HT_TXCAD13P HT_CADINN13
V20 L18
U20 HT_RXCAD14P HT_TXCAD14P M21
HT_CADOUTN14 U21 P21 HT_CADINN14 HT_TXCALP
U19
HT_RXCAD15P HT_TXCAD15P
P18 Ra Ra
HT_CADOUTN15 U18 M18 HT_CADINN15 301 ohm 1% 1.21k ohm 1%
HT_RXCAD15N HT_TXCAD15N
HT_TXCALN
HT_CLKOUTP0 T22 H24 HT_CLKINP0
HT_CLKOUTN0 HT_RXCLK0P HT_TXCLK0P HT_CLKINN0
T23 H25
HT_CLKOUTP1 HT_RXCLK0N HT_TXCLK0N HT_CLKINP1
AB23
HT_RXCLK1P HT_TXCLK1P
L21 HT_RXCALP
HT_CLKOUTN1 AA22 L20 HT_CLKINN1 Rb Rb
U39 HT_RXCLK1N HT_TXCLK1N
301 ohm 1% 1.21k ohm 1%
HT_CTLOUTP0 M22 M24 HT_CTLINP0 HT_RXCALN
SPM_VREFCA M9 SPM_DQ2 HT_CTLOUTN0 HT_RXCTL0P HT_TXCTL0P HT_CTLINN0
E4 M23 M25
SPM_VREFDQ H2 VREFCA DQL0 SPM_DQ1 HT_CTLOUTP1 HT_RXCTL0N HT_TXCTL0N HT_CTLINP1
F8 R21 P19
VREFDQ DQL1 SPM_DQ5 HT_CTLOUTN1 HT_RXCTL1P HT_TXCTL1P HT_CTLINN1
C F3 Ra R20 R18 Rb C
SPM_A0 DQL2 SPM_DQ3 HT_RXCTL1N HT_TXCTL1N
N4 F9 RES CHIP 1.21K 1/16W +-1%(0402)
SPM_A1 A0 DQL3 SPM_DQ7 R398 301/F_4 HT_RXCALP HT_TXCALP R399 301/F_4
P8 A1 DQL4 H4 C23 HT_RXCALP HT_TXCALP B24 P/N : CS21212FB18
SPM_A2 P4 H9 SPM_DQ0 HT_RXCALN A24 B25 HT_TXCALN
SPM_A3 A2 DQL5 SPM_DQ4 HT_RXCALN HT_TXCALN
N3 G3
SPM_A4 A3 DQL6 SPM_DQ6 RS880/RX881
P9 A4 DQL7 H8
SPM_A5 P3
SPM_A6 A5
R9
SPM_A7 A6 SPM_DQ13
R3 D8
SPM_A8 A7 DQU0 SPM_DQ8
T9 C4
SPM_A9 R4
A8
A9
DQU1
DQU2 C9 SPM_DQ10 This block is for UMA only , Discrete can remove all component
SPM_A10 L8 C3 SPM_DQ12
SPM_A11 A10/AP DQU3 SPM_DQ15
R8 A8
SPM_A12 A11 DQU4 SPM_DQ11
N8 A12/BC DQU5 A3
SPM_A13 T4 B9 SPM_DQ14
A13 DQU6 SPM_DQ9
T8 A4
A14 DQU7
M8 A15 +1.5V_MEM_VDDQ
SPM_BA0 M3 B3
SPM_BA1 BA0 VDD#B3 U22D +1.5V_MEM_VDDQ
N9 D10
SPM_BA2 BA1 VDD#D10
M4
BA2 VDD#G8
G8 PAR 4 OF 6
K3 SPM_A0 AB12 AA18 SPM_DQ0
VDD#K3 SPM_A1 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) SPM_DQ1
K9 AE16 AA20
VDD#K9 SPM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) SPM_DQ2
N2 V11 AA19
SPM_CLKP VDD#N2 SPM_A3 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) SPM_DQ3
J8 CK VDD#N10 N10 AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
R593 *SIDE@100/F_4 SPM_CLKN K8 R2 SPM_A4 AA12 V17 SPM_DQ4 C819 R584
SPM_CKE CK VDD#R2 SPM_A5 MEM_A4(NC) MEM_DQ4(NC) SPM_DQ5
K10 R10 AB16 AA17 SIDE@1K/F_4
CKE VDD#R10 +1.5V_MEM_VDDQ SPM_A6 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) SPM_DQ6 SIDE@0.1u/10V_4
AB14 AA15
SPM_A7 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) SPM_DQ7
AD14 Y15
B
SPM_ODT SPM_A8 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) SPM_DQ8
B
K2 A2 AD13 AC20
SPM_CS# ODT VDDQ#A2 SPM_A9 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) SPM_DQ9 SPM_VREF1
L3 A9 AD15 AD19
CS VDDQ#A9 MEM_A9(NC) MEM_DQ9/DVO_D5(NC)
SBD_MEM/DVO_I/F
SPM_RAS# J4 C2 SPM_A10 AC16 AE22 SPM_DQ10
SPM_CAS# RAS VDDQ#C2 SPM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) SPM_DQ11
K4 CAS VDDQ#C10 C10 AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
SPM_WE# L4 D3 SPM_A12 AC14 AB20 SPM_DQ12 C820 R583
WE VDDQ#D3 SPM_A13 MEM_A12(NC) MEM_DQ12(NC) SPM_DQ13
E10 Y14 AD22 SP@1K/F_4
VDDQ#E10 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) SPM_DQ14 SIDE@0.1u/10V_4
VDDQ#F2 F2 MEM_DQ14/DVO_D10(NC) AC22
SPM_DQS0P F4 H3 SPM_BA0 AD16 AD21 SPM_DQ15
SPM_DQS1P DQSL VDDQ#H3 SPM_BA1 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC)
C8 H10 AE17
DQSU VDDQ#H10 SPM_BA2 MEM_BA1(NC) SPM_DQS0P
AD17 Y17
MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) SPM_DQS0N
W18
SPM_DM0 SPM_RAS# MEM_DQS0N/DVO_IDCKN(NC) SPM_DQS1P
E8 A10 W12 AD20
SPM_DM1 DML VSS#A10 SPM_CAS# MEM_RASb(NC) MEM_DQS1P(NC) SPM_DQS1N
D4 DMU VSS#B4 B4 Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
E2 SPM_WE# AD18 IOPLLVDD18 - memory PLL
VSS#E2 SPM_CS# MEM_WEb(NC) SPM_DM0
G9 AB13 W17 not applicable to RX881
+1.5V_MEM_VDDQ SPM_DQS0N VSS#G9 SPM_CKE MEM_CSb(NC) MEM_DM0(NC) SPM_DM1
G4 DQSL VSS#J3 J3 AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
SPM_DQS1N B8 J9 SPM_ODT V14
DQSU VSS#J9 MEM_ODT(NC) IOPLLVDD18_SIDE_PORT L75 SP@BLM18PG221SN1D(220_1.4A)_6+1.8V
M2 AE23 15mA
R592 SIDE@10K/F_4 VSS#M2 SPM_CLKP IOPLLVDD18(NC) IOPLLVDD_SIDE_PORT L76 SP@BLM18PG221SN1D(220_1.4A)_6+1.1V
VSS#M10
M10 V15
MEM_CKP(NC) IOPLLVDD(NC)
AE24 26mA
P2 SPM_CLKN W14
VSS#P2 MEM_CKN(NC)
12 SP_DDR3_RST# T3 P10 AD23
RESET VSS#P10 R590 SIDE@40.2/F_4 SPM_COMPP IOPLLVSS(NC) C818
T2 AE12
VMA_ZQ2 VSS#T2 SIDE@40.2/F_4 SPM_COMPN MEM_COMPP(NC) SPM_VREF1
L9
ZQ VSS#T10
T10 +1.5V_MEM_VDDQ R591 AD12
MEM_COMPN(NC) MEM_VREF(NC)
AE18 SIDE@2.2u/6.3V_6 W/I SP W/O SP
C817
SIDE@2.2u/6.3V_6 R583 1K 0
R594 B2 RS880/RX881
VSSQ#B2
SIDE@240/F_4 VSSQ#B10 B10 L75 Bead 0
D2 40 mil~50 mil
VSSQ#D2
VSSQ#D9
D9 L76 Bead 0
A E3 A
VSSQ#E3 +1.5V_MEM_VDDQ +1.5V
J2 E9
NC#J2 VSSQ#E9 SIDE@0.1u/10V_4 SIDE@1u/6.3V_4
L2 F10
NC#L2 VSSQ#F10 R589 SIDE@0_8
J10 NC#J10 VSSQ#G2 G2
L10 G10
NC#L10 VSSQ#G10 C825 C826 C830 C829 C828 C827
100-BALL
SDRAM DDR3 SIDE@10u/6.3V_6 PROJECT : ZQ2
SIDE@H5TQ1G63AFR-14C
SIDE@0.1u/10V_4 SIDE@10u/6.3V_6 SIDE@1u/6.3V_4 Quanta Computer Inc.
RS880M-HT LINK I/F 1/4 1A
9,10,15,31,36,41,42 +1.8V
2,8..10,14,37 +1.1V
5 4 3 2 1
5 4 3 2 1
D4
C4
A3
B3
C2
U22B
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
PART 2 OF 6
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
A5
B5
A4
B4
C3
TX2_HDMI+_C
TX2_HDMI-_C
TX1_HDMI+_C
TX1_HDMI-_C
TX0_HDMI+_C
C593
C590
C587
C584
C583
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
TX2_HDMI+
TX2_HDMI-
TX1_HDMI+
TX1_HDMI-
24
24
24
24
16 PEG_RXN[7:0]
16 PEG_RXP[7:0]
PEG_RXN[7:0]
PEG_RXP[7:0]
PEG_TXN[7:0]
PEG_TXP[7:0]
Close to North Bridge

PEG_TXN[7:0] 16
PEG_TXP[7:0] 16 08
C1
E5
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_TX2P
GFX_TX2N
GFX_TX3P
B2
D1
TX0_HDMI-_C
TXC_HDMI+_C
C580
C574
0.1U/10V_4
0.1U/10V_4
TX0_HDMI+
TX0_HDMI-
TXC_HDMI+
24
24
24
HDMI
F5 D2 TXC_HDMI-_C C576 0.1U/10V_4
GFX_RX3N GFX_TX3N TXC_HDMI- 24
G5 GFX_RX4P GFX_TX4P E2
G6 E1
GFX_RX4N GFX_TX4N
H5 F4
GFX_RX5P GFX_TX5P
H6 GFX_RX5N GFX_TX5N F3
D D
J6 F1
GFX_RX6P GFX_TX6P
J5 F2
GFX_RX6N GFX_TX6N
J7 H4
GFX_RX7P GFX_TX7P
J8 H3
GFX_RX7N GFX_TX7N
PCIE I/F GFX

PEG_RXP0 L5 H1 PEG_TXP0_C C552 SW@0.1U/10V_4 PEG_TXP0
PEG_RXN0 GFX_RX8P GFX_TX8P PEG_TXN0_C C551 SW@0.1U/10V_4 PEG_TXN0
L6 H2
PEG_RXP1 GFX_RX8N GFX_TX8N PEG_TXP1_C C554 SW@0.1U/10V_4 PEG_TXP1
M8 J2
L8 GFX_RX9N GFX_TX9N J1
PEG_RXP2 P7 K4 PEG_TXP2_C C556 SW@0.1U/10V_4 PEG_TXP2
M7 K3
P5 K1
M5 K2
PEG_RXP4
PEG_RXN4
R8
P8
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_TX11N
GFX_TX12P
GFX_TX12N
M4
M3
PEG_TXP4_C
PEG_TXN4_C
C562
C561
SW@0.1U/10V_4
SW@0.1U/10V_4
PEG_TXP4
PEG_TXN4
GPU
PEG_RXP5 R6 M1 PEG_TXP5_C C564 SW@0.1U/10V_4 PEG_TXP5
R5 M2
P4 GFX_RX14P GFX_TX14P N2
PEG_RXN6 P3 N1 PEG_TXN6_C C565 SW@0.1U/10V_4 PEG_TXN6
T4 P1
T3 P2
GFX_RX15N GFX_TX15N
AE3 AC1 PCIE_TXP0_C C570 0.1U/10V_4
25 PCIE_RX1+ GPP_RX0P GPP_TX0P PCIE_TX1+ 25
AD4 AC2 PCIE_TXN0_C C569 0.1U/10V_4
25 PCIE_RX1-
AE2
GPP_RX0N
GPP_RX1P
GPP_TX0N
GPP_TX1P
AB4
PCIE_TX1- 25 To LAN
AD3 AB3
GPP_RX1N GPP_TX1N PCIE_TXP2_C C557 0.1U/10V_4
AD1 AA2
26
26
PCIE_RXP2
PCIE_RXN2 AD2
GPP_RX2P
GPP_RX2N PCIE I/F GPP
GPP_TX2P
GPP_TX2N
AA1 PCIE_TXN2_C C558 0.1U/10V_4
PCIE_TXP2 26
PCIE_TXN2 26
TO WLAN-2
V5 Y1
GPP_RX3P GPP_TX3P
W6 Y2
GPP_RX3N GPP_TX3N
U5 GPP_RX4P GPP_TX4P Y4
C C
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 V2
GPP_RX5N GPP_TX5N
AA8 AD7 A_TXP0_C C594 0.1U/10V_4
11 A_RXP0 SB_RX0P SB_TX0P A_TXP0 11
Y8 AE7 A_TXN0_C C591 0.1U/10V_4 A_TXN0 11
11 A_RXN0 SB_RX0N SB_TX0N
AA7 AE6 A_TXP1_C C585 0.1U/10V_4
11 A_RXP1 SB_RX1P SB_TX1P A_TXP1 11
Y7 AD6 A_TXN1_C C588 0.1U/10V_4
11
11
11
A_RXN1
A_RXP2
A_RXN2
AA5
AA6
SB_RX1N
SB_RX2P
SB_RX2N
PCIE I/F SB
SB_TX1N
SB_TX2P
SB_TX2N
AB6
AC6
A_TXP2_C
A_TXN2_C
C579
C582
0.1U/10V_4
0.1U/10V_4
A_TXN1
A_TXP2
A_TXN2
11
11
11
SB
W5 AD5 A_TXP3_C C572 0.1U/10V_4 A_TXP3 11
11 A_RXP3 SB_RX3P SB_TX3P
Y5 AE5 A_TXN3_C C575 0.1U/10V_4
11 A_RXN3 SB_RX3N SB_TX3N A_TXN3 11
AC8 NB_PCIECALRP R388 1.27K/F_4
PCE_CALRP(PCE_BCALRP) NB_PCIECALRN R389 2K/F_4
AB8 +1.1V
PCE_CALRN(PCE_BCALRN)
RS880/RX881
RS880 Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3

B DP0 B
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7

DP1
AUX1 and HPD1
A A
PROJECT : ZQ2
RS880M-PCIE I/F 2/4 1A
2,7,9,10,14,37 +1.1V
5 4 3 2 1
5 4 3 2 1
09
All RS880 variants do not support analog TV-out
functionality. As such, Y, C_Pr, and COMP_Pb U22C
+3V_AVDD_NB F12 A22
For Check list JTAG E12
AVDD1(NC)
AVDD2(NC) PART 3 OF 6
TXOUT_L0P(NC)
TXOUT_L0N(NC)
B22
LA_DATAP0
LA_DATAN0
23
23
+1.8V_AVDDDI_NB F14 A21 LA_DATAP1 23
R130 *4.7K_4 NB_PWRGD_IN AVDDDI(NC) TXOUT_L1P(NC)
G15 B21 LA_DATAN1 23
R115 *4.7K_4 INT_EDIDDATA +1.8V_AVDDQ_NB AVSSDI(NC) TXOUT_L1N(NC)
+3V H15 AVDDQ(NC) TXOUT_L2P(NC) B20 LA_DATAP2 23
R118 *4.7K_4 INT_EDIDCLK H14 A20 LA_DATAN2 23
R107 *4.7K_4 HDMI_DDC_DATA AVSSQ(NC) TXOUT_L2N(DBG_GPIO0)
+3V A19
TXOUT_L3P(NC)
E17 B19
CRT/TVOUT
C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
F17
Y(DFT_GPIO2)
F15 B18
COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC)
A18
TXOUT_U0N(NC)
23 INT_CRT_RED G18 A17
R394 140/F_4 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
G17 B17
REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2)
23 INT_CRT_GRE E18 D20
R395 150/F_4 GREEN(DFT_GPIO1) TXOUT_U2P(NC)
D F18 D21 D
GREENb(NC) TXOUT_U2N(NC)
23 INT_CRT_BLU E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
R396 150/F_4 F19 D19
BLUEb(NC) TXOUT_U3N(NC)
23 INT_CRT_HSYNC INT_CRT_HSYNC A11 B16 LA_CLK 23

INT_CRT_VSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
23 INT_CRT_VSYNC B11 A16 LA_CLK# 23
DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
23 INT_DDCDATA E8 DAC_SDA(PCE_TCALRN) TXCLK_UP(PCIE_RESET_GPIO4) D16
23 INT_DDCCLK F8 D17
DAC_SCL(PCE_RCALRN) TXCLK_UN(PCIE_RESET_GPIO1)
VGA R140 715/F_6 DAC_RSET_NB G14
DAC_RSET(PWM_GPIO1) +1.8V_VDDLTP18_NB
VDDLTP18(NC) A13 15mA
+1.1V_PLLVDD A12 B13
+1.8V_PLLVDD18 PLLVDD(NC) VSSLTP18(NC)
D14
LVTM
PLLVDD18(NC) +1.8V_VDDLT_18_NB
B12 A15 300mA
PLL PWR
PLLVSS(NC) VDDLT18_1(NC)
B15
+1.8V_VDDA18HTPLL VDDLT18_2(NC)
20mA H17 VDDA18HTPLL VDDLT33_1(NC) A14
B14
+1.8V_VDDA18PCIEPLL VDDLT33_2(NC)
120mA D7
VDDA18PCIEPLL1
E7 C14
VDDA18PCIEPLL2 VSSLT1(VSS)
D15
VSSLT2(VSS)
11,33 A_RST#_SB D8 C16
SYSRESETb VSSLT3(VSS)
12,15 NB_PWRGD_IN A10 C18
NB_LDT_STOP# POWERGOOD VSSLT4(VSS)
C10 C20
PM
NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS)
C12 E20
ALLOW_LDTSTOP VSSLT6(VSS)
C22
VSSLT7(VSS)
11 CLK_NB_HTREFP_PR C25
HT_REFCLKP
11 CLK_NB_HTREFN_PR C24 HT_REFCLKN
CLK_NB_REF_CLKP E11
11 CLK_NB_REF_CLKP REFCLK_P/OSCIN(OSCIN)
CLOCKs
CLK_NB_REF_CLKN F11 E9
11 CLK_NB_REF_CLKN REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) INT_LVDS_DIGON 23
F7 INT_DPST_PWM 23
R101 4.7K_4 NBGFX_CLKP LVDS_BLON(PCE_RCALRP)
T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12 INT_LVDS_BLON 23
R96 4.7K_4 NBGFX_CLKN T1
GFX_REFCLKN
For A11 version T73
GPP_REFCLKP U1
GPP_REFCLKP
C B18 GPP_REFCLKN U2 C
T72 GPP_REFCLKN
R108 *SP@49.9/F_4 CLK_SBLINKP
R105 *SP@49.9/F_4 CLK_SBLINKN V4
11 CLK_SBLINKP GPPSB_REFCLKP(SB_REFCLKP)
11 CLK_SBLINKN V3 GPPSB_REFCLKN(SB_REFCLKN)
23 INT_EDIDDATA A9 I2C_DATA
B9 D9
23 INT_EDIDCLK
B8
I2C_CLK MIS. TMDS_HPD(NC)
D10
INT_HDMI_HPD 24
24 HDMI_DDC_DATA DDC_DATA/AUX0N(NC) HPD(NC)
24 HDMI_DDC_CLK A8
DDC_CLK/AUX0P(NC) SUS_STAT#_NB R79 *Short_4
B7 D12 SUS_STAT# 12
AUX1P(NC) TVCLKIN(PWM_GPIO5)
DDC_DATA & DDC_CLK Not applicable to RX881 A7
AUX1N(NC)
THERMALDIODE_P AE8
+NB_CORE_ON B10 AD8 R80
38 +NB_CORE_ON STRP_DATA THERMALDIODE_N
*3K/J_4
G11 D13 TEST_EN
RSVD TESTMODE
RS880_AUX_CAL C8 R137
T74 AUX_CAL(NC) 1.8K/F_4
2,7,8,10,14,37 +1.1V
7,10,15,31,36,41,42 +1.8V RS880/RX881
2,4,5,10..15,19,23,24,26,28..33,35..42 +3V
RS880M --- ADD

L19 +3V_AVDD_NB L63 +1.1V_PLLVDD
STRAP_DEBUG_BUS_GPIO_ENABLEb +3V
BLM18PG221SN1D(220_1.4A)_6
+1.1V
BLM18PG221SN1D(220_1.4A)_6
1
AVDD-DAC Analog PLLVDD - Graphics PLL

C208 C539 C600 +1.8V
Enables the Test Debug Bus using GPIO. not applicable to RX780 not applicable to
2.2U/6.3V_6 1u/6.3V_4 2.2U/6.3V_6
RX780
2
RS880M L25 +1.8V_VDDLTP18_NB

INT_CRT_VSYNC R391 3K_4 +3V BLM18PG221SN1D(220_1.4A)_6
1 Disable V C242 VDDLTP18 - LVDS or DVI/HDMI PLL
0 Enable 2.2U/6.3V_6 not applicable to RX780
+1.8V
B B
R148 *Short_6 +1.8V_AVDDDI_NB

BLM21PG221SN1D(220,100M,2A)_8
AVDDI-DAC Digital +1.8V_VDDLT_18_NB
C278 not applicable to RX780 L30
0.1U/10V_4 +1.8V C268 C266 VDDLT18 - LVDS or DVI/HDMI
RS880M: Enables Side port memory L27 +1.8V_PLLVDD18 4.7U/6.3V_6 0.1U/10V_4
digital
BLM18PG221SN1D(220_1.4A)_6
not applicable to RX780
RS880M:INT_CRT_HSYNC PLLVDD18 - Graphics PLL
L18 +1.8V_AVDDQ_NB not applicable to RX780
BLM18PG221SN1D(220_1.4A)_6
Selects if Memory SIDE PORT is available or not AVDDQ-DAC Bandgap Reference C250 C248
1 = Memory Side port Not available C209 not applicable to RX780 *10U/6.3V_8 4.7U/6.3V_6
2.2U/6.3V_6
0 = Memory Side port available
Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]
for B
INT_CRT_HSYNC R392 *SP@3K_4 +3V +1.8V +1.8V
R393 SIDE@3K_4 VDDA18PCIEPLL -PCIE PLL

20mils width +1.8V DDR3 based CPU : Level shifted to 1.8 V on the
9/16 need modify PN Northbridge side using an open-drain buffer and
L23 +1.8V_VDDA18PCIEPLL R81 pulled up to 1.8V_S0 through a 2.2k Ohm 5% resistor
2.2K/J_4 on the Northbridge side.
5
BLM18PG221SN1D _6 + U5
C228 2 Open 4 NB_LDT_STOP#

2,11 CPU_LDT_STOP# Drain
2.2U/6.3V_6
- 74LVC07
3
For extrnal EEPROM Debug only

RS780/RX780/RS880
A
+NB_CORE_ON R390 2K/F_4

VDDA18HTPLL -HT LINK PLL 20mils width R132 1K/F_4
A
+1.8V
L28 +1.8V_VDDA18HTPLL
R123 *0_4 NB_ALLOW_LDTSTOP
2 CPU_LDT_REQ#
BLM18PG221SN1D _6 for B
C260 R129 *Short_4 EC-E
11 ALLOW_LDTSTOP
Display Port interface from PCIeGraphics (RS880/rs880M only) 2.2U/6.3V_6
The RS880 family does not support CLMC architecture PROJECT : ZQ2
RS880_AUX_CAL R387 *150/F_4 The LDTREQ# connection from the CPU to
Check----> no need DP ALLOW_LDTSTOP of the Northbridge is no longer Quanta Computer Inc.
required.
RS880M-SYSTEM I/F 3/4 1A

5 4 3 2 1
5 4 3 2 1
10
AE14
AC3
AC4
M11
AA4
AB5
AB1
AB7
AE1
AE4
AB2
D11
E14
E15
K14
L15
J15
J12
W1
W2
W4
W7
W8
M6
G1
G2
G4
G8
D3
D5
H7
R7
N4
R1
R2
R4
U4
A2
B1
E4
P6
V7
V8
V6
Y6
L1
L2
L4
L7
J4
U22F
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
D D
PART 6/6
GROUND
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
+1.1V
C +1.1V 2A for RS880M VDDPCIE - PCIE-E Main power C
0.6A L26 *Short_8 +1.1V_VDDHT

U22E
+1.1V_VDD_PCIE
2.5A R134 *Short_8
J17 VDDHT_1 VDDPCIE_1 A6 +1.1V
K16
VDDHT_2 PART 5/6 VDDPCIE_2
B6
L16 C6
C252 C255 C256 C259 VDDHT_3 VDDPCIE_3 C219 C235 C237 C232 C233
M16 VDDHT_4 VDDPCIE_4 D6
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 P16 E6 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 4.7U/6.3V_6
VDDHT_5 VDDPCIE_5
R16 F6
VDDHT_6 VDDPCIE_6
T16 G7
VDDHT_7 VDDPCIE_7
H8
0.7A L34 *Short_8 +1.1V_VDDHTRX H18
G19
VDDHTRX_1
VDDPCIE_8
VDDPCIE_9 J9
K9
VDDHTRX_2 VDDPCIE_10
F20 M9
C274 C270 C280 C279 VDDHTRX_3 VDDPCIE_11
E21 VDDHTRX_4 VDDPCIE_12 L9
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 D22 P9
B23 R9
+1.1V 2A for RS880M A23
T9
V9
+1.1V L32 *Short_6 0.4A +1.1V_VDDHTTX AE25
AD24
VDDHTTX_1
VDDPCIE_16
VDDPCIE_17
U9
0.95~1.1V@10A VDDC - Core Logic power
VDDHTTX_2
AC23 K12 NB_CORE
C264 C262 C269 C263 C272 VDDHTTX_3 VDDC_1
AB22 J14
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHTTX_4 VDDC_2
AA21 U16
VDDHTTX_5 VDDC_3 C249 C246 C247 C244 C257
Y20 J11
VDDHTTX_6 VDDC_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8
W19 K15
POWER
VDDHTTX_7 VDDC_5
V18 VDDHTTX_8 VDDC_6 M12
U17 L14
VDDHTTX_9 VDDC_7
T17 L11
VDDHTTX_10 VDDC_8
R17 M13
VDDHTTX_11 VDDC_9
P17 M15
B +1.8V 1A for RS780M+SB700 M17
VDDHTTX_12
VDDHTTX_13
VDDC_10
VDDC_11
N12
B
N14
+1.8V L24 0.7A +1.8V_VDDA18PCIE J10
VDDA18PCIE_1
VDDC_12
VDDC_13
P11 C253
0.1U/10V_4
C245
0.1U/10V_4
C243
0.1U/10V_4
C254
10U/6.3V_8
P10 VDDA18PCIE_2 VDDC_14 P13
BLM21PG221SN1D(220,100M,2A)_8 K10 P14
C240 C239 C236 C238 C231 C241 VDDA18PCIE_3 VDDC_15
M10 R12
4.7U/6.3V_6 4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDA18PCIE_4 VDDC_16
L10 VDDA18PCIE_5 VDDC_17 R15
W9 VDDA18PCIE_6 VDDC_18 T11 W/I SP W/O SP
H9
VDDA18PCIE_7 VDDC_19
T15 B01
T10
U12 C832 0.1U 0
R10 T14
Y9 J16
R138 *Short_6 25mA +1.8V_VDDG18_NB

AA9
VDDA18PCIE_10
VDDA18PCIE_11
VDDC_22
100mA L77
SIDE@0_8
+1.8V AB9 AE10 +1.5V
VDDA18PCIE_12 VDD_MEM1(NC)
AD9 AA11
VDDA18PCIE_13 VDD_MEM2(NC) C832 C833 C835 C836 C834
VDD18-RS880 I/O Transform AE9
U10
VDDA18PCIE_14 VDD_MEM3(NC) Y11
AD10
Ra SIDE@0.1U/10V_4 SIDE@0.1U/10V_4
C234 VDDA18PCIE_15 VDD_MEM4(NC) SP@0.1U/10V_4 SIDE@0.1U/10V_4 SIDE@4.7U/6.3V_6
AB10
1U/10V_4 VDD_MEM5(NC)
F9 AC10
VDDG18_1(VDD18_1) VDD_MEM6(NC) RS880
G9 VDDG18_2(VDD18_2)
AE11 H11 +3V_VDDG33 R106 *Short_4 DIS remove L77 ,
VDD18_MEM1(NC) VDDG33_1(NC) +3V
R146 SIDE@0_6 +1.8V_VDD18_MEM
+1.8V
C831
AD11
VDD18_MEM2(NC)
RS880/RX881
VDDG33_2(NC)
H12
C216
0.1U/10V_4
C215
0.1U/10V_4
60mA 3.3V(0.03A) add Ra(C832) as ohm to GND
VDD18_MEM For UMA RS880 only VDD33 - 3.3V I/O
SP@1U/10V_4
Not applicable to RX780 Not applicable to RX780
memory I/O transform
A A
PROJECT : ZQ2
31,38 NB_CORE
2,7..9,14,37 +1.1V
RS880M-POWER4/4 1A
7,9,15,31,36,41,42 +1.8V
2,4,5,9,11..15,19,23,24,26,28..33,35..42 +3V
5 4 3 2 1
5 4 3 2 1
26,29 PCIE_RST#
C730 180P/50V_4
R530 33/J_4 PCIE_RST#_SB

A_RST#_SB
P1
U29A
PCIE_RST#
SB800 Part 1 of 5
PCICLK0
W2 PCI_CLK0
PCI_CLK1 T107
+3V_S5
11
For AMD RST
NB, EC L1 W1
PCI CLKS
9,33 A_RST#_SB A_RST# PCICLK1/GPO36 PCI_CLK1 15
W3 PCI_CLK2 C492 0.1u/10V_4
PCICLK2/GPO37 PCI_CLK2 15
8 A_RXP0 C651 0.1U/10V_4 A_RX0P_C AD26 W4 PCI_CLK3 PCI_CLK3 15
A_TX0P PCICLK3/GPO38
5
C652 0.1U/10V_4 A_RX0N_C AD27 Y1 PCI_CLK4 R310
8 A_RXN0 A_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 15
8 A_RXP1 C641 0.1U/10V_4 A_RX1P_C AC28 33/J_4 2 A_RST#_SB
C642 0.1U/10V_4 A_RX1N_C A_TX1P A_RST#_AND
8 A_RXN1 AC29 V2 16,25,26 A_RST# 4
C645 0.1U/10V_4 A_RX2P_C A_TX1N PCIRST#
D 8 A_RXP2 AB29 A_TX2P 1 SB_GPIO_PCIE_RST# 12 D
8 A_RXN2 C646 0.1U/10V_4 A_RX2N_C AB28 GPU C493
A_TX2N
BALL OF SB820
C653 0.1U/10V_4 A_RX3P_C AB26 AA1 MINI-PCIE U14

8 A_RXP3
VERY CLOSE TO
3
A_TX3P AD0/GPIO0
To RS880
8 A_RXN3 C654 0.1U/10V_4 A_RX3N_C AB27 AA4 10p/50V_4 TC7SH08FU

A_TX3N AD1/GPIO1 Card reader
PLACE CAPS
AA3
A_TXP0 AD2/GPIO2
8 A_TXP0 AE24 A_RX0P AD3/GPIO3 AB1
A_TXN0 AE23 AA5 R308 *0_4
8 A_TXN0 A_RX0N AD4/GPIO4
PCI EXPRESS INTERFACES

A_TXP1 AD25 AB2
8 A_TXP1 A_RX1P AD5/GPIO5
A_TXN1 AD24 AB6
8 A_TXN1 A_TXP2 A_RX1N AD6/GPIO6 T111
8 A_TXP2 AC24 A_RX2P AD7/GPIO7 AB5
A_TXN2 AC25 AA6
8 A_TXN2 A_RX2N AD8/GPIO8 +AVBAT
A_TXP3
8 A_TXP3
A_TXN3
AB25
AB24
A_RX3P AD9/GPIO9
AC2
AC3 BOARD_ID0
For RTC
8 A_TXN3 A_RX3N AD10/GPIO10
AC4 BOARD_ID1
BOARD_ID0
BOARD_ID1
13
13
20MIL R441 499/F_4
R458 590/F_4 PCIE_CALRP_SB AD11/GPIO11 BOARD_ID2
AD29 AC1
+1.1V_PCIE_VDDR R244 2K/F_4 PCIE_CALRN_SB AD28
PCIE_CALRP AD12/GPIO12
AD1 BOARD_ID3
BOARD_ID2
BOARD_ID3
13
13 C636 20MIL
PCIE_CALRN AD13/GPIO13 BOARD_ID4 R436 10/J_4 +3VRTC_1
AD2 BOARD_ID4 13
AD14/GPIO14 1U/10V_4
AA28 AC6
AA29
GPP_TX0P AD15/GPIO15
AE2 20MIL D19
GPP_TX0N AD16/GPIO16 +3VRTC RB500V-40
Y29 AE1 T110 +3VPCU
Y28 AF8
GPP_TX1N AD18/GPIO18 D18
Y26 GPP_TX2P AD19/GPIO19 AE3
Y27 GPP_TX2N AD20/GPIO20 AF1 Change from 0ohm to 1K RB500V-40
W28 AG1 for safty issue
W29 AF2
GPP_TX3N AD22/GPIO22 R438 +VCCRTC_2
AE9 AD23 15 2 1
AD23/GPIO23 1K/F_4
AA22 AD9
Y21
GPP_RX0P AD24/GPIO24
AC11 AD25 15
AD24 15 20MIL 20MIL
GPP_RX0N AD25/GPIO25 R284 *Short_4 +BAT
AA25 AF6 AD26 15 VDDR_1.05_EN 13
GPP_RX1P AD26/GPIO26
AA24 AF4 AD27 15
GPP_RX1N AD27/GPIO27
C W23 GPP_RX2P AD28/GPIO28 AF3 EC-E C
1
V24 AH2 SB820_MEMHOT# BAT1
GPP_RX2N AD29/GPIO29 +3V +3V
W24 GPP_RX3P AD30/GPIO30 AG2
W25 AH3 BAT_CONN
GPP_RX3N AD31/GPIO31
PCI INTERFACE
AA8
2
CBE0#
CBE1# AD5
AD8 R538
CBE2# R523
AA10 *2.2K/J_4
CBE3#
AE8 2.2K/J_4
FRAME#
AB9
DEVSEL#
2
CLK_SBLINKP M23 AJ3 Q34
9 CLK_SBLINKP PCIE_RCLKP/NB_LNK_CLKP IRDY#
9 CLK_SBLINKN CLK_SBLINKN P23 AE7 RTC_X1
PCIE_RCLKN/NB_LNK_CLKN TRDY#
AC5 1 3 CPU_MEMHOT# 2,5 Y8
CLK_NB_REF_CLKP PAR
9 CLK_NB_REF_CLKP U29 NB_DISP_CLKP STOP# AF5
CLK_NB_REF_CLKN U28 AE6 *MMBT3904 3 2
9 CLK_NB_REF_CLKN NB_DISP_CLKN PERR#
AE4
CLK_NB_HTREFP_PR SERR#
9 CLK_NB_HTREFP_PR T26 NB_HT_CLKP REQ0# AE11
CLK_NB_HTREFN_PR T27 AH5
9 CLK_NB_HTREFN_PR NB_HT_CLKN REQ1#/GPIO40 T109
AH4 4 1 RTC_X2
CLK_CPU_BCLKP_PR REQ2#/CLK_REQ8#/GPIO41 R520
2 CLK_CPU_BCLKP_PR V21 CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 AC12 T66
CLK_CPU_BCLKN_PR T21 AD12
2 CLK_CPU_BCLKN_PR CPU_HT_CLKN GNT0# +3V 32.768KHZ
AJ5 R422 *10K_4
GNT1#/GPO44 PCH_ODD_EN 27
RP4 4 3 SW@0X2 SLT_GFX_CLKP V23 AH6 *20M/J_6 R518 20M/J_6
16 CLK_PCIE_VGAP SLT_GFX_CLKP GNT2#/GPO45 dGPU_VRON 19
16 CLK_PCIE_VGAN 2 INT 1 SLT_GFX_CLKN T23
SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46
AB12 T56
AB11 CLKRUN#_R R274 *Short_4
UMA Don't stuff 25 CLK_PCIE_LOM
CLK_PCIE_LOM L29
CLKRUN#
AD7
CLKRUN# 33
C728 C727
GPP_CLK0P LOCK# T65
25 CLK_PCIE_LOM# CLK_PCIE_LOM# L28 18P/50V_4 18P/50V_4
GPP_CLK0N
AJ6 dGPU_PWROK 19
INTE#/GPIO32
N29 AG6
GPP_CLK1P INTF#/GPIO33
N28 AG4
B GPP_CLK1N INTG#/GPIO34 B
AJ4 dGPU_RST_GPIO 16
CLK_PCIE_WLANP_2 INTH#/GPIO35
M29
26 CLK_PCIE_WLANP_2
26 CLK_PCIE_WLANN_2
CLK_PCIE_WLANN_2 M28
GPP_CLK2P
GPP_CLK2N
For STRAPS
CLOCK GENERATOR
LPC_CLK0 15
T25 GPP_CLK3P LPC_CLK1 15
V25 H24 LPC_CLK0 R478 22/J_4
GPP_CLK3N LPCCLK0 PCLK_DEBUG 26
H25 LPC_CLK1 R473 22/J_4
LPCCLK1 CLK_PCI_775 33
L24 GPP_CLK4P LAD0 J27 LPC_LAD0 26,33
L23 J26 C667
GPP_CLK4N LAD1 LPC_LAD1 26,33
H29 C676 for EMI
LPC
LAD2 LPC_LAD2 26,33

P25 H28 *5.6P/50V_4 *22P/50V_4 suggestion
GPP_CLK5P LAD3 LPC_LAD3 26,33
M25 G28 LPC_LFRAME# 26,33
GPP_CLK5N LFRAME# LDRQ0#_SB
LDRQ0# J25 T49
P29 AA18 LDRQ1#_SB
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 T53
P28 AB19 IRQ_SERIRQ 33
GPP_CLK6N SERIRQ/GPIO48
N26
GPP_CLK7P
N27
GPP_CLK7N *10K/F_4 R247
G21 ALLOW_LDTSTOP 9 +3V_S5
ALLOW_LDTSTP/DMA_ACTIVE#
T29 GPP_CLK8P PROCHOT# H21 CPU_PROCHOT# 2
T28 K19
CPU
GPP_CLK8N LDT_PG CPU_PWRGD 2

G22 CPU_LDT_STOP# 2,9
LDT_STP#
J24 CPU_LDT_RST# 2
CLK_14M_VGA LDT_RST#
16 CLK_14M_VGA L25 14M_25M_48M_OSC
C1 RTC_X1
32K_X1 INTRUDER_ALERT# Left not connected
C423 27P/50V_4 25M_X1 L26 C2 RTC_X2 +AVBAT
25M_X1 32K_X2 (Southbridge has 50-kohm internal
RTC
pull-up to VBAT).
A D2 RTC_CLK 33
A
RTCCLK
2
B2 INTRUDER_ALERT# R517
25MHz R240 25M_X2 INTRUDER_ALERT# *1M/F_4
L27 B1 +AVBAT
Y5 1M/J_4 25M_X2 VDDBT_RTC_G
1
G1
1
SB800 A11 *SHORT_ PAD1 C726
C421 27P/50V_4 IC CTRL(528P) SB710 A14(218-0660017)

0.1U/10V_4 PROJECT : ZQ2
2
P/N : AJ066000T01
12..15,25,30,31,35 +3V_S5
SB820-PCIE/PCI/CPU/LPC 1/4 1A
14 +1.1V_PCIE_VDDR
2,4,5,9,10,12..15,19,23,24,26,28..33,35..42 +3V
5 4 3 2 1
5 4 3 2 1
+3V_S5
R514
R313
NC only ,Can't be install
*2.2K/J_4
*2.2K/J_4
SB_TEST0
SB_TEST1
11,13..15,25,30,31,35
2,4,5,9..11,13..15,19,23,24,26,28..33,35..42
U29D
+3V_S5
+3V
USBCLK/41M_25M_48M_OSC pin is CLK input
pin when EXT CLKGEN mode.
It is output CLK source when INT CLKGEN mode.
12
J2 A10 USB_14_48M
T69 PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC T83
R305 *2.2K/J_4 SB_TEST2 K1 RI#/GEVENT22# USB_RCOMP_SB R270 11.8K/F_6
D3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP G19
33 SUSB# F1
SUSC# SLP_S3#
33 SUSC# H1
ACPI / WAKE UP EVENTS

SLP_S5#
F2
USB 1.1 USB MISC

D 33 DNBSWON# PWR_BTN# D
+3V SCL0/SDATA0is 3V tolerance Clock gen/Robson/TV
15 SB_PWRGD_IN H5
G6
PWR_GOOD SB800 J10
9 SUS_STAT# SUS_STAT# USB_FSD1P/GPIO186
AMD datasheet define it tuner SB_TEST0 B3 Part 4 of 5 H11
SB_TEST1 TEST0 USB_FSD1N
/DDR2/DDR2 C4
R249 2.2K/J_4 PCLK_SMB SB_TEST2 TEST1/TMS USB_FDS12P
F6 TEST2 USB_FSD0P/GPIO185 H9 T62
thermal/Accelerometer AD21 J8 USB_FSD12N
33 SIO_A20GATE GA20IN/GEVENT0# USB_FSD0N T58
R246 2.2K/J_4 PDAT_SMB SIO_RCIN# AE21
33 SIO_RCIN# KBRST#/GEVENT1#
LANLINK_STATE# K2 B12
T105 LPC_PME#/GEVENT3# USB_HSD13P USBP13+ 23
33 SIO_EXT_SMI# J29 LPC_SMI#/GEVENT23# USB_HSD13N A12 USBP13- 23 CAMERA EC-C
33 SIO_EXT_SCI# H2
SYS_RST# GEVENT5#
T108 J1 F11 USBP12+ 30
SYS_RESET#/GEVENT19# USB_HSD12P
+3V_S5 25,26 PCIE_WAKE# H6
WAKE#/GEVENT8# USB_HSD12N
E11 USBP12- 30 USBX3 board
SCL1/SDATA1 is 3V/S5 tolerance IR_RX1 F3
T106 SB_THERMTRIP# IR_RX1/GEVENT20#
AMD datasheet define it R295 *Short_4 J6 E14
2 CPU_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P USBP11+ 30
9,15 NB_PWRGD_IN AC19
NB_PWRGD USB_HSD11N
E12 USBP11- 30 USBX3 board
R287 10K_4 SB_SMBCLK1
R306 10K_4 SB_SMBDATA1 G1 J12
33 ICH_RSMRST# RSMRST# USB_HSD10P USBP10+ 29
USB_HSD10N
J14 USBP10- 29 Card reader EC-C
AD19
+3V_S5 CLK_REQ4#/SATA_IS0#/GPIO64
SCL2/SDATA2 is 3V/S5 tolerance AA16 A13 USBP9+ 30
SB_GPIO_PCIE_RST# CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P
AMD datasheet define it 11 SB_GPIO_PCIE_RST# AB21 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N B13 USBP9- 30 BLUETOOTH
25 CLK_PCIE_LAN_REQ# AC18 CLK_REQ0#/SATA_IS3#/GPIO60
R252 10K_4 SB_SCLK2 AF20 D13
SB_SDATA2 19 dGPU_PWR_EN SB_GPIO59 SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P USBP8+ 30
R248 10K_4
T51 AE19
SATA_IS5#/FANIN3/GPIO59 USB_HSD8N
C13 USBP8- 30 USBX3 board EC-C
28 SPKR AF19
PCLK_SMB SPKR/GPIO66
AD22 G12
USB 2.0
5,25,26 PCLK_SMB SCL0/GPIO43 USB_HSD7P
PDAT_SMB AE22 G14
5,25,26 PDAT_SMB SDA0/GPIO47 USB_HSD7N
SB_SMBCLK1 F5
+3V SB_SMBDATA1 SCL1/GPIO227
F4 G16
SDA1/GPIO228 USB_HSD6P
C
26 CLK_PCIE_2_REQ# AH21 CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N G18 C
R427 VGA_REQ#_GPIO61
*Short_4 AB18
17 VGA_REQ# CLK_REQ1#/FANOUT4/GPIO61
R296 4.7K/J_4 SUS_STAT# E1 D16
GPIO
IR_LED#/LLB#/GPIO184 USB_HSD5P
EC-E AJ21
SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N
C16 EC-C
7 SP_DDR3_RST# H4
DDR3_RST#/GEVENT7#
D5 GBE_LED0/GPIO183 USB_HSD4P B14 USBP4+ 26
D7
GBE_LED1/GEVENT9# USB_HSD4N
A14 USBP4- 26 WLAN Min-Card
G5
GBE_LED2/GEVENT10#
11/04 need check E_SB_OSC
K3
AA20
GBE_STAT0/GEVENT11# USB_HSD3P
E18
E16
T118 CLK_REQG#/GPIO65/OSCIN USB_HSD3N
J16
USB_HSD2P
30 OC_7# H3 J18
BLINK/USB_OC7#/GEVENT18# USB_HSD2N
30 OC_6# D1 USB_OC6#/IR_TX1/GEVENT6#
E4 B17
USB OC
2,4,32 PM_THERM# USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P T55
30 OC_4# D4 A17 T54
SB_JTAG_TDO USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N
E8 USB_OC3#/AC_PRES/TDO/GEVENT15#
SB_JTAG_TCK F7 A16
USB_OC2#/TCK/GEVENT14# USB_HSD0P USBP0+ 30
SB_JTAG_TDI E7 B16 On Board USB Connector
SB_JTAG_RST# USB_OC1#/TDI/GEVENT13# USB_HSD0N USBP0- 30
F8 USB_OC0#/TRST#/GEVENT12#
Only USB Port0 can be
HD audio interface is +3VS5 voltage configured as debug port.
R533 *10K_4 ACZ_BCLK M3 D25 SB_SCLK2
ACZ_SDOUT AZ_BITCLK SCL2/GPIO193 SB_SDATA2
15 ACZ_SDOUT N1 F23
R535 *10K_4 ACZ_SDIN0 AZ_SDOUT SDA2/GPIO194 SB_GPIO195
L2 B26
HD AUDIO
R294 *10K_4 ACZ_SDIN1 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 SB_GPIO196
M2 E26
+3V R304 *10K_4 ACZ_SDIN2 AZ_SDIN1/GPIO168 SDA3_LV/GPIO196
B05 M1
AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
F25 T122
R292 *10K_4 ACZ_SDIN3 M4 E22
R501 8.2K_4 CLK_PCIE_LAN_REQ# ACZ_SYNC AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198
N2 F22 GPIO199 15
B
R551 8.2K_4 CLK_PCIE_2_REQ# ACZ_RST# AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 B
P2 E21 GPIO200 15
+3V_S5 AZ_RST# EC_PWM3/EC_TIMER3/GPIO200
G24
R301 10K_4 GBE_COL KSI_0/GPIO201
T1 GBE_COL KSI_1/GPIO202 G25
R291 10K_4 GBE_CRS T4 E28
GBE_CRS KSI_2/GPIO203
L6 E29
R293 10K_4 GBE_MDIO GBE_MDCK KSI_3/GPIO204
L5 GBE_MDIO KSI_4/GPIO205 D29
T9 GBE_RXCLK KSI_5/GPIO206 D28
U1 C29
GBE_RXD3 KSI_6/GPIO207
D03 U3
GBE_RXD2 KSI_7/GPIO208
C28
T2
GBE LAN
GBE_RXD1
U2 B28
GBE_RXD0 KSO_0/GPIO209
EMBEDDED CTRL
T5 GBE_RXCTL/RXDV KSO_1/GPIO210 A27
R300 10K_4 GBE_RXERR V5 B27
GBE_RXERR KSO_2/GPIO211
P5 D26
GBE_TXCLK KSO_3/GPIO212
M5 GBE_TXD3 KSO_4/GPIO213 A26
P9 C26
GBE_TXD2 KSO_5/GPIO214
T7 A24
P7 B25
M7 A25
To Azalia P4
M9
GBE_TXCTL/TXEN
GBE_PHY_PD
KSO_8/GPIO217
KSO_9/GPIO218
D24
B24 Check list
ACZ_SDOUT R532 33/J_4 R290 10K_4 GBE_PHY_INTR GBE_PHY_RST# KSO_10/GPIO219
ACZ_SDOUT_AUDIO 28 V7 C24
GBE_PHY_INTR KSO_11/GPIO220 SB_GPIO195 R245 10K/F_4
KSO_12/GPIO221 B23
C732 *10P/50V_4 ADP_PRES0 E23 A23
T50 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
EMBEDDED CTRL
E24 D22
PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
F21 SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224 C22
ACZ_SYNC R531 33/J_4 G29 A22 SB_GPIO196 R243 10K/F_4
ACZ_SYNC_AUDIO 28 +3V_S5 FC_RST#/GPO160 KSO_16/GPIO225
B22
C731 *10P/50V_4 C485 KSO_17/GPIO226
A
CN12 D27 A
10P/50V_4 PS2KB_DAT/GPIO189
F28
PS2KB_CLK/GPIO190
F29
ACZ_BCLK R534 33/J_4 1 SB_JTAG_TCK PS2M_DAT/GPIO191
ACZ_BITCLK_AUDIO 28 2 E27 PS2M_CLK/GPIO192
SB_JTAG_TDO
C733 *10P/50V_4 3 SB_JTAG_TDI
4
5
SB_TEST1
SB800 A11 PROJECT : ZQ2
ACZ_RST# R529 33/J_4 6 SB_JTAG_RST#
ACZ_RST#_AUDIO 28 7
8
ACZ_SDIN0 Size Document Number Rev
ACZ_SDIN0 28
*S/W JTAG DEBUG JTAG DEBUG SB820-ACPI/GPIO/USB 2/4 1A

5 4 3 2 1
5 4 3 2 1
SATA PORT 0,1,2,3

can support AHCI
mode
C708 0.01u/16V_4 SATA_TX0+_C

U29B
SB800
TEMPIN0
Check list
R491 10K/F_4
13
27 SATA_TX0+ AH9 AH28 T84
C707 0.01u/16V_4 SATA_TX0-_C SATA_TX0P FC_CLK TEMPIN1 R492 10K/F_4
SATA HDD 27 SATA_TX0- AJ9
SATA_TX0N Part 2 of 5 FC_FBCLKOUT
AG28 T79
FC_FBCLKIN AF26 T80
27 SATA_RX0- AJ8 SATA_RX0N
AH8 AF28 MB_THRMDA_SB R496 10K/F_4
27 SATA_RX0+ SATA_RX0P FC_OE#/GPIOD145 T81
AG29 T75
C712 0.01u/16V_4 SATA_TX1+_C FC_AVD#/GPIOD146
D 27 SATA_TX1+ AH10 SATA_TX1P FC_WE#/GPIOD148 AG26 T82 D
27 SATA_TX1- C704 0.01u/16V_4 SATA_TX1-_C AJ10 AF27 SB_GPIO174 R500 10K/F_4
SATA_TX1N FC_CE1#/GPIOD149 T77
AE29
SATA ODD 27 SATA_RX1- AG10
FC_CE2#/GPIOD150
AF29
T78
SATA_RX1N FC_INT1/GPIOD144 T76 SB_GPIO175
27 SATA_RX1+ AF10 AH27 IF THERE IS NO IDE, TEST R511 10K/F_4
SATA_RX1P FC_INT2/GPIOD147 T85
AG12 AJ27 POINTS FOR DEBUG BUS
SATA_TX2P FC_ADQ0/GPIOD128 T86
AF12
SATA_TX2N FC_ADQ1/GPIOD129
AJ26 T87 IS MANDATORY SB_GPIO176 R512 10K/F_4
FC_ADQ2/GPIOD130 AH25 T89
AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24 T88
AH12 AG23 T90
SATA_RX2P FC_ADQ4/GPIOD132
AH23 T91
FC_ADQ5/GPIOD133
AH14 AJ22 T94
SATA_TX3P FC_ADQ6/GPIOD134
Signal Name Explanation AJ14 AG21 T101
FC_ADQ8/GPIOD136 AF21 T97
SB800 A11: 800-? 1% resistor to GND. AG14 AH22 T93
SATA_RX3N FC_ADQ9/GPIOD137
FLASH
AF14 AJ23 T92
SATA_RX3P FC_ADQ10/GPIOD138
SATA_CALRP SB800 A12: TBD-? 1% resistor to GND. (1K ohm) FC_ADQ11/GPIOD139 AF23 T95
AG17 AJ24 T114
SATA_TX4P FC_ADQ12/GPIOD140
AF17 AJ25 T115
SB800 A11: 931-? 1% resistor to VDDAN_11_SATA. AG25 T116
FC_ADQ14/GPIOD142
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26 T117
SATA_CALRN
SERIAL ATA
SB800 A12: TBD-? 1% resistor to VDDAN_11_SATA. AH17 SATA_RX4P
AJ18
SATA_TX5P
AH18 W5
SATA_TX5N FANOUT0/GPIO52
W6
E-SATA AH19
FANOUT1/GPIO53
Y9 BT_OFF#
SATA_RX5N FANOUT2/GPIO54 T60
AJ19
SATA_RX5P WWAN_DET#
W7 T67
+1.1V_AVDD_SATA FANIN0/GPIO56 CPPE_NC1#
C
FANIN1/GPIO57 V9 T59
C
R271 SP@1K/F_4 SATA_CALRP AB14 W8 CRD_REQ1#
SATA_CALRP FANIN2/GPIO58 T63
R267 SP@931/F_4 SATA_CALRN AA14 SATA_CALRN TEMPIN0
B6
TEMPIN0/GPIO171 TEMPIN1
A6
TEMPIN1/GPIO172 MB_THRMDA_SB
30 SATA_ACT# AD11 SATA_ACT#/GPIO67 TEMPIN2/GPIO173 A5
B5 SB_GPIO174
R277 10K/F_4 TEMPIN3/TALERT#/GPIO174 TEMP_COMM R276 *Short_4
+3V C7
TEMP_COMM
A3 SB_GPIO175
HW MONITOR
C694 *27P/50V_4 SATA_X1 VIN0/GPIO175 SB_GPIO176
AD16 SATA_X1 VIN1/GPIO176 B4
A4 SIDE_PORT_ID0
VIN2/GPIO177
2
C5 SIDE_PORT_ID1
*25MHz R483 VIN3/GPIO178 MEM_1V5
PLACE SATA_CAL Y6 *1M/J_4 VIN4/GPIO179 A7
B7
B16 BOM check
RES VERY CLOSE VIN5/GPIO180
B8 1 0
1
VIN6/GBE_STAT3/GPIO181
TO BALL OF SB820 AC16 SATA_X2 VIN7/GBE_LED3/GPIO182 A8
SATA_X2 R452 *10K/F_4 BOARD_ID0 R459 10K/F_4 ID0 15" 14"
+3V
C682 *27P/50V_4
R460 SW@10K/F_4 BOARD_ID1 R461 *SP@10K/F_4 ID1 DIS UMA

SB_GPIO164 J5 G27
T61 SPI_DI/GPIO164 NC1
SB_GPIO163 E2 Y2
SPI ROM
T64 SPI_DO/GPIO163 NC2

SB_GPIO162 K4 R449 SIDE@10K/F_4BOARD_ID2 R455 *SP@10K/F_4 ID2 Sideport
T68 SB_GPIO165 SPI_CLK/GPIO162
T57 K9
SPI_CS1#/GPIO165
W/I W/O
SB_GPIO161 G2
T70 ROM_RST#/GPIO161 R450 *SP@10K/F_4 BOARD_ID3 R456 SP@10K/F_4 ID3 JM JV
ZQ2B ZQ2
SB800 A11 R451 *10K/F_4 BOARD_ID4 R457 10K/F_4 ID4
B B
BOARD_ID0
11 BOARD_ID0
BOARD_ID1
11,12,14,15,25,30,31,35 +3V_S5 11 BOARD_ID1
BOARD_ID2
14 +1.1V_AVDD_SATA 11 BOARD_ID2 BOARD_ID3
2,4,5,9..12,14,15,19,23,24,26,28..33,35..42 +3V 11 BOARD_ID3
BOARD_ID4
11 BOARD_ID4
1 0
+3V
ID0
R550 SP@10K/F_4 SIDE_PORT_ID0 R502 *SP@10K/F_4 SAM HYX
+3V_S5
ID1
R471 *SP@10K/F_4 SIDE_PORT_ID1 R504 SP@10K/F_4 ATI PC69
0.1U/10V_4
U13
DDR3 Sideport Memory Device
5
TC7SH08FU
MEM_1V5 2
4 VDDR_OPT 39
BOARD_ID2 SIDE_PORT_ID1 SIDE_PORT_ID0 11 VDDR_1.05_EN 1
Vendor Vendor P/N STN B/S P/N GPIO12 GPIO178 GPIO177
3
VDDR_1.05_EN:
AKD5LZGTW04 0 1 : VDDR =1.05V
A Hynix H5TQ1G63BFR-12C (64M*16) (WO/Sideport) 0 0 A
0 : VDDR = 0.9V (Default) PR123 *0_4
AKD5LGGT506 1
Samsung K4W1G1646E-HC12 (64M*16) (W/Sideport) 0 1
PROJECT : ZQ2
AKD5LGGT700 1 Quanta Computer Inc.
ATI 23EY2387MA12-SZ (64M*16) (W/Sideport) 1 0
SB820-SATA/IDE/SPI 3/4 1A

5 4 3 2 1
5 4 3 2 1
VDDQ--3.3V I/O power

R297 *Short_6 +3V_VDDIO_PCIGP
131mA
U29C
PLACE ALL THE DECOUPLING CAPS ON
THIS SHEET CLOSE TO SB AS POSSIBLE.
SB800 Part 3 of 5 510mA

VDD-- S/B CORE power
+1.1V_VDDCR R269 *Short_6 +1.1V

14
+3V AH1 N13
VDDIO_33_PCIGP_1 VDDCR_11_1 U29E
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15
1
Y19 N17
CORE S0
C487 C480 C474 C484 C476 VDDIO_33_PCIGP_3 VDDCR_11_3 C471 C472 C468 C470 C455
AE5
AC21
VDDIO_33_PCIGP_4 VDDCR_11_4
U13
U17 0.1U/10V_4 0.1u/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 Y14
SB800 AJ2
2
10U/6.3V_8 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDIO_33_PCIGP_5 VDDCR_11_5 VSSIO_SATA_1 VSS_1
AA2 V12 Y16 A28
PCI/GPIO I/O
D VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_2 VSS_2 D
AB4 V18 AB16 A2
VDDIO_33_PCIGP_7 VDDCR_11_7 VSSIO_SATA_3 VSS_3
AC8 W12 AC14 E5
AA7 W18 AE12 D23
AA9 AE14 E25
VDDIO_33_PCIGP_10 L41 800A50T _8 VSSIO_SATA_6 VSS_6
AF7 VDDIO_33_PCIGP_11 4000 mA AF9 VSSIO_SATA_7 VSS_7 E6
AA19 K28 +1.1V_VDDAN_CLK +1.1V AF11 F24
VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 VSSIO_SATA_8 VSS_8
K29 AF13 N15
VDDAN_11_CLK_2 VSSIO_SATA_9 VSS_9
1
VDDAN_11_CLK_3 J28 AF16 VSSIO_SATA_10 VSS_10 R13
K26 C449 C447 C436 C425 C427 C426 AG8 R17
CLKGEN I/O
VDDAN_11_CLK_4 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 10U/6.3V_8 VSSIO_SATA_11 VSS_11
J21 AH7 T10
2
VDDAN_11_CLK_5 VSSIO_SATA_12 VSS_12
AF22 J20 AH11 P10
FLASH I/O
VDDIO_18_FC_1 VDDAN_11_CLK_6 VSSIO_SATA_13 VSS_13
AE25 K21 AH13 V11
VDDIO_18_FC_2 VDDAN_11_CLK_7 VSSIO_SATA_14 VSS_14
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 AH16 VSSIO_SATA_15 VSS_15 U15
R250 AC22 AJ7 M18
VDDIO_18_FC_4 VSSIO_SATA_16 VSS_16
*Short_4 AJ11 V19
VSSIO_SATA_17 VSS_17
V1 AJ13 M11
VDDRF_GBE_S VSSIO_SATA_18 VSS_18
AJ16 L12
POWER VDDIO_33_GBE_S
M10
VSSIO_SATA_19 VSS_19
VSS_20
L18
43mA A9
VSSIO_USB_1 VSS_21
J7
+3V L45 AE28 B10 P3
GBE LAN
BLM18PG221SN1D(220_1.4A)_6 VDDPL_33_PCIE VSSIO_USB_2 VSS_22
SB820 without GBE: Connected to GND plane. K11 VSSIO_USB_3 VSS_23 V4
C432 C433 B9 AD6
PCI EXPRESS
2.2U/6.3V_6 *0.1U/10V_4 VSSIO_USB_4 VSS_24
U26 L7 D10 AD4
+1.1V_PCIE_VDDR VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 VSSIO_USB_5 VSS_25
V22 L9 D12 AB7
L43 800A50T _8 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 VSSIO_USB_6 VSS_26
600mA V26
VDDAN_11_PCIE_3
D14
VSSIO_USB_7 VSS_27
AC9
+1.1V V27 VDDAN_11_PCIE_4 D17 VSSIO_USB_8 VSS_28 V8
V28 M6 E9 W9
VDDAN_11_PCIE_5 VDDIO_GBE_S_1 VSSIO_USB_9 VSS_29
1
1
V29 P8 F9 W10
C429 C430 C444 C448 C438 C428 VDDAN_11_PCIE_6 VDDIO_GBE_S_2 VSSIO_USB_10 VSS_30
W22 F12 AJ28
VDDAN_11_PCIE_7 VSSIO_USB_11 VSS_31
C W26 F14 B29 C
2
2
10U/6.3V_8 10U/6.3V_8 1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDAN_11_PCIE_8 VSSIO_USB_12 VSS_32
F16 VSSIO_USB_13 VSS_33 U4
C9 VSSIO_USB_14 VSS_34 Y18
+3V_VDDPL_SATA
93mA G11
VSSIO_USB_15 VSS_35
Y10
+3V L51 32mA
GROUND
AD14 F18 Y12
BLM18PG221SN1D(220_1.4A)_6 VDDPL_33_SATA +3V_VDDIO R256 *Short_6 +3V_S5 VSSIO_USB_16 VSS_36
VDDIO_33_S_1 A21 D9 VSSIO_USB_17 VSS_37 Y11
AJ20 D21 H12 AA11
VDDAN_11_SATA_1 VDDIO_33_S_2 VSSIO_USB_18 VSS_38
1
C469 C466 AF18 B21 H14 AA12
SERIAL ATA
VDDAN_11_SATA_4 VDDIO_33_S_3 C443 C441 C450 VSSIO_USB_19 VSS_39
AH20 K10 H16 G4
3.3V_S5 I/O
2.2U/6.3V_6 *0.1U/10V_4 VDDAN_11_SATA_2 VDDIO_33_S_4 *0.1U/10V_4 2.2U/6.3V_6 2.2U/6.3V_6 VSSIO_USB_20 VSS_40
AG19 L10 H18 J4
2
+1.1V_AVDD_SATA VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_21 VSS_41
AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9 J11 VSSIO_USB_22 VSS_42 G8
L42 800A50T _8 567mA AD18 T6 J19 G9
+1.1V AE16 T8 K12 M12
K14 VSSIO_USB_25 VSS_45 AF25
1
K16 VSSIO_USB_26 VSS_46 H7

C445 C446 C457 C464 C458 C459 113mA K18 AH29
CORE S5
+1.1V_VDDCR_11 R241 *Short_6 VSSIO_USB_27 VSS_47
F26 +1.1V_S5 H19 V10
2
*10U/6.3V_810U/6.3V_8 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 VDDCR_11_S_1 VSSIO_USB_28 VSS_48

A18 G26 P6
VDDAN_33_USB_S_1 VDDCR_11_S_2 VSS_49
1
A19 N4
VDDAN_33_USB_S_2 C437 C431 VSS_50
A20 VDDAN_33_USB_S_3 VDDIO_AZ_S M8 +VDDIO_AZ Y4 EFUSE VSS_51 L4
B18 197mA 1U/10V_4 1U/10V_4 L8
2
+3.3V_VDDAN_USB VDDAN_33_USB_S_4 VSS_52
B19 A11 +1.1V_USB_PHY_R D8
VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 VSSAN_HWM
658mA B20 B11
USB I/O
L71 VDDAN_33_USB_S_6 VDDCR_11_USB_S_2
+3V_S5 C18 M19 M20
BLM18PG221SN1D(220_1.4A)_6 VDDAN_33_USB_S_7 VSSXL VSSPL_SYS
C20
VDDAN_33_USB_S_8
1
For support USB D18 VDDAN_33_USB_S_9 VDDPL_33_SYS M21 +3V_VDDPL 47mA

wakeup-->3V_S5 C681 C452 C454 C456 D19 P21 H23
VDDAN_33_USB_S_10 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14
D20 L22 +1.1V_VDDPL 62mA P20 H26
2
10U/6.3V_8 10U/6.3V_8 1U/10V_4 1U/10V_4 VDDAN_33_USB_S_11 VDDPL_11_SYS_S VSSIO_PCIECLK_2 VSSIO_PCIECLK_15

E19 M22 AA21
PLL
VDDAN_33_USB_S_12 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16

B VDDPL_33_USB_S
F19 VDDPL_33_USB_S 17mA M24
VSSIO_PCIECLK_4 VSSIO_PCIECLK_17
AA23 B
M26 AB23
+1.1V_VDDAN_USB
xx mA C11
VDDAN_11_USB_S_1 VDDAN_33_HWM_S
D6 +3V_HWM_VDDAN 5mA P22
AD23
+1.1V_S5 L50 D11
VDDAN_11_USB_S_2
P24
AA26
BLM18PG221SN1D(220_1.4A)_6 L20 L48 +3V_S5 P26 AC26
VDDXL_33_S VSSIO_PCIECLK_8 VSSIO_PCIECLK_21
If the VDDIO_AZ_S BLM18PG221SN1D(220_1.4A)_6 T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20
1
power rail C473 C467 T22 W21
C453 C451 VSSIO_PCIECLK_10 VSSIO_PCIECLK_23
is configured for T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W20
2.2U/6.3V_6 0.1U/10V_4 SB800 A11 *0.1U/10V_4 2.2U/6.3V_6 V20 AE26
2
1.5V_S5 VSSIO_PCIECLK_12 VSSIO_PCIECLK_25
J23 L21
then AZ_SDIN[3:0] VSSIO_PCIECLK_13 VSSIO_PCIECLK_26
K20
VSSIO_PCIECLK_27
can not be
connected to 3.3-V Part 5 of 5
+3V_VDDPL
devices. +3V
+VDDIO_AZ +1.1V_S5 +1.1V_USB_PHY_R SB800 A11
L44
BLM18PG221SN1D(220_1.4A)_6
+3V_S5 R279 *Short_6 L49 *Short_6
1
1
C440 C435
1
*0.1U/10V_4 2.2U/6.3V_6
2
2
1
C462 C463 C460

C478 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8
2
2.2U/6.3V_6
2
+3V_S5 VDDPL_33_USB_S
+1.1V_S5
D04
+3V_S5 +3V_HWM_VDDAN +1.1V_VDDPL
A R430 0_4 A
L53 L40
BLM18PG221SN1D(220_1.4A)_6 BLM18PG221SN1D(220_1.4A)_6
1
C626 C538
C479 C482 C424 C434 0.1u/10V_4 2.2u/6.3V_6
*0.1U/10V_4 *2.2U/6.3V_6 *0.1U/10V_4 2.2U/6.3V_6
PROJECT : ZQ2
2

37 +1.1V_S5
11..13,15,25,30,31,35 +3V_S5
SB820-PWR/DECOUPLING 4/4 1A
2,7..10,37 +1.1V
2,4,5,9..13,15,19,23,24,26,28..33,35..42 +3V
5 4 3 2 1
5 4 3 2 1
REQUIRED STRAPS
OVERLAP COMMON PADS WHERE
POSSIBLE FOR DUAL-OP RESISTORS. 15
SB820M is For internal clock GEN.
supported Gen1
mode only.
+3V_S5 +3V_S5 +3V_S5
D +3V_S5 +3V +3V +3V +3V D
11..14,25,30,31,35 +3V_S5
7,9,10,31,36,41,42 +1.8V
2,4,5,9..14,19,23,24,26,28..33,35..42 +3V
R255 R262
R302 R540 R525 R541 R539 R472 *10K/F_4 10K/F_4
*10K/F_4 *10K/F_4 *10K/F_4 *10K/F_4 10K/F_4
10K/F_4
12 GPIO199
12 GPIO200
11 LPC_CLK1
11 LPC_CLK0
11 PCI_CLK4
11 PCI_CLK3
11 PCI_CLK2
11 PCI_CLK1
12 ACZ_SDOUT
1
R259 R253
R303 R528 R526 R542 R527 R477 2.2K/J_4 *2.2K/J_4
10K/F_4 10K/F_4 10K/F_4 10K/F_4 *10K/F_4 10K/F_4
2
AZ_SDOUT PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 GPIO200 GPIO199
D02
C C
PULL This is required as ALLOW Watchdog USE non_Fusion EC CLKGEN H, H=Reserved
HIGH the low power mode PCIE Gen2 Timer Enable DEBUG CLOCK MODE ENABLED ENABLED
H, L=SPI ROM
is not supported on STRAPS
the SB8xx DEFAULT DEFAULT
PULL PERFORMANCE FORCE Watchdog IGNORE Fusion EC CLKGEN L, H=LPC ROM DEFAULT
LOW MODE PCIE Gen1 Timer Disable DEBUG CLOCK MODE DISABLED DISABLED
L, L=FWH ROM
STRAPS
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
internal have
pull Hi 10K
DEBUG STRAPS
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
B
11 AD23 B
11 AD24
11 AD25
11 AD26
11 AD27 NB_PWRGD_IN:
RS880/RX881 = 1.8V;
1
Do NOT share it with SB_PWRGD when use Internal Clk Gen (Need SB PLL initialize firstly)
R524 R522 R283 R285 R272
*2.2K/J_4 *2.2K/J_4 *2.2K/J_4 *2.2K/J_4 *2.2K/J_4
R309 10K/F_4 R307 *Short_4 SB_PWRGD_IN
+3V_S5
2
SB_PWRGD_IN 12
C491
*2.2U/6.3V_6 NB/SB POWER GOOD CIRCUIT
+1.8V
+1.8V
D23 *BAS316 U15

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 1 5 C494 *0.1U/10V_4
2,33,36,38 CPU_COREPG NC VCC R317
2 300/J_4
D29 BAS316 A
USE PCI DISABLE ILA USE FC USE DEFAULT DISABLE PCI
PULL 3 4 R312 *33/J_4 NB_PWRGD_IN
PLL AUTORUN PLL PCIE STRAPS MEM BOOT 4,33 PWROK_EC GND Y NB_PWRGD_IN 9,12
HIGH *NL17SZ17DFT2G
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT SOT-353
AL17SZ17000 IC(5P) NL17SZ17DFT2G(SOT-353) SOT-353

PULL BYPASS ENABLE ILA BYPASS FC USE EEPROM ENABLE PCI
ALUC1G17000 IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5) SOT23-5
LOW PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT
A A
PROJECT : ZQ2
SB820-STRAPS 1A

5 4 3 2 1
5 4 3 2 1
8 PEG_TXP[7:0]
8 PEG_TXN[7:0]
PEG_TXP[7:0]
PEG_TXN[7:0]
U17A
16
PEG_RXP[7:0] PEG_TXP7 AA38 Y33 PEG_RXP7_C C125 SW@0.1u/10V_4_X7R
8 PEG_RXP[7:0] 8 PEG_TXP7 PCIE_RX0P PCIE_TX0P PEG_RXP7 8
PEG_TXN7 Y37 Y32 PEG_RXN7_C C114 SW@0.1u/10V_4_X7R
D PEG_RXN[7:0] 8 PEG_TXN7 PCIE_RX0N PCIE_TX0N PEG_RXN7 8 D
8 PEG_RXN[7:0]
PEG_TXP6 Y35 W33 PEG_RXP6_C C86 SW@0.1u/10V_4_X7R
8 PEG_TXP6 PCIE_RX1P PCIE_TX1P PEG_RXP6 8
PEG_TXN6 W36 W32 PEG_RXN6_C C77 SW@0.1u/10V_4_X7R
8 PEG_TXN6 PCIE_RX1N PCIE_TX1N PEG_RXN6 8
PEG_TXP5 W38 U33 PEG_RXP5_C C70 SW@0.1u/10V_4_X7R

PEG_TXN5 V37 U32 PEG_RXN5_C C58 SW@0.1u/10V_4_X7R
PEG_TXP4 V35 U30 PEG_RXP4_C C111 SW@0.1u/10V_4_X7R

PEG_TXN4 U36 U29 PEG_RXN4_C C112 SW@0.1u/10V_4_X7R
PEG_TXP3 U38 T33 PEG_RXP3_C C44 SW@0.1u/10V_4_X7R

PEG_TXN3 T37 T32 PEG_RXN3_C C36 SW@0.1u/10V_4_X7R
PCI EXPRESS INTERFACE

PEG_TXP2 T35 T30 PEG_RXP2_C C43 SW@0.1u/10V_4_X7R
PEG_TXN2 R36 T29 PEG_RXN2_C C53 SW@0.1u/10V_4_X7R
PEG_TXP1 R38 P33 PEG_RXP1_C C30 SW@0.1u/10V_4_X7R

PEG_TXN1 P37 P32 PEG_RXN1_C C23 SW@0.1u/10V_4_X7R
C 8 PEG_TXN1 PCIE_RX6N PCIE_TX6N PEG_RXN1 8 C
PEG_TXP0 P35 P30 PEG_RXP0_C C33 SW@0.1u/10V_4_X7R

PEG_TXN0 N36 P29 PEG_RXN0_C C26 SW@0.1u/10V_4_X7R
N38 N33
PCIE_RX8P PCIE_TX8P
M37 N32
PCIE_RX8N PCIE_TX8N
M35 N30 R82 *SW@10K/F_4

PCIE_RX9P PCIE_TX9P 17 GPIO24_TRSTB
L36 N29
PCIE_RX9N PCIE_TX9N R84 *SW@10K/F_4
17 GPIO27_TMS +3V_D
L38 L33 R71 *SW@0_4
PCIE_RX10P PCIE_TX10P 17 GPIO26_TCK CLK_14M_VGA 11
K37 L32
PCIE_RX10N PCIE_TX10N R43 *SW@10K/F_4
+3V_D 18 TESTEN +3V_D for B
K35 L30
PCIE_RX11P PCIE_TX11P
J36
PCIE_RX11N PCIE_TX11N
L29 JTAG SIGNAL STUFF OPTION FOR OPTION2
R42
J38
K33 SIGNALS NORMAL MODE JTAG MODE (DEBUG)
B SW@10K/F_4 H37 K32 B
D2 SW@BAS316
PCIE_RST_VGA# H35 J33 TESTEN "1" (PU) "1" (PU)
A_RST# 11,25,26 PCIE_RX13P PCIE_TX13P
G36 J32
D3 SW@BAS316 PCIE_RX13N PCIE_TX13N
dGPU_RST_GPIO 11
G38
K30 GPIO24_TRSTB "0" (PD) "1" (PU)
F37 K29
F35
H33 GPIO26_TCK CLK "1" (PU)
E37 H32
CLOCK GPIO27_TMS "1" (PU) "1" (PU)

11 CLK_PCIE_VGAP AB35
PCIE_REFCLKP
11 CLK_PCIE_VGAN AA36
PCIE_REFCLKN
For Madison and Park CALIBRATION

the PWRGOOD ball must AJ21 Y30 R29 SW@1.27K/F_4
NC#1 PCIE_CALRP
AK21
A be conneccted to ground R35 SW@10K_4 NC#2 R28 SW@2K/F_4 A
AH16
PWRGOOD PCIE_CALRN
Y29 +1V +1.0V
For Madison and Park PCIE_VDDC is 1.0V
PCIE_RST_VGA# AA30
PERSTB PROJECT : ZQ2
SW@Park_M2 Quanta Computer Inc.
Madison/Park-PCIE 1/6 1A
17,19,20,41 +1V
17..19,21 +3V_D
5 4 3 2 1
5 4 3 2 1
U17B
U17G
17
TXCAP_DPA3P AU24
TXCAM_DPA3N AV23
AT25 LVDS CONTROL AK27 R57 *SW@10K_4

MUTI GFX TX0P_DPA2P VARY_BL R53 *SW@10K_4
TX0M_DPA2N AR24 DIGON AJ27
DPA
TX1P_DPA1P AU26
For Park-M2 AV25
TX1M_DPA1N
NC pin AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27 TXCLK_UP_DPF3P AK35
D
AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 TXCLK_UN_DPF3N AL36 D
AP8
DVPCNTL_0
AW8 AR30 AJ38
DVPCNTL_1 TXCBP_DPB3P TXOUT_U0P_DPF2P
AR3 AT29 AK37
DVPCNTL_2 TXCBM_DPB3N TXOUT_U0N_DPF2N
AR1 DVPCLK
AU1 AV31 AH35
GPU Power-on sequence 21 RAM_STRAP0
21 RAM_STRAP1 AU3
AW3
DVPDATA_0
DVPDATA_1 DPB
TX3P_DPB2P
TX3M_DPB2N
AU30
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AJ36
21 RAM_STRAP2 DVPDATA_2
AP6 AR32 AG38
T27 DVPDATA_3 TX4P_DPB1P TXOUT_U2P_DPF0P
AW5 AT31 AH37
1 => +3V_D AU5
DVPDATA_4
DVPDATA_5
TX4M_DPB1N TXOUT_U2N_DPF0N
AR6 AT33 AF35
2 => +VGPU_CORE 1.8V GPIO AW6
DVPDATA_6
DVPDATA_7
TX5P_DPB0P
TX5M_DPB0N AU32
TXOUT_U3P
TXOUT_U3N AG36
AU6
DVPDATA_8
3 => +1V AT7
AV7
DVPDATA_9 TXCCP_DPC3P
AU14
AV13 LVTMDP
DVPDATA_10 TXCCM_DPC3N
4 => +1.5V_GPU AN7
AV9
DVPDATA_11
DVPDATA_12 TX0P_DPC2P AT15 TXCLK_LP_DPE3P AP34
AT9 AR14 AR34
5 => +1.8V_GPU AR10
DVPDATA_13
DVPDATA_14
TX0M_DPC2N TXCLK_LN_DPE3N
AW10 DPC AU16 AW37
6 => dGPU_PWROK AU10
DVPDATA_15
DVPDATA_16
TX1P_DPC1P
TX1M_DPC1N AV15
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N AU35
AP10
DVPDATA_17
AV11 AT17 AR37
DVPDATA_18 TX2P_DPC0P TXOUT_L1P_DPE1P
For Park-M2 NC AT11 DVPDATA_19 TX2M_DPC0N AR16 TXOUT_L1N_DPE1N AU39
AR12 DVPDATA_20
pin AW12
DVPDATA_21 TXCDP_DPD3P
AU20
TXOUT_L2P_DPE0P
AP35
AU12 AT19 AR35
DVPDATA_17 - AP12
DVPDATA_22 TXCDM_DPD3N TXOUT_L2N_DPE0N
+3V_D DVPDATA_23
DVPDATA_23 TX3P_DPD2P AT21 TXOUT_L3P AN36
AR20 AP37
TX3M_DPD2N TXOUT_L3N
DPD AU22
TX4P_DPD1P
AV21
R357 *SW@10K/F_4 EV_LVDS_BLON R51 R56 TX4M_DPD1N
+3V_D
SW@10K/F_4 SW@10K/F_4 I2C AT23
TX5P_DPD0P SW@Park_M2
TX5M_DPD0N AR22
R362 *SW@10K/F_4 AK26 SCL
C AJ26 C
SDA
AD39 EXT_CRT_RED
GENERAL PURPOSE I/O R
RB AD37
21 GPU_GPIO0 AH20 GPIO_0
AH18 AE36 EXT_CRT_GRE
21 GPU_GPIO1 GPIO_1 G
21 GPU_GPIO2 AN16 GPIO_2 GB AD35
21 GPIO3_SMBDAT AH23 GPIO_3_SMBDATA
AJ23 AF37 EXT_CRT_BLU
21 GPIO4_SMBCLK GPIO_4_SMBCLK B
IO_VID1 AH17 AE38
T121 IO_VID0 GPIO_5_AC_BATT DAC1 BB
AJ17
*SW@150/F_4
*SW@150/F_4
*SW@150/F_4
T120 EV_LVDS_BLON GPIO_6
AK17 GPIO_7_BLON HSYNC AC36 EXT_HSYNC 21
21 SOUT_GPIO8 AJ13 GPIO_8_ROMSO VSYNC AC38 EXT_VSYNC 21
R339
R338
R337
21 SIN_GPIO9 AH15
GPIO_9_ROMSI
21 SCLK_GPIO10 AJ16
GPIO_10_ROMSCK R30 SW@499/F_4
21 GPU_GPIO11 AK16 AB34
GPIO_11 RSET
21 GPU_GPIO12 AL16 GPIO_12
AM16 AD34 AVDD
21 GPU_GPIO13 GPIO_13 AVDD
AM14 AE34 +1.8V_GPU
+3V_D T21 GPIO_14_HPD2 AVSSQ
3.3V GPIO 40 GPU_VID1 AM13 GPIO_15_PWRCNTL_0 (1.8V@70mA AVDD)
GPU_VID3 AK14 AC33 VDD1DI 120 ohm/300mA
T17 GPIO_16_SSIN VDD1DI AVDD L57 SW@SBY100505T-121Y-N/0.3A/120ohm_4
21 ALT#_GPIO17 AG30 GPIO_17_THERMAL_INT VSS1DI AC34
AN14 SW@0.1u/10V_4_X7R SW@10u/6.3V_6
R350 T25 GPIO_18_HPD3
4 TEMP_FAIL AM17 GPIO_19_CTF
*SW@10K/F_4 AL13 AC30 C526 C525 C522
40 GPU_VID2 GPIO_20_PWRCNTL_1 R2
AJ14 AC31 SW@1u/6.3V_4
T10 GPIO_21_BB_EN R2B
21 SCS#_GPIO22 AK13
GPIO_22_ROMCSB
12 VGA_REQ# AN13 GPIO_23_CLKREQB G2 AD30
GPIO24_TRSTB AM23 AD31 (1.8V@100mA VDD1DI)
16 GPIO24_TRSTB JTAG_TRSTB G2B 120 ohm/300mA
GPIO25_TDI AN23
R349 GPIO26_TCK JTAG_TDI VDD1DI L5 SW@SBY100505T-121Y-N/0.3A/120ohm_4
16 GPIO26_TCK AK23 AF30
GPIO27_TMS JTAG_TCK B2
*SW@10K/F_4 16 GPIO27_TMS AL24 JTAG_TMS B2B AF31
GPIO28_TDO AM24 SW@0.1u/10V_4_X7R SW@10u/6.3V_6
JTAG_TDO C149 C150 C151
AJ19 GENERICA
AK19 AC32 SW@1u/6.3V_4
GENERICB C
AJ20 AD32
GENERICC Y
AK20 GENERICD COMP AF32
B
AJ24 GENERICE_HPD4 B
JTAG DEBUG PORT AH26 DAC2
+3V_D GENERICF T5
AH24 AD29
GENERICG H2SYNC
AC29 V2SYNC 21
R83 *SW@10K/F_4 GPIO24_TRSTB V2SYNC
EXT_HDMI_HPD AK24
R85 *SW@10K/F_4 GPIO27_TMS T19 HPD1 VDD1DI
VDD2DI AG31
VSS2DI AG32
R69 *SW@10K/F_4 GPIO25_TDI
R68 *SW@10K/F_4 GPIO28_TDO AG33 +3V_D (3.3V@130mA A2VDD)

A2VDD
R70 *SW@10K/F_4 GPIO26_TCK AD33 A2VDDQ
R78 SW@499/F_4 VREFG A2VDDQ C131
+1.8V_GPU AH13
VREFG SW@0.1u/10V_4_X7R
AF33
A2VSSQ
R75 C195
SW@249/F_4 AA29 R31 SW@715/F_4
SW@0.1u/10V_4_X7R R2SET
+1.8V(75mA)
120 ohm/300mA
L11 SW@SBY100505T-121Y-N/0.3A/120ohm_4 DPLL_PVDD DDC/AUX AM26
+1.8V_GPU DDC1CLK
PLL/CLOCK AN26 T52
C178 C176 C172 DPLL_PVDD DDC1DATA T119
AM32 DPLL_PVDD
AN32 AM27
SW@10u/6.3V_6
SW@1u/6.3V_4
SW@0.1u/10V_4_X7R DPLL_PVSS AUX1P T24 +1.8V_GPU
AL27
AUX1N T20 (1.8V@2mA A2VDDQ)
DPLL_VDDC AN31 AM19 120 ohm/300mA
C533 SW@27p/50V_4 DPLL_VDDC DDC2CLK T18 A2VDDQ L56 SW@SBY100505T-121Y-N/0.3A/120ohm_4
AL19
DDC2DATA T15
+1.0V(125mA)
2
120 ohm/300mA XTALI_27M AV33 AN20 SW@1u/6.3V_4

L12 SW@SBY100505T-121Y-N/0.3A/120ohm_4 DPLL_VDDC Y3 R345 XTALO_27M XTALIN AUX2P T22 C524 C523
+1V AU34 AM20
SW@1M_4 XTALOUT AUX2N T13 SW@0.1u/10V_4_X7R
SW@27MHZ
C179 C175 C171 AL30
1
DDCCLK_AUX3P T12
AM30
SW@10u/6.3V_6
SW@1u/6.3V_4
SW@0.1u/10V_4_X7R C532 SW@27p/50V_4 DDCDATA_AUX3N T16
AL29
DDCCLK_AUX4P T23
21 GPU_D+ AF29 DPLUS DDCDATA_AUX4N AM29
A AG29 THERMAL T26 A
21 GPU_D- DMINUS
+1.8V(5mA) DDCCLK_AUX5P AN21
120 ohm/300mA AM21
L6 SW@SBY100505T-121Y-N/0.3A/120ohm_4 TS_VDD T14 DDCDATA_AUX5N
+1.8V_GPU AK32
TS_VDD TS_FDO
AJ32 TSVDD DDC6CLK AJ30
C163 C161 AJ33 AJ31
TSVSS DDC6DATA
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R AK30
NC_DDCCLK_AUX7P T9
AK29
NC_DDCDATA_AUX7N T11
PROJECT : ZQ2
SW@Park_M2 Quanta Computer Inc.
19..21,41 +1.8V_GPU
Madison/Park-HOST 2/6 1A
16,19,20,41 +1V
16,18,19,21 +3V_D
5 4 3 2 1
5 4 3 2 1
18
VMB_DQ[63..0]
22 VMB_DQ[63..0]
VMB_DM[7..0]
22 VMB_DM[7..0]
U17C U17D
DDR2 DDR2 VMB_RDQS[7..0] DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 22 VMB_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 VMB_WDQS[7..0] DDR3 DDR3
22 VMB_WDQS[7..0]
C37 G24 VMB_DQ0 C5 P8 VMB_MA0
DQA0_0/DQA_0 MAA0_0/MAA_0 VMB_DQ1 DQB0_0/DQB_0 MAB0_0/MAB_0 VMB_MA1
C35 J23 C3 T9
MEMORY INTERFACE A
D DQA0_1/DQA_1 MAA0_1/MAA_1 VMB_MA[13..0] VMB_DQ2 DQB0_1/DQB_1 MAB0_1/MAB_1 VMB_MA2 D
A35 H24 22 VMB_MA[13..0] E3 P9
MEMORY INTERFACE B
E34 J24 E1 N7
G32 H26 F1 N8
DQA0_4/DQA_4 MAA0_4/MAA_4 VMB_BA0 VMB_DQ5 DQB0_4/DQB_4 MAB0_4/MAB_4 VMB_MA5
D33 DQA0_5/DQA_5 MAA0_5/MAA_5 J26 22 VMB_BA0 F3 DQB0_5/DQB_5 MAB0_5/MAB_5 N9
F32 H21 VMB_BA1 VMB_DQ6 F5 U9 VMB_MA6
DQA0_6/DQA_6 MAA0_6/MAA_6 22 VMB_BA1 DQB0_6/DQB_6 MAB0_6/MAB_6
E32 G21 VMB_BA2 VMB_DQ7 G4 U8 VMB_MA7
DQA0_7/DQA_7 MAA0_7/MAA_7 22 VMB_BA2 DQB0_7/DQB_7 MAB0_7/MAB_7
D31 H19 VMB_DQ8 H5 Y9 VMB_MA8
F30 H20 H6 W9
C30 DQA0_10/DQA_10 MAA1_2/MAA_10 L13 J4 DQB0_10/DQB_10 MAB1_2/MAB_10 AC8
A30 G16 VMB_DQ11 K6 AC9 VMB_MA11
F28 DQA0_12/DQA_12 MAA1_4/MAA_12 J16 K5 DQB0_12/DQB_12 MAB1_4/MAB_12 AA7
C28 H16 VMB_DQ13 L4 AA8 VMB_BA2
DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 VMB_DQ14 DQB0_13/DQB_13 MAB1_5/BA2 VMB_BA0
A28 J17 M6 Y8
DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 VMB_DQ15 DQB0_14/DQB_14 MAB1_6/BA0 VMB_BA1
E28 H17 M1 AA9
DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 VMB_DQ16 DQB0_15/DQB_15 MAB1_7/BA1
D27 DQA0_16/DQA_16 M3 DQB0_16/DQB_16
F26 A32 VMB_DQ17 M5 H3 VMB_DM0
DQA0_17/DQA_17 WCKA0_0/DQMA_0 VMB_DQ18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 VMB_DM1
C26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 C32 N4 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 H1
A26 D23 VMB_DQ19 P6 T3 VMB_DM2
F24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 E22 P5 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 T5
C24 C14 VMB_DQ21 R4 AE4 VMB_DM4
A24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 A14 T6 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AF5
E24 E10 VMB_DQ23 T1 AK6 VMB_DM6
C22 D9 U4 AK5
DQA0_24/DQA_24 WCKA1B_1/DQMA_7 VMB_DQ25 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
A22 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3
V6 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3
F22 C34 VMB_DQ26 V1 F6 VMB_RDQS0
DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 VMB_DQ27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 VMB_RDQS1
D21 D29 V3 K3
A20 D25 Y6 P3
F20
DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3
E20 Y1
DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3
V5 QSB[7..0]
D19 E16 VMB_DQ30 Y3 AB5 VMB_RDQS4
E18 E12 Y5 AH1
C18 J10 AA4 AJ9
A18 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 D7 AB6 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 AM5
F18 VMB_DQ34 AB1
DQA1_2/DQA_34 VMB_DQ35 DQB1_2/DQB_34 VMB_WDQS0
D17 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 A34 AB3 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 G7
A16 E30 VMB_DQ36 AD6 K1 VMB_WDQS1
DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 VMB_DQ37 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 VMB_WDQS2
F16 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 E26 AD1 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 P1
D15 C20 VMB_DQ38 AD3 W4 VMB_WDQS3 QSB#[7..0]
C E14 C16 AD5 AC4 C
F14 C12 AF1 AH3
D13 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 J11 AF3 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AJ8
F12 F8 VMB_DQ42 AF6 AM3 VMB_WDQS7
DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 VMB_DQ43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 DQA1_11/DQA_43 AG4 DQB1_11/DQB_43
D11 J21 VMB_DQ44 AH5 T7
DQA1_12/DQA_44 ADBIA0/ODTA0 DQB1_12/DQB_44 ADBIB0/ODTB0 VMB_ODT0 22
F10 G19 VMB_DQ45 AH6 W7
DQA1_13/DQA_45 ADBIA1/ODTA1 DQB1_13/DQB_45 ADBIB1/ODTB1 VMB_ODT1 22
A10 VMB_DQ46 AJ4
DQA1_14/DQA_46 VMB_DQ47 DQB1_14/DQB_46 VMB_CLKP0
C10 DQA1_15/DQA_47 CLKA0 H27 AK3 DQB1_15/DQB_47 CLKB0 L9 VMB_CLKP0 22
G13 G27 VMB_DQ48 AF8 L8 VMB_CLKN0
DQA1_16/DQA_48 CLKA0B DQB1_16/DQB_48 CLKB0B VMB_CLKN0 22
H13 VMB_DQ49 AF9
DQA1_17/DQA_49 VMB_DQ50 DQB1_17/DQB_49 VMB_CLKP1
J13 DQA1_18/DQA_50 CLKA1 J14 AG8 DQB1_18/DQB_50 CLKB1 AD8 VMB_CLKP1 22
H11 H14 VMB_DQ51 AG7 AD7 VMB_CLKN1
DQA1_19/DQA_51 CLKA1B DQB1_19/DQB_51 CLKB1B VMB_CLKN1 22
G10 VMB_DQ52 AK9
DQA1_20/DQA_52 VMB_DQ53 DQB1_20/DQB_52 VMB_RAS0#
G8 K23 AL7 T10 VMB_RAS0# 22
DQA1_21/DQA_53 RASA0B VMB_DQ54 DQB1_21/DQB_53 RASB0B VMB_RAS1#
K9 K19 AM8 Y10 VMB_RAS1# 22
DQA1_22/DQA_54 RASA1B VMB_DQ55 DQB1_22/DQB_54 RASB1B
K10 DQA1_23/DQA_55 AM7 DQB1_23/DQB_55
G9 K20 VMB_DQ56 AK1 W10 VMB_CAS0#
DQA1_24/DQA_56 CASA0B DQB1_24/DQB_56 CASB0B VMB_CAS0# 22
+1.5V_GPU A8 K17 VMB_DQ57 AL4 AA10 VMB_CAS1#
DQA1_25/DQA_57 CASA1B DQB1_25/DQB_57 CASB1B VMB_CAS1# 22
C8 +1.5V_GPU VMB_DQ58 AM6
DQA1_26/DQA_58 VMB_DQ59 DQB1_26/DQB_58 VMB_CS0#
E8 K24 AM1 P10 VMB_CS0# 22
DQA1_27/DQA_59 CSA0B_0 VMB_DQ60 DQB1_27/DQB_59 CSB0B_0
A6 DQA1_28/DQA_60 CSA0B_1 K27 AN4 DQB1_28/DQB_60 CSB0B_1 L10
C6 VMB_DQ61 AP3
R13 DQA1_29/DQA_61 VMB_DQ62 DQB1_29/DQB_61 VMB_CS1#
E6 DQA1_30/DQA_62 CSA1B_0 M13 AP1 DQB1_30/DQB_62 CSB1B_0 AD10 VMB_CS1# 22
SW@40.2/F_4 A5 K16 R5 VMB_DQ63 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 SW@40.2/F_4 DQB1_31/DQB_63 CSB1B_1
MVREFDA L18 K21 U10 VMB_CKE0
MVREFDA CKEA0 CKEB0 VMB_CKE0 22
MVREFSA L20 J20 MVREFDB Y12 AA11 VMB_CKE1
MVREFSA CKEA1 MVREFDB CKEB1 VMB_CKE1 22
MVREFSB AA12
SW@100/F_4
SW@0.1u/10V_4_X7R
R22 *SW@240/F_4 L27 MVREFSB VMB_WE0#

K26 N10
SW@100/F_4
SW@0.1u/10V_4_X7R
MEM_CALRN0 WEA0B WEB0B VMB_WE0# 22
R26 SW@240/F_4 N12 L15 +3V_D R39 *SW@10K_4 AB11 VMB_WE1#
MEM_CALRN1 WEA1B WEB1B VMB_WE1# 22
C8
R38 *SW@240/F_4 AG12
MEM_CALRN2
R14
C19
R10
+1.5V_GPU
R17 SW@240/F_4 M12 R33 SW@10K_4 TESTEN VMB_MA13 R25 *SW@4.7K_4
GDDR5
H23 AD28 T8
GDDR5
MEM_CALRP1 MAA0_8 TESTEN MAB0_8 +1.5V_GPU
R23 *SW@240/F_4 M27 J19 W8
R55 *SW@240/F_4 AH12 MEM_CALRP0 MAA1_8 MAB1_8
AK10
MEM_CALRP2 CLKTESTA R86 SW@51_4
AL10 CLKTESTB DRAM_RST AH11 MEM_RST# 22
+1.5V_GPU R347
B B
+1.5V_GPU R88
*SW@0_4
TP1 AL31
RSVD
*SW@0_4
C55 R87
R21 SW@68p/50V_4
SW@40.2/F_4 SW@Park_M2 R4 SW@Park_M2 SW@10K_4
SW@40.2/F_4
For PARK
SW@100/F_4
SW@0.1u/10V_4_X7R
MEM_CALRNP0
SW@100/F_4
SW@0.1u/10V_4_X7R
R20
C27
R7
C10
MEM_CALRNP1 stuff TESTEN

16 TESTEN
MEM_CALRNP2
DDR3/GDDR3 Memory Stuff Option Designator For M97-M2 For Mannhatton
GDDR5 GDDR3 DDR3

Ra 10K 10K
+1.5V_VGA 1.5V 1.8V/1.5V 1.5V
Rb 0R/Short 680R
Ra 40.2R 40.2R 40.2R
A
Rc DNI DNI A
Rb 100R 100R 100R

2.2nF 68pF
Ca
PROJECT : ZQ2
Madison/Park-MEM 3/6 1A
19,22,41 +1.5V_GPU
5 4 3 2 1
5 4 3 2 1
18,22,41 +1.5V_GPU
19
17,20,21,41 +1.8V_GPU
16,17,20,41 +1V
2,4,5,9..15,23,24,26,28..33,35..42 +3V
31,40 +VGPU_CORE
U17F
16..18,21 +3V_D
U17E
AB39 A3
+1.5V_GPU MEM I/O +1.8V_GPU PCIE_VSS#1 GND#1
For DDR3, MVDDQ = 1.5V (7.5A) E39 A37
PCIE 180 ohm/1.5A PCIE_VSS#2 GND#2
(1.8V@400mA PCIE_VDDR) F34
PCIE_VSS#3 GND#3
AA16
AC7 AA31 PCIE_VDDR L3 SW@HCB1608KF-181T15/180ohm/1.5A_6 F39 AA18
VDDR1#1 PCIE_VDDR#1 PCIE_VSS#4 GND#4
AD11 AA32 G33 AA2
AF7 AA33 G34 AA21
C42 C16 C502 C54 C500 VDDR1#3 PCIE_VDDR#3 C88 C104 C91 C102 C139 C103 C87 C140 PCIE_VSS#6 GND#6
AG10 AA34 H31 AA23
SW@10u/6.3V_6 SW@10u/6.3V_6 VDDR1#4 PCIE_VDDR#4 SW@0.1u/10V_4_X7R SW@1u/6.3V_4 SW@1u/6.3V_4 SW@10u/6.3V_6 PCIE_VSS#7 GND#7
AJ7 V28 H34 AA26
SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 VDDR1#5 PCIE_VDDR#5 SW@0.1u/10V_4_X7R SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#8 GND#8
AK8 W29 H39 AA28
D VDDR1#6 PCIE_VDDR#6 PCIE_VSS#9 GND#9 D
AL9 W30 J31 AA6
G11 Y31 J34 AB12
G14 K31 AB15
VDDR1#9 PCIE_VSS#12 GND#12
G17 K34 AB17
VDDR1#10 +1V PCIE_VSS#13 GND#13
G20 G30 K39 AB20
C115 C51 C22 C89 C85 C18 VDDR1#11 PCIE_VDDC#1 PCIE_VSS#14 GND#14
G23
VDDR1#12 PCIE_VDDC#2
G31 (1.0V@1.1A PCIE_VDDC) L31
PCIE_VSS#15 GND#15
AB22
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 G26 H29 L34 AB24
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR1#13 PCIE_VDDC#3 PCIE_VSS#16 GND#16
G29 H30 M34 AB27
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#17 GND#17
H10 J29 M39 AC11
VDDR1#15 PCIE_VDDC#5 C38 C32 C39 C62 C50 C48 C72 C24 PCIE_VSS#18 GND#18
J7 J30 N31 AC13
VDDR1#16 PCIE_VDDC#6 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@10u/6.3V_6 PCIE_VSS#19 GND#19
J9 L28 N34 AC16
VDDR1#17 PCIE_VDDC#7 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#20 GND#20
K11 M28 P31 AC18
K13 N28 P34 AC2
K8 R28 P39 AC21
C144 C138 C28 C63 C29 C132 VDDR1#20 PCIE_VDDC#10 PCIE_VSS#23 GND#23
L12 T28 R34 AC23
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR1#21 PCIE_VDDC#11 PCIE_VSS#24 GND#24
L16 U28 T31 AC26
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR1#22 PCIE_VDDC#12 +VGPU_CORE PCIE_VSS#25 GND#25
L21 T34 AC28
VDDR1#23 PCIE_VSS#26 GND#26
L23
VDDR1#24 (30A or more) T39
PCIE_VSS#27 GND#27
AC6
L26 AA15 U31 AD15
VDDR1#25 CORE VDDC#1 PCIE_VSS#28 GND#28
L7 AA17 U34 AD17
VDDR1#26 VDDC#2 PCIE_VSS#29 GND#29
M11 AA20 V34 AD20
VDDR1#27 VDDC#3 C73 C90 C56 C99 C67 C107 C109 C59 C81 C75 PCIE_VSS#30 GND#30
N11 AA22 V39 AD22
C143 C41 C17 C15 C147 VDDR1#28 VDDC#4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#31 GND#31
P7 AA24 W31 AD24
SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R VDDR1#29 VDDC#5 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#32 GND#32
R11 AA27 W34 AD27
SW@1u/6.3V_4 SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R VDDR1#30 VDDC#6 PCIE_VSS#33 GND#33
U11 AB16 Y34 AD9
U7 AB18 Y39 AE2
Y11 AB21 AE6
VDDR1#33 VDDC#9 GND#36
Y7 AB23 AF10
VDDR1#34 VDDC#10 GND#37
AB26 AF16
VDDC#11 GND#38
AB28 AF18
VDDC#12 C98 C108 C118 C84 C68 C40 C82 C60 C76 C66 GND#39
AC17 AF21
LEVEL
VDDC#13
VDDC#14
VDDC#15
AC20
AC22 SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
F15
GND#100
GND GND#40
GND#41
GND#42
AG17
AG2
(1.8V@110mA VDD_CT) TRANSLATION AC24 F17 AG20
VDDC#16 GND#101 GND#43
POWER
+1.8V_GPU L17 SW@SBY100505T-121Y-N/0.3A/120ohm_4 VDDC_CT AF26 AC27 F19 AG22
VDD_CT#1 VDDC#17 GND#102 GND#44
AF27 AD18 F21 AG6
VDD_CT#2 VDDC#18 GND#103 GND#45
AG26 AD21 F23 AG9
C141 C134 C126 VDD_CT#3 VDDC#19 GND#104 GND#46
C AG27 AD23 F25 AH21 C
SW@1u/6.3V_4 VDD_CT#4 VDDC#20 GND#105 GND#47
AD26 F27 AJ10
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R VDDC#21 C119 C57 C120 C74 C97 C64 C100 C83 C128 C110 GND#106 GND#48
AF17 F29 AJ11
I/O VDDC#22 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#107 GND#49
(3.3V@60mA)) VDDC#23
AF20 F31
GND#108 GND#50
AJ2
+3V_D AF23 AF22 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 F33 AJ28
VDDR3#1 VDDC#24 GND#109 GND#51
AF24 AG16 F7 AJ6
AG23 AG18 F9 AK11
C190 C135 C127 C129 VDDR3#3 VDDC#26 GND#111 GND#53
AG24 AG21 G2 AK31
SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR3#4 VDDC#27 GND#112 GND#54 +3V
AH22 G6 AK7
SW@10u/6.3V_6 SW@1u/6.3V_4 VDDC#28 GND#113 GND#55
AH27 H9 AL11
VDDC#29 C117 C92 C52 C79 C95 C93 GND#114 GND#56
AF13 AH28 J2 AL14
VDDR4#4 VDDC#30 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 GND#115 GND#57 R65
AF15 M26 J27 AL17
120 ohm/300mA VDDR4#5 VDDC#31 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 GND#116 GND#58
AG13 N24 J6 AL2
L13 SW@SBY100505T-121Y-N/0.3A/120ohm_4
VDDR4 VDDR4#7 VDDC#32 GND#117 GND#59 *SW@10K_4
+1.8V_GPU AG15 N27 J8 AL20
R18 K14 AL21
R21 K7 AL23
C187 C183 VDDC#35 GND#120 GND#62
AD12 R23 L11 AL26
SW@0.1u/10V_4_X7R VDDR4#1 VDDC#36 GND#121 GND#63 R62
AF11 R26 L17 AL32
SW@1u/6.3V_4 VDDR4#2 VDDC#37 GND#122 GND#64
AF12 T17 L2 AL6
VDDR4#3 VDDC#38 GND#123 GND#65 SW@0_4
AG11 T20 L22 AL8
T22 L24 AM11
T24 L6 AM31
T27 M17 AM9
U16 M22 AN11
T1 VDDC#43 GND#128 GND#70
M20 U18 M24 AN2
T2 NC_VDDRHA VDDC#44 GND#129 GND#71
M21 U21 N16 AN30
NC_VSSRHA VDDC#45 GND#130 GND#72
U23 N18 AN6
U26 N2 AN8
T4 VDDC#47 GND#132 GND#74
V12 V17 N21 AP11
T3 NC_VDDRHB VDDC#48 GND#133 GND#75
U12 V20 N23 AP7
NC_VSSRHB VDDC#49 GND#134 GND#76
V22 N26 AP9
V24 N6 AR5
V27 R15 AW34
Y16 R17 B11
120 ohm/300mA PLL VDDC#53 GND#138 GND#80
(1.8V@40mA PCIE_PVDD) VDDC#54
Y18 R2
GND#139 GND#81
B13
+1.8V_GPU L55 SW@SBY100505T-121Y-N/0.3A/120ohm_4 PCIE_PVDD AB37 Y21 R20 B15
PCIE_PVDD VDDC#55 GND#140 GND#82
Y23 R22 B17
MPV18 VDDC#56 GND#141 GND#83
H7 Y26 R24 B19
B
C513 C515 C516 MPV18#1 VDDC#57 GND#142 GND#84 B
H8 Y28 R27 B21
SW@1u/6.3V_4 MPV18#2 VDDC#58 GND#143 GND#85
R6 B23
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R GND#144 GND#86
T11 B25
SPV18 GND#145 GND#87
AM10 T13 B27
120 ohm/300mA SPV18 GND#146 GND#88
(1.8V@150mA MPV18) VDDCI#1
AA13 T16
GND#147 GND#89
B29
+1.8V_GPU L1 SW@SBY100505T-121Y-N/0.3A/120ohm_4 SPV10 AN9 AB13 T18 B31
SPV10 VDDCI#2 GND#148 GND#90
AC12 T21 B33
VDDCI#3 C37 C106 C121 C71 C65 GND#149 GND#91
AN10 AC15 T23 B7
C11 C14 C20 SPVSS VDDCI#4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#150 GND#92
AD13 T26 B9
SW@1u/6.3V_4 VDDCI#5 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#151 GND#93
AD16 U15 C1
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R VDDCI#6 +VGPU_CORE GND#153 GND#94
M15 U17 C39
VDDCI#7 GND#154 GND#95
M16 U2 E35
VOLTAGE VDDCI#8 GND#155 GND#96
M18 U20 E5
120 ohm/300mA SENESE VDDCI#9 VDDCI L64 GND#156 GND#97
(1.8V@75mA SPV18) VDDCI#10
M23 U22
GND#157 GND#98
F11
L7 SW@SBY100505T-121Y-N/0.3A/120ohm_4 N13 UPB201212T-121Y-N(120,100M,5A)_8 +3V U24 F13
+1.8V_GPU VDDCI#11 GND#158 GND#99
T7 AF28 N15 U27
FB_VDDC VDDCI#12 C122 C105 C47 C45 C46 GND#159
VDDCI#13
N17 (DDR3 1.12V@4A VDDCI) or more U6
GND#160
C159 C154 N20 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 V11
VDDCI#14 GND#161
1
SW@0.1u/10V_4_X7R T6 AG28 N22 SW@1u/6.3V_4 SW@1u/6.3V_4 V16
SW@10u/6.3V_6 FB_VDDCI ISOLATED VDDCI#15 GND#163
R12 V18
CORE I/O VDDCI#16 R13 R125 V21
GND#164
VDDCI#17 GND#165 PowerXpress control signal for Park only
T8 AH29 R16 2 V23 If not used, can be disconnected.
120 ohm/300mA FB_GND VDDCI#18 *SW@0_6 GND#166
(1.0V@120mA SPV10) VDDCI#19
T12 V26
GND#167 PX_EN = LOW, turn on
+1V L8 SW@SBY100505T-121Y-N/0.3A/120ohm_4 T15 W2
VDDCI#20 GND#168 PX_EN = HIGH, turn off
V15 C35 C94 C49 Q35 SW@AO3413 1A W6
VDDCI#21 GND#169 PX_EN is used to turn ON/OFF some
Y13 SW@10u/6.3V_6 Y15
3
VDDCI#22 GND#170 regulators for PowerXpress mode. An
C160 C153 SW@10u/6.3V_6 SW@10u/6.3V_6 +3V_D_EXT Y17
SW@0.1u/10V_4_X7R GND#171 output high ¯3.3Vˇ will turn the regulators
Y20
SW@10u/6.3V_6 SW@Park_M2 C612 C611 C613 GND#172 OFF. An output low ¯0Vˇ will turn the
Y22 A39
GND#173 VSS_MECH#1 regulators ON. PX_EN outputs low (0V)
Y24 AW1
SW@1u/6.3V_4 GND#174 VSS_MECH#2 by default.
Y27 AW39
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R GND#175 VSS_MECH#3 If this signal is unused, it can be NC (not
U13
+3V GND#152 connected) or connected to ground.
V13
GPU power enable GPU all PWROK GND#162
GPU +3V_D power SW@Park_M2
+3V EC-C +3V +3V
R76 Fine-tune Power-on sequence
A Change from 100K to 4.7K SW@10K_4 R131 A
dGPU_VRON
1
2ms R549 R361 *SW@0_6
dGPU_PWREN SW@4.7K_4 SW@4.7K_4
dGPU_PWROK 11
R355 R73
3
SW@10K_4 EC-D 2
Q2 dGPU_PWREN R366 *SW@0_6
SW@2N7002K SW@0_4 EC-C
12 dGPU_PWR_EN dGPU_PWREN 40,41
3
SW@BAS316 D25 2 Q26 SW@AO3413 1A
3
11 dGPU_VRON
3
*SW@BAS316 D26 +1.5V_GPU R367

*SW@0_4
2
SW@DTC144EUA +3V_D PROJECT : ZQ2
C734 2 C573 Q27 C185 C180 C174
+1.8V_GPU
1
>1mS delay is required between all MXM power rail stable SW@0.1u/10V_4
1
and MXM_PWREN(enables the module internal power) SW@1u/6.3V_4 SW@1u/6.3V_4

Q25 SW@10u/6.3V_6 SW@0.1u/10V_4_X7R Size Document Number Rev
1
SW@PDTC143TT 1A
Madison/Park (PWR/GND)4/6
5 4 3 2 1
5 4 3 2 1
+1.8V_GPU
120 ohm/300mA
L14 SW@0_4
(1.8V@130mA DPA_VDD18)
DPA_VDD18
DPA_VDD18
U17H
DP C/D POWER DP A/B POWER
DPA_VDD18
DPA_VDD10
(1.0V@110mA DPA_VDD10)
C170 C165 C157

L10
120 ohm/300mA
SW@0_4
+1V
20
AP20 AN24
C192 C182 C188 DPC_VDD18#1 DPA_VDD18#1 *SW@1u/6.3V_4
AP21 AP24
*SW@1u/6.3V_4 DPC_VDD18#2 DPA_VDD18#2 *SW@10u/6.3V_6 *SW@0.1u/10V_4_X7R
*SW@10u/6.3V_6 *SW@0.1u/10V_4_X7R
D D
DPA_VDD10 AP13 AP31 DPA_VDD10
DPC_VDD10#1 DPA_VDD10#1
AT13 AP32
DPC_VDD10#2 DPA_VDD10#2
AN17 AN27
DPC_VSSR#1 DPA_VSSR#1
AP16 AP27
AP17 AP28
AW14 AW24
AW16 AW26
DPA_VDD18 AP22 AP25 DPA_VDD18

DPD_VDD18#1 DPB_VDD18#1
AP23 AP26
DPA_VDD10 AP14 AN33 DPA_VDD10

AP15 AP33
C AN19 AN29 C
DPD_VSSR#1 DPB_VSSR#1
AP18 AP29
AP19 AP30
AW20 AW30
AW22 AW32
R348 SW@150/F_4
DPCD_CALR AW18 AW28 DPAB_CALR R346 SW@150/F_4
DPCD_CALR DPAB_CALR
+1.8V_GPU
(1.8V@?mA DPA_PVDD) 120 ohm/300mA
DP E/F POWER DP PLL POWER
AH34 AU28 DPA_PVDD L62 SW@0_4
DPA_VDD18 DPE_VDD18#1 DPA_PVDD
AJ34 AV27
DPE_VDD18#2 DPA_PVSS
C544 C534 C537
*SW@1u/6.3V_4
*SW@10u/6.3V_6
*SW@0.1u/10V_4_X7R
AL33 AV29
DPA_VDD10 DPE_VDD10#1 DPB_PVDD
AM33 AR28
DPE_VDD10#2 DPB_PVSS
AN34 AU18
DPE_VSSR#1 DPC_PVDD
AP39 AV17
DPE_VSSR#2 DPC_PVSS
B AR39 B
DPE_VSSR#3
AU37
DPE_VSSR#4
AW35
DPE_VSSR#5
AV19
DPD_PVDD
AR18
DPD_PVSS
AF34
DPA_VDD18 DPF_VDD18#1
AG34
DPF_VDD18#2
AM37
DPE_PVDD
AN38
DPE_PVSS
AK33
DPA_VDD10 DPF_VDD10#1
AK34
DPF_VDD10#2
AL38
NC_DPF_PVDD
AM35
NC_DPF_PVSS
AF39
DPF_VSSR#1
AH39
DPF_VSSR#2
AK39
DPF_VSSR#3
AL34
DPF_VSSR#4
AM34
DPF_VSSR#5
A R343 SW@150/F_4DPEF_CALR AM39 A

DPEF_CALR
SW@Park_M2
PROJECT : ZQ2
Madison/Park (DP_PWR/GND)5/6 1A
17,19,21,41 +1.8V_GPU
16,17,19,41 +1V
5 4 3 2 1
5 4 3 2 1
21
PIN STRAPS Memory Aperture size
CONFIGURATION STRAPS
GPIO[13:11] Size ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
+3V_D THEY MUST NOT CONFLICT DURING RESET
R66 *SW@10K/F_4
17 GPU_GPIO13 000 128MB STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS DEFAULT REMARK
R67 *SW@10K/F_4
17 GPU_GPIO12
001 256MB
R64 SW@10K/F_4 TX_PWRS_ENB GPIO0 0 = 50% TX OUTPUT SWING 0
D 17 GPU_GPIO11 D
1 = FULL TX OUTPUT SWING
010 64MB
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0
R49 *SW@10K/F_4 0 = TX DE-EMPHASIS DISABLED
17 GPU_GPIO0
011 32MB 1 = TX DE-EMPHASIS ENABLED
R48 *SW@10K/F_4 ENABLE EXTERNAL BIOS ROM
17 GPU_GPIO1
BIOS_ROM_EN GPIO_22_ROMCSB 0 = DISABLE 0
1 = ENABLE
ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

R44 *SW@10K/F_4 NUMONYX M25P10A : 101 000 See ROM table
17 GPIO3_SMBDAT
R41 *SW@10K/F_4
17 GPIO4_SMBCLK
BIF_GEN2_EN_A GPIO2 0 = PCIE DEVICE AS 2.5GT/S CAPABLE 0
ROM Table 1 = PCIE DEVICE AS 5GT/S CAPABLE
SCS#_GPIO22 R74 *SW@10K/F_4
EXT_HSYNC EXT_VSYNC GPIO_8_ROMSO GPIO8
Discription H2SYNC H2SYNC Reserved Only 0
R63 *SW@10K/F_4 GPIO_21_BB_EN GPIO21
17 GPU_GPIO2
0 0 No Audio AUD[1:0]
R336 *SW@10K/F_4 AUD[1] HSYNC 00: NO AUDIO FUNCTION.
17 EXT_HSYNC
01: AUDIO FOR DISPLAYPORT AND HDMI IF
R335 *SW@10K/F_4 0 1 Any one by dectec AUD[0] VSYNC ADAPTER IS DETECTED. See Audio table
17 EXT_VSYNC 11
10: AUDIO FOR DISPLAYPORT ONLY.
SIN_GPIO9 R45 *SW@10K/F_4 1 0 DP only 11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.
R32 *SW@10K/F_4
17 V2SYNC
1 1 Both DP & HDMI GPIO_9_ROMSI GPIO9 0 = VGA controller capacity enable
C
0 C
VIP_DEVICE_STRAP_ENA V2SYNC 0 = DRIVER would ignore the value sample on VHAD_0 during RESET. 0
EEPROM DDR3 Memory Aperture size

U20
DDR3 Memory Aperture size
SIN_GPIO9 5 2 SOUT_GPIO8 RAM_STRAP2 RAM_STRAP1 RAM_STRAP0
17 SIN_GPIO9 D Q SOUT_GPIO8 17
Vendor Vendor P/N STN B/S P/N GPU
17 SCLK_GPIO10 6
C DVPDATA_2 DVPDATA_1 DVPDATA_0
SCS#_GPIO22 1 AKD5LZGTW 04
17 SCS#_GPIO22 S
H5TQ1G63BFR-12C Park
+3V_D_EXT 7
HOLD
(64M*16) 1 1 0
R356 *SW@10K_4 3 Hynix AKD5LZGTW 04
W
H5TQ1G63BFR-12C Madison
R364
8
VCC VSS
4 (64M*16) 1 0 0
*SW@10K_4 *SW@M25P10-AVMN6P
C548
*SW@0.1u/10V_4 2Gb 1 1 1
B B
AKD5LGGT506
D09 K4W 1G1646E-HC12 Park
(64M*16) 0 1 0
AKD5LGGT506
Thermal Sensor K4W 1G1646E-HC12 Madison
Samsung (64M*16) 0 0 0
K4W 2G1646B-HC12 AKD5MGGT500 2Gb 0 0 1
Vendor P/N
WINDBOND AL83L771K01 23EY2387MA12-SZ AKD5LGGT700 Park 0 1 1
GMT AL000780000 USD0.16 AMD
+3V_D_EXT
23EY2387MA12-SZ AKD5LGGT700 Madison 1 0 1
+3V_D_EXT
R344 R637
SW@10K_4 *SW@10K_4
C540 SW@0.1u/10V_4_X7R Samsung-1GB +1.8V_GPU
U19
R358 *SP@10K/F_4
17 RAM_STRAP2
8 1
A
33 MXM_SMCLK12 SCLK VCC GPU_D+ 17 R365 SP@10K/F_4 RAM_STRAP2 SET DDR3 Vendor A
7 2 C531
33 MXM_SMDATA12 SDA DXP RAM_STRAP[1:0] SET SIZE.
6 3 SW@2200p/50V_4
17 ALT#_GPIO17 ALERT# DXN R363 SP@10K/F_4
GPU_D- 17 17 RAM_STRAP1
33 VGA_THERM# 4 5
OVERT# GND R360 *SP@10K/F_4
PROJECT : ZQ2
SW@G780-1P81U(MSOP)
R359 *SP@10K/F_4 Quanta Computer Inc.
Address ID: 98H 17 RAM_STRAP0
R72 SP@10K/F_4 Size Document Number Rev
Medison/Park Strip/Thermal 6/6 1A

5 4 3 2 1
5 4 3 2 1
CHANNEL B: 512MB DDR3 (64M*16*4pcs)

18 VMB_DQ[63..0]
18 VMB_DM[7..0]
18 VMB_RDQS[7..0]
VMB_DQ[63..0]
VMB_DM[7..0]
VMB_RDQS[7..0]
VMB_WDQS[7..0]
QSA[7..0]
U2 U16
U18 U3
22
18 VMB_WDQS[7..0] QSA#[7..0]
VREFC_VMB3 M8 E3 VMB_DQ36 VREFC_VMB4 M8 E3 VMB_DQ54
VREFC_VMB1 VMB_DQ6 VREFC_VMB2 VMB_DQ17 VREFD_VMB3 VREFCA DQL0 VMB_DQ39 VREFD_VMB4 VREFCA DQL0 VMB_DQ51
M8 E3 M8 E3 H1 F7 H1 F7
VREFD_VMB1 VREFCA DQL0 VMB_DQ3 VREFD_VMB2 VREFCA DQL0 VMB_DQ23 VREFDQ DQL1 VMB_DQ33 VREFDQ DQL1 VMB_DQ53
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQL2 F2 DQL2 F2
F2 VMB_DQ5 F2 VMB_DQ18 VMB_MA0 N3 F8 VMB_DQ34 VMB_MA0 N3 F8 VMB_DQ50
18
18
VMB_MA0
VMB_MA1
VMB_MA0
VMB_MA1
VMB_MA2
N3
P7
A0
A1
DQL2
DQL3
DQL4
F8
H3
VMB_DQ1
VMB_DQ7
VMB_DQ0 0
VMB_MA0
VMB_MA1
VMB_MA2
N3
P7
A0
A1
DQL2
DQL3
DQL4
F8
H3
VMB_DQ16
VMB_DQ20
VMB_DQ22 2
VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ37
VMB_DQ32
VMB_DQ38
4 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ52
VMB_DQ48
VMB_DQ55
6
18 VMB_MA2 P3 H8 P3 H8 N2 G2 N2 G2
VMB_MA3 A2 DQL5 VMB_DQ4 VMB_MA3 A2 DQL5 VMB_DQ19 VMB_MA4 A3 DQL6 VMB_DQ35 VMB_MA4 A3 DQL6 VMB_DQ49
18 VMB_MA3 N2 A3 DQL6 G2 N2 A3 DQL6 G2 P8 A4 DQL7 H7 P8 A4 DQL7 H7
VMB_MA4 P8 H7 VMB_DQ2 VMB_MA4 P8 H7 VMB_DQ21 VMB_MA5 P2 VMB_MA5 P2
D 18 VMB_MA4 A4 DQL7 A4 DQL7 A5 A5 D
VMB_MA5 P2 VMB_MA5 P2 VMB_MA6 R8 VMB_MA6 R8
18 VMB_MA5 A5 A5 A6 A6
VMB_MA6 R8 VMB_MA6 R8 VMB_MA7 R2 D7 VMB_DQ62 VMB_MA7 R2 D7 VMB_DQ41
18 VMB_MA6 A6 A6 A7 DQU0 A7 DQU0
VMB_MA7 R2 D7 VMB_DQ24 VMB_MA7 R2 D7 VMB_DQ15 VMB_MA8 T8 C3 VMB_DQ56 VMB_MA8 T8 C3 VMB_DQ46
18 VMB_MA7 A7 DQU0 A7 DQU0 A8 DQU1 A8 DQU1
VMB_MA8 T8 C3 VMB_DQ31 VMB_MA8 T8 C3 VMB_DQ10 VMB_MA9 R3 C8 VMB_DQ63 VMB_MA9 R3 C8 VMB_DQ40
18
18
18
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA9
VMB_MA10
VMB_MA11
R3
L7
A8
A9
A10/AP
DQU1
DQU2
DQU3
C8
C2
VMB_DQ28
VMB_DQ30
VMB_DQ26 3
VMB_MA9
VMB_MA10
VMB_MA11
R3
L7
A8
A9
A10/AP
DQU1
DQU2
DQU3
C8
C2
VMB_DQ14
VMB_DQ11
VMB_DQ12 1
VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ58
VMB_DQ61
VMB_DQ57
7 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ42
VMB_DQ44
VMB_DQ45
5
18 VMB_MA11 R7 A11 DQU4 A7 R7 A11 DQU4 A7 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2
VMB_MA12 N7 A2 VMB_DQ27 VMB_MA12 N7 A2 VMB_DQ9 VMB_MA13 T3 B8 VMB_DQ60 VMB_MA13 T3 B8 VMB_DQ43
18 VMB_MA12 A12/BC DQU5 A12/BC DQU5 A13 DQU6 A13 DQU6
VMB_MA13 T3 B8 VMB_DQ25 VMB_MA13 T3 B8 VMB_DQ13 T7 A3 VMB_DQ59 T7 A3 VMB_DQ47
18 VMB_MA13 A13 DQU6 A13 DQU6 A14 DQU7 A14 DQU7
T7 A3 VMB_DQ29 T7 A3 VMB_DQ8 M7 M7
A14 DQU7 A14 DQU7 A15 +1.5V_GPU A15 +1.5V_GPU
M7 A15 M7 A15
+1.5V_GPU +1.5V_GPU
VMB_BA0 M2 B2 VMB_BA0 M2 B2
VMB_BA0 VMB_BA0 VMB_BA1 BA0 VDD#B2 VMB_BA1 BA0 VDD#B2
18 VMB_BA0 M2 B2 M2 B2 N8 D9 N8 D9
VMB_BA1 BA0 VDD#B2 VMB_BA1 BA0 VDD#B2 VMB_BA2 BA1 VDD#D9 VMB_BA2 BA1 VDD#D9
18 VMB_BA1 N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9 M3 BA2 VDD#G7 G7 M3 BA2 VDD#G7 G7
VMB_BA2 M3 G7 VMB_BA2 M3 G7 K2 K2
18 VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 VDD#K2 VDD#K2
VDD#K2 K2 VDD#K2 K2 VDD#K8 K8 VDD#K8 K8
K8 K8 N1 N1
VDD#K8 VDD#K8 VMB_CLKP1 VDD#N1 VMB_CLKP1 VDD#N1
VDD#N1 N1 VDD#N1 N1 18 VMB_CLKP1 J7 CK VDD#N9 N9 J7 CK VDD#N9 N9
VMB_CLKP0 J7 N9 VMB_CLKP0 J7 N9 VMB_CLKN1 K7 R1 VMB_CLKN1 K7 R1
18 VMB_CLKP0 CK VDD#N9 CK VDD#N9 18 VMB_CLKN1 CK VDD#R1 CK VDD#R1
VMB_CLKN0 K7 R1 VMB_CLKN0 K7 R1 VMB_CKE1 K9 R9 VMB_CKE1 K9 R9
18 VMB_CLKN0 CK VDD#R1 CK VDD#R1 18 VMB_CKE1 CKE VDD#R9 CKE VDD#R9
VMB_CKE0 K9 R9 VMB_CKE0 K9 R9 +1.5V_GPU +1.5V_GPU
18 VMB_CKE0 CKE VDD#R9 CKE VDD#R9
+1.5V_GPU +1.5V_GPU
VMB_ODT1 K1 A1 VMB_ODT1 K1 A1
18 VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_CS1# L2 A8 VMB_CS1# L2 A8
18 VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 18 VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_CS0# L2 A8 VMB_CS0# L2 A8 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
18 VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 18 VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_CAS1# K3 C9 VMB_CAS1# K3 C9
18 VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 18 VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_CAS0# K3 C9 VMB_CAS0# K3 C9 VMB_WE1# L3 D2 VMB_WE1# L3 D2
18 VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 18 VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
VMB_WE0# L3 D2 VMB_WE0# L3 D2 E9 E9
18 VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 VDDQ#E9 VDDQ#E9
E9 E9 F1 F1
VDDQ#E9 VDDQ#E9 VMB_RDQS4 VDDQ#F1 VMB_RDQS6 VDDQ#F1
F1 F1 F3 H2 F3 H2
VMB_RDQS0 VDDQ#F1 VMB_RDQS2 VDDQ#F1 VMB_RDQS7 DQSL VDDQ#H2 VMB_RDQS5 DQSL VDDQ#H2
F3 DQSL VDDQ#H2 H2 F3 DQSL VDDQ#H2 H2 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9
VMB_RDQS3 C7 H9 VMB_RDQS1 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9
VMB_DM4 E7 A9 VMB_DM6 E7 A9
VMB_DM0 VMB_DM2 VMB_DM7 DML VSS#A9 VMB_DM5 DML VSS#A9
E7 DML VSS#A9 A9 E7 DML VSS#A9 A9 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3
VMB_DM3 D3 B3 VMB_DM1 D3 B3 E1 E1
DMU VSS#B3 DMU VSS#B3 VSS#E1 VSS#E1
C E1 E1 G8 G8 C
VSS#E1 VSS#E1 VMB_WDQS4 VSS#G8 VMB_WDQS6 VSS#G8
G8 G8 G3 J2 G3 J2
VMB_WDQS0 VSS#G8 VMB_WDQS2 VSS#G8 VMB_WDQS7 DQSL VSS#J2 VMB_WDQS5 DQSL VSS#J2
G3 DQSL VSS#J2 J2 G3 DQSL VSS#J2 J2 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8
VMB_WDQS3 B7 J8 VMB_WDQS1 B7 J8 M1 M1
DQSU VSS#J8 DQSU VSS#J8 VSS#M1 VSS#M1
VSS#M1 M1 VSS#M1 M1 VSS#M9 M9 VSS#M9 M9
M9 M9 P1 P1
VSS#M9 VSS#M9 MEM_RST# VSS#P1 MEM_RST# VSS#P1
VSS#P1 P1 VSS#P1 P1 T2 RESET VSS#P9 P9 T2 RESET VSS#P9 P9
MEM_RST# T2 P9 MEM_RST# T2 P9 T1 T1
18 MEM_RST# RESET VSS#P9 RESET VSS#P9 VMB_ZQ3 VSS#T1 VMB_ZQ4 VSS#T1
VSS#T1 T1 VSS#T1 T1 L8 ZQ VSS#T9 T9 L8 ZQ VSS#T9 T9
VMB_ZQ1 L8 T9 VMB_ZQ2 L8 T9
ZQ VSS#T9 ZQ VSS#T9
VSSQ#B1 B1 VSSQ#B1 B1
VSSQ#B1 B1 VSSQ#B1 B1 VSSQ#B9 B9 VSSQ#B9 B9
B9 B9 R342 D1 R52 D1
R15 VSSQ#B9 R332 VSSQ#B9 VSSQ#D1 VSSQ#D1
D1 D1 SW@240/F_4 D8 SW@240/F_4 D8
VSSQ#D1 VSSQ#D1 VSSQ#D8 VSSQ#D8
SW@240/F_4 D8 SW@240/F_4 D8 E2 E2
VSSQ#D8 VSSQ#D8 VSSQ#E2 VSSQ#E2
VSSQ#E2 E2 VSSQ#E2 E2 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8
J1 E8 J1 E8 L1 F9 L1 F9
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 100-BALL 100-BALL
100-BALL 100-BALL SDRAM DDR3 SDRAM DDR3
SDRAM DDR3 SDRAM DDR3 SW@VRAM _DDR3 SW@VRAM _DDR3
SW@VRAM _DDR3 SW@VRAM _DDR3
BOT Down TOP Down TOP Up BOT Up
Group-B0 VREF Group-B1 VREF

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R16 R8 R334 R331 R36 R341 R37 R61

SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4
VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4
R24 C31 R12 C13 R333 C503 R330 C498 R46 C142 R340 C521 R47 C137 R60 C155
SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R
SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4
Group-B0 decoupling CAP Group-B1 decoupling CAP

MEM_B0 CLK MEM_B1 CLK
+1.5V_GPU +1.5V_GPU
VMB_CLKP1
VMB_CLKP0 VMB_CLKN1
C499 C507 C496 C501 C497 C9 C113 C145 C162 C166 C96 C519 C148 C152 C520
VMB_CLKN0 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 R58 R59
SW@56.2/F_4
R11 R9 SW@56.2/F_4
SW@56.2/F_4 +1.5V_GPU +1.5V_GPU
SW@56.2/F_4
A C146 A
C506 C123 C4 C7 C25 C505 C6 C101 C511 C177 C78 C158 C510 C512 C518 SW@0.01u/25V_4
C12 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4
SW@0.01u/25V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4
+1.5V_GPU +1.5V_GPU
PROJECT : ZQ2
C21 C1 C509 C508 C504 C173 C34 C514 C69 C517
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6 SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
MEMORY 2 channel B 1A

5 4 3 2 1
1 2 3 4 5 6 7 8
CRT
C571
C202
C204
*.1u_4 CRTVDD5
*10p/50V_4 CRTVSYNC
*10p/50V_4 CRTHSYNC
23
EC-C
C581 0.22u/6.3V_4
C545 10p/50V_4 DDCCLK_1 1A/30V D17
C546 10p/50V_4 DDCDAT_1 F1 2 1 SMD1206P100TF CRTVDD5
16
+5V 2 1
CN15
A A
D12 CRT
RSX101M-30
6
CRTVDD5 INT_CRT_RED L22 BLM18BA470SN1_6 CRT_R1 1 11 CRT_11 T28
9 INT_CRT_RED
7
C541 INT_CRT_GRE L21 BLM18BA470SN1_6 CRT_G1 2 12 DDCDAT_1
9 INT_CRT_GRE
*4.7U/6.3V_6 8
+3V
INT_CRT_BLU L20 BLM18BA470SN1_6 CRT_B1 3 13 CRTHSYNC
9 INT_CRT_BLU
C206 9
4 14 CRTVSYNC
0.1u/10V_4 U21 R128 R127 R126 D08 10
1 16 CRT_VSYNC1 R89 *Short_4 CRTVSYNC C222 C221 C220 C212 C213 C214 5 15 DDCCLK_1
VCC_SYNC SYNC_OUT2 CRT_HSYNC1 R93 *Short_4 CRTHSYNC 140/F_4 150/F_4 150/F_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4
14
SYNC_OUT1
7
C577 .22u/25V_6 CRT_BYP VCC_DDC
8
17
BYP INT_CRT_VSYNC
15 INT_CRT_VSYNC 9
SYNC_IN2 INT_CRT_HSYNC
+3V 2
VCC_VIDEO SYNC_IN1
13 INT_CRT_HSYNC 9 EC-C EC-C
C586
CRT_R1 3 10 INT_DDCCLK
0.1u/10V_4 CRT_G1 VIDEO_1 DDC_IN1 INT_DDCDATA
4 11
CRT_B1 VIDEO_2 DDC_IN2
5
VIDEO_3 DDCCLK_1 R351 2.7K_4 CRTVDD5
9
DDC_OUT1 DDCDAT_1 R354 2.7K_4
6 12
GND DDC_OUT2
CM2009-02QR
INT_DDCDATA R353 2.7K_4

9 INT_DDCDATA
INT_DDCCLK R352 2.7K_4 +3V
9 INT_DDCCLK
B B
LVDS(LDS) LCD PW(LDS) +3V

CN4
G_0
+3V LCDVCC
1
2 U4
3 G_1 C168
R117 4.7K_4 INT_EDIDCLK INT_EDIDCLK 4 1U/10V_4 R421 *Short_6 LCDVCC
+3V 9 INT_EDIDCLK 6 1
R114 4.7K_4 INT_EDIDDATA INT_EDIDDATA 5 IN OUT
9 INT_EDIDDATA 6
4 2
7 IN GND C198 C197 C196 C199
9 LA_DATAN0 8
9 LA_DATAP0 9 INT_LVDS_DIGON 3 5
9 ON/OFF GND 1U/10V_4 *.1u_4 0.01u/16V_4
22u_8
10
9 LA_DATAN1 11 IC(5P) G5243T11U
9 LA_DATAP1 12 R77
13
9 LA_DATAN2 14 100K_4
9 LA_DATAP2 15 G_2
16
9 LA_CLK# 17
9 LA_CLK 18
19
Ra- for DIS 20
B02 C02 21
Rb- for UMA Ra
C
33 CONTRAST
R54
R50
*0_4
0_4 LVDS_BRIGHT
22
23
Backlight Control(LDS) C
9 INT_DPST_PWM Rb 24
BL_ON
+3V 25
VIN 33 DCR_EN 26 +3V
27
0.8A 28 G_4
VIN R40 *Short_8
C2 C167 R34 *Short_8 INVCC0 29
G_3
C116 C133 30
0.1u/50V_6 1000p/50V_4 R311
4.7u/25V_8 1000p/50V_4 LVDS-A30SFYG+
10K_4
BL_ON D16 2 1 BAS316 LID591# 30,33
R320
10K_4
3
CAMERA Module(CCD)
3
BL# 2
EC-C EC-C 2 EC_FPBACK# 33
3
EC-C Q20
CN3 2N7002K Q21
USBP13+ +3V R116*Short_6 DMIC_POWER 1 DTC144EUA
12 USBP13+
1
USBP13- R6 *Short_6 CCD_POWER 2 2
12 USBP13- 9 INT_LVDS_BLON
USBP13- 3
USBP13+ 4 Q22
5 2N7002K
6 R318
1
D R481 33_6 DMIC_CLK_R 7 9 D
28 DMIC_CLK
28 DMIC_DAT R484 33_6 DMIC_DAT_R 8 10 100K_4
C699 C695 CCD&MIC

+3V
2
*22P/50V_4 *22P/50V_4
C610 C409 PROJECT : ZQ2

1
EC-C C527
0.1u/50V_6 1000p/50V_4 1000p/50V_6
11/19
CRT/LVDS/LID 1A

1 2 3 4 5 6 7 8
5 4 3 2 1
HDMI HPD SENSE

(HDM)
Close to HDMI Connector
R172 715/F_4 TX2_HDMI+
+3V
R135
24
10K/F_4
R171 715/F_4 TX2_HDMI-
+5V
3
D R169 715/F_4 TX1_HDMI+ D
Q11
2N7002E R163 715/F_4 TX1_HDMI-
3
2 +3V
R176 715/F_4 TX0_HDMI+ Q10
R143
2N7002E
R173 715/F_4 TX0_HDMI- 2 HDMI_DET_R HDMI_DET
10K/F_4
1
R145 R159 715/F_4 TXC_HDMI+ R141 R144

200K/F_4
200K/F_4
R157 715/F_4 TXC_HDMI-
1
100K/F_4 R142 *Short_4
9 INT_HDMI_HPD
3
Q9
2N7002E
USE RS880M to display the HDMI 2 R136 *Short_4
HDMI_HPD_EC# 33
Stuff 715 ohm P/N--> CS17152FB17
1
C C
HDMI PORT
CN17
20
EMI reserve for HDMI(HDM) ESD Protect 8 TX2_HDMI+
TX2_HDMI+ 1
SHELL1
D2+SHELL3
22
2
TX2_HDMI- D2 Shield
8 TX2_HDMI- 3
TX1_HDMI+ D2-
Close connector close to HDMI connector 8 TX1_HDMI+ 4
D1+
5
TX1_HDMI- D1 Shield
8 TX1_HDMI- 6
U7 TX0_HDMI+ D1-
8 TX0_HDMI+ 7
TX2_HDMI+ HDMI_DDC_CLK HDMI_DDC_CLK D0+
1 10 8
HDMI_DDC_DATA 1 10 HDMI_DDC_DATA TX0_HDMI- D0 Shield
2 9 8 TX0_HDMI- 9
R174 2 9 TXC_HDMI+ D0-
3 8 TXC_HDMI+ 10
100/F_4 GND_3/8 CK+
4 7 11
TX2_HDMI- HDMI_DET 4 7 HDMI_DET TXC_HDMI- CK Shield
5 6 8 TXC_HDMI- 12
5 6 CK-
13
TX1_HDMI+ *RClamp0524P CE Remote
14
HDMI_DDC_CLK NC
9 HDMI_DDC_CLK 15
R170 U8 F2 HDMI_DDC_DATA DDC CLK
9 HDMI_DDC_DATA 16
100/F_4 TX1_HDMI+ TX1_HDMI+ SMD1206P100TF DDC DATA
B 1 10 17 B
TX1_HDMI- TX1_HDMI- 1 10 TX1_HDMI- D4 2 +5V_HDMI GND
2 9 +5V 2 1 1 18
2 9 RSX101M-30 HDMI_DET +5V
3 19 23
TX0_HDMI+ TXC_HDMI+ GND_3/8 TXC_HDMI+ HP DET
SHELL4
4
4 7
7 EC-C SHELL2
21
TXC_HDMI- 5 6 TXC_HDMI-
R177 5 6 C277 QJ1119C-NK01-8F
100/F_4 *RClamp0524P
TX0_HDMI- 0.22u/6.3V_4
U9
TXC_HDMI+ TX0_HDMI+ 1 10 TX0_HDMI+
TX0_HDMI- 1 10 TX0_HDMI-
2 9
R164 2 9
3
100/F_4 TX2_HDMI+ GND_3/8 TX2_HDMI+ +5V
4 7
TXC_HDMI- TX2_HDMI- 4 7 TX2_HDMI-
5 6
5 6
*RClamp0524P HDMI_DDC_CLK R156 4.7K_4
HDMI_DDC_DATA R155 4.7K_4
A A
PROJECT : ZQ2
+5V 23,27,28,32,35,42
+3V 2,4,5,9..15,19,23,26,28..33,35..42
HDMI 1A

5 4 3 2 1
5 4 3 2 1
Giga-LAN AR8151
+3V_S5
R238 *Short_6 +3V_LAN

close Pin1 +3V_LAN
25
C415 C416 C414 C413 C412 U12
10u/6.3V_8 10u/6.3V_8 1u/6.3V_4 0.1u/10V_4 *1000p/50V_4 1 22 AVDDH C398 0.1u/10V_4

9/16 VDD33 AVDDH
2 23 T47
11,16,26 A_RST# PERSTn CLKREQn/LED2
D 3 24 DVDDL C401 0.1u/10V_4 D
12,26 PCIE_WAKE# WAKEn DVDDL
R235 *Short_4 8151_CLKREQ# 4 25 SMCLK_8151 R435 *0_4
12 CLK_PCIE_LAN_REQ# CLKREQn SMCLK PCLK_SMB 5,12,26
C633 0.1u/10V_4 +VDDCT 5 VDDCT
AR8151
5X5mm SMDATA 26 SMDATA_8151 R439 *0_4
PDAT_SMB 5,12,26
C406 1u/6.3V_4 AVDDL 6 40-Pin QFN 27 SMBus PU at PCH side already
AVDDL_REG TESTMODE
C408 0.1u/10V_4 XTLO 7 28 R648 *0_4 AVDDH
XTLO TEST_RST
XTLI 8 29 PCIE_RXN6_C C407 0.1u/10V_4
XTLI TX_N PCIE_RX1- 8
C393 1u/6.3V_4 AVDDH 9 30 PCIE_RXP6_C C410 0.1u/10V_4
AVDDH_REG TX_P PCIE_RX1+ 8
C394 0.1u/10V_4 R426 2.37K/F_4 RBIAS 10 31 AVDDL C419 0.1u/10V_4
RBIAS AVDDL
TX0P 11 32
TRXP0 REFCLK_N CLK_PCIE_LOM# 11
Wake# and CLKREQ# PU at PCH side already TX0N 12 33
TRXN0 REFCLK_P CLK_PCIE_LOM 11
C622 0.1u/10V_4 AVDDL 13 34 AVDDL C420 0.1u/10V_4
NC/AVDDL AVDDL
TX1P 14 35
TRXP1 RX_P PCIE_TX1+ 8
TX1N 15 36
TRXN1 RX_N PCIE_TX1- 8
C623 0.1u/10V_4 AVDDH 16 37 DVDDL C417 1u/6.3V_4
C399 33p/50V_4 XTLO NC/AVDDH DVDDL_REG C418 0.1u/10V_4
TX2P 17 38 LAN_ACTLED R239 5.1K_4
NC/TRXP2 LED0
1
1.2H Y2 TX2N 18 39 LAN_LINKLED#

25MHz NC/TRXN2 LED1
C624 0.1u/10V_4 AVDDL 19 40 LX L67 4.7uH/1A_2X2 +VDDCT
2
C
C396 33p/50V_4 XTLI NC/AVDDL LX C
TX3P 20 41 C648 C647 C650
NC/TRXP3 GND
TX3N 21 Layout : *1000p/50V_4 0.1u/10V_4 10u/6.3V_8
NC/TRXN3
AR8151 need isolate GND RJ45(LAN)
TRANSFORMER(LAN) CN20
9
LAN_ACTLED R400 220_8 YELLOW_N
10
YELLOW_P
TX0P
TX1P
TX0N
TX1N
GND2 14
X-TX0P 1 13
0+ GND1
R222
R221
R220
R219
X-TX0N 2
X-TX1P 0-
reverse 1000p*4 for EMI X-TX2P
3
1+
4
X-TX2N 2+
Close Transformer U28 5
2-
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
X-TX1N 6
X-TX3P 1-
7 3+
AVDD_CEN L36 +VDDCT X-TX3N 8
PBY160808T-181Y-N/2A/180ohm_6 3-
+3V_LAN
LAN_N1
LAN_N2
reverse 1000p*4 for EMI C381 1U/10V_4 LAN_LINKLED# 11

R223 220_8 LAN_LNK_LED_PWR GREEN_N
12
GREEN_P
EC-D
U26 RJ45
B C378 C377 C356 0.1u/10V_4 1 24 B
TX0P TCT1 MCT1 X-TX0P
2 23
0.1U/10V_4 0.1U/10V_4 TX0N TD1+ MX1+ X-TX0N
3 22
TD1- MX1-
C359 0.1u/10V_4 4 21
5 TD2+ MX2+ 20
TX1N 6 19 X-TX1N
TD2- MX2-
C366 0.1u/10V_4 7 18
8 17
TX2N TD3+ MX3+ X-TX2N
9 16
TD3- MX3- LAN_ACTLED
TX2P
TX3P
TX2N
TX3N
C372 0.1u/10V_4 10 15
TX3P TCT4 MCT4 X-TX3P LAN_LINKLED#
11 14
TD4+ MX4+
R218
R217
R216
R215
TX3N 12 13 X-TX3N
TD4- MX4-
TRANSFORMER
C605 C619
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
R197 R200 R207 R213 *0.1u//50V_8 *0.1u//50V_8

Delta LFE9276C-R (DB0ZR1LAN00) 75/F_8 75/F_8 75/F_8 75/F_8
FCE NS892407 (DB0LL1LAN00)
LAN_N3
LAN_N4
Bothhand GST5009B (DB0Z06LAN00)
C376 C375 C391

1500p/3KV_18
0.1U/10V_4 0.1u/10V_4
A A
PROJECT : ZQ2
LAN (AR8151) 1A

5 4 3 2 1
5 4 3 2 1
MINI-CARD WLAN(MPC)
+3.3V: 1000mA
+3.3Vaux:330mA
+1.5V:500mA CN23
H=5.6mm
+3V
R454 *Short_8 +WL_VDD

26
51 52 +WL_VDD
Reserved +3.3V R469 *10K_4 C655 C663 C677 C711
49 50 +WL_VDD
R465 *Short_4 PCIRST#_R_2 Reserved GND 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
11,29 PCIE_RST# 47 48 +1.5V_WL
R466 *Short_4 PCLK_DEBUG_R_2 Reserved +1.5V 10U/6.3V_8
11 PCLK_DEBUG 45 46
Reserved LED_WPAN# R467 *Short_4
43 44 RF_LED# 31,33
Reserved LED_WLAN# R468 *Short_4
+WL_VDD 41 42
Reserved LED_WWAN#
39 40
D Reserved GND D
37 38 USBP4+ 12
Reserved USB_D+
35 36 USBP4- 12
GND USB_D-
8 PCIE_TXP2 33 34
PETp0 GND R470 *0_4
8 PCIE_TXN2 31 32 PDAT_SMB 5,12,25
PETn0 SMB_DATA R475 *0_4
29 30 PCLK_SMB 5,12,25
GND SMB_CLK
27 28 +1.5V_WL
GND +1.5V
8 PCIE_RXP2 25 26
PERp0 GND +1.5V
8 PCIE_RXN2 23 24 +WL_VDD
PERn0 +3.3Vaux
21 22 A_RST# 11,16,25
GND PERST#
19 20 RF_EN 33
UIM_C4 W_DISABLE# +1.5V_WL R27 *Short_6
17 18
UIM_C8 GND
EC-C
15 16 A_LFRAME#_R_2 R485 *Short_4 LPC_LFRAME#
GND UIM_VPP LPC_LFRAME# 11,33
13 14 A_LAD3_R_2 R487 *Short_4 LPC_LAD3 C702 C674 C659
11 CLK_PCIE_WLANP_2 REFCLK+ UIM_RST LPC_LAD3 11,33
11 12 A_LAD2_R_2 R489 *Short_4 LPC_LAD2 1000p/50V_4 0.1u/10V_4 10u/6.3V_8
11 CLK_PCIE_WLANN_2 REFCLK- UIM_CLK LPC_LAD2 11,33
9 10 A_LAD1_R_2 R490 *Short_4 LPC_LAD1
GND UIM_DATA LPC_LAD1 11,33
7 8 A_LAD0_R_2 R493 *Short_4 LPC_LAD0
12 CLK_PCIE_2_REQ# CLKREQ# UIM_PWR LPC_LAD0 11,33
5 6 +1.5V_WL
Q33 Reserved +1.5V
3 4
GND
GND
WLAN_WAKE#_2 Reserved GND
12,25 PCIE_WAKE# 3 1 1 2 +WL_VDD
WAKE# +3.3V
*2N7002E MINI-CARD 5.6H
53
54
2
8/28 modify
R519 *10K_4
+WL_VDD
C C
B B
A A
PROJECT : ZQ2
Mini-Card/WL 1A

5 4 3 2 1
1 2 3 4
SATA HDD(HDD)
CN22
SATA ODD (ODD)
27
23
GND23 CN16
1 14
GND1 GND14
2 SATA_TX0+ 13
A RXP A
3 SATA_TX0- 13 1
RXN GND
4 2 SATA_TX1+ 13
GND2 SATA_RX0-_C C672 0.01u/16V_4 A+
5 SATA_RX0- 13 3 SATA_TX1- 13
TXN SATA_RX0+_C C666 0.01u/16V_4 A-
6 SATA_RX0+ 13 4
TXP GND SATA_RX1-_C C604 0.01u/16V_4
7 5 SATA_RX1- 13
GND3 B- SATA_RX1+_C C603 0.01u/16V_4
6 SATA_RX1+ 13
B+
7
GND +5V_ODD
8
3.3V
3.3V
9 B03
10 8 SATA_DP R397 1K_4 1.8A (MAX.)
3.3V DP
11 9
GND 5V
12 10
GND 5V
+
13 11 C275 C273 C261 C271 C602
GND MD C601
14 12
5V GND 0.01u/16V_4 0.01u/16V_4 *0.1u/10V_4 *0.1u/10V_4 *10u/6.3V_6 100u/6.3V_3528
15 +5V_HDD 13
5V GND
16
5V
17 15
GND GND15
18
RSVD SP@SATA_ODD
19
GND +5V_HDD
20
12V
21
12V
22 1A (MAX.)
12V R425 *Short_8
+5V
24
B GND24 JV-12.7mm(H=5.5mm)-ZQ2 JM-9.5mm(H=2.4mm)-ZQ2B B
+
C630 C632 C634 C639 C637

SATA_HDD C625
100u/6.3V_3528 10u/6.3V_6 0.1u/10V_4 *0.1u/10V_4 0.01u/16V_4 0.01u/16V_4
Main DFHS13FR017 Main DFHS13FR078, DFHS13FR077
Second DFHS13FR006, DFHS13FR005 Second DFHS13FR075
B03
1.8A (MAX.)
Q37
+5V AO6402A +5V_ODD_R +5V_ODD
ODD POWER(ODD) +3VPCU
6
5 4 R429 *Short_8
C 2 C
1
1
R278
100K R225
3
+15V 2 1 MOD_EN_5V
100K
3
2
3
Q38
1
DMN601K-7
C614
1
33 EC_ODD_EN R419 0_4 ODD_EN 2 0.1u/25V_6
2
1
11 PCH_ODD_EN R420 *0_4 Q39
DMN601K-7
R133
1
*100K
2
D D
PROJECT : ZQ2
SATA-HDD/ODD/HOLE 1A

1 2 3 4
5 4 3 2 1
28
HPR
Codec(ADO) HPL
LINE-OUT/SPDIFO(AMP) +3V_SPD
reverse R441
R275 *0_4 ADOGND +3V 1 3
R495 0_4 MIC1-VREFO-L Q32 C715

BSS84
2
MIC1-VREFO-R LINEOUT_JD: 0.22u/6.3V_4
reverse R429
MIC1-VREFO-L-R
ADOGND HP not insert->H
EC-C HP insert->L
R280 *0_4 MIC1-VREFO-L ADOGND CN25
HP_JD 1
C705 10u/6.3V_6 ADOGND 68ohm ohm 2
C692 HPL R286 68_4 HPL-1 L52 BK1608LL121/150mA/120ohm_6 HPL_SYS 3

Place next to pin 27 HPR R289 68_4 HPR-1 L54 BK1608LL121/150mA/120ohm_6 HPR_SYS 4
+
2.2u/6.3V_6 5
ADOGND
R298 R282 C489 C477
D 7 LED D
C710 C713 *1K_4 *1K_4 2200p/50V_4 2200p/50V_4 SPDIF_OUT 8 Drive
C690 ADOGND +5VA 6 IC
10u/6.3V_6 0.1u/10V_4
+5VA +
SPDIF_BLACK
2.2u/6.3V_6 ADOGND
Normal OPEN Jack
C683 C688 PN: AL000271000 C721
10u/6.3V_6 0.1u/10V_4
36
35
34
33
32
31
30
29
28
27
26
25
U31
C719 +5VA HP_JD
0.1u/10V_4
VREF
HP-OUT-L
MIC1-VREFO-L
AVSS1
AVDD1
MIC2-VREFO
CBN
HP-OUT-R
MIC1-VREFO-R
CBP
CPVEE
LDO-CAP
10u/6.3V_6
LINEOUT_JD
1
ADOGND ANALOG ADOGND
Place next to pin 38 R513 D24
3
Spilt by AGND 37 24 ADOGND +5VA Near CN25
AVSS2 LINE1-R 10K_4 *VPORT_6
Place next to pin 25
2
38 23
AVDD2 LINE1-L LINE_JD# 2
R265 *Short_6 +5VPVDD1 39 22 MIC1_R1 R516 Q19
+5V PVDD1 MIC1-R
3
ADOGND
L_SPK+ 40 21 MIC1_L1 22K_4 2N7002K
C669 C668 C679 C685 SPK-L+ MIC1-L
1
L_SPK- 41 20 HP_JD 2
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 SPK-L- MONO-OUT Q18
GND_EARTH 42 19 R507 20K/F_4
PVSS1 (Vista Premium Version) JDREF ADOGND
2N7002K ADOGND
43 18
1
PVSS2 Sense-B
Place next to pin 39 R_SPK- 44 17
SPK-R- MIC2-R Placement near Audio Codec ADOGND
R_SPK+ 45 16
SPK-R+ MIC2-L
Spilt by PGND
+5V R258 *Short_6 +5VPVDD2 46 15
PVDD2 LINE2-R
GPIO0/DMIC-DATA
EAPD# GPIO1/DMIC-CLK
47 14
C670 C671 C680 C684 SPDIFO2/EAPD LINE2-L
Spilt by DGND
SPDIF_OUT_R 48 SENSEA R509 39.2K/F_4 LINEOUT_JD C07
SDATA-OUT
13
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 SPDIFO Sense A
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
49 R508 20K/F_4 MIC1_JD
DVDD1
DVSS2
PGND
SYNC
ANALOG HPL_SYS
PD#
3
C C
Place next to pin 46 ALC271X EAPD_HP 2 Q46
1
10
11
12
PCBEEP dont coupling any signals if possible *MMBT3904
DIGITAL 8/17 separate PCBEEP to Digital from Realtek suggestion
1
1.6Vrms
R423 *Short_6 +AZA_VDD
+3V
PCBEEP C720 1u/10V_6 BEEP_1 R515 47K_4 ADOGND
SPKR 12
HPR_SYS
C691 C689 C725 R510
3
4.7K_4 If either HDA device io power use +1.5V,
0.1u/10V_4 10u/6.3V_6 100p/50V_4 all device IO power change to +1.5V 2 Q47
*MMBT3904
1
Place next to pin 1
R497 *Short_6 +AZA_VDD
23 DMIC_DAT DMIC_DAT ADOGND
DMIC_CLK
23 DMIC_CLK apply for codec suggestion
C706 C709
ACZ_RST#_AUDIO
ACZ_RST#_AUDIO 12
C698 C696 PD# 0.1u/10V_4 10u/6.3V_6
ACZ_SYNC_AUDIO 12
*22P/50V_4 *22P/50V_4
ACZ_SDIN0_R R494 22_4 MIC1-VREFO-R
ACZ_SDIN0 12
MIC(AMP) MIC1-VREFO-L
ACZ_SDOUT_AUDIO 12
Place next to pin 9
0V : Power down Class D SPK amplifer R264 R261
3.3V : Power up Class D SPK amplifer 4.7K/F_4 4.7K/F_4
ACZ_BITCLK_AUDIO 12
PINK
C475 *22p/50V_4 1 CN24 7
MIC1_L1 C461 4.7u/6.3V_6 MIC1_L2 R268 1K/F_4 MIC1_L3 L47 MIC1_L 2
Reserve for EMI BK1608LL121/150mA/120ohm_6 6
MIC1_R1 C442 4.7u/6.3V_6 MIC1_R2 R257 1K/F_4 MIC1_R3 L46 MIC1_R 3
BK1608LL121/150mA/120ohm_6 MIC1_JD 4
8
5
SPDIF_OUT L70 BLM15BD121SN1/300mA/120ohm_4 SPDIF_OUT_R JAS7331-P30H9-7F
C439 C465
470p/50V_4 470p/50V_4 Normal OPEN Jack
B B
GND_EARTH don't coupling AGND and SPK signals Max. 100mVrms input for Mic-IN
C675
*33p/50V_4 R242 *0_6
GND_EARTH R260 0_6
R537 *0_6 ADOGND ADOGND
R266 *0_6 MIC1_JD
R263 *0_6
1
R536 0_6
D14
R281 *0_6
R521 *0_6 *VPORT_6 Near CN28
2
R251 *0_6
Power (ADO) R273 *0_6
Tied at one point only under the
C481 *1000p/50V_4
L69 Place close to Codec C723 *1000p/50V_4 ALC269 or near the ALC269
Demodulation Filter ADOGND
+5VA
DIGITAL ANALOG ADOGND
L69 BLM21PG221SN1D(220,100M,2A)_8
+5V
U28 Internal Speaker(AMP)

3
IN OUT
4 Mute(ADO)
C07
2
GND
1 5 R474 *29.4K/F_4
SHDN SET +5VA
ramp change to +5V
*G923-330T1UF C678 C673 CN13
R476 +3V +5V
D10 C3C 2
*10K/F_4 1
10U/6.3V_8 0.1u/10V_4 R_SPK+ R288 *Short_6 R_SPK+_1
C656 C662 R654 R_SPK- R299 *Short_6 R_SPK-_1 Speak CN1
R254 *0_4 R498 R568 L_SPK- R186 *Short_6 L_SPK-_1
*10K_4 L_SPK+ R189 *Short_6 L_SPK+_1 CN8
0.1u/10V_4 10U/6.3V_8 *10K_4 1K_4
1
ADOGND PD# BAS316 D22 ACZ_RST#_AUDIO EAPD_HP C486 C488 C343 C350 2
A A
*0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6 Speak CN2
3
ADOGND Q45
ramp reserve R568 for codec *2N7002K
*BAS316 D20 EAPD# 2

C656, C662 close U28 pin3 and L69
1
BAS316 D21
AMP_MUTE# 33
ADOGND
PROJECT : ZQ2
Vset =1.25V Quanta Computer Inc.
Vout =Vset[1+AR(1,2)/AR(2,GND)] Size Document Number Rev
apply for codec suggestion ALC271X / AMP / SPK 1A

5 4 3 2 1
A B C D E
Main ?? XD_RDY
XD_RE#
XD_CE#
XD_CLE
1
2
3
CN10
XD-R/B
XD-RE
XD-CE
4 IN 1 CARD READER (MMC)
MS-DATA1
MS-BS
4IN1-GND2
20
21
22
MS_DATA1
MS_BS
VCC_XD
29
Second ?? XD_ALE
4
XD-CLE SD-VCC
23
SD_CLK
VCC_XD
5 24
XD_WE# XD-ALE SD-CLK SD_DAT0
6 25
XD_WP# XD-WE SD-DAT0 XD_D2
7 26
XD_D0 XD-WP XD-D2 XD_D3
8 27
XD_D1 XD-D0 XD-D3 DATA4
9 28
4 SD_DAT2 XD-D1 XD-D4 SD_DAT1 4
10 29
SD_DAT3 SD-DAT2 SD-DAT1 DATA5
11 30
SD_CMD SD-DAT3 XD-D5 DATA6
12 31
SD-CMD XD-D6 DATA7
13 32
4IN1-GND1 XD-D7
VCC_XD 14 33
MS_SCLK MS-VCC XD-VCC XD_CD#
15 34
MS_DATA3 MS-SCLK XD-CD-SW SD_WP
16 35
MS_INS# MS-DATA3 SD-WP-SW SD_CD#
17 36
MS_DATA2 MS-INS SD-CD-SW
18
MS_DATA0 MS-DATA2
19
MS-DATA0 VCC_XD
37
SHIELD1-GND
38
SHIELD2-GND R464 C658 C657
41
SHIELD3-GND *5.1K_4 4.7u/10V_6 0.1u/10V_4
42
SHIELD4-GND
CONN_CARDREADER
Close to CN10 pin 14 & pin23

+1.8V_VDD
4.7u CAP close to pin23
B04
+3V_VDD T104 T103
R488 *Short_4 XTALSEL C700 C703
SD_DAT0
Clock input selection +3V_VDD 0.1u/10V_4 0.1u/10V_4
3 3
XTALSEL
DATA0 MS_DATA0
CRMD_N
'1' for 48MHz input [Default]
DATA1
DATA0
DATA7
DATA6
CTRL1
CTRL3
NBMD
'0' for 12MHz input C740 XD_D0
EC-D
0.1u/10V_4 SD_DAT1
DATA1 MS_DATA1
48
47
46
45
44
43
42
41
40
39
38
37
U30
B04 XD_D1
CTRL0, CRTL 1 trace length shorter ,
XTALSEL
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
GND
VDD
NBMD
TRIST
VDDHM
R506 *100K_4 +3V_VDD and surround with GND.
R503 *Short_4 SD_DAT2
11,26 PCIE_RST#
C716 *0.47u/6.3V_4 1 36 CTRL0 DATA2 MS_DATA2
GPON7 CTRL0 DATA5
2 35
EXT48IN DATA5 CTRL2 XD_D2
3 34
R499 330_4 RSTN CTRL2 GPI4
4 33
R486 *Short_6 +3V_VDD REXT GPI4 DATA4 T100 SD_DAT3
+3V 5 32
VD33P DATA4 DATA3
12 USBP10+ 6 31
C701 DP AU6437-GBL DATA3 DATA2 DATA3 MS_DATA3
12 USBP10- 7 30
DM DATA2 XD_WP#
8 29
4.7u/10V_6 C724 C722 XI VS33P XDWPN GPI2 XD_D3
9 28
XO XI GPI2 XD_CE# T99
10 27
*5p/50V_4 *5p/50V_4 XO XDCEN EEPDATA
+1.8V_VDD 11 26
VDD EEPDATA GPI1 T96
12
VDD GPI1
25
T98
Close to connector
SDWPEN
AGND5V
EEPCLK
VDDHM
CF_V33
XDCDN
PN?
VCC33
CTRL4
R462 *Short_4 SD_CLK

GND
VDD
V18
V33
2 2
CTRL0 XD_ALE
C660
13
14
15
16
17
18
19
20
21
22
23
24
MS_BS *10p/50V_4
crystal trace width needs at least 10 mils.
pin13 output 20mils EEPCLK T102 SD_WP
C714
C718 18p/50V_4 XI CAP close PIN11,12 CTRL1 XD_CLE
4.7u/10V_6
R463 *Short_4 MS_SCLK
Y7 R505
12MHz 270K_4 SD_CMD
*0_4 R482 C661
VCC_XD
C717 18p/50V_4 XO XD_CD# CTRL2 XD_RDY *10p/50V_4

pin14 output 15mils CTRL4 SD write protect
+1.8V_VDD 1:decided by SDWP[Default] SD_CD#
0:letting SD always CTRL3 XD_WE#
+3V_VDD +3V_VDD write-able
C697 C693 MS_INS#
4.7u/10V_6 0.1u/10V_4 CTRL4 XD_RE#
1 1
PROJECT : ZQ2
AU6437 CardReader 1A

A B C D E
5 4 3 2 1
USB PORT(USB/MB)
+5V_S5
USBPWR1
C629
330u/6.3V_6.3X5.8
+
12
12
USBP11-
USBP11+
2
3
L73
2
3
EC-C
1
4
1
4
*DLW21HN900SQ2L/330mA/90ohm
USBP11-
USBP11+
+5V_S5
C483
USB BOARD CONN(USB/SB)
2.2u/6.3V_6
23,33 LID591#
+3VPCU
+5V_S5
CN11
20
19
18
30
C405 17
CN21
U11 16
1 8
1u/10V_6 USBPWR1 USBP0- 1 8 15
2 8 2 7
D IN1 OUT3 USBP0+ 2 7 14 D
3 7 3 6 12 OC_7#
IN2 OUT2 3 6 13
6 4 5 12 OC_4#
OUT1 4 5 USBON# 12
33 USBON#
4
EN#
EC-C 11
1 USB_MB L72
GND 10
1
5 2 1 USBP12- USBP11-
OC# OC_6# 12 12 USBP12- 2 1 9
RV1 RV2 3 4 USBP12+ USBP11+
12 USBP12+ 3 4 8
APL3510BXI-TRG
4.7pF_4 *DLW21HN900SQ2L/330mA/90ohm USBP12- 7
2
4.7pF_4 USBP12+ 6
5
USBP8- 4
EC-C 3
USBP8+
USBP0- 2
12 USBP0- 3 4
3 4 USBP0+ 1
12 USBP0+ 2
2 1
1 EC-C
EC-C L74 USB_CONN
L68 2 1 USBP8-
12 USBP8- 2 1
*DLW21HN900SQ2L/330mA/90ohm 3 4 USBP8+
12 USBP8+ 3 4
C
+3V_S5 C
31,33 PWRLED#
BLUETOOTH CONN(BTM)
POWER BOARD CONN(UIF) 31,33 SUSLED#
1
+3VPCU +3V_S5
1
+3V Q14
1
SB side have pull-up R175 2 BSS84
3
*100K_4
Q12
2 *BSS84 R659 +3V 30mil
33 ACPRN
R2 C05 100_4 CN1 +3V_S5 1 3 BT_POWER
3
5
*10K/F_4 1 1
4 SATA_LED#_R Q13 B07 2 Q17
2 *BSS84 SUS_LED 3 C392 R227 + C400 C404
13 SATA_ACT#
3
2
U1 PIPE_LED 4 .33u/10V_6 47K_4 AO3413
3
*TC7SH08FU D1 BAS316 5 2.2u/6.3V_6 1000p/50V_4

33 NBSWON#
6
R3 0_4 R660 453/F_4 7
33 NUMLED#
R661 453/F_4 8
33 CAPSLED#
SATA_LED#_R R662 453/F_4 9
B 10 13 B
11 14 R231 4.7K_4
33 BT_POWERON#
12
POWER/B
BSS84 Q36 EC-C CN9

LED BOARD CONNECTOR(UIF) +3V 1 3 P_SAVE_LED +3V
BT_POWER
5
USBP9+ 4
12 USBP9+ 3 4
C3 3 4 USBP9- 3
12 USBP9- 2 1
2
+3V 2 1 T48 BT_LED 2 7

33 P_SAVE_LED# *0.1u/10V_4 L39 1 6
BT_CONN
3 1 C422
33 ODD_EJ
*0.01u/16V_4
Q41 B06
R643 BSS84 R651
2
100K_4 100K_4
+3V
C05 CN2
+3V 1
A R663 2.2K_4 1 A
2
ODD_EJ_CON 2
3
POWER_SAVE_CON 3
33 POWER_SAVE 3 1 4
4
Q42
5
6
5
7
8
7
8
PROJECT : ZQ2
R644 BSS84 R652 6
2
100K_4 100K_4 SW/LED

USB/BT/TP 1A

5 4 3 2 1
5 4 3 2 1
EE RETURN-PATH CAPACITORS(EMC) +1.8V
EC3
VIN
VIN
C528
C529
1000p/50V_4
1000p/50V_4
+3V
CPU_VDDNB_CORE
LED(UIF)
Amber
LED1
+3V_S5 31
For fix HyperTransport nets
VIN C535 1000p/50V_4 CPU_VDDNB_CORE R314 806/F_4 4 2
across plane splits 30,33 SUSLED#
11/19 R315 56_4 3 1
D 30,33 PWRLED# D
*0.1U/10V_4
LED_A/B
EC2 *0.01U/25V_4 EC-C
+VGPU_CORE +1.8V
C490 0.1u/16V_6 Blue
+5V_S5 +3V
EC1 *0.01U/25V_4 R319 *1M_4 +3VPCU +3VPCU
C411 *0.01u/50V_6
R323 *1M_4 Amber
C664 *0.01u/50V_6 LED2
R316 806/F_4 4 2
33 BATLED1#
C543 1000p/50V_4
+5VPCU
VIN C547 *0.01u/50V_6 R322 56_4 3 1
33 BATLED0#
C549 33p/50V_4 C729 *0.01u/50V_6
EC-C LED_A/B
C495 *0.01u/50V_6
BAT-V C738 0.1u/10V_4
34 BAT-V Blue
C665 *0.01u/50V_6 VIN C737 0.1u/10V_4
+3V C739 *0.1u/10V_4 RF_LED_EN#
+3V C374 *0.01u/50V_6 +3V
2
EC-C VIN C194 *0.01u/50V_6 +3V Q40
*BSS84
C5 *0.01u/50V_6
+5V_S5 VIN
C735 *0.1u/10V_4 R647 *0_4
Amber 3 1
NB_CORE 33 RF_LED_EN#
C C
+3V C316 *0.01u/50V_6 VIN C736 *0.1u/10V_4 R649 0_4 R321 806/F_4 R653 0_4
26,33 RF_LED#
LED3 LED
C403 *0.1u/10V_4 C687 *0.1u/10V_4

AMBER LED (HKC)
+5V_S5 +3V
C402 *0.01u/16V_4 C686 *0.01u/16V_4
HOLE(OTH) NB MiniCard VGA CPU

HOLE10 HOLE11
HOLE7 HOLE4 HOLE3 HOLE12 HOLE20 HOLE5 H-C236D142P2 H-C236D142P2
*HG-C315D87P2 *HG-C315D118P2 *HG-C315D118P2 HOLE21 HOLE17 H-C197D122P2 H-C197D51P2 H-C197D122P2
7 6 7 6 7 6 H-C217D142P2 H-C217D122P2
8 5 8 5 8 5
9 4 9 4 9 4
1
1
2
3
1
2
3
1
2
3
1
1
B HOLE14 HOLE15 B
HOLE8 H-C236D142P2 H-C236D142P2
HOLE6 HOLE24 HOLE23 H-C197D122P2
HG-C276D142P2 *HG-C315D118P2 *HG-C315D118P2 HOLE1 HOLE18
7 6 7 6 7 6 *H-C236D118P2 *H-C236D118P2 EC-C HOLE27
8 5 8 5 8 5 H-C197D122P2
9 4 9 4 9 4 DEL Hole26
1
1
1
2
3
1
2
3
1
2
3
1
HOLE13 HOLE25 HOLE22
*HG-C315D110P2 *HG-C315D118P2 *HG-C315D118P2 HOLE19 HOLE2
7 6 7 6 7 6 H-C177D79P2 *H-C94D94N
8 5 8 5 8 5 HOLE31 HOLE32 HOLE33 HOLE34 HOLE35 HOLE36
9 4 9 4 9 4 *ss-fm_cmp *ss-fm_cmp *ss-fm_cmp *ss-fm_cmp *ss-fm_cmp *ss-fm_cmp
HOLE28 HOLE29 HOLE30
*SPAD-ZQ2-2 *SPAD-ZQ2-3 *SPAD-ZQ2-4
1
2
3
1
2
3
1
2
3
1
A HOLE9 HOLE16 A
1
1
*HG-C276D118P2 *HG-C315D118P2
7 6 7 6
8
9
5
4
8
9
5
4
11/19
PROJECT : ZQ2
1
2
3
1
2
3

POWER/USB/BT/TP/MDC 1A

5 4 3 2 1
5 4 3 2 1
K/B(KBC)
33
33
33
33
33
MY0
MY1
MY2
MY3
MY4
MY0
MY1
MY2
MY3
MY4
MY5
1
2
3
4
5
CN6
+3VPCU
32
33 MY5 6
MY6 7 RP1 10K_10P8R
33 MY6
MY7 8 10 1 MX1
33 MY7
D MY8 9 MX7 9 2 MX0 D
33 MY8
MY9 10 MX6 8 3 MX2
33 MY9
MY10 11 MX5 7 4 MX3
33 MY10 MY11 MX4
33 MY11 12 6 5
EC-C MY12 13
33 MY12 MY13
33 MY13 14
MY14
Del CAP 33 MY14 MY15
15
16
33 MY15 MY16
33 MY16 17
MY17 18
33 MY17 MX7
33 MX7 19
MX6 20
33 MX6 MX5
33 MX5 21
MX4 22
33 MX4
MX3 23
33 MX3
MX2 24 27
33 MX2
MX1 25 28
33 MX1
MX0 26
33 MX0
KB
C C
TOUCHPAD BOARD CONN(TPD)
+5V +5V 50mil

L33 BK1608HS220/1A/22ohm_6 +TPVDD
C287 C281
R147 R139
10K_4 10K_4 *0.1u/10V_4 0.1u/10V_4 CN7
12
11 14
B L31 LZA10-2ACB104MT/100mA_6 TPDATA_R B
33 TPDATA 10 13
L29 LZA10-2ACB104MT/100mA_6 TPCLK_R 9 +3V +3V +5V +3V +5V
33 TPCLK
8 CPU FAN(THM)
7
C276 C267 RIGHT# 6
5 R326 R329 R328
*0.01u/16V_4 4 R325 R327
*0.01u/16V_4 3 10K_4 10K_4 10K_4 *Short_6
2 R324 10K_4
LEFT# 1 *10K_4
SW1 FAN_PWM_E
TP/B CN14
LEFT# 33 FANSIG +5V_FAN
1 2 1
2
3 4
2
3
5 C542
SWITCH_1.5 Q23 FAN_PWM_CN 3
6 1000p/50V_4 2 1 3
2,4,12 PM_THERM# 4
MMBT3904
Q24 30mil FAN CONN
1
SW2 MMBT3904
RIGHT# 33 CPUFAN#
1 2
3 4
A 5 A
SWITCH_1.5 6
PROJECT : ZQ2
KB/FAN/EE RETURN CAP 1A

5 4 3 2 1
5 4 3 2 1
EC(KBC) I/O ADDRESS SETTING(KBC)

33
L37 BK1608HS220/1A/22ohm_6 +A3VPCU
+3V
C383 C389
30mil
0.1u/10V_4 4.7u/10V_6
+3VPCU E775AGND
D7 C369 C361
R228 2.2_6 +3VPCU_EC 0.03A(30mils)
BAS316 4.7u/10V_6 0.1u/10V_4
C390 C351 C382 C368 C357 C335
115
102
19
46
76
88
Take care of power side
4
4.7u/10V_6 0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 U10
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
E775AGND C388 *0.01u/50V_6 ICMNT SHBM=0: Enable shared memory with host BIOS
D D
C384 0.01u/16V_4
11,26 LPC_LFRAME# 3 97 TEMP_MBAT 34
LFRAME GPIO90/AD0 WL_SW
11,26 LPC_LAD0 126 98 T42
LAD0 GPIO91/AD1 TPD_TRIP
11,26 LPC_LAD1 127 99
LAD1 GPIO92/AD2
11,26 LPC_LAD2 128
LAD2 A/D GPIO93/AD3
100 ICMNT 34
1 108 SHBM SHBM_R R202 10K_4
11,26 LPC_LAD3 LAD3 GPIO05 NB_CORE_ON 38
CLK_PCI_775 CLK_PCI_775 2 96 R645 *0_4
11 CLK_PCI_775 LCLK GPIO04 VGA_THERM# 21
11 CLKRUN# 8
GPIO11/CLKRUN 1/13 Comfirm by vendor mail :
101 POWER_SAVE 30 Disabled ('1') if using FWH device on LPC.
R214 GPIO94/DA0 DISP_IN
12 SIO_A20GATE 121 105 T43
GPIO85/GA20 GPI95/DA1 TP_LED# Enabled ('0') if using SPI flash for both system BIOS and EC firmware
D/A GPI96/DA2
106 T44
*22_4 122 107 TP_SW# T45
12 SIO_RCIN# KBRST/GPIO86 GPI97
12 SIO_EXT_SCI# 29
ECSCI/GPIO54 LPC
64 ACIN 34
C373 EC_FPBACK# GPIO01/TB2
23 EC_FPBACK# 6 95 NBSWON# 30
GPIO24/LDRQ GPIO03
*10p/50V_4 93 LID591# 23,30
T71 NOCIR# GPIO06/IOX_DOUT
124 94 SUSB# 12
GPIO10/LPCPD GPIO07
119 MXM_SMCLK12 21
GPIO23/SCL3
7 109 SM Bus 3 for VGA
9,11 A_RST#_SB
USBON#
LREST GPIO30/CIRTX2
GPIO31/SDA3
120
ACPRN 30
MXM_SMDATA12 21 SM BUS PU(KBC)
30 USBON# 123 65 BATLED0# 31
GPIO67/PWUREQ GPIO32/D_PWM
66 BATLED1# 31
IRQ_SERIRQ GPIO33/H_PWM MBCLK R178 2.2K_4
11 IRQ_SERIRQ 125 15 VRON 36,39 +3VPCU
SERIRQ GPIO36 MBDATA R179 2.2K_4
16 SUSLED# 30,31
GPIO40/F_PWM VGA_ON_EC MXM_SMCLK12 R224 SW@2.2K_4
12 SIO_EXT_SMI# 9 17 T112 +3V_D_EXT
GPIO65/SMI GPIO42/TCK MXM_SMDATA12 R230 SW@2.2K_4
GPIO GPIO43/TMS
20 AMP_MUTE# 28
21 VR2.5_ON 42
MX0 GPIO44/TDI +3V
32 MX0 54 22 CPUFAN# 32
MX1 KBSIN0 GPIO45/E_PWM
32 MX1 55 23 T123
MX2 KBSIN1 GPIO46/CIRRXM/TRST
32 MX2 56 24 VIN_ON 34
MX3 KBSIN2 GPO47/SCL4
C 32 MX3 57 25 D/C# 34 C
MX4 KBSIN3 GPIO50/TDO
32 MX4 58 26 S5_ON 35,37,42
MX5 KBSIN4 GPIO51 CPU_SMBCLK R181 10K_4
32 MX5 59 27 HDMI_HPD_EC# 24
MX6 KBSIN5 GPIO52/CIRTX2/RDY CPU_SMBDATA R180 10K_4
32 MX6 60 28 EC_ODD_EN 27
MX7 KBSIN6 GPIO53/SDA4 EC_ODD_EN R190 10K_4
32 MX7 61 91 DNBSWON# 12
KBSIN7 GPIO81 ReservedEC 1.2V_ON R201 10K_4
110 T46
MY0 GPO82/TEST VR2.5_ON R193 10K_4
32 MY0 53 112 RF_LED_EN# 31
MY1 KBSOUT0/JENK GPO84/TRIST DCR_EN_R R646 *Short_4
32 MY1 52 80 DCR_EN 23
MY2 KBSOUT1/TCK GPIO41
32 MY2 51
MY3 KBSOUT2/TMS 1/28
32 MY3 50
MY4 KBSOUT3/TDI ODDLED
32 MY4 49
KBSOUT4/JEN0 KB GPIO56/TA1
31 T33
MY5 48 117
32 MY5 KBSOUT5/TDO GPIO20/TA2/IOX_DIN SUSON 39
MY6 47 63
32 MY6 KBSOUT6/RDY GPIO14/TB1 FANSIG 32
MY7 43
32 MY7 KBSOUT7
MY8 42 TIMER 32
32 MY8 KBSOUT8 GPIO15/A_PWM CONTRAST 23
MY9 41 118
32
32
MY9
MY10
MY10
MY11
40
KBSOUT9/SDP_VIS
KBSOUT10/P80_CLK
GPIO21/B_PWM
GPIO13/C_PWM
62
NUMLED# 30
PWRLED# 30,31 SPI FLASH(KBC)
32 MY11 39 81 CAPSLED# 30
MY12 KBSOUT11/P80_DAT GPIO66/G_PWM +3VPCU
32 MY12 38
MY13 KBSOUT12/GPIO64
32 MY13 37
MY14 KBSOUT13/GPIO63 ODD_EJ U23
32 MY14 36 84 ODD_EJ 30
MY15 KBSOUT14/GPIO62 GPIO77/SPI_DI SHBM_R SPI_SDI_uR R167 22_4 SPI_SDI_uR_R
32 MY15 35
KBSOUT15/GPIO61/XOR_OUT SPI GPO76/SPI_DO/SHBM
83 2
SO VDD
8
MY16 34 82
32 MY16 GPIO60/KBSOUT16 GPIO75/SPI_SCK RF_LED# 26,31
MY17 33 R166 100K_4 SPI_SDO_uR 5 7 C298
32 MY17 GPIO57/KBSOUT17 1/28 SI HOLD
75 RSMRST#_uR R192 *Short_4 SPI_SCK_uR 6 3 0.1u/10V_4
GPIO72/IRRX1/SIN2 ICH_RSMRST# 12 SCK WP
MBCLK 70 73
34 MBCLK GPIO17/SCL1 GPIO70/IRRX2_IRSL0 SUSC# 12
SM Bus 1 for BATT MBDATA 69 74 PWROK_EC_uR R188 *Short_4 +3VPCU R168 10K_4 SPI_CS0#_uR 1 4
34 MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC 4,15 CE VSS
4 CPU_SMBCLK CPU_SMBCLK 67 SMB IR 113 RF_EN
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN 26
SM Bus 2 for CPU 4 CPU_SMBDATA CPU_SMBDATA 68 14 CIRR_X2 T36 A25L080M
GPIO74/SDA2 GPIO34/CIRRXL HWPG
114
GPIO16/CIRTX P_SAVE_LED# At 11/24 add
111 P_SAVE_LED# 30
TPCLK GPO83/SOUT_CR/XORTR Winbond W25X16AVSSIG AKE38ZP0N01
32 TPCLK 72
GPIO37/PSCLK1 1/13 Comfirm by vendor mail :
TPDATA 71 MXIC MX25L1605AM2C-15G AKE37FP0Z13
32 TPDATA
1.2V_ON GPIO35/PSDAT1 SPI_SDI_uR
If the Southbridge enables 'Long Wait Abort' by
B 37 1.2V_ON 10 86 EON EN25F16-100HIP AKE38ZA0Q00 B
GPIO26/PSCLK2 F_SDI SPI_SDO_uR_R R149 22_4 SPI_SDO_uR default, the flash device should be 50MHz (or faster)AMIC A25L016
30 BT_POWERON# 11
GPIO27PSDAT2 PS/2 F_SDO
87 AKE38ZN0800
12 FIU 90 SPI_CS0#_uR
39,42 MAINON GPIO25/PSCLK3 F_CS0
for 781 T35 13 92 SPI_SCK_uR_R R150 22_4 SPI_SCK_uR
GPIO12/PSDAT3 F_SCK
R196 781@0_4 E775_32KX1 77 30 ECDB_CLOCK T34
11 RTC_CLK GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN +3V
VCC_POR
85 VCC_POR# R203 47K/F_4 +3VPCU HWPG(KBC)
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
for 775 R198 *775@20M_6 E775_32KX2 79 104 VREF_uR R226 *Short_4 +A3VPCU
GPIO02 VREF R233
1/28 10K_4
R199 NPCE781
5
18
45
78
89
116
103
VCORF_uR 44
*775@33K/F_4 SM BUS ARRANGEMENT TABLE D12 BAS316

39 HWPG_1.5V
Y1
SM Bus 1 Battery D11 BAS316 HWPG
38 HWPG_0.95V
L38
*775@32.768KHz BK1608HS220/1A/22ohm_6 D27 *SP@BAS316
36,39,42 HWPG_2.5V
C355 C358 C336 SM Bus 2 CPU
*775@15P/50V_4 *775@15P/50V_4 D10 BAS316
35 SYS_HWPG
E775AGND 1u/6.3V_4
SM Bus 3 VGA D9 BAS316
37 HWPG_1.1V
775@ Value use for WPCE775 only D8 *SP@BAS316
781@ Value use for NPC781 only 37,42 HWPG_1.8V
E775AGND
D13 BAS316
39 HWPG_0.9V
D28 *SP@BAS316
2,15,36,38 CPU_COREPG
Palm Rest Thermal Sensor(THM) POWER-ON Switch(KBC)
+3V
INTERNAL KEYBOARD STRIP SET(KBC)
D27 for VRON enable +Vcore/0.9V
A
Near TP on TOP side D8 for 1.2V_ON enable +1.1V A
R229 and only for AMD
47K_6 SW3
platform Palm Rest use. *SWITCH_1.5 +3VPCU
TPD_TRIP NBSWON# 1 2 MY0 R182 10K_4

3 4
2
5
RT1
100K/F/NTC_4
D15
*VPORT_6
6
PROJECT : ZQ2
t Quanta Computer Inc.
1

E775AGND WPCE775C_0DG & FLASH 1A

5 4 3 2 1
5 4 3 2 1
EC-D
For EMI VA1 PD2
PL2 SBR1045SP5-13 PQ45 VIN_SRC PQ38
POWER_JACK HI0805R800R-00_8 1 FDD6685 FDD6685
4 VA 3 VA2 3 4 1 2 3 4
3 2
2
1 PC39 PC40 PC74 PC75
1
PC36 PC38 PR47 PR187 VIN_SRC PC102 PC31 PR22
PJ2 PL1 0.1u/50V_6 0.1u/50V_6 220K/F_6 0.01/F_7520 0.1u/50V_6 2200p/50V_6 33K_6
HI0805R800R-00_8
1
CSIP_1
D D
0.1u/50V_6 22u/25V_1206
PD3 1 6
2200p/50V_6 22u/25V_1206 PD1 SMAJ20A PR24
2
SW1010CPT PR45 2 5 10K_6
D/C# 33
220K/F_6
3 4 PR46
3
*Short_6
PQ9
IMD2AT108
VIN_SRC 2
PQ6
CSIP_1 DMN601K-7
EC-D
1
VIN_SRC
For EMI
PC28
1u/16V_6
PR43 PR42 PC105 PC18 PC14 PC9 PC72 PC73
10/F_6 10/F_6
PC30
0.1u/50V_6 PR38
4.7_6 PC21
1u/16V_6 2200p/50V_6 *10u/25V_1206 *10u/25V_1206
27 CSIN
28 CSIP
ISL88731_VDDP 10u/25V_1206 *10u/25V_1206 *10u/25V_1206
5
6
7
8
33
32
31
30
26
21
C C
1
+3VPCU PD7
*RB500V-40 4
NC
GND
GND
GND
GND
CSSN
VCC
CSSP
VDDP
PC29 PR37 PC26
0.1u/50V_6 2.7_6 0.1u/50V_8
+3VPCU 11 25 88731B_2 88731B_1 PQ42 0.01_3720
VDDSMB BOOT AO4468 PR153
PL7
3
2
1
MBDATA 9 24 ISL88731_UGATE 6.8uH
PR36 SDA UGATE
1 2
100K/F_6
5
6
7
8
MBCLK 10 23 ISL88731_PHASE
SCL PHASE
13 20 ISL88731_LGATE 4 PR184
33 ACIN ACOK LGATE *4.7_6
PR186 PC22 19
49.9/F_6 0.1u/50V_6 PGND PQ41
DCIN 22 AO4710
DCIN PR32 PC11 PC10
3
2
1
PR39 10/F_6 PC98 2200p/50V_6 10u/25V_1206
82.5K_6 PU4 18 CSOP CSOP_1 *680p/50V_6 PC6
PC1 88731ACSET ISL88731A CSOP CSOP_1 10u/25V_1206
2
0.1u/50V_6 ACIN
2 1 PC23
3 0.1u/50V_6 BAT-V
PC2 PR40 VREF
B CSON 17 CSON BAT-V B
100p/50V_6 PL3 22K/F_6
HI0805R800R-00_8 4 PR33 VIN_SRC VIN
ICOMP 10/F_6 PQ8
NC 16
MBAT+ BAT-V AOL1413
5 PR35 1
PJ1 PL4 NC *Short_4 2 5
HI0805R800R-00_8 15 BAT-V 3
10 1 VBF BAT-V 31
PR7 6
2 100_4 VCOMP PR34
29
3 TEMP_MBAT_C GND 100_4 PC201
VIN
GND
TEMP_MBAT 33
4
4
ICM
PR18
NC
NC
5 1U/25V_6 150K_6
6 PR41
+3VPCU
7
14
12
7 2.21K/F_6
9 8 PR8
Batt_Conn 100K/F_6
PC4 PC3
47p/50V_6 47p/50V_6 PC37 PR15
0.01u/50V_6
ISL88731 thermal pad 39K
PR6
tie to Pin12
ICMNT 33
3
*Short_6
PR5 PR4
100_4 100_4 PC32 PC33 PC34
*1u/16V_6 0.01u/50V_6 *0.01u/50V_6 2
33 VIN_ON
MBCLK 33
PQ5
DMN601K-7
A MBDATA 33 A
1
PU1
CM1293A-04SO
1
CH1 CH4
6 MBDATA
PROJECT : ZQ2
2 5
VN VP +3VPCU
TEMP_MBAT_C 3 4 MBCLK
CH2 CH3 Size Document Number Rev
CHARGER (ISL88731) 1A
Add ESD diode base on EC FAE suggestion
5 4 3 2 1
5 4 3 2 1
MAIND
MAIND 42
VL
2,4,42 SYS_SHDN#
PR249
*Short_4
0805 0805
1
VIN_SRC VIN_SRC VIN_SRC
D VIN_SRC D
PR250
39K/F_4 VL
+ EC-E
2
PC188 EC-E
2
3V5V_EN 4.7u/10V_8
PC168 PR132
100u/25V_6X5.8 EC-E EC-E EC-E *Short_4
1
PR133
PR260 PR261 D06 *Short_4
+3VPCU
1
*Short_4 *Short_4
PR124 PC197 PR137 PC178
PC169 PC171 390K_4 PC194 1u/16V_6 *0_4 4.7u/25V_0805
2
5V_EN
3V_EN
2.2n/50V_6 *4.7u/25V_0805 EC-E 0.1u/50V_6 PC181 OCP : 8A
5
6
7
8
PC170 PC196 2.2n/50V_4
2
*4.7u/25V_0805 0.01u/16V_4 PC198
0.1u/50V_6
5.03A
1
8206_ONLDO REF 4
1
EC-E 3V_DH +3VPCU
8
7
6
5
OCP: 10A PR127 PR129 PQ67
150K_4 *0_6 AO4468
6.15A
8
7
6
5
4
3
2
1
4 5V_DH
+5VPCU +5VPCU PL16
LDO
ONLDO
LDOREFIN
VIN
NC
VCC
TON
REF
3
2
1
2R2uH-5.8mR
PQ63 +3VPCU
AO4468 PR259 3V_LX
5
6
7
8
+5VPCU 9 32 REFIN2 191K/F_6
PL15 BYP REFIN2 PC183
10 31 1 2
1
2
3
2R2uH-5.8mR OUT1 ILIM2 PR134 330u/6.3V_6X5.7
C 11 FB1 OUT2 30 C
+5VPCU 5V_LX 1 2 12 PU14 29 SKIP 4 PD12 *4.7_6
PR122 DDPWRGD_R 13 ILIM1 RT8206B SKIP# DDPWRGD_R SX34
8
PGOOD1 PGOOD2 28
7
6
5
220K/F_6 5V_EN 14 27 3V_EN +
EN1 EN2
15 26
PR251 PR234 DH1 DH2 PC70
16 LX1 LX2 25
+ *0_4 *4.7_6 4 5V_DL 37 *680p/50V_6 PR139 PC193
PD4 PAD 0_6 0.1u/50V_6
36
3
2
1
PAD
PGND
PVCC
PC172 PC163 SX34 PQ68
BST1
BST2
GND
PAD
PAD
PAD
DL1
DL2
NC
330u/6.3V_6X5.7 0.1u/50V_6 PC186 PC199 AO4710
PC162 0.1u/50V_6 0.1u/50V_6 1 2
PC167 *680p/50V_6 PQ64 PR258 PR135 *0_4
35
34
33
17
18
19
20
21
22
23
24
*10u/25V_1206 PR252 AO4710 PR248 1/F_6 +3VPCU_OUT 1 2
1
2
3
0_4 1/F_6 1 2 PR138 0_4

1 2 3V_DL
PR256 VL SKIP REF

+5VPCU_FB *0_6 PR136
PC177 PR128 PR130 *0_6
2 0.1u/50V_6 PC195 *Short_6 *0_6
PD10 1u/16V_6
1PS302 3
PR131
1 *Short_6 +3VPCU
PC182 PR257
0.1u/50V_6 *Short_6
2
PD9
OCP:10A 1PS302 3 OCP:8A PR120
B B
L(ripple current) PC176 L(ripple current) *100K/F_4
1 0.1u/50V_6
=(19-5)*5/(2.2u*0.4M*19) =(19-3.3)*3.3/(2.2u*0.5M*19) 10/08
~4.18A +15V_ALWP 1 2 RT8206B_PIN20 ~2.48A
+15V DDPWRGD_R
SYS_HWPG 33
1
Iocp=10-(4.18/2)=7.91A PR240 PR238 Iocp=8-(2.48/2)=6.67A
22_8 *200K/F_4 PR237 PR121
Vth=7.91A*14.2mOhm=112.322mV PC174 *39K/F_4 Vth=6.67A*15mOhm=94.714mV *Short_4
R(Ilim)=(112.322mV*10)/5uA 0.1u/50V_6 R(Ilim)=(94.714mV*10)/5uA
2
~220K ~191K
+5VPCU +3VPCU
VIN_SRC +3V_S5 +5V_S5 +15V VIN_SRC +5VPCU +3VPCU
PR116 PR125 PR126 PR118 PR119

5
6
7
8
5
6
7
8
3
1M_6 22_8 22_8 1M_6 *1M_6
5
6
7
8
MAIND 4 MAIND 4 S5D 2

S5D 4
+3V_S5
3
PQ26 PQ28 PQ29

A PQ27 AO4468 AO4468 AO3404 A
1
2 AO4468
33,37,42 S5_ON
2 2 2 1.3A
3
2
1
3
2
1
+3V_S5
3
2
1
PR117 PQ31 PQ32

1
PQ30 1M_6 DMN601K-7 DMN601K-7 PC185

DTC144EU PQ33 *2.2n/50V_4
PROJECT : ZQ2
1
+5V_S5 +5V +3V

DMN601K-7
3~4A 3.2~4.3A 3.2A Quanta Computer Inc.
+5V_S5 +5V +3V SYSTEM 5V/3V (RT8206) 1A

5 4 3 2 1
A B C D E
4,31 CPU_VDDNB_CORE CPU_VDDNB_CORE 3A PL12

2.2uH 0805
LGATE_NB
CPU_VDDNB_CORE VIN
Offset &
OFS/VFIXEN Droop SVI VFIX
1
GND O O X 2 CPU_VDDNB_FB_H +
2
1
D1
D1
S2
G2
+3.3V X X O PR84
2
10/F_6 + PC143
+5V X O X *10u/25V_1206
2
PQ60 PC147 PC146 PC61 PC202
2
2 CPU_VDDNB_FB_L AO4932 *4.7u/25V_0805 *4.7u/25V_0805 0.1u/50V_6 100u/25V_6X5.8
S1/D2
PR89 PR85
G1
Metal VID Codes 10/F_6 10/F_6
4 4
+5VPCU
8
SVC SVD Output PC139
330u_2V_7343
2
0 0 1.1 UGATE_NB
PC138
1
0 1 1.0 1u/25V_8
1
PR210 PC132
1 0 0.9 22.1K/F_4 1000p/50V_6
2
1 1 0.8
PR222 PC135
*Short_8 33p/50V_4
PC136
1200p/50V_4
VFIXEN VID Codes VIN
1
SVC SVD Output PR219 0805
2
10/F_6
VIN
2
0 0 1.4
1
PC140 PR78 LGATE_NB
1
0 1 1.2 0.1u/50V_6 11.3K/F_4 +
2
1 0 1.0 PR213 PHASE_NB
2
44.2K/F_4 PQ59
5
1 1 0.8 EC-C EC-E AOL1448
UGATE_NB PC59 PC127 PC128 PC129 PC126
+3V PR98 0.1u/50V_6 *4.7u/25V_0805 *4.7u/25V_0805 0.1u/50V_6 100u/25V_6X5.8
1
+5VPCU *Short_4 UGATE_0 4
49
48
47
46
45
44
43
42
41
40
39
38
37
20A
1
2
3
1
PR97 *0_4 PR76 PL11
GND
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
+3V
1/F_6 0.36uH/25A
PR147
10K_4 1 2 +VCORE
1 36
2
PR218 OFS/VFIXEN BOOT_NB PR75 PR67

EC-E EC-E EC-E
4
*Short_4 PR96 *10K/F_4 1/F_6 *2.2/F_4
3
2,15,33,38 CPU_COREPG 2
PGOOD BOOT_0
35 1 2 PQ58 PR207 PR206 +VCORE 3
5
AOL1718 *Short_6 *Short_6 + +
PR95 *Short_4 PC58
1
+1.8V +3V 3 34 UGATE_0 0.1u/50V_6 PC54
PWROK UGATE_0 *2200p/50V_4
Pin 49 is GND Pin 4
PR94 *Short_4
2
2
PQ19 4 33 PHASE_0 PC52 PC51

2 CPU_SVD
1
2
3
*DTC144EU PR100 SVD PHASE_0 ISP_0 330u/2V_7343 330u/2V_7343
*10K/F_6 PR93 *Short_4
5 32 ISN_0
2 CPU_SVC SVC PGND_0
2 CPU_PWRGD_SVID_REG 1 3
PR92 *0_4
33,39 VRON
PR101 *Short_4 6265_EN 6 PU11 31 LGATE_0 +5VPCU
ENABLE ISL6265A LGATE_0
33,42 HWPG_2.5V 2 1 0805
PR140 0_4
VIN
7 30 6265_PVCC 1 2
RBIAS PVCC
1
2 1 PR99 PR90 PC56 +
19.6K/F_4 97.6K/F_4 8 29 LGATE_1 2.2u/10V_8 PQ56
2
OCSET LGATE_1
5
PR221 PC144 AOL1448
2
255/F_4 4700p/25V_4
9 VDIFF_0 PGND_1 28
6265_EN UGATE_1 4 PC117 PC119 PC114 PC124
PR216 *4.7u/25V_0805 *4.7u/25V_0805 0.1u/50V_6 100u/25V_6X5.8
1K/F_4 10 27 PHASE_1
1
2
3
FB_0 PHASE_1
PR91 1 2 11 COMP_0 UGATE_1 26 UGATE_1 PL10 20A

100K/F_6 0.36uH/25A
PR217 PC145 +VCORE
54.9K/F_4 1 2 1200p/50V_4 12 25 1 2 1 2
VW_0 BOOT_1
COMP_1
VDIFF_1
VSEN_0
VSEN_1
PC142 PR220 PR77 PC57 PR203

RTN_0
RTN_1
4
ISN_0
ISN_1
ISP_0
VW_1
ISP_1
180p/50V_4 6.81K/F_4 1/F_6 0.1u/50V_6 PQ57 *2.2/F_4
FB_1
5
2 1 AOL1718
+ +
PC141
13
14
15
16
17
18
19
20
21
22
23
24
1
1000p/50V_6 LGATE_1 4 PC113
2 2
*2200p/50V_4
EC-E EC-E
1
2
3
2
PC53
ISP_0 PR202 PR201 PC49 330u/2V_7343
*Short_6 *Short_6 *330u/2V_7343
Close to
2
PR214 ISN_1
CPU socket 18.2K/F_4 PC137
PR215 0.1u/50V_6
+VCORE
1
2
3.92K/F_4 PR79
PR88 ISN_0 PC60 3.92K/F_4
10/F_6 1 0.1u/50V_6
2
PR208
2 CPU_VDD0_FB_H 6.81K/F_4 ISP_1
1
2 CPU_VDD0_FB_L PC130 PR80

1000p/50V_6 18.2K/F_4 ISN_1
+1.5VSUS
Parallel
PR83
1K/F_4
PR86
10/F_6
Close to
CPU socket
1
PR82
*0_4 PC131 +VCORE CPU_VDDNB_CORE
2
1200p/50V_4
2
1
PR81 PC134
10/F_6 + PC71 + PC200
1
4700p/25V_4
2 CPU_VDD1_FB_L PC133 330u/2V_7343
2
PR212 180p/50V_4 *330u_2V_7343
2
2 CPU_VDD1_FB_H 1K/F_4
1 PR211 1
255/F_4
+VCORE
PR87
10/F_6
PR209
54.9K/F_4
PROJECT : ZQ2
CPU_CORE 1A

A B C D E
5 4 3 2 1
VIN
VIN
+5VPCU
+1.1V_S5
PR247
10/F_6
5
6
7
8
PD11
D RB500V-40
OCP: 10A D
PR253 PR241
1M_6 2.2/F_6 PC187 4
6A
4.7u/6.3V_6 PQ66 +1.1V_S5
PR255 AO4468 PC180 PC192
PU13 *Short_6 2.2n/50V_4 10u/25V_1206
PR254 UP6111AQDD
*Short_6 PC191
15 13 0.1u/50V_6
33,35,42 S5_ON
3
2
1
EN/DEM BOOT PL14
+3V 16 12 UGATE-1.1V 1R0uH-3mR
TON UGATE
1 11 PHASE-1.1V +1.1V_S5
VOUT PHASE
PR244 2 10 PR243
VDD OC
5
6
7
8
*10K/F_6 7.15K/F_6
PC190 3 9 PC173 PR239
*0.1u/50V_6 FB VDDP 1u/16V_6 *4.7_6
4 8 LGATE-1.1V 4 +
33 HWPG_1.1V PGOOD LGATE
6 7
GND PGND PC175
5 17 *680p/50V_6
NC TPAD PQ65
14 AO4710
3
2
1
C NC C
PC179 PC189 PC161 PC158 PC157
1u/16V_6 *1000p/50V_6 560u/2.5V_6X5.7 *10u/10V_8 0.1u/50V_6
Rds*OCP=RILIM*20uA
PR246
5.1K/F_6 PC184
R1 *33p/50V_6
1.1V_FB
VOUT=(1+R1/R2)*0.75
PR245
10K/F_6
TON=3.85p*RTON*Vout/(Vin-0.5) AO4710 Rdson=11.7~14.2mOhm R2 PR242
*Short_6
L(ripple current)
B Frequency=Vout/(Vin*TON) =(19-1.1)*1.1/(1u*272k*19) B
~3.81A
TON=3.85p*1M*1/(Vin-0.5)
14.2m*10=RILIM*20uA
Frequency=1/(0.0036767)=272K RILIM=7.1K--- 7.15K
+1.1V
39 HWPG1.8V_D
VIN_SRC +1.1V +15V +1.1V_S5
PR111 PR102 PR110

5
6
7
1M_6 22_8 1M_6 8
2 1 DMN601K-7
33 1.2V_ON
PR107 *0_4 HWPG1.8V_D 4
3
PQ22
A A
2 1 2 PR105 AO4468
33,42 HWPG_1.8V
PR108 0_4 1M_6 2 2
3
2
1
PR104
PQ21 PQ20
DMN601K-7
PQ23
DMN601K-7 PC63 PROJECT : ZQ2
1
100K/F_6 *2200p/50V_4
+1.1V
1
7.5A Size Document Number Rev

VCCP 1.1V(UP6111A) 1A

5 4 3 2 1
5 4 3 2 1
VIN
VIN
+5V_S5
PR172
10/F_6
5
6
7
8
D EC-C PD6 D
RB500V-40
OCP: 10A
PR143 PR180 PR185
*0_6 1M_6 2.2/F_6 PC101 4
7.5A
PR144 4.7u/6.3V_6 PQ43 NB_CORE
33 NB_CORE_ON
100K/F_6 PR182 AO4468 PC104 PC103
PU8 *Short_6 2.2n/50V_4 10u/25V_1206
PR27 UP6111AQDD
*Short_6 PC100
15 13 0.1u/50V_6
15,33,36 CPU_COREPG
3
2
1
EN/DEM BOOT PL8
+3V UP6111AQDD_PIN16 16 12 UGATE-NB 1R0uH-3mR
TON UGATE
1 11 PHASE-NB NB_CORE
VOUT PHASE
PR178 UP6111AQDD_PIN2 2 10 PR183
VDD OC
5
6
7
8
*10K/F_6 7.15K/F_6
PC97 3 9 PC99 PR44
*0.1u/50V_6 FB VDDP 1u/16V_6 *4.7_6
4 8 LGATE-NB 4 +
33 HWPG_0.95V PGOOD LGATE
6 7
C GND PGND PC35 C
5 17 *680p/50V_6
NC TPAD PQ44
14 AO4710
3
2
1
NC
PC93 PC94 PC108 PC107 PC106
1u/16V_6 *1000p/50V_6 560u/2.5V_6X5.7 *10u/10V_8 0.1u/50V_6
Rds*OCP=RILIM*20uA
VOUT=(1+R1/R2)*0.75
PR175
2.74K/F_4 PC92
R1 *33p/50V_6 PR164 +5VPCU
13.3K/F_4
NB_CORE_FB NB_CORE_FB
PR181
*Short_6
3
B PR17 B
PR176 10K/F_4
10K/F_6
R2 2
PQ40
DMN601K-7 PR16
100_4 PR25
HI --- 0.95V
1
*0_4
PC15
LOW ---1.1V
3
0.01u/25V_4
TON=3.85p*RTON*Vout/(Vin-0.5) 2 +NB_CORE_ON 9
AO4710 Rdson=11.7~14.2mOhm
1
PQ7
DMN601K-7
Frequency=Vout/(Vin*TON) L(ripple current) PR26
1
=(19-1.05)*1.05/(1u*272k*19) *100K_4
2
A TON=3.85p*1M*1/(Vin-0.5) ~3.646A A
14.2m*10=RILIM*20uA
Frequency=1/(0.0036767)=272K RILIM=7.1K--- 7.15K
PROJECT : ZQ2
NB_CORE(UP6111A) 1A

5 4 3 2 1
5 4 3 2 1
[PWM]
PC159
10u/10V_8
PR230 PC155
*Short_6 0.1u/50V_6
8207A_VBST 0805 100u/25V_6X5.8
+0.75V_DDR_VTT
VIN
VIN
8207A_DH
PC166 PC165
1.71A
1
10u/10V_8 10u/10V_8 8207A_LX
D + D
5
8207A_DL
+1.5VSUS
2
4
PC151
25
24
23
22
21
20
19
PC152 PC153 PC203 OCP 22A
1
2
3
PQ62 2200p/50V_6 *10u/25V_0805 *10u/25V_0805
18A
LL
DRVL
GND
VTT
VLDOIN
VBST
DRVH
AOL1448 PL13
0.56uH
1 18 +1.5VSUS +1.5VSUS
VTTGND PGND
2 17
VTTSNS CS_GND
*560u/2.5V_6X5.7
3 RT8207A 16 PR224
GND PU12 CS 4.02K/F_6
PR114
+1.5VSUS 4 15 4 4 *4.7_6 + +
MODE V5IN +5V_S5
PQ61 PQ24
1
2
3
1
2
3
5 14 AOL1718 AOL1718
+SMDDR_VREF VTTREF V5FILT
1
PR225 PC68
VDDQSNS
VDDQSET
PC164 +5V_S5 6 13 PC154 5.1/F_6 PC150 *680p/50V_6
0.75A 0.033u/50V_6 COMP PGOOD 1u/6.3V_4 1u/6.3V_4 PC156 PC149 PC148
2
560u/2.5V_6X5.7 10u/10V_8
NC
NC
S3
S5
PR223 +3VPCU
*100K/F_6
7
10
11
12
FOR DDR III
C HW PG_1.5V 33 C
PR226 (For RT8207A 400KHZ )

VIN
620K/F_4
S5_1.8V PR227
0_6 SUSON 33
PR115
*Short_6 EC-E
S3_1.8V PR229
*0_6 MAINON 33,42
PR233
D07 +5V_S5
*0_6
2 VDDIO_FB_H
1 2
PR236 *0_4
PC160 PR232
*33p/50V_6 10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
AO1718 Rdson=3.8~4.3mOhm
8207A_SET
L(ripple current)
PR228
=(9-1.5)*1.5/(0.56u*400k*9)
0_6 ~5.58A +1.5VSUS
PR231 S5_1.8V S3_1.8V
10K/F_4
Vtrip= (22-2.79)(*4.3mohm/2)=0.0413V
RILIM=Vtrip/10uA~4.13K
1 2
5
6
7
8
2 VDDIO_FB_L PR235 *0_4
B B
HW PG1.8V_D 4
37 HW PG1.8V_D
PQ25
AO4468
+3V
3
2
1
PR49
33,36 VRON 2 1 +5VPCU *100K/F_4 CPU_VDDR (0.9V) +1.5V
PR200 *0_4 PC44 PU5
0.1u/50V_6 RT9025-25PSP
3.62A
4 1 HW PG_0.9V 33
VPP PGOOD
33,42 HW PG_2.5V 2 1 2 6 CPU_VDDR

PR48 0_4 VEN VO
+1.5VSUS 3
8
VIN PR53
0.75A
ADJ
GND
9
GND NC
5 R1 4.02K/F_6
0.8V PC46
7
1.2VADJ0.9V 10u/10V_8
PR52
PC43 PC41 PC42 R2 30.1K/F_6
10u/10V_8 0.1u/50V_6 *0.1u/50V_6 PR56
A A
22.1K/F_4
PQ55
VO=0.8(1+R1/R2)
3
DMN601K-7
=0.9V
13 VDDR_OPT PR204 33_4 2 VO=(0.8(R1+R2)/R2)
R2<120Kohm PROJECT : ZQ2
PC118 Quanta Computer Inc.
1
220P/50V_4
DDR 1.5V(TPS51116) 1A
Date: W ednesday, May 27, 2009 Sheet 39 of 46

5 4 3 2 1
1 2 3 4 5
+VGPU_CORE
0805
+5V_S5 VIN
VIN
A A
1
+ OCP=33A
PR12 22.5A
+3V +3V_D_EXT *SW@0_4 PC204
2
PR165
5
SW@200K/F_4 +VGPU_CORE
PC83 SW@1u/10V_6 8792TON
SW@10K_4
*SW@10K_4
2 7
VDD TON PQ37
C03 8792DH
5 4 SW@AOL1448
8792VCC DH
PR149
PR151
PC77 SW@1u/10V_6 13 PC76
VCC SW@2200p/50V_4 PC79 PC78 PC80
1
2
3
6 8792BST *SW@4.7u/25V_0805 SW@100u/25V_6X5.8
BST PR162 PC88 *SW@4.7u/25V_0805
41 PG_GPUIO_EN 14
PGOOD SW@1_6 SW@0.22u/25V_6 PL6 *SW@4.7u/25V_0805
8792_EN 1 SW@0.36uH
19,41 dGPU_PWREN EN 8792LX +VGPU_CORE
4
PR145 PU7 LX
*SW@0_4 8792SKIP# 12 SW@MAX8792ETD+T
SKIP# 8792DL
3
5
PC82 PR11 *SW@0_4 DL
+3V_D_EXT
SW@0.1u/10V_4 8792REFIN 10 PR9
PR146 REFIN SW@1_6
8
SW@0_4 FB + + +
4 4
PR150 REF-2V
SW@100K_4 8792REF 11 9 8792ILIM PC90
1
2
3
1
2
3
REF ILIM SW@330u/2V
PC8
EP
SW@1000p/50V_4
R1 PR158
15
B B
PR157
SW@39.2K/F_4 SW@120K/F_4 PR141 PC7
SW@0_6 *SW@4700P/25V_4 PQ1 PQ35 PC95 PC12 PC13
R3 SW@AOL1718 SW@AOL1718 SW@0.1u/50V_6 *SW@330u/2V SW@330u/2V
Place near GND pin15
PR14 PC84
3
SW@332K/F_4 SW@1000P/50V_4
PR159
SW@100K_4
2
17 GPU_VID1
PQ4
PR154 SW@DMN601K-7
SW@100K_4 R2 PR161
1
PC89
SW@0.01u/16V_4
R4 SW@49.9K/F_4
VIN_SRC +VGPU_CORE
PR13
3
SW@130K/F_4
Frequency(PR220=200K) 300K PR2 PR3
SW@1M_6 *SW@22_8
C 2 C
17 GPU_VID2
PQ3
3
PR155 SW@DMN601K-7
SW@100K_4
1
3
AMD Madison VID Table 2
8792_EN 2
GPU_VID1 (GPIO15) GPU_VID2 (GPIO20) +VGPU_CORE PQ2
PR1 DMN601K-7
1
PC81 PQ34 SW@1M_6
0 0 1.05V
1
SW@0.01u/16V_4 PR142 SW@DTC144EU
1 0 1.0V *SW@100K_4
0 1 0.95V
2
1 1 0.9V
Park -XT
GPU_VID1 (GPIO15) GPU_VID2 (GPIO20) +VGPU_CORE
0 0 1.12V
1 0 1.05V
0 1 0.95V
D D
1 1 0.9V
R3 R4 R1 R2 VREF
332K 130K 39.2K 49.9K 2V PROJECT : ZQ2
R1 change to 39.2K/F_4 (CS33922FB15)
R3 change to 332K/F_4 (CS43322FB15)
R4 change to 130K/F_4 (CS41302FB00) GPU CORE(MAX8792) 1A

1 2 3 4 5
5 4 3 2 1
+3V
+1V
1
+5VPCU PR29
SW@10K_4
PC27 PU3
2
D SW@0.1u/50V_6 SW@RT9018A D
4 1 PG_1.5V_EN
VPP PGOOD
2 6 +1V
40 PG_GPUIO_EN VEN VO
+1.5VSUS 3
VIN 1.5A
8
ADJ
GND
SW@10u/10V_8
SW@0.1u/50V_6
SW@0.1u/50V_6
9 5
1
PR31 GND NC PR28
SW@100K_4 PC25 PC24 PC20 SW@9.1K/F_6
7
PC19
2
SW@22u/10V_1206
0.8V
1V_ADJ
PR30
SW@34K/F_6
Vout =0.8(1+R1/R2)
=1V
C C
+1.5V_GPU
VIN_SRC +1.5V_GPU +15V +1.5VSUS
PR72 PR69
5
6
7
8
SW@1M/F_6 SW@22_8 PR68
SW@1M/F_6
PG_1.5V_EN PR73 SW@0_6 DGPU_1.5V_ON_R 4
3
3
PQ54
PR74 *SW@0_6 2 SW@AO4468
19,40 dGPU_PWREN
2 2
PQ16
3
2
1
1
PR71 PQ18
PR70 SW@DMN601K-7 SW@1M/F_6 SW@DMN601K-7 PQ17 +1.5V_GPU
1
B SW@100K_4 SW@DMN601K-7 B
1
1
PC55 5.63A
2
*SW@2.2n/50V_4
VIN_SRC +1.8V_GPU +15V +1.8V
PR193 PR194 PR188

+1.8V_GPU
3
SW@1M/F_6 SW@22_8 SW@1M/F_6

PG_1.5V_EN PR148 SW@0_6
2
3
PR195
*SW@0_4 PQ50
A
+1.5V_GPU 2 SW@AO3404 A
1
2 2
PQ49 PR197
+1.8V_GPU
PC112 SW@DMN601K-7
SW@1M/F_6 PQ53
SW@DMN601K-7
PQ46
SW@DMN601K-7
PC109
*SW@2.2n/50V_4
PROJECT : ZQ2
0.96A
1
*SW@1U/10V_4
1

+1V/+1.5_GPU/+1.8_GPU 1A

5 4 3 2 1
5 4 3 2 1
+3VPCU
1.95A
+1.8V
PC123
PC125 0.1u/25V_4
10u/10V_8
PU10 HPA00835RTER
16 10 PH10_11_12
D VIN PH +1.8V D
1 11 PL9
VIN PH 1uH_7X7X3
PR60 2 12
*Short_4 VIN PH *Short_6
15 13 PR205
33,39 MAINON EN BOOT
54418-1.8_VFB 6 14 PC121
VSNS PWRGD 0.1u/50V_6
PC122 COMP_PIN7 7 3
1000p/50V_4 COMP GND
8
RT/CLK GND
4 R1
PAD
PAD
PAD
PAD
PAD
PAD
HW PG_1.8V 33,37
9 5 PR59
PR58 PR57 SS AGND PR65
10K_4
15K/F_4 182K/F_4 +3V 100K/F_4 PC116 PC115 PC45
22
21
20
19
18
17
0.1u/25V_4 10u/10V_8 10u/10V_8
PC48
*100P/50V_4 PC120
0.01u/25V_4 54418-1.8_VFB
PC50 VIN_SRC
1200p/50V_4
PR61 PD8
V0=0.8*(R1+R2)/R2 R2 78.7K/F_4 SW 1010CPT
C C
PR189
1
1M_6
PQ52
PR109 +2.5V AO3409
EC-C 10K_4 2
PC66 +5VPCU
+3V
MAINON 2 1 1u/16V_6 PU6
3
PR112 0_4 RT9025-25PSP
4 1 HW PG_2.5V 33,36,39
3
VPP PGOOD S5_ON
33,35,37 S5_ON 2
33 VR2.5_ON 2 1 2 6 +2.5V
PR113 *0_4 VEN VO
3
0.2A PQ47
+3VPCU
1
VIN PR103 DTC144EU PR190
8 R1 Thermal protection
ADJ
GND VL VL *Short_6
9 5 73.2K/F_4
GND NC
PC62
7
10u/10V_8
0.8V PR106 LM393_PIN8

SYS_SHDN# 2,4,35
PC65 PC67 PC64
10u/10V_8 0.1u/50V_6 *0.1u/50V_6
R2 34K/F_6
PR196 PR198
1.2K/F_4 200K/F_4 PR191
200K_6
Vout =0.8(1+R1/R2) PC110
B 0.1u/50V_6 B
=2.5V
3
8
PR192
THERMISTOR_10K_6(NTC) 2.469V 3
+
1 2
LM393_PIN2 2
- PQ48
PU9A DMN601K-7
4
VIN_SRC +3V +5V +1.8V +1.5V +15V LM393 PC111
1
0.1u/50V_6
PR199
3
PR62 PR50 PR51 PR66 PR55 PR54 200K/F_4
1M_6 22_8 22_8 22_8 22_8 1M_6
S5_ON 2
MAINON_ON_G MAIND 5
MAIND 35 PQ51 +
7
3
DMN601K-7 6
3
1
PR63 PU9B
MAINON 2 PQ14 1M_6 2 2 2 2 2 LM393
DTC144EU PC47
PQ10 PQ11 PQ15 PQ12 PQ13 *2200p/50V_4
DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7
For EC control thermal protection (output 3.3V)
1
PR64
1
*100K/F_6
A A
PROJECT : ZQ2
Discharge /Thermal protection 1A

5 4 3 2 1
5 4 3 2 1
ZQ2 Power tree
+5VPCU (6.15A)
<Alway ON>
<S5_ON--->S5D> AO4468 +5V_S5 (3~4A) USB/M*1

<S5D> PQ27 USB/S*3
Page32
Page37
HDD
ODD
<MAINON--->MAIND> AO4468 +5V (3.2~4.3A) FAN
D
<MAIND> PQ26 ALC271 D
Page37
ADAPTER Smart
65W/90W +3VPCU (5.03A)
Charger <Alway ON>
RT8206B
ISL88731A BT
BATTERY PU4 PU0001 AO3404
<S5_ON--->S5D> +3V_S5 (1.3A)
Page36 PQ29 LAN
<S5D>
Page37
Page37
<MAINON--->MAIND> AO4468 +3V (3.2A)
VIN_SRC
<MAIND> PQ28
Page37 +3V_D
--<EC>-- SW@AO3413 (1A)
<dGPU_VRON>
Q26
RT9025 *<+1.5V_GPU> Page20
--<EC>--
*<VR2.5_ON> PU6 +2.5V (0.2A)
<+3V> Page44 +CPUVDDA
HPA00835RTER +1.8V (1.95A)

--<EC>-- PU10
<MAINON>
Page44
SW@AO3404 +1.8V_GPU (0.96A)
Q50
C
<+1.5V_GPU> Page45 C
SW@AO3404 +1.5V_GPU (10.7A)

<PG_1V_EN--->PG_1.5V_EN> PQ54
<PG_1.5V_EN> Page41
--<EC>-- AO1413 +1.5VSUS (18.71A) +1.5VSUS
<VIN_ON> PQ8
Page36
SW@G9018A
PU3 +1V (1.5A)
<PG_GPUIO_EN-->PG_1V_EN>
<PG_1V_EN> Page44
RT8207A
--<EC>-- PU12 RT9025 CPU_VDDR

<SUSON> (0.75A)
<VR2.5_ON-->HWPG_2.5V> PU5
<HWPG_2.5V>
*<MAINON> Page41 --<EC>-- Page45
*<VRON>
AO4468
VIN
--<EC>-- PQ25 +1.5V (7.87A)

<MAINON> Page41
B B
+0.75V_DDR_VTT (1.71A)
+SMDDR_VREF (0.75V) (0.75A)
UP6111A +1.1V_S5 (6A)

--<EC>-- PU13
<S5_ON>
Page39
<MAINON--->HWPG_1.8V> AO4468 +1.1V (5.5~7.8A)

<HWPG_1.8V> PQ22
--<EC>--
*<1.2V_ON> Page39
UP6111A
NB_CORE (7.5A)
<VRON-->CPU_COREPG> PU8
<CPU_COREPG> Page40
SW@MAX8792 +VGPU_CORE (22.5A)

--<EC>-- PU7
<dGPU_VRON> Page42
SW@ISL62872 +VGPU_IO (4A)

<dGPU_VRON-->PG_GPUIO_EN> PU2
A
<PG_GPUIO_EN> Page43 A
+VCORE (20A)
ISL6265A
PU11
--<EC>-- CPU_VDDNB_CORE
<VRON> Page38 (3A)
PROJECT : ZQ2
Power Tree 1A
5 4 3 2 1
1 2 3 4 5 6 7 8
47
Power on Sequence required:
SB800:
1, +3.3VDUAL ramp before +1.1VDUAL
2, +3.3V ramp before +1.8v CPU_LDT_RST#
3, +1.8V ramp before +1.1v (SB TO CPU)
4, +3.3v ramp before +1.1v
5, +3.3VALW_R ramping down time > 300us
6, 50uS <= All power rails except +3.3VALW_R <= 40mS
7, 100uS <= +3.3VALW_R <= 40mS CPU_PW ROK
(SB TO CPU) >1 mS Req.
RS880: CPU_CLKP/N running
A
1, 0 <(+3.3V) - (+1.8v) < 2.1 A
2, +1.8V ramp before +1.1v
3. +1.1V ramp before VCC_NB >1 mS Req.
running
>1 mS Req. NB_CORE(all NB power) valid before NB_PW RGD_IN

SB OUTPUT NB_PW RGD
NB_PW RGD_IN
SLP_S3# 1V1DUAL_PW RGD
SB INPUT SB_PW RGD_IN SYS_RST# 1V5_PW RGD/DNI
+1.2V_PW RGD KBC_GPIO77/DNI
HW PG_0.95V
RC=~22ms NB_CORE should not ramp before +1.1v

NB_CORE
RC=~4.7ms
VLDT
GROUP B
VRM_PW RGD AND HW PG_1.8V (modify at B)

+1.1V
CPU_COREPG
RC=0
CPU_VDDR
RC=0
+VCC_CORE
RC=0
CPU_VDDNB_CORE
B B
HW PG_2.5V
GROUP A
+2.5V
(CPU_VDDA_2.5_RUN)
+1.5V
HW PG_1.8V
RC=0
+1.8V
+5V/+3.3V
MAIN_ON
to S3
SUSB#
VDRAM_PW RGD
CPU MEM CTL &
DDR3 SODIMM PWRS +0.75V_DDR_VTT +0.75V_DDR_VTT only will be shut down in S3 mode, and +0.75V_DDR_VTT for DDR3 SODIMM only.
+SMDDR_VREF
+1.5V_SUS
SUSC#
C C
Power button from EC to SB
DNBSW ON#
20mS
CPU_THM/SB/SB_SCL1/2 delay
SB_KB/SPI/LPC ROM PWRS RSMRST#
HW PG_1.1V
+5V_S5/+3.3_S5/+1.1_S5
S5 RAILS W hen IMC, always on at all time( always PW R)
SUSD
S5_ON
Power button pressed

NBSW ON#
KBC is ready
AC not present scenario = LOW AC present= high
ACIN
(ACIN detect)
KBC is powered by
+3.3VPCU +5VPCU/+3.3VPCU
LDO:5.4V
(from DCIN)
Battery inserted/AC IN
VIN_SRC
+AVBAT
D D
PROJECT : ZQ2
Power squence 1A

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3VPCU
3 HWPG_1.1V
Group-A
47
+3.3V_S5
Power on Sequence required:
PWRGD PWRGD 2
EC +1.1VEN
+1.5V
S5_ON 1 +5V_S5 +1.1V_S5 +1.5V_SUS
A
RT8206B UP6111A SB800: A
SMSC HWPG_1.8V SWITCH 1, +3.3V_S5 ramp before +1.1_S5
+1.8V (OPTION) 2, +3.3V ramp before +1.8v
DNBSWON# HPA00835RTER
4 3, +1.8V ramp before +1.1v
+1.5V_SUS +1.8VEN
PWRGD
+1.1V_S5 +1.1V 4, +3.3v ramp before +1.1v
SUSON 5 MAX8207A 5, +3.3VALW_R ramping down time > 300us
SB820 5 +0.75V_DDR_VTT SWITCH 6, 50uS <= All power rails except +3.3VALW_R <=
MAIN_ON
+1.2V_ON 40mS
MAIN_ON 5
7, 100uS <= +3.3VALW_R <= 40mS
+5V_S5 5 +5V
CPU_VDDR RS880:
7 +2.5V 9
+3.3V_S5 SWITCH +3.3V RT9025 1, 0 <(+3.3V) - (+1.8v) < 2.1
6 RT9025 +VCORE 2, +1.8V ramp before +1.1v
B LDO 9 3. +1.1V ramp before VCC_NB B
+2.5V_ON EN
HWPG_2.5V 8 ISL6265A
CPU_VDDNB_CORE
9
CPU_COREPG PWRGD
10 NB_CORE
UP6111A
POWER RAILS Sequencing

SB820 Sequencing RS880 Sequencing EC Sequencing
1 S5_ON 13 +1.8V 1 +3.3V_S5 1 +3.3V 1 3VPCU
C 2 +3.3V_S5 14 HWPG_1.8V 2 ICH_RSMRST# 2 NB POWER RAILS 2 NBSWON# C
3 +5V_S5 15 +1.5V 3 S0 POWER 3 ATX PS_PWRGD 3 VIN_ON
4 +1.1V_S5 16 +2.5V 4 PCIE_RCLKP/N 4 NB INPUT CLOCKS 4 S5_ON
5 HWPG_1.1V 17 HWPG_2.5V 5 PCICLK[4:0] 5 CPUCLK 5 ICH_RSMRST#
6 DNBSWON# 18 CPU_VDDNB_CORE 6 SB_PWRGD_IN 6 NB_PWRGD 6 -DNBSWON#
7 SUSON 19 +VCC_CORE 7 NB_PWRGD_IN 7 SB_PWRGD 7 SUSB#/SUSC#
8 +1.5V_SUS 20 CPU_VDDR 8 LDT_PG 8 LDT_PG/CPU_PWRGD 8 SUSON/USB_ON#
9 +SMDDR_VTERM 21 CPU_COREPG 9 KBRST# 9 PCIRST#,NB_RST# 9 MAIN_ON/HWPG

D D
10 MAIN_ON 22 +1.1V 10 A_RST# 10 LDT_RST# 10 VRON

PROJECT : ZQ2
11 +5V 23 NB_CORE 11 PCIRST# 11 11 PWROK
12 +3.3V 24 12 LDT_RST# 12 12 Hole, Nuts 1A

1 2 3 4 5 6 7 8
5 4 3 2 1
MODEL
ZQ2
Model REV CHANGE LIST FROM To
X 1A
1A 1.A01 del Ext-CLK Gen component X 1A
ZQ2 MB 2.A02 del Power VGPU-IO 1A 2A
1A 2A
3.A03 page 7,9,10 add side-port
1A 2A
4.A04 page9 R123 no stuff ,R129 stuff for A-test boot issue 1A 2A
5.A05 page9 U22.D8 change to A_RST#_SB 1A 2A
6.A06 page11 move dGPU_PWROK from U29.AA4 to U29.AJ6 1A 2A
1A 2A
D 7.A07 page11 move BOARD_ID[0:5] to U29.AC3 D
1A 2A
8.A08 page12,17 add VGA_REQ# for VGA_CLK request 1A 2A
9.A09 page13 move MEM_1V5 to U29.A7 1A 2A
10.A10 page13 update Board_ID table 1A 2A
11.A11 page13 add sideport table 1A 2A

1A 2A
12.A12 page 15 del R471 for just only use int-clkgen 1A 2A
13.A13 page 11,16 add CLK_14M_VGA for Park boot 1A 2A
14.A14 page 17 modify GPU_VID gpio relation 1A 2A
15.A15 page18 modify R86 from 680 to 51 1A 2A
1A 2A
16.A16 page19 add +3V_D_EXT for leakage issue 1A 2A
17.A17 page20 del don't use port for cost down 1A 2A
1A 2A
2A 1A 2A
B01 Page10 modify L77 footprint 1A 2A
B02 Page23 modify R54 stuff for Discrete,R50 for UMA 1A 2A
B03 Page27 modify ODD power connection 1A 2A
B04 Page change 0-ohm R185,R89,R93,R136,R142,R485,R487,R488,R489,R490,R493,R503 to short pad 2A 3A
B05 Page12 add CLK request pull up R501,R551 2A 3A
B06 Page30 add Q41,Q42,R651,R652,R633 from LED board 2A 3A
B07 Page add R659,R660,R661,R662 from power board 2A 3A
B08 Page modify R314,R315,R316,R322 follow ZQ1 2A 3A
B09 Page add Q40,and RF_LED_EN# with RF_LED# to EC 2A 3A
C
B10 Page change U26,CN10,U12 footprint 2A 3A C
B11 Page C534C537C154C147C144C129C14C20C18C17C15C32C39 2A 3A

C50C62C72C88C87C103C102C29 from CC0402-C to CC0402. 2A 3A
L8 R48 R41 R30 L1 L14 from RC0402-C to RC0402.
2A 3A
B12 Page R377 stuff ,R247 no stuff follow AMD sch.
2A 3A
B13 Page change D2,D3,D23,D25,D26,D29 to BAS316
2A 3A
B14 Page reserve R152,R423,L4 (USBP2)option for CCD issue
B01 2A 3A
B15 Page change U26,CN10,U12 footprint
2A 3A
B16 Page13 Change board ID power rail from +3V_S5 to +3V.
2A 3A
B17 Page10 W/O Sideport ,R146 no-stuff, C831 connect to GND
2A 3A
B18 Page9 no-stuff R108,R105
2A 3A
B19 Page28 del D20,D21,D22 &R498 from 10K->1K & add Q43,Q44,Q45
2A 3A
2A 3A
3A
C01 Page02 Add H/W shutdown function and add CPU_COREPG shutdown design(add Q43,R152) 2A 3A
C02 Page23 Option brightness switch control just only by NB R50 2A 3A
C03 Page40 Change PG_GPUIO_EN pull high power rail from +3V to +3V_D_EXT. For Park GPU SG mode hang up issue. 2A 3A
C04 Page42 Change PR60 from 10k to 0ohm. 2A 3A
C05 Page30 chang LED R R660,R661,R662,R663,R314,R316,R321 2A 3A
C06 PageX change R 0ohm to short pad 2A 3A
C07 PageX audio for codec suggestion 2A 3A
C08 PageX X. 2A 3A
C09 PageX X 2A 3A
C10 PageX X. 2A 3A
C11 PageX X. 2A 3A
C12 PageX X. 2A 3A
B
2A 3A B
3A 3B
4A D01 Page03 Change CPU VDDR_SENSE pull high power rail to CPU_VDDR and remove trace connect to controller IC.
3A 3B
D02 Page15 Modify text note.
3A 3B
D03 Page12 Change "GBE_COL" ,"GBE_CRS" ,"GBE_RXERR" to GND follow SCL V1.04 version.
3A 3B
D04 Page14 Change USB PLL power rail source to separate VDDPL_33_USB_S follow SCL V1.04 version.
3A 3B
D05 Page04 R409 no stuff, R413 stuff
3A 3B
D06 Page09 del PD5, PR124-390k for panasonic battery low power protect issue.
3A 3B
D07 Page36 PR229 no stuff
3A 3B
D08 Page23 C212,C213,C214,C220,C221,C222 from 33p to 10p
3A 3B
D09 Page21 modify DDR3 Memory table
3A 3B
D10 Page28 R568 stuff and R498 no stuff for Audio issue
3A 3B
D11 Page2/4 Q3 pin 3 change to PM_THERM#,Q3 pin 8 add PM_THERM#
3A 3B
D12 Page23 reserve C541 for monitor test issue
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
A
3A 3B A
3A 3B
3A 3B
3A 3B
3A 3B
3C
PROJECT : ZQ2
DOC NO. PROJECT MODEL : ZQ2 APPROVED BY: DATE: 2009/08/13 Quanta Computer Inc.
Change list 1A
PART NUMBER: DRAWING BY: REVISON: 1A
5 4 3 2 1

Acer Aspire 4553 4553g 5553 5553g 4625 4625g 5625 5625g Quanta zq2 Rev 1a SCH PDF

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1 2 3 4 5 6 7 8

PCB STACK UP ZQ2 SYSTEM DIAGRAM 01

DDR3-SODIMM2 DDR3 channel B

NB_CORE (UP6111AQDD) PAGE 12,13,14,15,16 0 8 5 4

SYSTEM 5V/3V (RT8206) Switch BOARD

1.1V(UP6111AQDD) SPI Digital MIC AUDIO CONN Speaker

CPU_LDT_REQ#_CPU 1 3 +1.5VSUS R405 1K/F_4

G2 +1.5V R413 1K/F_4

+1.5VSUS R90 *1K/F_4 Q4

15,33,36 CPU_COREPG CPU_DBREQ# 7 8 CPUTEST21 R121 1K/F_4

Q8 D11 C530 *0.1U/10V_4 23 24 CPU_LDT_RST_HTPA#

VDDR=>1.75A CPU_VDDR D01

PLACE THEM CLOSE TO D10 W10 +SMDDR_VREF

5 M_B_DQSP0 C12 G13 M_A_DQSP0 5

U6 *.1U/10V_4 MB_DQS_L6 MA_DQS_L6

1 R100 *OPA343NA/3K SOCKET_638_PIN 1

1K/F_4 *0.47U/10V_4 R111

R109 *0/J_4 PROJECT : ZQ2

+3V PROCESSOR POWER AND GROUND

A MSOP R187 *10K/F_4 A

Adress ID: 9A R402 *10K/F_4

S1G4 PWR & GND 3/3 1A

Date: Wednesday, May 27, 2009 Sheet 4 of 46

3 M_A_A[0..15] +1.5VSUS M_A_DQ[0..63] 3 3 M_B_A[0..15] +1.5VSUS M_B_DQ[0..63] 3

DQS2 DQ32 M_A_DQ36 DQS2 DQ32 M_B_DQ32

137 141 137 141

DQS4 DQ34 2 DQS4 DQ34

3 M_A_DQSP5 154 143 21

3 M_B_DQSP5 154 143 31

171 130 171 130

188 132 188 132

DQS7 DQ37 M_A_DQ33 DQS7 DQ37 M_B_DQ38

DQS0# DQ39 DQS0# DQ39

DQS2# DQ41 DQS2# DQ41

DQS3# DQ42 M_A_DQ47

DQS3# DQ42 M_B_DQ47

135 159 135 159

3 M_A_DQSN4 DQS4# DQ43 3 M_B_DQSN4 DQS4# DQ43

152 146 152 146

DQS5# DQ44 DQS5# DQ44

3 M_A_DQSN6 169 148 115

3 M_B_DQSN6 169 148 125

DQS6# DQ45 DQS6# DQ45

186 158 186 158

DQS7# DQ46 DQS7# DQ46

101 165 101 165

CK0 DQ49 CK0 DQ49

103 175 103 175

CK0# DQ50 CK0# DQ50

102 177 102 177

CK1 DQ51 CK1 DQ51

104 164 104 164

CK1# DQ52 M_A_DQ48

CK1# DQ52 M_B_DQ49

DQ53 M_A_DQ50 DQ53 M_B_DQ55

VSS7 VSS31 R94 2.2K/J_4 Q6 VSS7 VSS31

Place these Caps near So-Dimm H=8.

C326 C333 C344 C297 C317

C313 C307 C337 C306 C345

Place these Caps near So-Dimm H=4.

C340 C339 C341 C329 C325

C315 C305 C324 C308 C346

Date: Wednesday, May 27, 2009 Sheet 6 of 46