CSE 260 – Digital Computers: Organization and Logical Design

Homework 10 Solutions
Jon Turner

1. (20 points) Consider the circuit shown below. Assume that the circuit elements have the
following timing characteristics.

gate delays can vary from 0.5 ns to 2

flip flop propagation delays can vary from 1.5 ns to 4 ns
setup time: 1 ns
hold time: 0.5 ns
maximum clock skew: 0.5 ns

Explain why this circuit is not subject to hold time violations. By how much could the clock
skew increase without creating the possibility of hold time violations?

The minimum flip propagation delay minus the clock skew is 1 ns, which is larger than the hold time
of 0.5 ns, so even if the combinational logic delay between flip flops were zero, we could not have a
hold time violation.

The shortest path from a flip flop output to a flip flop input has two gates, so the minimum
combinational circuit delay is 1 ns. So, adding the minimum flip flop propagation delay to the

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minimum combinational circuit delay we get 2.5 ns. With a hold time of 0.5 ns, we would need a
clock skew of at least 2 ns before a hold time violation could occur.

What is the maximum safe operating frequency for this circuit?

The longest combinational circuit path passes through 3 gates. At 2 ns per gate, that gives us a
maximum combinational circuit delay of 6 ns. Adding this to the max flip flop propagation delay plus
the setup time plus the clock skew gives us a minimum clock period of 11.5 ns, which corresponds to a
maximum safe operating frequency of 87 MHz.

During what time period relative to a rising clock edge must the inputs A and B be stable?

The circuit paths from A to the flip flops all have 2 or 3 gates yielding a delay that ranges from 1 ns to
6 ns. With a setup time of 1 ns and a hold time of 0.5 ns, this means that A must be stable from 7 ns
before the clock edge to 0.5 ns before the clock edge.

The circuit paths from B to the flip flops all have between 2 and 3 gates yielding a delay that ranges
from 1 ns to 8 ns. This means that B must be stable from 9 ns before the clock edge to 0.5 ns before the
clock edge.

During what time period relative to a rising clock edge is it possible for output X to change?
How does your answer change during a period when input B is stable?

Output X can change at any time, since it is connected by a combinational circuit path to input B.
During a period when input B is stable, any change to X is a result of a change in one of the flip flops.
Since the circuit paths from the flip flop outputs to X have either 2 or 3 gates, X can change from 2.5
ns after the clock edge to 10 ns after the clock edge.

If the output X is connected to the A input of a second copy of the same circuit, what is the
maximum safe operating frequency for the combination of the two circuits?

In this case the longest path from a flip flop output to a flip flop input passes through 6 gates. This
increases the minimum clock period from 11.5 ns to 17.5 ns, giving us a maximum safe operating
frequency of 57 MHz.

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