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R22 SYSTEM DIAGRAM 01


DDR3-SODIMM1 DDR3 channel A
AMD Champlain CPU THERMAL
PAGE 6 SENSOR
35mm X 35mm
A A
S1G4 Processor PAGE 5
DDR3-SODIMM2 DDR3 channel B
638P (PGA)35W/25W
PAGE 7 PAGE 3,4,5

HT3

PCI-Express 8X
PCI-E HDMI
PAGE 25
X1 X1 X1 NORTH BRIDGE ATI
CRT
Flash Media LAN Mini PCI-E RS880M A12 PAGE 24 SEYMOUR-XT
RTS5219-GR Realtek Card
PAGE 26 PCIE-LAN
RTS8165EH-CG (Wireless LAN)
21mm X 21mm, 528pin BGA LVDS
B
(10/100) 23mm X 23mm B
PAGE 23
Side port
PAGE 30 PAGE 33 DDR3
PAGE 17,18,19
PAGE 8,9,10,11 20,21
DDR3 RAM
VRAM
for UMA only PAGE 22
RJ45 PAGE 8
ALINK X4
PAGE 30
SYSTEM CHARGER(ISL6251) USB2.0
PAGE 40 0,5,8 15 2 10
SATA - HDD
SATA0 150MB
SOUTH BRIDGE USB2.0 Ports BT softbreeze Webcam
PAGE 29 PAGE 29 PAGE 29
PCI-E WLAN Card x1
SYSTEM POWER ISL6237 X3 X1 PAGE 23 PAGE 33
PAGE 34 SB820 A13
SATA - CD-ROM
SATA4 150MB
21mm X 21mm, 605pin FCBGA
DDR II SMDDR_VTERM PAGE 29
1.8V/1.8VSUS(RT8207) 4.5W(Ext)
C PAGE 37 4.3W(Int) Azalia C

PAGE 12,13,14,15,16
VCCP +1.1V AND +1.2V(RT8204)

PAGE 35 IDT
92HD80
LPC
VGACORE(1.1V~1.2V)Oz8118 PAGE 27
PAGE 38
ENE KBC
AUDIO CONN
CPU CORE ISL6265HRTZ-T KB3930 Qx DIG MIC
(Phone/ MIC)
PAGE 36
PAGE 32 PAGE 27 PAGE 28

SMBUS TABLE
Clock gen/Robson/TV tuner
SB--SCL0/SD0 /DDR2/DDR2 thermal/Accelerometer +3V
D Keyboard PAGE 31 FAN SPI D

Touch Pad PAGE 31


epress card PAGE 28 PAGE 31
Wlan Card +3VS5
PROJECT : R22
EC --SCL/SD Battery charge/discharge +3VPCU Quanta Computer Inc.
EC--SCL2/SD2 VGA thermal/system thermal +3V Size Document Number Rev
Custom 1A
Block Diagram
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 1 of 43
1 2 3 4 5 6 7 8
5 4 3 2 1

02
D D

Use internal CLK GEN

C C

B B

A A

PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Clock Generator
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 2 of 43
5 4 3 2 1
5 4 3 2 1

PBY201209T-221Y-N H_THRMDC

03
+CPUVDDA
W/S= 15 mil/20mil H_THRMDA
H_THRMDC 5
+2.5V H_THRMDA 5
VLDT use 1.5A Max current L31 CPU CLK CPU_PWRGD 300_4 R148
+1.1V +1.1V_VLDT C414 LS0805-100M-N C386 C319 C322 CPUCLKP CPU_LDT_RST# 300_4 R149
12 CPUCLKP
4.7U/6.3V_6 4.7U/6.3V_6 0.22U/25V_6 3300P/50V_4 CPUCLKN CPU_LDT_STOP# 300_4 R177
12 CPUCLKN
R174 *0_6/S CPU_LDT_REQ#_CPU *300/F_4 R147 +1.5V
Keep trace from resisor to CPU within 0.6"
+1.1V +1.1V_VLDT_R +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U19D
R54 *0_6/S U19A W/S= 15 mil/20mil
+CPUVDDA F8 M11
+1.1V_VLDT +1.1V_VLDT_R 10U/6.3V_8 C111 CPUCLKIN R150 169/F_4 CPUCLKIN# +CPUVDDA VDDA1 VSS
D1 VLDT_A0 HT LINK VLDT_B0 AE2 F9 VDDA2 RSVD11 W18
C389 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT_R 0.22U/6.3V_4 C126
D C385 0.22U/6.3V_4 +1.1V_VLDT VLDT_A1 VLDT_B1 +1.1V_VLDT_R 180P/50V_4 C133 CPUCLKP C395 3900P/25V_4 CPUCLKIN CPU_SVC_R D
D3 VLDT_A2 VLDT_B2 AE4 A9 CLKIN_H SVC A6
C383 180P/50V_4 +1.1V_VLDT D4 AE5 +1.1V_VLDT_R 10U/6.3V_8 C548 CPUCLKN C394 3900P/25V_4 CPUCLKIN# A8 A4 CPU_SVD_R
VLDT_A3 VLDT_B3 CLKIN_L SVD
HT_NB_CPU_CAD_H0 E3 AD1 HT_CPU_NB_CAD_H0 CPU_LDT_RST# B7
L0_CADIN_H0 L0_CADOUT_H0 12 CPU_LDT_RST# RESET_L
HT_NB_CPU_CAD_L0 E2 AC1 HT_CPU_NB_CAD_L0 CPU_PWRGD A7
L0_CADIN_L0 L0_CADOUT_L0 12 CPU_PWRGD PWROK
HT_NB_CPU_CAD_H1 E1 AC2 HT_CPU_NB_CAD_H1 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L#
L0_CADIN_H1 L0_CADOUT_H1 10,12 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
HT_NB_CPU_CAD_L1 F1 AC3 HT_CPU_NB_CAD_L1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_NB_CPU_CAD_H2 L0_CADIN_L1 L0_CADOUT_L1 HT_CPU_NB_CAD_H2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 AB1 AA8 T10
HT_NB_CPU_CAD_L2 L0_CADIN_H2 L0_CADOUT_H2 HT_CPU_NB_CAD_L2 CPU_SIC MEMHOT_L
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1 5 CPU_SIC AF4 SIC
HT_NB_CPU_CAD_H3 G1 AA2 HT_CPU_NB_CAD_H3 SideBand Temp sense I2C CPU_SID AF5
HT_NB_CPU_CAD_H[15..0] L0_CADIN_H3 L0_CADOUT_H3 5 CPU_SID SID
HT_NB_CPU_CAD_L3 H1 AA3 HT_CPU_NB_CAD_L3 CPU_ALERT AE6 W7 H_THRMDC
8 HT_NB_CPU_CAD_H[15..0] L0_CADIN_L3 L0_CADOUT_L3 5 CPU_ALERT ALERT_L THERMDC
HT_NB_CPU_CAD_H4 J1 W2 HT_CPU_NB_CAD_H4 W8 H_THRMDA
HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CAD_L4 L0_CADIN_H4 L0_CADOUT_H4 HT_CPU_NB_CAD_L4 R81 44.2/F_4 CPU_HTREF0 THERMDA
K1 W3 R6
8 HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CAD_H5 L0_CADIN_L4 L0_CADOUT_L4 HT_CPU_NB_CAD_H5 +1.5VSUS R83 44.2/F_4 CPU_HTREF1 HT_REF0
L3 L0_CADIN_H5 L0_CADOUT_H5 V1 +1.1V_VLDT P6 HT_REF1
HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_L5 L2 U1 HT_CPU_NB_CAD_L5 place them to CPU within 1.5"
8 HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_H6 L0_CADIN_L5 L0_CADOUT_L5 HT_CPU_NB_CAD_H6 VDDIO_FB_H
L1 U2 36 CPU_VDD0_RUN_FB_H F6 W9 VDDIO_FB_H 37
HT_NB_CPU_CLK_L[1..0] HT_NB_CPU_CAD_L6 L0_CADIN_H6 L0_CADOUT_H6 HT_CPU_NB_CAD_L6 VDD0_FB_H VDDIO_FB_H VDDIO_FB_L
8 HT_NB_CPU_CLK_L[1..0] M1 L0_CADIN_L6 L0_CADOUT_L6 U3 36 CPU_VDD0_RUN_FB_L E6 VDD0_FB_L VDDIO_FB_L Y9 VDDIO_FB_L 37
HT_NB_CPU_CAD_H7 N3 T1 HT_CPU_NB_CAD_H7 R169
HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CAD_L7 L0_CADIN_H7 L0_CADOUT_H7 HT_CPU_NB_CAD_L7
N2 R1 36 CPU_VDD1_RUN_FB_H Y6 H6 CPU_VDDNB_RUN_FB_H 36
8 HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CAD_H8 L0_CADIN_L7 L0_CADOUT_L7 HT_CPU_NB_CAD_H8 510/F_4 VDD1_FB_H VDDNB_FB_H
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 36 CPU_VDD1_RUN_FB_L AB6 VDD1_FB_L VDDNB_FB_L G6 CPU_VDDNB_RUN_FB_L 36
HT_NB_CPU_CTL_L[1..0] HT_NB_CPU_CAD_L8 F5 AD3 HT_CPU_NB_CAD_L8
8 HT_NB_CPU_CTL_L[1..0] HT_NB_CPU_CAD_H9 L0_CADIN_L8 L0_CADOUT_L8 HT_CPU_NB_CAD_H9 CPU_DBRDY
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 G10 DBRDY
HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_L9 F4 AC5 HT_CPU_NB_CAD_L9 CPUTEST25H CPU_TMS AA9 E10 CPU_DBREQ#
8 HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_H10 L0_CADIN_L9 L0_CADOUT_L9 HT_CPU_NB_CAD_H10 CPU_TCK TMS DBREQ_L
G5 AB4 AC9
HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_L10 L0_CADIN_H10 L0_CADOUT_H10 HT_CPU_NB_CAD_L10 CPUTEST25L CPU_TRST# TCK CPU_TDO
H5 AB3 AD9 AE9
8 HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_H11 L0_CADIN_L10 L0_CADOUT_L10 HT_CPU_NB_CAD_H11 CPU_TDI TRST_L TDO
H3 AB5 AF9
HT_CPU_NB_CLK_H[1..0] HT_NB_CPU_CAD_L11 L0_CADIN_H11 L0_CADOUT_H11 HT_CPU_NB_CAD_L11 R168 TDI
H4 AA5
8 HT_CPU_NB_CLK_H[1..0] HT_NB_CPU_CAD_H12 L0_CADIN_L11 L0_CADOUT_L11 HT_CPU_NB_CAD_H12 CPUTEST23
K3 Y5 T4 AD7 J7
HT_CPU_NB_CLK_L[1..0] HT_NB_CPU_CAD_L12 L0_CADIN_H12 L0_CADOUT_H12 HT_CPU_NB_CAD_L12 510/F_4 TEST23 TEST28_H
K4 W5 H8
8 HT_CPU_NB_CLK_L[1..0] HT_NB_CPU_CAD_H13 L0_CADIN_L12 L0_CADOUT_L12 HT_CPU_NB_CAD_H13 CPUTEST18 TEST28_L
L5 V4 T24 H10
C HT_CPU_NB_CTL_H[1..0] HT_NB_CPU_CAD_L13 L0_CADIN_H13 L0_CADOUT_H13 HT_CPU_NB_CAD_L13 CPUTEST19 TEST18 CPUTEST17 C
8 HT_CPU_NB_CTL_H[1..0] M5 L0_CADIN_L13 L0_CADOUT_L13 V3 T27 G9 TEST19 TEST17 D7 T45
HT_NB_CPU_CAD_H14 M3 V5 HT_CPU_NB_CAD_H14 E7 CPUTEST16
HT_CPU_NB_CTL_L[1..0] L0_CADIN_H14 L0_CADOUT_H14 TEST16 T40
HT_NB_CPU_CAD_L14 M4 U5 HT_CPU_NB_CAD_L14 CPUTEST25H E9 F7 CPUTEST15
8 HT_CPU_NB_CTL_L[1..0] L0_CADIN_L14 L0_CADOUT_L14 TEST25_H TEST15 T26
HT_NB_CPU_CAD_H15 N5 T4 HT_CPU_NB_CAD_H15 CPUTEST25L E8 C7 CPUTEST14
L0_CADIN_H15 L0_CADOUT_H15 TEST25_L TEST14 T49
HT_NB_CPU_CAD_L15 P5 T3 HT_CPU_NB_CAD_L15 place them to CPU within 1.5"
L0_CADIN_L15 L0_CADOUT_L15 CPUTEST21 AB8 TEST21 TEST7 C3
HT_NB_CPU_CLK_H0 J3 Y1 HT_CPU_NB_CLK_H0 CPUTEST20 AF7 K8 R163 *300/F_4 +1.1V_VLDT
L0_CLKIN_H0 L0_CLKOUT_H0 T108 TEST20 TEST10
HT_NB_CPU_CLK_L0 J2 W1 HT_CPU_NB_CLK_L0 CPUTEST24 AE7
HT_NB_CPU_CLK_H1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CPU_NB_CLK_H1 CPUTEST22 TEST24
J5 Y4 +1.5VSUS T5 AE8 C4
HT_NB_CPU_CLK_L1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CPU_NB_CLK_L1 R375 300/F_4 CPU_DBREQ# CPUTEST12 TEST22 TEST8 CPUTEST29H
K5 Y3 T3 AC8 T46
L0_CLKIN_L1 L0_CLKOUT_L1 CPUTEST27 TEST12
AF8
HT_NB_CPU_CTL_H0 HT_CPU_NB_CTL_H0 R310 1K/F_4 CPUTEST27 TEST27 R116
N1 R2 C9
HT_NB_CPU_CTL_L0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CPU_NB_CTL_L0 R160 *0_4/S TEST29_H
P1 R3 C2 C8
HT_NB_CPU_CTL_H1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CPU_NB_CTL_H1 R309 *300/F_4 TEST9 TEST29_L 80.6/F_4
P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 AA6 TEST6
HT_NB_CPU_CTL_L1 P4 R5 HT_CPU_NB_CTL_L1 CPUTEST29L
L0_CTLIN_L1 L0_CTLOUT_L1 T50
A3 H18
RSVD1 RSVD10
FOX PZ63826-284R-41F A5
RSVD2 RSVD9
H19
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN B3 AA7 Route as 80ohm, diff
RSVD3 RSVD8
MLX 47296-4131 B5 D5
RSVD4 RSVD7
C1 RSVD5 RSVD6 C5
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2)
TYC 4-1903401-2
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN

+1.5VSUS
CN4
20
HDT Connector Serial VID VFIX MODE VID Override table (VDD)
B 19 +1.5VSUS B
18 SVC SVD Output Voltage
17
CPU_LDT_RST_HTPA# 16 +1.5V 0 0 1.1V
CPU_DBREQ# 15
CPU_DBRDY 14 R203 1K/F_4 +1.5VSUS
0 1 1.0V
CPU_TCK 13 R181 R182 R204 1K/F_4
CPU_TMS 12 +1.5V 1 0 0.9V
CPU_TDI 11 SI Change HDT connector fo FFC type *1K/F_4 *1K/F_4

CPU_TRST# 10 CPU_SVC_R R188 *0_4/S CPU_SVC 1 1 0.8V


9 CPU_SVC 36
CPU_TDO CPU_SVD_R R189 *0_4/S CPU_SVD
8 CPU_SVD 36
CPU_PWRGD R191 *0_4/S CPU_PWRGD_SVID_REG
7 CPU_PWRGD_SVID_REG 36
CPUTEST12 R47 1K/F_4
6 CPUTEST19 R104 1K/F_4
5 CPUTEST18 R106 1K/F_4
4 R198 *220_4 CPUTEST20 R311 1K/F_4
3 R197 *220_4 CPUTEST21 R53 1K/F_4
2 R199 *220_4 CPUTEST22 R52 1K/F_4
1 CPUTEST24 R49 1K/F_4
HDT CONN
88511-2001-20p-l

+3V R224 10K/F_4 R187 10K/F_4


Can remove on MP +1.5VSUS +1.5VSUS

+1.5VSUS R225 300_4 +1.5VSUS R373 1K/F_4

2
Q23
A C718 MMBT3904 A
0.1U/10V_4 CPU_THERMTRIP_L# 1 3
5 CPU_THERMTRIP_L# CPU_THERMTRIP# 13
U30 CPU_PROCHOT_L# R209 *0_4/S
5

TC7SH08FU Q26
2 CPU_LDT_RST#
CPU_LDT_RST_HTPA# 4
1
32 CPU_PROCHOT#
R219 *0_4/S 1 3
MMBT3904
CPU_PROCHOT_R#
CPU_PROCHOT_R# 12 PROJECT : R22
Quanta Computer Inc.
3

EC new option Size Document Number Rev


Custom 1A
S1G4 HT,CTL I/F 1/3
NB5/RD2
Date: Wednesday, September 15, 2010Sheet 3 of 43
5 4 3 2 1
A B C D E

+1.5VSUS

R306

*0_4/S
PLACE THEM CLOSE TO
CPU WITHIN 1"
+0.9V

D10
C10
B10
AD10
U19B

VDDR1 MEM:CMD/CTRL/CLKVDDR5
VDDR2
VDDR3
VDDR6
VDDR7
W 10
AC10
AB10
AA10
+0.9V
VDDR = 0.9V for 25W & 35W CPU
VDDR = 1.05V for 35W & 45W CPU 7 MEM_MB_DATA[0..63]

DDR_VTTREF 6,7,37
Processor Memory Interface
MEM_MB_DATA0 C11
U19C
MEM:DATA
G12 MEM_MA_DATA0
MEM_MA_DATA[0..63]
04
6
VDDR4 VDDR8 R77 MEM_MB_DATA1 MB_DATA0 MA_DATA0 MEM_MA_DATA1
VDDR9 A10 A11 MB_DATA1 MA_DATA1 F12
R312 39.2/F_4 M_ZP AF10 *0_4 MEM_MB_DATA2 A14 H14 MEM_MA_DATA2
R308 39.2/F_4 M_ZN MEMZP CPU_VTT_SENSE Reserved MEM_MB_DATA3 MB_DATA2 MA_DATA2 MEM_MA_DATA3
AE10 MEMZN VDDR_SENSE Y10 CPU_VTT_SENSE 37 B14 MB_DATA3 MA_DATA3 G14
MEM_MB_DATA4 G11 H11 MEM_MA_DATA4
MEM_MA_RESET# H16 MB_DATA4 MA_DATA4
6 MEM_MA_RESET# MA_RESET_L MEMVREF W 17 MEMVREF_CPU MEM_MB_DATA5 E11 MB_DATA5 MA_DATA5 H12 MEM_MA_DATA5
C547 MEM_MB_DATA6 D12 C13 MEM_MA_DATA6
4
10U/6.3V_8 MB_DATA6 MA_DATA6 4
6 MEM_MA0_ODT0 T19 MA0_ODT0 MB_RESET_L B18 MEM_MB_RESET# MEM_MB_RESET# 7
MEM_MB_DATA7 A13 MB_DATA7 MA_DATA7 E13 MEM_MA_DATA7
V22 MEM_MB_DATA8 A15 H15 MEM_MA_DATA8
6 MEM_MA0_ODT1 MA0_ODT1 MB_DATA8 MA_DATA8
U21 W 26 MEM_MB_DATA9 A16 E15 MEM_MA_DATA9
T14 MA1_ODT0 MB0_ODT0 MEM_MB0_ODT0 7 MB_DATA9 MA_DATA9
V19 W 23 C202 C195 MEM_MB_DATA10 A19 E17 MEM_MA_DATA10
T12 MA1_ODT1 MB0_ODT1 MEM_MB0_ODT1 7 MB_DATA10 MA_DATA10
Y26 0.01U/16V_4 1000P/50V_4 MEM_MB_DATA11 A20 H17 MEM_MA_DATA11
MB1_ODT0 T112 MB_DATA11 MA_DATA11
T20 MEM_MB_DATA12 C14 E14 MEM_MA_DATA12
6 MEM_MA0_CS#0 MA0_CS_L0 MB_DATA12 MA_DATA12
U19 V26 MEM_MB_DATA13 D14 F14 MEM_MA_DATA13
6 MEM_MA0_CS#1 MA0_CS_L1 MB0_CS_L0 MEM_MB0_CS#0 7 MB_DATA13 MA_DATA13
U20 W 25 MEM_MB_DATA14 C18 C17 MEM_MA_DATA14
T13 MA1_CS_L0 MB0_CS_L1 MEM_MB0_CS#1 7 MB_DATA14 MA_DATA14
V20 U22 MEM_MB_DATA15 D18 G17 MEM_MA_DATA15
T11 MA1_CS_L1 MB1_CS_L0 T15 MB_DATA15 MA_DATA15
MEM_MB_DATA16 D20 G18 MEM_MA_DATA16
MEM_MB_DATA17 MB_DATA16 MA_DATA16 MEM_MA_DATA17
6 MEM_MA_CKE0 J22 MA_CKE0 MB_CKE0 J25 MEM_MB_CKE0 7 A21 MB_DATA17 MA_DATA17 C19
J20 H26 MEM_MB_DATA18 D24 D22 MEM_MA_DATA18
6 MEM_MA_CKE1 MA_CKE1 MB_CKE1 MEM_MB_CKE1 7 MB_DATA18 MA_DATA18
MEM_MB_DATA19 C25 E20 MEM_MA_DATA19
MEM_MB_DATA20 MB_DATA19 MA_DATA19 MEM_MA_DATA20
6 MEM_MA_CLK5_P N19 MA_CLK_H5 MB_CLK_H5 P22 MEM_MB_CLK5_P 7 B20 MB_DATA20 MA_DATA20 E18
N20 R22 MEM_MB_DATA21 C20 F18 MEM_MA_DATA21
6 MEM_MA_CLK5_N MA_CLK_L5 MB_CLK_L5 MEM_MB_CLK5_N 7 MB_DATA21 MA_DATA21
E16 A17 MEM_MB_DATA22 B24 B22 MEM_MA_DATA22
T34 MA_CLK_H1 MB_CLK_H1 T119 MB_DATA22 MA_DATA22
F16 A18 MEM_MB_DATA23 C24 C23 MEM_MA_DATA23
T31 MA_CLK_L1 MB_CLK_L1 T120 MB_DATA23 MA_DATA23
Y16 AF18 MEM_MB_DATA24 E23 F20 MEM_MA_DATA24
T8 MA_CLK_H7 MB_CLK_H7 T110 MB_DATA24 MA_DATA24
AA16 AF17 MEM_MB_DATA25 E24 F22 MEM_MA_DATA25
T9 MA_CLK_L7 MB_CLK_L7 T109 MB_DATA25 MA_DATA25
P19 R26 MEM_MB_DATA26 G25 H24 MEM_MA_DATA26
6 MEM_MA_CLK4_P MA_CLK_H4 MB_CLK_H4 MEM_MB_CLK4_P 7 MB_DATA26 MA_DATA26
P20 R25 MEM_MB_DATA27 G26 J19 MEM_MA_DATA27
6 MEM_MA_CLK4_N MA_CLK_L4 MB_CLK_L4 MEM_MB_CLK4_N 7 MB_DATA27 MA_DATA27
MEM_MB_DATA28 C26 E21 MEM_MA_DATA28
6 MEM_MA_ADD[0..15] MEM_MB_ADD[0..15] 7 MB_DATA28 MA_DATA28
MEM_MA_ADD0 N21 P24 MEM_MB_ADD0 MEM_MB_DATA29 D26 E22 MEM_MA_DATA29
MEM_MA_ADD1 MA_ADD0 MB_ADD0 MEM_MB_ADD1 MEM_MB_DATA30 MB_DATA29 MA_DATA29 MEM_MA_DATA30
M20 MA_ADD1 MB_ADD1 N24 G23 MB_DATA30 MA_DATA30 H20
MEM_MA_ADD2 N22 P26 MEM_MB_ADD2 MEM_MB_DATA31 G24 H22 MEM_MA_DATA31
MEM_MA_ADD3 MA_ADD2 MB_ADD2 MEM_MB_ADD3 MEM_MB_DATA32 MB_DATA31 MA_DATA31 MEM_MA_DATA32
M19 MA_ADD3 MB_ADD3 N23 AA24 MB_DATA32 MA_DATA32 Y24
MEM_MA_ADD4 M22 N26 MEM_MB_ADD4 MEM_MB_DATA33 AA23 AB24 MEM_MA_DATA33
MEM_MA_ADD5 MA_ADD4 MB_ADD4 MEM_MB_ADD5 MEM_MB_DATA34 MB_DATA33 MA_DATA33 MEM_MA_DATA34
L20 MA_ADD5 MB_ADD5 L23 AD24 MB_DATA34 MA_DATA34 AB22
MEM_MA_ADD6 M24 N25 MEM_MB_ADD6 MEM_MB_DATA35 AE24 AA21 MEM_MA_DATA35
MEM_MA_ADD7 MA_ADD6 MB_ADD6 MEM_MB_ADD7 MEM_MB_DATA36 MB_DATA35 MA_DATA35 MEM_MA_DATA36
3 L21 MA_ADD7 MB_ADD7 L24 AA26 MB_DATA36 MA_DATA36 W 22 3
MEM_MA_ADD8 L19 M26 MEM_MB_ADD8 MEM_MB_DATA37 AA25 W 21 MEM_MA_DATA37
MEM_MA_ADD9 MA_ADD8 MB_ADD8 MEM_MB_ADD9 MEM_MB_DATA38 MB_DATA37 MA_DATA37 MEM_MA_DATA38
K22 MA_ADD9 MB_ADD9 K26 AD26 MB_DATA38 MA_DATA38 Y22
MEM_MA_ADD10 R21 T26 MEM_MB_ADD10 MEM_MB_DATA39 AE25 AA22 MEM_MA_DATA39
MEM_MA_ADD11 MA_ADD10 MB_ADD10 MEM_MB_ADD11 MEM_MB_DATA40 MB_DATA39 MA_DATA39 MEM_MA_DATA40
L22 MA_ADD11 MB_ADD11 L26 AC22 MB_DATA40 MA_DATA40 Y20
MEM_MA_ADD12 K20 L25 MEM_MB_ADD12 MEM_MB_DATA41 AD22 AA20 MEM_MA_DATA41
MEM_MA_ADD13 MA_ADD12 MB_ADD12 MEM_MB_ADD13 MEM_MB_DATA42 MB_DATA41 MA_DATA41 MEM_MA_DATA42
V24 MA_ADD13 MB_ADD13 W 24 AE20 MB_DATA42 MA_DATA42 AA18
MEM_MA_ADD14 K24 J23 MEM_MB_ADD14 MEM_MB_DATA43 AF20 AB18 MEM_MA_DATA43
MEM_MA_ADD15 MA_ADD14 MB_ADD14 MEM_MB_ADD15 MEM_MB_DATA44 MB_DATA43 MA_DATA43 MEM_MA_DATA44
K19 MA_ADD15 MB_ADD15 J24 AF24 MB_DATA44 MA_DATA44 AB21
MEM_MB_DATA45 AF23 AD21 MEM_MA_DATA45
MEM_MB_DATA46 MB_DATA45 MA_DATA45 MEM_MA_DATA46
6 MEM_MA_BANK0 R20 MA_BANK0 MB_BANK0 R24 MEM_MB_BANK0 7 AC20 MB_DATA46 MA_DATA46 AD19
R23 U26 MEM_MB_DATA47 AD20 Y18 MEM_MA_DATA47
6 MEM_MA_BANK1 MA_BANK1 MB_BANK1 MEM_MB_BANK1 7 MB_DATA47 MA_DATA47
J21 J26 MEM_MB_DATA48 AD18 AD17 MEM_MA_DATA48
6 MEM_MA_BANK2 MA_BANK2 MB_BANK2 MEM_MB_BANK2 7 MB_DATA48 MA_DATA48
MEM_MB_DATA49 AE18 W 16 MEM_MA_DATA49
MEM_MB_DATA50 MB_DATA49 MA_DATA49 MEM_MA_DATA50
6 MEM_MA_RAS# R19 MA_RAS_L MB_RAS_L U25 MEM_MB_RAS# 7 AC14 MB_DATA50 MA_DATA50 W 14
T22 U24 MEM_MB_DATA51 AD14 Y14 MEM_MA_DATA51
6 MEM_MA_CAS# MA_CAS_L MB_CAS_L MEM_MB_CAS# 7 MB_DATA51 MA_DATA51
T24 U23 MEM_MB_DATA52 AF19 Y17 MEM_MA_DATA52
6 MEM_MA_WE# MA_W E_L MB_W E_L MEM_MB_WE# 7 MB_DATA52 MA_DATA52
MEM_MB_DATA53 AC18 AB17 MEM_MA_DATA53
MEM_MB_DATA54 MB_DATA53 MA_DATA53 MEM_MA_DATA54
AF16 MB_DATA54 MA_DATA54 AB15
SOCKET_638_PIN MEM_MB_DATA55 AF15 AD15 MEM_MA_DATA55
MEM_MB_DATA56 MB_DATA55 MA_DATA55 MEM_MA_DATA56
AF13 MB_DATA56 MA_DATA56 AB13
MEM_MB_DATA57 AC12 AD13 MEM_MA_DATA57
MEM_MB_DATA58 MB_DATA57 MA_DATA57 MEM_MA_DATA58
AB11 MB_DATA58 MA_DATA58 Y12
MEM_MB_DATA59 Y11 W 11 MEM_MA_DATA59
+0.9V Place close to socket MEM_MB_DATA60 AE14
MB_DATA59 MA_DATA59
AB14 MEM_MA_DATA60
MEM_MB_DATA61 MB_DATA60 MA_DATA60 MEM_MA_DATA61
AF14 MB_DATA61 MA_DATA61 AA14
MEM_MB_DATA62 AF11 AB12 MEM_MA_DATA62
MEM_MB_DATA63 MB_DATA62 MA_DATA62 MEM_MA_DATA63
AD11 MB_DATA63 MA_DATA63 AA12
C102 C101 C416 C415 C98 C96 C405 C402
7 MEM_MB_DM[0..7] MEM_MA_DM[0..7] 6
4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 MEM_MB_DM0 A12 E12 MEM_MA_DM0
2
MEM_MB_DM1 MB_DM0 MA_DM0 MEM_MA_DM1 2
B16 MB_DM1 MA_DM1 C15
MEM_MB_DM2 A22 E19 MEM_MA_DM2
MEM_MB_DM3 MB_DM2 MA_DM2 MEM_MA_DM3
E25 MB_DM3 MA_DM3 F24
MEM_MB_DM4 AB26 AC24 MEM_MA_DM4
MEM_MB_DM5 MB_DM4 MA_DM4 MEM_MA_DM5
AE22 MB_DM5 MA_DM5 Y19
+0.9V MEM_MB_DM6 AC16 AB16 MEM_MA_DM6
MEM_MB_DM7 MB_DM6 MA_DM6 MEM_MA_DM7
AD12 MB_DM7 MA_DM7 Y13

7 MEM_MB_DQS0_P C12 MB_DQS_H0 MA_DQS_H0 G13 MEM_MA_DQS0_P 6


C107 C104 C393 C390 C115 C114 C387 C100 B12 H13
7 MEM_MB_DQS0_N MB_DQS_L0 MA_DQS_L0 MEM_MA_DQS0_N 6
1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 D16 G16
7 MEM_MB_DQS1_P MB_DQS_H1 MA_DQS_H1 MEM_MA_DQS1_P 6
7 MEM_MB_DQS1_N C16 MB_DQS_L1 MA_DQS_L1 G15 MEM_MA_DQS1_N 6
7 MEM_MB_DQS2_P A24 MB_DQS_H2 MA_DQS_H2 C22 MEM_MA_DQS2_P 6
7 MEM_MB_DQS2_N A23 MB_DQS_L2 MA_DQS_L2 C21 MEM_MA_DQS2_N 6
7 MEM_MB_DQS3_P F26 MB_DQS_H3 MA_DQS_H3 G22 MEM_MA_DQS3_P 6
+1.5VSUS E26 G21
7 MEM_MB_DQS3_N MB_DQS_L3 MA_DQS_L3 MEM_MA_DQS3_N 6
7 MEM_MB_DQS4_P AC25 MB_DQS_H4 MA_DQS_H4 AD23 MEM_MA_DQS4_P 6
7 MEM_MB_DQS4_N AC26 MB_DQS_L4 MA_DQS_L4 AC23 MEM_MA_DQS4_N 6
7 MEM_MB_DQS5_P AF21 MB_DQS_H5 MA_DQS_H5 AB19 MEM_MA_DQS5_P 6
R184 0_4 AF22 AB20
7 MEM_MB_DQS5_N MB_DQS_L5 MA_DQS_L5 MEM_MA_DQS5_N 6
7 MEM_MB_DQS6_P AE16 MB_DQS_H6 MA_DQS_H6 Y15 MEM_MA_DQS6_P 6
+3VS5
Reserved for AMD suggest 7 MEM_MB_DQS6_N AD16
AF12
MB_DQS_L6 MA_DQS_L6 W 15
W 12
MEM_MA_DQS6_N 6
C417 7 MEM_MB_DQS7_P MB_DQS_H7 MA_DQS_H7 MEM_MA_DQS7_P 6
R196 AE12 W 13
7 MEM_MB_DQS7_N MB_DQS_L7 MA_DQS_L7 MEM_MA_DQS7_N 6
1K/F_4
SOCKET_638_PIN
*.1U/10V_4
5

U12
3 + R185 *10_4
1 1 1 2 MEMVREF_CPU 1
4 -
R193 C423 *OPA343NA/3K
2

1K/F_4 *0.47u/6.3V_4 R183

R186 *0_4
*10K/F_4
PROJECT : R22
R180 *0_4
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
S1G4 DDRII MEMORY I/F 2/3
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 4 of 43
A B C D E
5 4 3 2 1

+VCORE U19E +VCORE


AA4
AA11
AA13
AA15
U19F

VSS1
VSS2
VSS3
VSS66
VSS67
VSS68
J6
J8
J10
J12
+VCORE
BOTTOM SIDE DECOUPLING
05
VSS4 VSS69
G4 VDD0_1 VDD1_1 P8 AA17 VSS5 VSS70 J14
H2 VDD0_2 VDD1_2 P10 AA19 VSS6 VSS71 J16
J9 VDD0_3 VDD1_3 R4 AB2 VSS7 VSS72 J18
J11 R7 AB7 K2 C201 C235 C249 C266 C275 C274 C273
VDD0_4 VDD1_4 VSS8 VSS73 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 0.22U/6.3V_4 0.01U/16V_4 180P/50V_4
J13 VDD0_5 VDD1_5 R9 AB9 VSS9 VSS74 K7
D
J15 VDD0_6 VDD1_6 R11 AB23 VSS10 VSS75 K9 D
K6 VDD0_7 VDD1_7 T2 AB25 VSS11 VSS76 K11
K10 VDD0_8 VDD1_8 T6 AC11 VSS12 VSS77 K13
K12 VDD0_9 VDD1_9 T8 AC13 VSS13 VSS78 K15
K14 T10 AC15 K17 +VCORE
VDD0_10 VDD1_10 VSS14 VSS79
L4 VDD0_11 VDD1_11 T12 AC17 VSS15 VSS80 L6
L7 VDD0_12 VDD1_12 T14 AC19 VSS16 VSS81 L8
L9 VDD0_13 VDD1_13 U7 AC21 VSS17 VSS82 L10
L11 VDD0_14 VDD1_14 U9 AD6 VSS18 VSS83 L12
L13 U11 AD8 L14 C261 C270 C247 C234 C198 C199 C197
VDD0_15 VDD1_15 VSS19 VSS84 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 0.22U/6.3V_4 0.01U/16V_4 180P/50V_4
L15 VDD0_16 VDD1_16 U13 AD25 VSS20 VSS85 L16
M2 VDD0_17 VDD1_17 U15 AE11 VSS21 VSS86 L18
M6 VDD0_18 VDD1_18 V6 AE13 VSS22 VSS87 M7
M8 VDD0_19 VDD1_19 V8 AE15 VSS23 VSS88 M9
M10 VDD0_20 VDD1_20 V10 AE17 VSS24 VSS89 AC6
N7 V12 AE19 M17 +CPUVDDNB +1.5VSUS
+CPUVDDNB VDD0_21 VDD1_21 VSS25 VSS90
N9 VDD0_22 VDD1_22 V14 AE21 VSS26 VSS91 N4
N11 VDD0_23 VDD1_23 W4 AE23 VSS27 VSS92 N8
4A VDD1_24 Y2 B4 VSS28 VSS93 N10
K16 VDDNB_1 VDD1_25 AC4 B6 VSS29 VSS94 N16
M16 AD2 +1.5VSUS B8 N18 C243 C229 C256 C231 C246 C257 C276 C277
VDDNB_2 VDD1_26 VSS30 VSS95 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 0.22U/6.3V_4 0.22U/6.3V_4 180P/50V_4
P16 VDDNB_3 B9 VSS31 VSS96 P2
+1.5VSUS T16 Y25 B11 P7
VDDNB_4 VDDIO27 VSS32 VSS97
V16 VDDNB_5 VDDIO26 V25 B13 VSS33 VSS98 P9
2A VDDIO25 V23 B15 VSS34 VSS99 P11
H25 VDDIO1 VDDIO24 V21 B17 VSS35 VSS100 P17
J17 VDDIO2 VDDIO23 V18 B19 VSS36 VSS101 R8
K18 VDDIO3 VDDIO22 U17 B21 VSS37 VSS102 R10
K21 VDDIO4 VDDIO21 T25 B23 VSS38 VSS103 R16
K23 VDDIO5 VDDIO20 T23 B25 VSS39 VSS104 R18
C K25 VDDIO6 VDDIO19 T21 D6 VSS40 VSS105 T7 C
L17 T18 D8 T9
M18
VDDIO7
VDDIO8
VDDIO18
VDDIO17 R17 D9
VSS41
VSS42
VSS106
VSS107 T11 DECOUPLING BETWEEN PROCESSOR AND DIMMs
M21 VDDIO9 VDDIO16 P25 D11 VSS43 VSS108 T13
M23 P23 D13 T15
M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21 D15
VSS44
VSS45
VSS109
VSS110 T17 PLACE CLOSE TO PROCESSOR AS POSSIBLE
N17 VDDIO12 VDDIO13 P18 D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
D21 U8 +1.5VSUS
SOCKET_638_PIN VSS48 VSS113
D23 VSS49 VSS114 U10
D25 VSS50 VSS115 U12
E4 VSS51 VSS116 U14
+1.5VSUS +1.5VSUS F2 U16
VSS52 VSS117 C128 C137 C309 C307 C130 C134
F11 VSS53 VSS118 U18
F13 V2 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 0.22U/6.3V_4
VSS54 VSS119
F15 VSS55 VSS120 V7
R226 R206 F17 V9
R216 R201 R176 VSS56 VSS121 +1.5VSUS
2K/F_4 2K/F_4 F19 VSS57 VSS122 V11
1K/F_4 1K/F_4 1K/F_4 F21 V13
VSS58 VSS123
F23 VSS59 VSS124 V15
F25 VSS60 VSS125 V17
2

Q27 H7 W6
MMBT3904 VSS61 VSS126 C144 C141 C208 C193 C305 C303 C209
H9 VSS62 VSS127 Y21
32,40 MBCLK MBCLK 3 1 CPU_SIC H21 Y23 0.22U/6.3V_4 0.22U/6.3V_4 0.01U/16V_4 0.1U/10V_4 180P/50V_4 180P/50V_4 0.1U/10V_4
CPU_SIC 3 VSS63 VSS128
H23 VSS64 VSS129 N6
1 2 J4 VSS65
2

RB501V-40 D20 Q25


MMBT3904 SOCKET_638_PIN
32,40 MBDATA MBDATA 3 1 CPU_SID
CPU_SID 3
B B
1 2
RB501V-40 D19

CPU_ALERT
CPU_ALERT 3 PROCESSOR POWER AND GROUND
+3V +3V

EC10 *0.01U/16V_4 +VGA_CORE +3V


+1.5V_VGA +3V
R356
EC5 EC12
200/F_6 +1.8V_VGA EC14 *0.01U/16V_4 +3V
R367 R368 R360
+VGA_CORE EC8 *0.01U/16V_4 *0.1U/10V_4 *0.1U/10V_4
+3V
10K/F_4 10K/F_4 10K/F_4 C619
0.1U/10V_4
U22
+1.5V_VGA EC11 *0.01U/16V_4 +3V
32 MBCLK2 8 SCLK VCC 1 H_THRMDA 3
R190 *0_4/S 3920_RST#
3920_RST# 32
32 MBDATA2 7 2 C621 Q24 +5V EC6 *0.01U/16V_4 +1.5VSUS EC9 *0.01U/16V_4 +1.1V
SDA DXP +3V
1000P/50V_4
3

MMBT3904 D18
6 ALERT# DXN 3
2 2 1 ECPWROK +VGA_CORE EC13 *0.01U/16V_4 +1.8V_VGA
H_THRMDC 3 ECPWROK 16,20,32
13 PM_THERM# 4 OVERT# GND 5
For fix HyperTransport nets
1

A MSOP CH501H-40PT A
across plane splits
G786P8 SMBALERT# R194 10K/F_4
+3V
3

+1.5V R374 10K/F_4


R200 10K/F_4
PROJECT : R22
PQ30 2 TEMP_FAIL 18 Quanta Computer Inc.
2

Q36
MMBT3904 *2N7002E-G ADD VGA TEMP_ FAIL function
CPU_THERMTRIP_L# 1 3 SMBALERT# M92 is active Hi Size Document Number Rev
3 CPU_THERMTRIP_L# Custom
S1G4 PWR & GND 3/3 1A
1

NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 5 of 43
5 4 3 2 1
5 4 3 2 1

+1.5VSUS
06
CN20A MEM_MA_DATA[0..63] 4 CN20B
4 MEM_MA_ADD[0..15]
MEM_MA_ADD0 98 5 MEM_MA_DATA0 75 44
MEM_MA_ADD1 A0 DQ0 MEM_MA_DATA1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
MEM_MA_ADD2 96 15 MEM_MA_DATA2 81 49
MEM_MA_ADD3 A2 DQ2 MEM_MA_DATA3 VDD3 VSS18
95 A3 DQ3 17 82 VDD4 VSS19 54
D MEM_MA_ADD4 92 4 MEM_MA_DATA4 87 55 D
MEM_MA_ADD5 A4 DQ4 MEM_MA_DATA5 VDD5 VSS20
91 A5 DQ5 6 88 VDD6 VSS21 60
MEM_MA_ADD6 90 16 MEM_MA_DATA6 93 61
MEM_MA_ADD7 A6 DQ6 MEM_MA_DATA7 VDD7 VSS22
86 A7 DQ7 18 94 VDD8 VSS23 65
MEM_MA_ADD8 89 21 MEM_MA_DATA8 99 66
MEM_MA_ADD9 A8 DQ8 MEM_MA_DATA9 VDD9 VSS24
85 A9 DQ9 23 100 VDD10 VSS25 71
MEM_MA_ADD10 107 33 MEM_MA_DATA10 105 72
MEM_MA_ADD11 A10/AP DQ10 MEM_MA_DATA11 VDD11 VSS26
84 35 106 127

PC2100 DDR3 SDRAM SO-DIMM


MEM_MA_ADD12 A11 DQ11 MEM_MA_DATA12 VDD12 VSS27
83 A12/BC# DQ12 22 111 VDD13 VSS28 128
MEM_MA_ADD13 119 24 MEM_MA_DATA13 112 133
MEM_MA_ADD14 A13 DQ13 MEM_MA_DATA14 VDD14 VSS29
80 A14 DQ14 34 117 VDD15 VSS30 134
MEM_MA_ADD15 78 36 MEM_MA_DATA15 118 138
A15 DQ15 MEM_MA_DATA16 VDD16 VSS31
4 MEM_MA_BANK[0..2] 39 123 139
DQ16 VDD17 VSS32

PC2100 DDR3 SDRAM SO-DIMM


MEM_MA_BANK0 109 41 MEM_MA_DATA17 124 144
MEM_MA_BANK1 108 BA0 DQ17 MEM_MA_DATA18 VDD18 VSS33
51 145
MEM_MA_BANK2 79 BA1 DQ18 MEM_MA_DATA19 VSS34
53 +3V 199 150
BA2 DQ19 MEM_MA_DATA20 VDDSPD VSS35
4 MEM_MA0_CS#0 114 S0# DQ20 40 VSS36 151
121 42 MEM_MA_DATA21 77 155
4 MEM_MA0_CS#1 S1# DQ21 NC1 VSS37
101 50 MEM_MA_DATA22 122 156
4 MEM_MA_CLK5_P CK0 DQ22 NC2 VSS38
103 52 MEM_MA_DATA23 MEM_MA_TEST 125 161
4 MEM_MA_CLK5_N CK0# DQ23 T7 NCTEST VSS39
102 57 MEM_MA_DATA24 162
4 MEM_MA_CLK4_P CK1 DQ24 VSS40
104 59 MEM_MA_DATA25 198 167
4 MEM_MA_CLK4_N CK1# DQ25 14 MEM_MA_EVENT# EVENT# VSS41
73 67 MEM_MA_DATA26 MEM_MA_RESET# 30 168
4 MEM_MA_CKE0 CKE0 DQ26 4 MEM_MA_RESET# RESET# VSS42
74 69 MEM_MA_DATA27 172
4 MEM_MA_CKE1 CKE1 DQ27 VSS43
115 56 MEM_MA_DATA28 173
4 MEM_MA_CAS# CAS# DQ28 VSS44
110 58 MEM_MA_DATA29 +VREF_DQ 1 178
4 MEM_MA_RAS# RAS# DQ29 7 +VREF_DQ VREF_DQ VSS45
113 68 MEM_MA_DATA30 +VREF_CA_A 126 179
4 MEM_MA_WE# WE# DQ30 VREF_CA VSS46
197 70 MEM_MA_DATA31 184
SA0 DQ31 MEM_MA_DATA32 VSS47
201 129 185
PCLK_SMB SA1 DQ32 MEM_MA_DATA33 VSS48
7,13 PCLK_SMB 202 131 2 189
C PDAT_SMB SCL DQ33 MEM_MA_DATA34 C407 C549 VSS1 VSS49 C
7,13 PDAT_SMB 200 SDA DQ34 141 3 VSS2 VSS50 190
143 MEM_MA_DATA35 1000P/50V_4 1000P/50V_4 8 195
DQ35 MEM_MA_DATA36 VSS3 VSS51
116 130 9 196

(204P)
4 MEM_MA0_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 MEM_MA_DATA37 13
4 MEM_MA0_ODT1 ODT1 DQ37 VSS5
140 MEM_MA_DATA38 14
MEM_MA_DM0 DQ38 MEM_MA_DATA39 VSS6
4 MEM_MA_DM[0..7] 11 DM0 DQ39 142 19 VSS7
MEM_MA_DM1 28 147 MEM_MA_DATA40 20
MEM_MA_DM2 DM1 DQ40 MEM_MA_DATA41 VSS8
46 149 25
MEM_MA_DM3 DM2 DQ41 MEM_MA_DATA42 VSS9
63 157 26 203
(204P)

DM3 DQ42 VSS10 VTT1 +0.75V_DDR_VTT


MEM_MA_DM4 136 159 MEM_MA_DATA43 31 204
MEM_MA_DM5 DM4 DQ43 MEM_MA_DATA44 VSS11 VTT2
153 146 32
MEM_MA_DM6 DM5 DQ44 MEM_MA_DATA45 VSS12
170 148 37
MEM_MA_DM7 DM6 DQ45 MEM_MA_DATA46 VSS13
187 158 38
DM7 DQ46 MEM_MA_DATA47 VSS14 R162 0_8
DQ47 160 43 VSS15 VSS53 205
12 163 MEM_MA_DATA48 206 R301 0_8
4 MEM_MA_DQS0_P DQS0 DQ48 VSS54
29 165 MEM_MA_DATA49
4 MEM_MA_DQS1_P DQS1 DQ49
47 175 MEM_MA_DATA50 DDR3-DIMM1
4 MEM_MA_DQS2_P DQS2 DQ50
64 177 MEM_MA_DATA51
4 MEM_MA_DQS3_P DQS3 DQ51
137 164 MEM_MA_DATA52
4 MEM_MA_DQS4_P DQS4 DQ52
154 166 MEM_MA_DATA53
4
4
MEM_MA_DQS5_P
MEM_MA_DQS6_P 171
DQS5
DQS6
DQ53
DQ54 174 MEM_MA_DATA54 +1.5VSUS Place close to DIMMs
188 176 MEM_MA_DATA55
4 MEM_MA_DQS7_P DQS7 DQ55
10 181 MEM_MA_DATA56
4 MEM_MA_DQS0_N DQS#0 DQ56
27 183 MEM_MA_DATA57
4 MEM_MA_DQS1_N DQS#1 DQ57
45 191 MEM_MA_DATA58 R165 0_4
4 MEM_MA_DQS2_N DQS#2 DQ58
62 193 MEM_MA_DATA59
4 MEM_MA_DQS3_N DQS#3 DQ59 +3VS5
135 180 MEM_MA_DATA60
4 MEM_MA_DQS4_N DQS#4 DQ60
152 182 MEM_MA_DATA61
4 MEM_MA_DQS5_N DQS#5 DQ61 C418
169 192 MEM_MA_DATA62 R179 C409
4 MEM_MA_DQS6_N DQS#6 DQ62
186 194 MEM_MA_DATA63
B 4 MEM_MA_DQS7_N DQS#7 DQ63 B
1K/F_4 *.1U/10V_4
*.1U/10V_4

5
DDR3-DIMM1 U10
H=5.2 footprint: "ddr-c-2013289-204p" 3 + R166 *10_4
1 1 2 +VREF_DQ
4 -
SO-DIMM BYPASS PLACEMENT : R164 C406 *OPA343NA/3K

2
Place these Caps near So-Dimm1. 1K/F_4 *1n/50V_4 R167 C408

No Vias Between the Trace of PIN to CAP. *10K/F_4 0.01U/16V_4


R192 *0_4

R195 *0_4

+1.5VSUS DE-COUPLING FOR DIMM1(ONE CAP PER POWER PIN)

C588 C578 C550 C140 C272 C218 C552 C583 C557 C306 C245 C152
.1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 *.1U/10V_4 *.1U/10V_4 *.1U/10V_4 .1U/10V_4 *.1U/10V_4 .1U/10V_4
+1.5VSUS

+VREF_CA_A R317
DE-COUPLING FOR DIMM1 *2K/F_4
A A

+3V +0.75V_DDR_VTT +0.75V_DDR_VTT R314 *0_4/S VREF_CA_A


4,7,37 DDR_VTTREF
+1.5VSUS

R318
1

C39 C40 C28 C31


C27 *.1U/10V_4
+1.5VSUS + C116
*2K/F_4 PROJECT : R22
1U/6.3V_4 *.1U/10V_4 4.7U/6.3V_6 *22U/6.3V_8
C30 .1U/10V_4
C211
10U/6.3V_8
C146 C164
10U/6.3V_8 10U/6.3V_8 *150u_6.3V_3528
Quanta Computer Inc.
2

Size Document Number Rev


Custom 1A
DDR3 SODIMMS: A/B CHANNEL
NB5/RD2
Date: Wednesday, September 15, 2010Sheet 6 of 43
5 4 3 2 1
5 4 3 2 1

+1.5VSUS
07
CN19A MEM_MB_DATA[0..63] 4
4 MEM_MB_ADD[0..15]
MEM_MB_ADD0 98 5 MEM_MB_DATA0
MEM_MB_ADD1 A0 DQ0 MEM_MB_DATA1
97 A1 DQ1 7 CN19B
MEM_MB_ADD2 96 15 MEM_MB_DATA2
MEM_MB_ADD3 A2 DQ2 MEM_MB_DATA3
95 A3 DQ3 17 75 VDD1 VSS16 44
MEM_MB_ADD4 92 4 MEM_MB_DATA4 76 48
D
MEM_MB_ADD5 A4 DQ4 MEM_MB_DATA5 VDD2 VSS17 D
91 A5 DQ5 6 81 VDD3 VSS18 49
MEM_MB_ADD6 90 16 MEM_MB_DATA6 82 54
MEM_MB_ADD7 A6 DQ6 MEM_MB_DATA7 VDD4 VSS19
86 A7 DQ7 18 87 VDD5 VSS20 55
MEM_MB_ADD8 89 21 MEM_MB_DATA8 88 60
MEM_MB_ADD9 A8 DQ8 MEM_MB_DATA9 VDD6 VSS21
85 A9 DQ9 23 93 VDD7 VSS22 61
MEM_MB_ADD10 107 33 MEM_MB_DATA10 94 65
MEM_MB_ADD11 A10/AP DQ10 MEM_MB_DATA11 VDD8 VSS23
84 A11 DQ11 35 99 VDD9 VSS24 66
MEM_MB_ADD12 83 22 MEM_MB_DATA12 100 71
MEM_MB_ADD13 A12/BC# DQ12 MEM_MB_DATA13 VDD10 VSS25
119 A13 DQ13 24 105 VDD11 VSS26 72
MEM_MB_ADD14 80 34 MEM_MB_DATA14 106 127

PC2100 DDR3 SDRAM SO-DIMM


MEM_MB_ADD15 A14 DQ14 MEM_MB_DATA15 VDD12 VSS27
78 A15 DQ15 36 111 VDD13 VSS28 128
39 MEM_MB_DATA16 112 133
4 MEM_MB_BANK[0..2] DQ16 VDD14 VSS29

PC2100 DDR3 SDRAM SO-DIMM


MEM_MB_BANK0 109 41 MEM_MB_DATA17 117 134
MEM_MB_BANK1 BA0 DQ17 MEM_MB_DATA18 VDD15 VSS30
108 BA1 DQ18 51 118 VDD16 VSS31 138
MEM_MB_BANK2 79 53 MEM_MB_DATA19 123 139
BA2 DQ19 MEM_MB_DATA20 VDD17 VSS32
4 MEM_MB0_CS#0 114 40 124 144
+3V S0# DQ20 MEM_MB_DATA21 VDD18 VSS33
4 MEM_MB0_CS#1 121 S1# DQ21 42 VSS34 145
101 50 MEM_MB_DATA22 199 150
4 MEM_MB_CLK5_P CK0 DQ22 +3V VDDSPD VSS35
103 52 MEM_MB_DATA23 151
4 MEM_MB_CLK5_N CK0# DQ23 VSS36
102 57 MEM_MB_DATA24 77 155
4 MEM_MB_CLK4_P CK1 DQ24 NC1 VSS37
R300 104 59 MEM_MB_DATA25 122 156
4 MEM_MB_CLK4_N CK1# DQ25 NC2 VSS38
4.7K_4 4 MEM_MB_CKE0 73 67 MEM_MB_DATA26 MEM_MB_TEST 125 161
CKE0 DQ26 T6 NCTEST VSS39
4 MEM_MB_CKE1 74 69 MEM_MB_DATA27 162
CKE1 DQ27 MEM_MB_DATA28 VSS40
4 MEM_MB_CAS# 115 56 14 MEM_MB_EVENT# 198 167
CAS# DQ28 MEM_MB_DATA29 MEM_MB_RESET# EVENT# VSS41
4 MEM_MB_RAS# 110 58 4 MEM_MB_RESET# 30 168
RAS# DQ29 MEM_MB_DATA30 RESET# VSS42
4 MEM_MB_WE# 113 68 172
DIM2_SA0 DIM2_SA0 WE# DQ30 MEM_MB_DATA31 VSS43
197 70 173
SA0 DQ31 MEM_MB_DATA32 +VREF_DQ VSS44
201 129 6 +VREF_DQ 1 178
PCLK_SMB SA1 DQ32 MEM_MB_DATA33 VREF_DQ VSS45
6,13 PCLK_SMB 202 131 +VREF_CA_B 126 179
PDAT_SMB SCL DQ33 MEM_MB_DATA34 VREF_CA VSS46
C
6,13 PDAT_SMB 200 141 184 C
SDA DQ34 MEM_MB_DATA35 VSS47
DQ35 143 VSS48 185
116 130 MEM_MB_DATA36 2 189
4 MEM_MB0_ODT0 ODT0 DQ36 VSS1 VSS49
120 132 MEM_MB_DATA37 C388 C125 3 190
4 MEM_MB0_ODT1 ODT1 DQ37 VSS2 VSS50
140 MEM_MB_DATA38 1000P/50V_4 1000P/50V_4 8 195
4 MEM_MB_DM[0..7] DQ38 VSS3 VSS51
MEM_MB_DM0 11 142 MEM_MB_DATA39 9 196

(204P)
MEM_MB_DM1 DM0 DQ39 MEM_MB_DATA40 VSS4 VSS52
28 DM1 DQ40 147 13 VSS5
MEM_MB_DM2 46 149 MEM_MB_DATA41 14
MEM_MB_DM3 DM2 DQ41 MEM_MB_DATA42 VSS6
63 157 19
(204P)

MEM_MB_DM4 DM3 DQ42 MEM_MB_DATA43 VSS7


136 159 20
MEM_MB_DM5 DM4 DQ43 MEM_MB_DATA44 VSS8
153 146 25
MEM_MB_DM6 DM5 DQ44 MEM_MB_DATA45 VSS9
170 148 26 203 +0.75V_DDR_VTT
MEM_MB_DM7 DM6 DQ45 MEM_MB_DATA46 VSS10 VTT1
187 158 31 204
DM7 DQ46 MEM_MB_DATA47 VSS11 VTT2
160 32
DQ47 MEM_MB_DATA48 VSS12
4 MEM_MB_DQS0_P 12 DQS0 DQ48 163 37 VSS13
29 165 MEM_MB_DATA49 38
4 MEM_MB_DQS1_P DQS1 DQ49 VSS14
47 175 MEM_MB_DATA50 43 205 R159 0_8
4 MEM_MB_DQS2_P DQS2 DQ50 VSS15 VSS53
64 177 MEM_MB_DATA51 206 R298 0_8
4 MEM_MB_DQS3_P DQS3 DQ51 VSS54
137 164 MEM_MB_DATA52
4 MEM_MB_DQS4_P DQS4 DQ52
154 166 MEM_MB_DATA53 DDR3-DIMM2
4 MEM_MB_DQS5_P DQS5 DQ53
171 174 MEM_MB_DATA54
4 MEM_MB_DQS6_P DQS6 DQ54
188 176 MEM_MB_DATA55
4 MEM_MB_DQS7_P DQS7 DQ55
10 181 MEM_MB_DATA56
4 MEM_MB_DQS0_N DQS#0 DQ56
27 183 MEM_MB_DATA57
4 MEM_MB_DQS1_N DQS#1 DQ57
45 191 MEM_MB_DATA58
4 MEM_MB_DQS2_N DQS#2 DQ58
62 193 MEM_MB_DATA59
4 MEM_MB_DQS3_N DQS#3 DQ59
135 180 MEM_MB_DATA60
4 MEM_MB_DQS4_N DQS#4 DQ60
152 182 MEM_MB_DATA61
4 MEM_MB_DQS5_N DQS#5 DQ61
169 192 MEM_MB_DATA62
4 MEM_MB_DQS6_N DQS#6 DQ62
186 194 MEM_MB_DATA63
B 4 MEM_MB_DQS7_N DQS#7 DQ63 B

DDR3-DIMM2
H=9.2 footprint: "ddr-c-2013310-204p-1"
SO-DIMM BYPASS PLACEMENT :
Place these Caps near So-Dimm1.
No Vias Between the Trace of PIN to CAP.

+1.5VSUS DE-COUPLING FOR DIMM2(ONE CAP PER POWER PIN)

C214 C171 C138 C215 C172 C139 C248 C190 C151 C244 C191 C149 C753 C754
.1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 *.1U/10V_4 *.1U/10V_4 *.1U/10V_4 *.1U/10V_4 *.1U/10V_4 *.1U/10V_4 *68p/50V_4 *68p/50V_4
+1.5VSUS

DB to SI:UEMI suggestion on BOT side(6847,5047)(6847,4200)


+VREF_CA_B R61
DE-COUPLING FOR DIMM2 *2K/F_4
A A

+3V +0.75V_DDR_VTT +0.75V_DDR_VTT +1.5VSUS


R55 *0_4/S +VREF_CA_B
4,6,37 DDR_VTTREF
1

C35 C36 C29 C46


C24 *.1U/10V_4
+1.5VSUS C194 C167 C184
+ C176 R59
*2K/F_4
PROJECT : R22
1U/6.3V_4 *.1U/10V_4 4.7U/6.3V_6 *22U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 *150u_6.3V_3528 Quanta Computer Inc.
2

C34 .1U/10V_4

Size Document Number Rev


Custom 1A
DDR3 SODIMMS TERMINATIONS
NB5/RD2
Date: Wednesday, September 15, 2010Sheet 7 of 43
5 4 3 2 1
5 4 3 2 1

U20A

HT_CPU_NB_CAD_H[15..0]

HT_CPU_NB_CAD_L[15..0]
HT_CPU_NB_CAD_H[15..0] 3
HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
Y25
Y24
V22
V23
V25
V24
U24
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
PART 1 OF 6
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
D24
D25
E24
E25
F24
F25
F23
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
08
HT_CPU_NB_CAD_L[15..0] 3 HT_CPU_NB_CAD_L3 HT_RXCAD3P HT_TXCAD3P HT_NB_CPU_CAD_L3
U25 HT_RXCAD3N HT_TXCAD3N F22
HT_CPU_NB_CLK_H[1..0] HT_CPU_NB_CAD_H4 T25 H23 HT_NB_CPU_CAD_H4
HT_CPU_NB_CLK_H[1..0] 3 HT_CPU_NB_CAD_L4 HT_RXCAD4P HT_TXCAD4P HT_NB_CPU_CAD_L4
T24 HT_RXCAD4N HT_TXCAD4N H22
HT_CPU_NB_CLK_L[1..0] HT_CPU_NB_CAD_H5 P22 J25 HT_NB_CPU_CAD_H5
HT_CPU_NB_CLK_L[1..0] 3 HT_CPU_NB_CAD_L5 HT_RXCAD5P HT_TXCAD5P HT_NB_CPU_CAD_L5
P23 HT_RXCAD5N HT_TXCAD5N J24
HT_CPU_NB_CTL_H[1..0] HT_CPU_NB_CAD_H6 P25 K24 HT_NB_CPU_CAD_H6
D HT_CPU_NB_CTL_H[1..0] 3 HT_RXCAD6P HT_TXCAD6P D

HYPER TRANSPORT CPU I/F


HT_CPU_NB_CAD_L6 P24 K25 HT_NB_CPU_CAD_L6
HT_CPU_NB_CTL_L[1..0] HT_CPU_NB_CAD_H7 HT_RXCAD6N HT_TXCAD6N HT_NB_CPU_CAD_H7
HT_CPU_NB_CTL_L[1..0] 3 N24 HT_RXCAD7P HT_TXCAD7P K23
HT_CPU_NB_CAD_L7 N25 K22 HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H[15..0] HT_RXCAD7N HT_TXCAD7N
HT_NB_CPU_CAD_H[15..0] 3 HT_CPU_NB_CAD_H8 HT_NB_CPU_CAD_H8
AC24 HT_RXCAD8P HT_TXCAD8P F21
HT_NB_CPU_CAD_L[15..0] HT_CPU_NB_CAD_L8 AC25 G21 HT_NB_CPU_CAD_L8 signals RS880 RX880
HT_NB_CPU_CAD_L[15..0] 3 HT_CPU_NB_CAD_H9 HT_RXCAD8N HT_TXCAD8N HT_NB_CPU_CAD_H9
AB25 HT_RXCAD9P HT_TXCAD9P G20
HT_NB_CPU_CLK_H[1..0] HT_CPU_NB_CAD_L9 AB24 H21 HT_NB_CPU_CAD_L9
HT_NB_CPU_CLK_H[1..0] 3 HT_CPU_NB_CAD_H10 HT_RXCAD9N HT_TXCAD9N HT_NB_CPU_CAD_H10
AA24 HT_RXCAD10P HT_TXCAD10P J20 HT_TXCALP
HT_NB_CPU_CLK_L[1..0] HT_CPU_NB_CAD_L10 AA25 J21 HT_NB_CPU_CAD_L10 R430 R430
HT_NB_CPU_CLK_L[1..0] 3 HT_CPU_NB_CAD_H11 HT_RXCAD10N HT_TXCAD10N HT_NB_CPU_CAD_H11
Y22 HT_RXCAD11P HT_TXCAD11P J18 301 ohm 1% 1.21k ohm 1%
HT_NB_CPU_CTL_H[1..0] HT_CPU_NB_CAD_L11 Y23 K17 HT_NB_CPU_CAD_L11 HT_TXCALN
HT_NB_CPU_CTL_H[1..0] 3 HT_CPU_NB_CAD_H12 HT_RXCAD11N HT_TXCAD11N HT_NB_CPU_CAD_H12
W 21 HT_RXCAD12P HT_TXCAD12P L19
HT_NB_CPU_CTL_L[1..0] HT_CPU_NB_CAD_L12 W 20 J19 HT_NB_CPU_CAD_L12
HT_NB_CPU_CTL_L[1..0] 3 HT_CPU_NB_CAD_H13 HT_RXCAD12N HT_TXCAD12N HT_NB_CPU_CAD_H13
V21 HT_RXCAD13P HT_TXCAD13P M19 HT_RXCALP
HT_CPU_NB_CAD_L13 V20 L18 HT_NB_CPU_CAD_L13 R434 R434
HT_CPU_NB_CAD_H14 HT_RXCAD13N HT_TXCAD13N HT_NB_CPU_CAD_H14
U20 HT_RXCAD14P HT_TXCAD14P M21 301 ohm 1% 1.21k ohm 1%
HT_CPU_NB_CAD_L14 U21 P21 HT_NB_CPU_CAD_L14 HT_RXCALN
HT_CPU_NB_CAD_H15 HT_RXCAD14N HT_TXCAD14N HT_NB_CPU_CAD_H15
U19 HT_RXCAD15P HT_TXCAD15P P18
HT_CPU_NB_CAD_L15 U18 M18 HT_NB_CPU_CAD_L15
HT_RXCAD15N HT_TXCAD15N
HT_CPU_NB_CLK_H0 T22 H24 HT_NB_CPU_CLK_H0
HT_CPU_NB_CLK_L0 HT_RXCLK0P HT_TXCLK0P HT_NB_CPU_CLK_L0
T23 HT_RXCLK0N HT_TXCLK0N H25
HT_CPU_NB_CLK_H1 AB23 L21 HT_NB_CPU_CLK_H1
HT_CPU_NB_CLK_L1 HT_RXCLK1P HT_TXCLK1P HT_NB_CPU_CLK_L1
AA22 HT_RXCLK1N HT_TXCLK1N L20

U17 HT_CPU_NB_CTL_H0 M22 M24 HT_NB_CPU_CTL_H0


HT_CPU_NB_CTL_L0 HT_RXCTL0P HT_TXCTL0P HT_NB_CPU_CTL_L0
M23 HT_RXCTL0N HT_TXCTL0N M25
SPM_VREF1 M9 E4 SPM_DQ2 HT_CPU_NB_CTL_H1 R21 P19 HT_NB_CPU_CTL_H1
SPM_VREF2 VREFCA DQL0 SPM_DQ1 HT_CPU_NB_CTL_L1 HT_RXCTL1P HT_TXCTL1P HT_NB_CPU_CTL_L1
C H2 VREFDQ DQL1 F8 R20 HT_RXCTL1N HT_TXCTL1N R18 C
F3 SPM_DQ5
SPM_A0 DQL2 SPM_DQ3 R358 301/F_4 HT_RXCALP HT_TXCALP R359 301/F_4
N4 A0 DQL3 F9 C23 HT_RXCALP HT_TXCALP B24
SPM_A1 P8 H4 SPM_DQ7 HT_RXCALN A24 B25 HT_TXCALN
SPM_A2 A1 DQL4 SPM_DQ0 HT_RXCALN HT_TXCALN
P4 A2 DQL5 H9
SPM_A3 N3 G3 SPM_DQ4 RS880
SPM_A4 A3 DQL6 SPM_DQ6
P9 A4 DQL7 H8
SPM_A5 P3
SPM_A6 A5
R9 A6
SPM_A7 R3 D8 SPM_DQ13
SPM_A8 A7 DQU0 SPM_DQ8
T9 A8 DQU1 C4
SPM_A9 R4 C9 SPM_DQ10
SPM_A10 A9 DQU2 SPM_DQ12
L8 A10/AP DQU3 C3
SPM_A11 R8 A8 SPM_DQ15
SPM_A12 A11 DQU4 SPM_DQ11
N8 A3
SPM_A13 T4
A12/BC
A13
DQU5
DQU6 B9 SPM_DQ14 This block is for UMA only , DIS can remove all component
T8 A4 SPM_DQ9
A14 DQU7
M8 A15 +1.5V_MEM_VDDQ
+1.5V
SPM_BA0 M3 B3
SPM_BA1 BA0 VDD#B3 U20D +1.5V_MEM_VDDQ
SPM_BA2
N9 BA1 VDD#D10 D10 40mils wdith or more
M4 BA2 VDD#G8 G8 PAR 4 OF 6
K3 SPM_A0 AB12 AA18 SPM_DQ0 R307 *0_6
VDD#K3 SPM_A1 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) SPM_DQ1
VDD#K9 K9 AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
N2 SPM_A2 V11 AA19 SPM_DQ2
SPM_CLKP VDD#N2 SPM_A3 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) SPM_DQ3 C93 C85 C78
J8 CK VDD#N10 N10 AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
R58 *100_4 SPM_CLKN K8 R2 SPM_A4 AA12 V17 SPM_DQ4 *0.1U/10V_4 *10U/6.3V_8 *10U/6.3V_8
SPM_CKE CK VDD#R2 SPM_A5 MEM_A4(NC) MEM_DQ4(NC) SPM_DQ5
K10 CKE VDD#R10 R10 AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
+1.5V_MEM_VDDQ SPM_A6 AB14 AA15 SPM_DQ6
B
SPM_A7 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) SPM_DQ7 B
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
SPM_ODT K2 A2 SPM_A8 AD13 AC20 SPM_DQ8
SPM_CS# ODT VDDQ#A2 SPM_A9 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) SPM_DQ9
L3 CS VDDQ#A9 A9 AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19

SBD_MEM/DVO_I/F
SPM_RAS# J4 C2 SPM_A10 AC16 AE22 SPM_DQ10
SPM_CAS# RAS VDDQ#C2 SPM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) SPM_DQ11
K4 CAS VDDQ#C10 C10 AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
SPM_WE# L4 D3 SPM_A12 AC14 AB20 SPM_DQ12 C91 C99 C94
WE VDDQ#D3 SPM_A13 MEM_A12(NC) MEM_DQ12(NC) SPM_DQ13 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4
VDDQ#E10 E10 T16 Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
F2 AC22 SPM_DQ14
SPM_DQS0P VDDQ#F2 SPM_BA0 MEM_DQ14/DVO_D10(NC) SPM_DQ15
F4 DQSL VDDQ#H3 H3 AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
SPM_DQS1P C8 H10 SPM_BA1 AE17
DQSU VDDQ#H10 SPM_BA2 MEM_BA1(NC) SPM_DQS0P
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
W 18 SPM_DQS0N
SPM_DM0 SPM_RAS# MEM_DQS0N/DVO_IDCKN(NC) SPM_DQS1P
E8 DML VSS#A10 A10 W 12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
SPM_DM1 D4 B4 SPM_CAS# Y12 AE21 SPM_DQS1N
DMU VSS#B4 SPM_WE# MEM_CASb(NC) MEM_DQS1N(NC)
VSS#E2 E2 AD18 MEM_W Eb(NC)
G9 SPM_CS# AB13 W 17 SPM_DM0
+1.5V_MEM_VDDQ SPM_DQS0N VSS#G9 SPM_CKE MEM_CSb(NC) MEM_DM0(NC) SPM_DM1
G4 DQSL VSS#J3 J3 AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
SPM_DQS1N B8 J9 SPM_ODT V14
DQSU VSS#J9 MEM_ODT(NC) +1.8V_IOPLLVDD18 *PBY160808T-221Y-N L52
VSS#M2 M2 IOPLLVDD18(NC) AE23 +1.8V
R305 *10K/F_4 M10 SPM_CLKP V15 AE24 +1.1V_IOPLLVDD *PBY160808T-221Y-N L14 +1.1V
VSS#M10 SPM_CLKN MEM_CKP(NC) IOPLLVDD(NC)
VSS#P2 P2 W 14 MEM_CKN(NC)
T3 P10 AD23 C574 C154
13 SP_DDR3_RST# RESET VSS#P10 IOPLLVSS(NC)
T2 R324 *40.2/F_4 SPM_COMPP AE12
VMA_ZQ2 VSS#T2 *40.2/F_4 SPM_COMPN MEM_COMPP(NC)
L9 ZQ VSS#T10 T10 R320 AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18 SPM_VREF *2.2U/6.3V_6 *2.2U/6.3V_6
+1.5V_MEM_VDDQ
RS880
VSSQ#B2 B2
B10 R322 *1K/F_4 R323 *1K/F_4
R56 VSSQ#B10
VSSQ#D2 D2
A *243/F_4 VSSQ#D9 D9 A

VSSQ#E3 E3
J2 E9 SPM_VREF1 SPM_VREF2 C564 *0.1U/10V_4 C563 *0.1U/10V_4 +1.5V_MEM_VDDQ
NC#J2 VSSQ#E9
L2 NC#L2 VSSQ#F10 F10
J10 NC#J10 VSSQ#G2 G2
L10 NC#L10 VSSQ#G10 G10

100-BALL
R46 *1K/F_4 R48 *1K/F_4 R62 *1K/F_4 R63 *1K/F_4
PROJECT : R22
SDRAM DDR3
*H5TQ1G63AFR-14C
Quanta Computer Inc.
C92 *0.1U/10V_4 C87 *0.1U/10V_4 +1.5V_MEM_VDDQ C132 *0.1U/10V_4 C147 *0.1U/10V_4 +1.5V_MEM_VDDQ
Size Document Number Rev
Custom 1A
RS880-HT LINK I/F 1/5
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 8 of 43
5 4 3 2 1
5 4 3 2 1

UMA can remove all GFX_TX CAP


GFX_RX can remove
at next stage for MUXLESS

D4
U20B
A5 C_PEG_TX#15
To HDMI CONN 09
GFX_RX0P GFX_TX0P C_PEG_TX#15 25
C4 PART 2 OF 6 B5 C_PEG_TX15
GFX_RX0N GFX_TX0N C_PEG_TX15 25
A3 A4 C_PEG_TX#14
GFX_RX1P GFX_TX1P C_PEG_TX#14 25
B3 B4 C_PEG_TX14
GFX_RX1N GFX_TX1N C_PEG_TX14 25
C2 C3 C_PEG_TX13
D GFX_RX2P GFX_TX2P C_PEG_TX13 25 D
C1 B2 C_PEG_TX#13
GFX_RX2N GFX_TX2N C_PEG_TX#13 25
E5 D1 C_PEG_TX12
GFX_RX3P GFX_TX3P C_PEG_TX12 25
F5 D2 C_PEG_TX#12
GFX_RX3N GFX_TX3N C_PEG_TX#12 25
G5 GFX_RX4P GFX_TX4P E2
G6 GFX_RX4N GFX_TX4N E1
H5 GFX_RX5P GFX_TX5P F4
H6 GFX_RX5N GFX_TX5N F3
J6 F1
GFX_RX6P GFX_TX6P
J5 GFX_RX6N GFX_TX6N F2
J7 H4
GFX_RX7P GFX_TX7P
J8 GFX_RX7N GFX_TX7N H3

PCIE I/F GFX


PEG_RX7 L5 H1 C_PEG_TX7 C614 0.1U/10V_4 PEG_TX7
PEG_RX#7 GFX_RX8P GFX_TX8P C_PEG_TX#7 C613 0.1U/10V_4 PEG_TX#7
L6 H2
PEG_RX6 GFX_RX8N GFX_TX8N C_PEG_TX6 C_PEG_TX#6 C610 0.1U/10V_4 PEG_TX6
M8 GFX_RX9P GFX_TX9P J2
PEG_RX#6 L8 J1 C_PEG_TX#6 C_PEG_TX6 C612 0.1U/10V_4 PEG_TX#6
PEG_RX5 GFX_RX9N GFX_TX9N C_PEG_TX5 C_PEG_TX#5 C608 0.1U/10V_4 PEG_TX5
P7 K4
PEG_RX#5 GFX_RX10P GFX_TX10P C_PEG_TX#5 C_PEG_TX5 C609 0.1U/10V_4 PEG_TX#5
M7 GFX_RX10N GFX_TX10N K3
PEG_RX4 P5 K1 C_PEG_TX4 C_PEG_TX#4 C606 0.1U/10V_4 PEG_TX4
PEG_RX#4 GFX_RX11P GFX_TX11P C_PEG_TX#4 C_PEG_TX4 C607 0.1U/10V_4 PEG_TX#4
M5 K2
PEG_RX3 GFX_RX11N GFX_TX11N C_PEG_TX3 C604 0.1U/10V_4 PEG_TX3
R8 GFX_RX12P GFX_TX12P M4
PEG_RX#3 P8 M3 C_PEG_TX#3 C605 0.1U/10V_4 PEG_TX#3
PEG_RX2 GFX_RX12N GFX_TX12N C_PEG_TX2 C601 0.1U/10V_4 PEG_TX2
R6 GFX_RX13P GFX_TX13P M1
PEG_RX#2 R5 M2 C_PEG_TX#2 C599 0.1U/10V_4 PEG_TX#2
PEG_RX1 GFX_RX13N GFX_TX13N C_PEG_TX1 C597 0.1U/10V_4 PEG_TX1
P4 N2
PEG_RX#1 GFX_RX14P GFX_TX14P C_PEG_TX#1 C598 0.1U/10V_4 PEG_TX#1
P3 N1
PEG_RX0 GFX_RX14N GFX_TX14N C_PEG_TX0 C590 0.1U/10V_4 PEG_TX0
T4 P1
PEG_RX#0 GFX_RX15P GFX_TX15P C_PEG_TX#0 C594 0.1U/10V_4 PEG_TX#0
T3 P2
GFX_RX15N GFX_TX15N PEG_RX#[15:0] PEG_TX#[15:0]
17 PEG_RX#[15:0] PEG_TX#[15:0] 17
AE3 AC1
GPP_RX0P GPP_TX0P PEG_RX[15:0] PEG_TX[15:0]
AD4 AC2 17 PEG_RX[15:0] PEG_TX[15:0] 17
C PCIE_RXP1 GPP_RX0N GPP_TX0N PCIE_TXP1_C C177 0.1U/10V_4 C
33 PCIE_RXP1 AE2 GPP_RX1P GPP_TX1P AB4 PCIE_TXP1 33
PCIE_RXN1 AD3 AB3 PCIE_TXN1_C C178 0.1U/10V_4 TO WLAN
33 PCIE_RXN1 GPP_RX1N GPP_TX1N PCIE_TXN1 33
PCIE_RXP2_LAN AD1 AA2 PCIE_TXP2_C C562 0.1U/10V_4
30 PCIE_RXP2_LAN GPP_RX2P GPP_TX2P PCIE_TXP2_LAN 30
PCIE_RXN2_LAN AD2 PCIE I/F GPP AA1 PCIE_TXN2_C C561 0.1U/10V_4 TO PCIE-LAN
30 PCIE_RXN2_LAN GPP_RX2N GPP_TX2N PCIE_TXN2_LAN 30
V5 GPP_RX3P GPP_TX3P Y1
W6 GPP_RX3N GPP_TX3N Y2
U5 Y4
GPP_RX4P GPP_TX4P
U6 Y3
PCIE_RXP5 GPP_RX4N GPP_TX4N PCIE_TXP5_C C559 0.1U/10V_4
26 PCIE_RXP5 U8 V1 PCIE_TXP5 26
PCIE_RXN5 GPP_RX5P GPP_TX5P PCIE_TXN5_C C560 0.1U/10V_4
26 PCIE_RXN5 U7
GPP_RX5N GPP_TX5N
V2 PCIE_TXN5 26 TO PCIE CARD READER
AA8 AD7 A_TX0P_C C567 0.1U/10V_4 PCIE_NB_SB_TX0P 12
12 PCIE_SB_NB_RX0P SB_RX0P SB_TX0P
Y8 AE7 A_TX0N_C C568 0.1U/10V_4 PCIE_NB_SB_TX0N 12
12 PCIE_SB_NB_RX0N SB_RX0N SB_TX0N
AA7 AE6 A_TX1P_C C566 0.1U/10V_4 PCIE_NB_SB_TX1P 12
12 PCIE_SB_NB_RX1P SB_RX1P SB_TX1P
Y7 AD6 A_TX1N_C C565 0.1U/10V_4 PCIE_NB_SB_TX1N 12
12 PCIE_SB_NB_RX1N SB_RX1N SB_TX1N
AA5 PCIE I/F SB AB6 A_TX2P_C C179 0.1U/10V_4 PCIE_NB_SB_TX2P 12
12 PCIE_SB_NB_RX2P SB_RX2P SB_TX2P
AA6 AC6 A_TX2N_C C180 0.1U/10V_4 PCIE_NB_SB_TX2N 12
12 PCIE_SB_NB_RX2N SB_RX2N SB_TX2N
W5 AD5 A_TX3P_C C569 0.1U/10V_4 PCIE_NB_SB_TX3P 12
12 PCIE_SB_NB_RX3P SB_RX3P SB_TX3P
Y5 AE5 A_TX3N_C C570 0.1U/10V_4 PCIE_NB_SB_TX3N 12
12 PCIE_SB_NB_RX3N SB_RX3N SB_TX3N
AC8 NB_PCIECALRP R65 1.27K/F_4
PCE_CALRP(PCE_BCALRP) NB_PCIECALRN R67 2K/F_4
AB8 +1.1V
PCE_CALRN(PCE_BCALRN)

RS880

RS880 Display Port Support (muxed on GFX)


B B

GFX_TX0,TX1,TX2 and TX3


DP0
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7


DP1
AUX1 and HPD1

A A

PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
RS880-PCIE I/F 2/5
NB5/RD2
Date: Wednesday, September 15, 2010Sheet 9 of 43
5 4 3 2 1
5 4 3 2 1

10
U20C
+3V_AVDD_NB F12 A22 LA_DATAP0
AVDD1(NC) TXOUT_L0P(NC) LA_DATAP0 23
E12 PART 3 OF 6 B22 LA_DATAN0
AVDD2(NC) TXOUT_L0N(NC) LA_DATAN0 23
+1.8V_AVDDDI_NB F14 A21 LA_DATAP1
AVDDDI(NC) TXOUT_L1P(NC) LA_DATAP1 23
G15 B21 LA_DATAN1
AVSSDI(NC) TXOUT_L1N(NC) LA_DATAN1 23
+1.8V_AVDDQ_NB H15 B20 LA_DATAP2
AVDDQ(NC) TXOUT_L2P(NC) LA_DATAP2 23
H14 A20 LA_DATAN2
AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) LA_DATAN2 23
R135 for UMA use 140 ohm TXOUT_L3P(NC) A19
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19

CRT/TVOUT
140ohm CS11402FB19 F17 Y(DFT_GPIO2)
133ohm CS11332FB00 F15 B18 LB_DATAP0
COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) LB_DATAP0 23
A18 LB_DATAN0
TXOUT_U0N(NC) LB_DATAN0 23
24 CRT_R G18 A17 LB_DATAP1
RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) LB_DATAP1 23
R136 140/F_4 G17 B17 LB_DATAN1
REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) LB_DATAN1 23
24 CRT_G E18 D20 LB_DATAP2
GREEN(DFT_GPIO1) TXOUT_U2P(NC) LB_DATAP2 23
R138 150/F_4 F18 D21 LB_DATAN2
GREENb(NC) TXOUT_U2N(NC) LB_DATAN2 23
D 24 CRT_B E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18 D
R133 150/F_4 F19 D19
BLUEb(NC) TXOUT_U3N(NC)
24 HSYNC_COM HSYNC_COM A11 B16 LA_CLK
DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) LA_CLK 23
24 VSYNC_COM VSYNC_COM B11 A16 LA_CLK#
DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) LA_CLK# 23
E8 D16 LB_CLK
24 DDCDATA DAC_SDA(PCE_TCALRN) TXCLK_UP(PCIE_RESET_GPIO4) LB_CLK 23
F8 D17 LB_CLK#
24 DDCCLK DAC_SCL(PCE_RCALRN) TXCLK_UN(PCIE_RESET_GPIO1) LB_CLK# 23
R129 715/F_6 DAC_RSET_NB G14 DAC_RSET(PWM_GPIO1) +1.8V_VDDLTP18_NB
VDDLTP18(NC) A13
+1.1V_PLLVDD A12 B13
+1.8V_PLLVDD18 PLLVDD(NC) VSSLTP18(NC)
D14 PLLVDD18(NC)

LVTM
B12 A15 +1.8V_VDDLT_18_NB
PLLVSS(NC) VDDLT18_1(NC)

PLL PWR
VDDLT18_2(NC) B15
+1.8V_VDDA18HTPLL H17 A14
VDDA18HTPLL VDDLT33_1(NC)
VDDLT33_2(NC) B14
+1.8V_VDDA18PCIEPLL D7 VDDA18PCIEPLL1
E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
VSSLT2(VSS) D15
NB_RST#_IN D8 C16
12 NB_PLTRST# SYSRESETb VSSLT3(VSS)
NB_PWRGD_IN A10 C18
16 NB_PWRGD_IN POWERGOOD VSSLT4(VSS)
NB_LDT_STOP# C10 C20
LDTSTOPb VSSLT5(VSS)

PM
NB_ALLOW_LDTSTOP C12 E20
ALLOW_LDTSTOP VSSLT6(VSS)
VSSLT7(VSS) C22
NBHT_REFCLKP C25
12 NBHT_REFCLKP HT_REFCLKP
NBHT_REFCLKN C24 I
12 NBHT_REFCLKN HT_REFCLKN
NB_REFCLK_P E11
12 NB_REFCLK_P REFCLK_P/OSCIN(OSCIN)

CLOCKs
NB_REFCLK_N F11 I E9 DISP_ON
12 NB_REFCLK_N REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) DISP_ON 23
F7 DPST_PWM
LVDS_BLON(PCE_RCALRP) DPST_PWM 23
NBGFX_CLKP T2 G12 LVDS_BLON
GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) LVDS_BLON 23
NBGFX_CLKN T1 I/O
GFX_REFCLKN
NBGPP_CLKP U1
T19 GPP_REFCLKP
NBGPP_CLKN U2 I/O
T17 GPP_REFCLKN
C R93 R92 C
SBLINK_CLKP V4
12 SBLINK_CLKP GPPSB_REFCLKP(SB_REFCLKP)
4.7K_4 4.7K_4 SBLINK_CLKN V3
12 SBLINK_CLKN GPPSB_REFCLKN(SB_REFCLKN)
NB_I2C_DATA A9
23 EDIDDATA_NB I2C_DATA
NB_I2C_CLK B9 D9 TMDS_HPD0
23 EDIDCLK_NB
B8
I2C_CLK MIS. TMDS_HPD(NC)
D10 TMDS_HPD1
INT_TMDS_HPD 25
T116 DDC_DATA/AUX0N(NC) HPD(NC) T117
T118 A8 DDC_CLK/AUX0P(NC)
B7 D12 SUS_STAT#_NB R156 *0_4/S
25 HDMI_DDC_CLK DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) SUS_STAT# 13
25 HDMI_DDC_DATA A7 DDC_DATA1A/AUX1N(NC)
THERMALDIODE_P AE8
DYN_PWR_EN B10 AD8
35 DYN_PWR_EN STRP_DATA THERMALDIODE_N
G11 RSVD TESTMODE D13 TEST_EN

C8 R361
T115 AUX_CAL(NC) 1.8K_4
RS880

PBY160808T-221Y-N(220,2A) 65 mA VDDLTP18 - LVDS or DVI/HDMI PLL


MUXLESS need 110 mA +1.1V +1.1V_PLLVDD not applicable to RS880
+3V L30 +3V_AVDD_NB L63
add PLL power PBY160808T-221Y-N(220,2A) PLLVDD - Graphics PLL
C628 +1.8V
for LVDS AVDD-DAC Analog
not applicable to
C379 2.2U/6.3V_6 RS880 PBY160808T-221Y-N(220,2A) 15 mA
not applicable to RS880
2.2U/6.3V_6 +1.8V_VDDLTP18_NB
L66
C630

+1.8V 2.2U/6.3V_6
B
STRAP_DEBUG_BUS_GPIO_ENABLEb +1.8V
B

R117 0_6 +1.8V_AVDDDI_NB AVDDI-DAC Digital PBY201209T-221Y-N(220,2A) 300 mA


Enables the Test Debug Bus using GPIO. L32 +1.8V_PLLVDD18 +1.8V_VDDLT_18_NB
not applicable to RS880
PBY160808T-221Y-N(220,2A) C348 L64
RS880M
VSYNC_COM R369 3K_4 +3V 0.1U/10V_4
1 Disable C400 C364 C631 C627
0 Enable 10U/6.3V_8 2.2U/6.3V_6
PBY160808T-221Y-N(220,2A) 4 mA 4.7U/6.3V_6 0.1U/10V_4
+1.8V_AVDDQ_NB
PLLVDD18 - Graphics PLL L29 VDDLT18 - LVDS or
not applicable to RS880 AVDDQ-DAC Bandgap Reference DVI/HDMI digital
C357 not applicable to RS880 not applicable to
2.2U/6.3V_6
RS880
RS880M: Enables Side port memory
RS880M:HSYNC#

Selects if Memory SIDE PORT is available or not +1.8V


1 = Memory Side port Not available VDDA18PCIEPLL -PCIE PLL
0 = Memory Side port available 20mils width +1.8V
Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1] L28 +1.8V_VDDA18PCIEPLL

PBY160808T-221Y-N(220,2A) +1.8V
R143
C381
2.2U/6.3V_6 1K/F_4
HSYNC_COM R365 3K_4 +3V
C636 R178
R364 *3K_4 U11 2K/F_4 12 ALLOW_LDTSTOP
VDDA18HTPLL -HT LINK PLL 0.1U/10V_4 1 5
NC VCC
A A
20 mA 2 R145 *0_4/S NB_ALLOW_LDTSTOP
3,12 CPU_LDT_STOP# IN
L27 +1.8V_VDDA18HTPLL
3 4 NB_LDT_STOP#
PBY160808T-221Y-N(220,2A) GND OUT
For external EEPROM Debug only
RS780/RX780 74LVC1G07GW
C362
DYN_PWR_EN R363 2K/F_4 2.2U/6.3V_6

PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
RS880-SYSTEM I/F 3/5
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 10 of 43
5 4 3 2 1
5 4 3 2 1

RS880M POWER TABLE 11

AE14
AC3
AC4

M11
AA4
AB5
AB1
AB7

AE1
AE4
AB2

D11

E14
E15

K14

L15
J15
J12
W1
W2
W4
W7
W8
M6
G1
G2
G4

G8
D3
D5

H7

R7

N4

R1
R2
R4

U4
A2
B1

E4

P6

V7

V8
V6

Y6
L1
L2
L4
L7
J4
U20F PIN NAME PIN NAME
RS880M RS880M
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VDDHT +1.1V IOPLLVDD +1.1V

VDDHTRX +1.1V AVDD +3.3V

VDDHTTX +1.2V AVDDDI +1.8V


PART 6/6

D D
GROUND VDDA18PCIE +1.8V AVDDQ +1.8V

VDDG18 +1.8V PLLVDD +1.1V

VDD18_MEM +1.8V PLLVDD18 +1.8V


VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
VDDPCIE +1.1V VDDA18PCIEPLL +1.8V
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VDDC +1.1V VDDA18HTPLL +1.8V

VDD_MEM +1.8V/1.5V VDDLTP18 +1.8V


A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VDDG33 +3.3V VDDLT18 +1.8V

IOPLLVDD18 +1.8V VDDLT33 NC

VDDHT - HT +1.1V

C
LINK digital
I/O for
+1.1V 2A for RS880M VDDPCIE - PCIE-E Main power C
U20E
RX780/RS780 0.6A L49 +1.1V_VDDHT +1.1V_VDD_PCIE
2.5A R146 *0_8/S
J17 VDDHT_1 VDDPCIE_1 A6 +1.1V
*0_8/S K16 PART 5/6 B6
VDDHT_2 VDDPCIE_2
L16 VDDHT_3 VDDPCIE_3 C6
C551 C278 C329 C293 M16 D6 C315 C370 C336 C359 C378
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHT_4 VDDPCIE_4 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 4.7U/6.3V_6
P16 VDDHT_5 VDDPCIE_5 E6
VDDHTRX - HT R16 VDDHT_6 VDDPCIE_6 F6
LINK RX I/O for T16 VDDHT_7 VDDPCIE_7 G7
RX780/RS780 0.7A L65 +1.1V_VDDHTRX VDDPCIE_8 H8
H18 VDDHTRX_1 VDDPCIE_9 J9
*0_8/S G19 K9
VDDHTRX_2 VDDPCIE_10
F20 VDDHTRX_3 VDDPCIE_11 M9
VDDHTTX - HT C632 C350 C345 C629 E21 L9
4.7U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHTRX_4 VDDPCIE_12
LINK TX I/O for D22 VDDHTRX_5 VDDPCIE_13 P9
RS880 B23 VDDHTRX_6 VDDPCIE_14 R9
A23 VDDHTRX_7 VDDPCIE_15 T9
RS880 0.5A V9
+1.1V L9 +1.1V 2A for RS880M +1.1V_VDDHTTX AE25 VDDHTTX_1
VDDPCIE_16
VDDPCIE_17 U9
*0_8/S AD24 7A VDDC - Core Logic power
VDDHTTX_2
AC23 VDDHTTX_3 VDDC_1 K12 +1.1V_DYN
C196 C228 C241 C260 C219 AB22 J14
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHTTX_4 VDDC_2
AA21 VDDHTTX_5 VDDC_3 U16
Y20 J11 C264 C304 C314 C317 C545 C544 C542
VDDHTTX_6 VDDC_4 560P/50V 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4
W 19 K15

POWER
VDDHTTX_7 VDDC_5
V18 VDDHTTX_8 VDDC_6 M12
U17 VDDHTTX_9 VDDC_7 L14
T17 VDDHTTX_10 VDDC_8 L11
R17 VDDHTTX_11 VDDC_9 M13
P17 M15
B +1.8V 1A for RS780M+SB700 M17
VDDHTTX_12 VDDC_10
N12
B
VDDHTTX_13 VDDC_11
L16
700mA +1.8V_VDDA18PCIE VDDC_12 N14
C296 C290 C265 C546 C543
+1.8V J10 VDDA18PCIE_1 VDDC_13 P11 VDD_MEM For UMA RS780 only
P10 P13 0.1U/10V_4 0.1U/10V_4 560P/50V 10U/6.3V_8 560P/50V
PBY201209T-221Y-N(220,2A) K10
VDDA18PCIE_2 VDDC_14
P14 Not applicable to RX780
C213 C204 C267 C238 C281 C255 VDDA18PCIE_3 VDDC_15
VDDA18PCIE - M10 VDDA18PCIE_4 VDDC_16 R12 memory I/O transform
PCIE TX stage 4.7U/6.3V_6 4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 L10 R15
VDDA18PCIE_5 VDDC_17
I/O for W9 VDDA18PCIE_6 VDDC_18 T11
H9 VDDA18PCIE_7 VDDC_19 T15
RX780/RS780 T10 U12
VDDA18PCIE_8 VDDC_20
R10 VDDA18PCIE_9 VDDC_21 T14
Y9 VDDA18PCIE_10 VDDC_22 J16
AA9 VDDA18PCIE_11
AB9 AE10 +1.5V_VDD_MEM L53 *0_8 +1.5V
VDDA18PCIE_12 VDD_MEM1(NC)
R141 *0_6/S
25mA AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11
C225 C206 C205 C222 C220
VDD18 - RS780 I/O +1.8V AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
transform U10 AD10 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 0_4 *4.7U/6.3V_6
C328 VDDA18PCIE_15 VDD_MEM4(NC)
VDD_MEM5(NC) AB10
1U/10V_4 +1.8V_VDDG18_NB F9 AC10
VDDG18_1(VDD18_1) VDD_MEM6(NC) RS780
G9 VDDG18_2(VDD18_2) +3V_VDDG33 R142 *0_6/S
3.3V(0.06A)
R321 *0_6/S
25mA +1.8V_VDD18_MEM
AE11 VDD18_MEM1(NC) VDDG33_1(NC) H11 +3V This is side port power
+1.8V AD11 H12
VDD18_MEM2(NC) VDDG33_2(NC) C366 C360 VDD33 - 3.3V I/O DIS remove L55 ,
VDD18_MEM For UMA RS780 only C558 RS880 0.1U/10V_4 0.1U/10V_4 change C205 to 0 ohm
1U/10V_4 Not applicable to RX780
Not applicable to RX780 and short to GND
memory I/O transform

A A

PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
RS880-POWER5/5
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 11 of 43
5 4 3 2 1
5 4 3 2 1

30 LAN_PLTRST# R396
R397
33_4
33_4
U28A
12
33 MINI_PLTRST#
R415 33_4 P1
SB800 Part 1 of 5
W2
26 5219_RST_R# PCIE_RST# PCICLK0 T63
10 NB_PLTRST# R391 33_4 A_RST# L1 W1 PCI_CLK_TPM 16

PCI CLKS
A_RST# PCICLK1/GPO36
PCICLK2/GPO37 W3 PCI_CLK2 16
9 PCIE_SB_NB_RX0P C523 0.1U/10V_4 A_RX0P_C AD26 W4 PCI_CLK3 16
C522 0.1U/10V_4 A_RX0N_C A_TX0P PCICLK3/GPO38
PLACE THESE 9 PCIE_SB_NB_RX0N
C527 0.1U/10V_4 A_RX1P_C
AD27 A_TX0N PCICLK4/14M_OSC/GPO39 Y1 PCI_CLK4 16
9 PCIE_SB_NB_RX1P AC28 A_TX1P
D
PCIE AC 9 PCIE_SB_NB_RX1N C525 0.1U/10V_4 A_RX1N_C AC29 V2 PCIRST#_L R399 33_4 PCIRST# PCIRST# 32
D
C528 0.1U/10V_4 A_RX2P_C A_TX1N PCIRST#
COUPLING CAPS 9 PCIE_SB_NB_RX2P AB29 A_TX2P
9 PCIE_SB_NB_RX2N C529 0.1U/10V_4 A_RX2N_C AB28 A_TX2N
CLOSE TO SB 9 PCIE_SB_NB_RX3P C520 0.1U/10V_4 A_RX3P_C AB26 A_TX3P AD0/GPIO0 AA1
9 PCIE_SB_NB_RX3N C521 0.1U/10V_4 A_RX3N_C AB27 AA4 C672
A_TX3N AD1/GPIO1
AD2/GPIO2 AA3 150P/50V_4
PCIE_NB_SB_TX0P AE24 AB1
9 PCIE_NB_SB_TX0P A_RX0P AD3/GPIO3
To RS880
PCIE_NB_SB_TX0N AE23 AA5
9 PCIE_NB_SB_TX0N A_RX0N AD4/GPIO4

PCI EXPRESS INTERFACES


PCIE_NB_SB_TX1P AD25 AB2
9 PCIE_NB_SB_TX1P A_RX1P AD5/GPIO5
PCIE_NB_SB_TX1N AD24 AB6
9 PCIE_NB_SB_TX1N A_RX1N AD6/GPIO6
PCIE_NB_SB_TX2P AC24 AB5
9 PCIE_NB_SB_TX2P A_RX2P AD7/GPIO7
PCIE_NB_SB_TX2N AC25 AA6 D21
9 PCIE_NB_SB_TX2N A_RX2N AD8/GPIO8
PCIE_NB_SB_TX3P AB25 AC2 RB500V-40
9 PCIE_NB_SB_TX3P A_RX3P AD9/GPIO9 +AVBAT
PCIE_NB_SB_TX3N AB24 AC3 1 2
9 PCIE_NB_SB_TX3N A_RX3N AD10/GPIO10 +3VPCU
AD11/GPIO11 AC4
R437 590/F_4 PCIE_CALRP_SB AD29
+1.1V_PCIE_VDDR R438 2.0K/F_4 PCIE_CALRN_SB AD28 PCIE_CALRP AD12/GPIO12 AC1
AD1
20MIL R418 499/F_4 +3VRTC_1 R420 10_4 +3VRTC 1 2
PCIE_CALRN AD13/GPIO13
AD14/GPIO14 AD2
D22
AA28 AC6
20MIL 20MIL

+VCCRTC_2
GPP_TX0P AD15/GPIO15 RB500V-40
AA29 GPP_TX0N AD16/GPIO16 AE2
Y29 AE1 C677
GPP_TX1P AD17/GPIO17
Y28 GPP_TX1N AD18/GPIO18 AF8
Y26 AE3 1U/10V_4
Y27
GPP_TX2P AD19/GPIO19
AF1 20MIL
GPP_TX2N AD20/GPIO20
W 28 GPP_TX3P AD21/GPIO21 AG1
W 29 AF2 R269
GPP_TX3N AD22/GPIO22 VDDR_1.05_EN 39
AE9 AD23
AD23/GPIO23 T86
AA22 AD9 AD24 RTC_X1 1K/F_4
GPP_RX0P AD24/GPIO24 AD24 39
Y21 AC11 AD25
GPP_RX0N AD25/GPIO25 T83 Y3
C AA25 AF6 AD26 C

+BAT
GPP_RX1P AD26/GPIO26 T72
AD27
AA24
W 23
GPP_RX1N AD27/GPIO27 AF4
AF3
T66 3 2
20MIL
GPP_RX2P AD28/GPIO28 SB_MEMHOT#
V24 GPP_RX2N AD29/GPIO29 AH2 T64
W 24 GPP_RX3P AD30/GPIO30 AG2
W 25 AH3 4 1 RTC_X2
GPP_RX3N AD31/GPIO31

PCI INTERFACE
AA8 All the PCI bus has R389 CN27
CBE0#
AD5
CBE1#
AD8 build-in Pull-UP/Down 32.768KHZ
CBE2# *20M_6 R409 20M_6 1
CBE3# AA10 resistors 2
FRAME# AE8
DEVSEL# AB9
SBLINK_CLKP RP8 2 1 0_4P2R_4 SBLINK_CLKP_R M23 AJ3 C673 C675 88266-020L
10 SBLINK_CLKP PCIE_RCLKP/NB_LNK_CLKP IRDY#
SBLINK_CLKN 4 3 SBLINK_CLKN_R P23 AE7 33P/50V_4 33P/50V_4
10 SBLINK_CLKN PCIE_RCLKN/NB_LNK_CLKN TRDY#
AC5 C469 100P/50V_4
NB_REFCLK_P RP9 PAR
10 NB_REFCLK_P 2 1 0_4P2R_4 NB_REFCLK_P_R U29 NB_DISP_CLKP STOP# AF5
NB_REFCLK_N 4 3 NB_REFCLK_N_R U28 AE6
10 NB_REFCLK_N NB_DISP_CLKN PERR#
AE4 SERR# DB to SI Change C673,C675 to 33P
SERR# SERR# 32
NBHT_REFCLKP RP12 2 1 0_4P2R_4 NBHT_REFCLKP_R T26 AE11
10 NBHT_REFCLKP NB_HT_CLKP REQ0#
NBHT_REFCLKN 4 3 NBHT_REFCLKN_R T27 AH5
10 NBHT_REFCLKN NB_HT_CLKN REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41 AH4 DB to SI CN27 Change PN
CPUCLKP RP11 4 3 0_4P2R_4 CPUCLKP_R V21 AC12
3 CPUCLKP
CPUCLKN 2 1 CPUCLKN_R T21
CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42
AD12
T90 :DFWF02MS022
PN:
3 CPUCLKN CPU_HT_CLKN GNT0#
GNT1#/GPO44 AJ5 :50273-0027N-001-2P-L
Footprint:
EXT_GFX_CLKP RP14 4 3 0_4P2R_4 EXT_GFX_CLKP_R V23 AH6 VGA_ON_SB VGA_ON_SB 32
17 EXT_GFX_CLKP SLT_GFX_CLKP GNT2#/GPO45
EXT_GFX_CLKN 2 1 EXT_GFX_CLKN_R T23 AB12
17 EXT_GFX_CLKN SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 T93
CLKRUN# AB11 CLKRUN# 32
PCIE_MINI1_CLKP RP10 2 1 0_4P2R_4 PCIE_MINI1_CLKP_R L29 AD7
33 PCIE_MINI1_CLKP GPP_CLK0P LOCK# T75
PCIE_MINI1_CLKN 4 3 PCIE_MINI1_CLKN_R L28
33 PCIE_MINI1_CLKN GPP_CLK0N
AJ6 R406 0_4
B INTE#/GPIO32 VGA_PWROK 20,32,37,38 B
PCIE_CARD_CLKP RP15 2 1 0_4P2R_4 PCIE_CARD_CLKP_R N29 AG6
26 PCIE_CARD_CLKP GPP_CLK1P INTF#/GPIO33
PCIE_CARD_CLKN 4 3 PCIE_CARD_CLKN_R N28 AG4
26 PCIE_CARD_CLKN GPP_CLK1N INTG#/GPIO34
AJ4 VGA_RSTB
INTH#/GPIO35
M29 GPP_CLK2P
M28 GPP_CLK2N
CLOCK GENERATOR

LPC_CLK0 16
PCIE_LAN_CLKP RP13 4 3 0_4P2R_4 PCIE_LAN_CLKP_R T25
30 PCIE_LAN_CLKP GPP_CLK3P LPC_CLK1 16
PCIE_LAN_CLKN 2 1 PCIE_LAN_CLKN_R V25 H24 LPC_CLK0 R290 22_4
30 PCIE_LAN_CLKN GPP_CLK3N LPCCLK0 PCLK_LPC_DEBUG 33
H25 LPC_CLK1 R287 22_4
LPCCLK1 PCLK_LPC_KB3920 32
L24 J27 LAD0
GPP_CLK4P LAD0 LAD0 32,33
L23 J26 LAD1
All RP resistor need GPP_CLK4N LAD1
H29 LAD2
LAD1 32,33
LPC

+3V LAD2 LAD2 32,33


LAD3 C518
within 0.5"of SB P25
M25
GPP_CLK5P LAD3 H28
G28 LFRAME#
LAD3 32,33
C524
C458 GPP_CLK5N LFRAME# LFRAME# 32,33
J25 LDRQ0#_SB 5.6P/50V_6 22P/50V_4
LDRQ0# T106
P29 AA18 LDRQ1#_SB EMI suggestion
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 T100
P28 AB19 SERIRQ
GPP_CLK6N SERIRQ/GPIO48 SERIRQ 32
U15 0.1U/10V_4 R277 10K/F_4
N26 GPP_CLK7P +3VS5
5

TC7SH08FU N27
A_RST# GPP_CLK7N ALLOW_LDTSTOP
2 ALLOW _LDTSTP/DMA_ACTIVE# G21 ALLOW_LDTSTOP 10
17 PCIE_RST# R232 33_4 4 T29 H21 CPU_PROCHOT_R#
GPP_CLK8P PROCHOT# CPU_PROCHOT_R# 3
1 VGA_RSTB T28 K19 CPU_PWRGD
CPU

GPP_CLK8N LDT_PG CPU_PWRGD 3


G22 CPU_LDT_STOP# CPU_LDT_STOP# 3,10 +AVBAT +AVBAT
LDT_STP# CPU_LDT_RST#
J24 CPU_LDT_RST# 3
3

LDT_RST#
L25 14M_25M_48M_OSC 20MIL

1
G2
C1 RTC_X1 *SHORT_ PAD1 C465
R233 *33_4 A_RST# 32K_X1
17 PCIE_RST# RTC_CLK 16,32 0.1U/10V_4
A C714 27P/50V_4 R436 *0_4/S 25M_X1 L26 C2 RTC_X2 A

2
25M_X1 32K_X2
RTC
1

D2 RTC_CLK
Y4 R440 RTCCLK INTRUDER_ALERT# R416 *1M/F_4
INTRUDER_ALERT# B2 +AVBAT
Support BACO, remove R465 25M_X2 L27 B1 +AVBAT
25MHZ 1M/F_4 25M_X2 VDDBT_RTC_G
and U6508 , add R6601
2

C709 27P/50V_4 SB820M A12 PROJECT : R22


Quanta Computer Inc.
INTRUDER_ALERT# Left not connected (Southbridge Size Document Number Rev
Custom 1A
has 50-kohm internal pull-up to VBAT). SB820-PCIE/PCI/CPU/LPC 1/4
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 12 of 43
5 4 3 2 1
5 4 3 2 1

+3VS5

R245

R417
NC,no install by default
*2.2K_4

*2.2K_4
SB_TEST0

SB_TEST1
remove pull hi
( chip internal
have pull hi )
14 MEM_GEVEN#

32
T122
T68
SUSB#
RI#
SPI_CS3#
SUSB#
SUSC#
J2
K1
D3
F1
H1
U28D
PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
USBCLK/14M_25M_48M_OSC

USB_RCOMP
A10

G19
CLK_48M_USB

USB_RCOMP_SB R270 11.8K/F_6


13
32 SUSC# SLP_S5#

ACPI / WAKE UP EVENTS


DNBSWON# F2
32 DNBSWON#

USB 1.1 USB MISC


R239 *2.2K_4 SB_TEST2 SB_PWRGD_IN PW R_BTN#
16 SB_PWRGD_IN
SUS_STAT#
H5
G6
PW R_GOOD SB800 J10
CLK_48M_USB
10 SUS_STAT# SUS_STAT# USB_FSD1P/GPIO186 USBP15+ 29
SB_TEST0 B3 Part 4 of 5 H11 BLUETOOTH
TEST0 USB_FSD1N USBP15- 29
SB_TEST1 C4
T71 TEST1/TMS
SB_TEST2 F6 H9
D +3VS5 TEST2 USB_FSD0P/GPIO185 T79 D
SCL1/SDATA1 is 3V/S5 tolerance GATEA20 AD21 J8 C485
32 GATEA20 GA20IN/GEVENT0# USB_FSD0N T84
AMD datasheet define it RCIN# AE21 *2.2P/50V_4
32 RCIN# KBRST#/GEVENT1#
K2 LPC_PME#/GEVENT3# USB_HSD13P B12 T85
R412 2.2K_4 SB_SMBCLK1 J29 A12
32 KBSMI# LPC_SMI#/GEVENT23# USB_HSD13N T78
R411 2.2K_4 SB_SMBDATA1 SCI# H2 for EMI
32 SCI# GEVENT5#
SYS_RST# J1 F11
SYS_RESET#/GEVENT19# USB_HSD12P T88
30,33 PCIE_WAKE# H6 W AKE#/GEVENT8# USB_HSD12N E11 T89
F3 IR_RX1/GEVENT20#
3 CPU_THERMTRIP# J6 THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P E14 T95
WD_PWRGD AC19 E12
+3V SCL0/SDATA0 16 WD_PWRGD NB_PW RGD USB_HSD11N T92
is 3V tolerance Clock gen/Robson/TV
AMD datasheet define it tuner C477 RSMRST# G1 J12
32 RSMRST# RSMRST# USB_HSD10P USBP10+ 33
100P/50V_4 J14 WLAN Min-Card
/DDR2/DDR2 USB_HSD10N USBP10- 33
R282 2.2K_4 PCLK_SMB AD19
thermal/Accelerometer 26 CARD_CLKREQ# CLK_REQ4#/SATA_IS0#/GPIO64
30 LAN_CLKREQ# AA16 CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P A13 T87
R281 2.2K_4 PDAT_SMB R404 *0_4 LAN_DISABLE#_SB AB21 B13
+3V 30,32 LAN_DISABLE# SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N T77
AC18 CLK_REQ0#/SATA_IS3#/GPIO60
T104 AF20 SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P D13 T97
T101 AE19 SATA_IS5#/FANIN3/GPIO59 USB_HSD8N C13 T91
R430 ACZ_SPKR AF19
27 ACZ_SPKR SPKR/GPIO66
PCLK_SMB AD22 G12

USB 2.0
6,7 PCLK_SMB SCL0/GPIO43 USB_HSD7P T94
Pure UMA can PDAT_SMB AE22 G14
6,7 PDAT_SMB SDA0/GPIO47 USB_HSD7N T96
remove D25 SB_SMBCLK1 F5
10K/F_4 SB_SMBDATA1 SCL1/GPIO227
F4 SDA1/GPIO228 USB_HSD6P G16 USBP6+ 29
RB501V-40 D25 AH21 G18 USB Connector
33 WLAN_CLKREQ# CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N USBP6- 29
1 2 VGA_REQ_R AB18
37 VGA_REQ CLK_REQ1#/FANOUT4/GPIO61

GPIO
T121 E1 IR_LED#/LLB#/GPIO184 USB_HSD5P D16 USBP5+ 29
T129 AJ21 SMARTVOLT2/SHUTDOW N#/GPIO51 USB_HSD5N C16 USBP5- 29 USB Connector
8 SP_DDR3_RST# H4 DDR3_RST#/GEVENT7#
C
T65 D5 GBE_LED0/GPIO183 USB_HSD4P B14 T126
C
T73 D7 GBE_LED1/GEVENT9# USB_HSD4N A14 T128
T74 G5 GBE_LED2/GEVENT10#
+3VS5 SCL2/SDATA2 is 3V/S5 tolerance K3 E18
T70 GBE_STAT0/GEVENT11# USB_HSD3P T102
AMD datasheet define it EXT_SB_OSC AA20 E16
T105 CLK_REQG#/GPIO65/OSCIN USB_HSD3N T99
R286 2.2K_4 SB_SCLK2 J16
USB_HSD2P USBP2+ 23
R284 2.2K_4 SB_SDATA2 H3 J18 Carama USB
BLINK/USB_OC7#/GEVENT18# USB_HSD2N USBP2- 23
R408 *10K_4 SYS_RST# D1
For Zero ODD R238 *0_4 SMBALERT#_1 E4
USB_OC6#/IR_TX1/GEVENT6#
B17

USB OC
5 PM_THERM# USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P T98
31 ODD_DA#_FCH D4 USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N A17 T127
+3VS5 E8
31 ODD_PLUGIN# USB_OC3#/AC_PRES/TDO/GEVENT15#
SB_JTAG_TCK F7 A16
T81 USB_OC2#/TCK/GEVENT14# USB_HSD0P USBP0+ 29
R413 2.2K_4 DNBSWON# SB_JTAG_TDI E7 B16 USB Connector
T76 USB_OC1#/TDI/GEVENT13# USB_HSD0N USBP0- 29
SB_JTAG_RST# F8
+3V T80 USB_OC0#/TRST#/GEVENT12#

R414 4.7K_4 SUS_STAT# R248 *10K/F_4


ACZ_BCLK M3 D25 SB_SCLK2
R431 8.2K_4 WLAN_CLKREQ# ACZ_SDOUT AZ_BITCLK SCL2/GPIO193 SB_SDATA2
16 ACZ_SDOUT N1 AZ_SDOUT SDA2/GPIO194 F23
R272 8.2K_4 LAN_CLKREQ# R392 *10K/F_4 ACZ_SDIN0 L2 B26 SB_SCLK3
T130

HD AUDIO
R394 *10K/F_4 ACZ_SDIN1 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195
HD audio M2 AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 E26 T132
interface is R393 *10K/F_4 ACZ_SDIN2_R M1 F25
R395 *10K/F_4 ACZ_SDIN3_R AZ_SDIN2/GPIO169 EC_PW M0/EC_TIMER0/GPIO197
M4 E22
To Azalia 3.3S5 voltage ACZ_SYNC
ACZ_RST#
N2
AZ_SDIN3/GPIO170
AZ_SYNC
EC_PW M1/EC_TIMER1/GPIO198
EC_PW M2/EC_TIMER2/GPIO199 F22 SB_GPIO199
SB_GPIO200
SB_GPIO199 16
ACZ_SDOUT R240 33_4
P2 AZ_RST# EC_PW M3/EC_TIMER3/GPIO200 E21 SB_GPIO200 16 SPI/LPC define
ACZ_SDOUT_AUDIO 27
KSI_0/GPIO201 G24
C461 *10P/50V_4 R398 10K/F_4 T1 G25
R390 10K/F_4 GBE_COL KSI_1/GPIO202
B
T4 GBE_CRS KSI_2/GPIO203 E28 B
L6 GBE_MDCK KSI_3/GPIO204 E29
ACZ_SYNC R244 33_4 +3VS5 R235 10K/F_4 L5 D29
ACZ_SYNC_AUDIO 27 GBE_MDIO KSI_4/GPIO205
T9 GBE_RXCLK KSI_5/GPIO206 D28
C467 *10P/50V_4 U1 C29
GBE_RXD3 KSI_6/GPIO207
U3 GBE_RXD2 KSI_7/GPIO208 C28
T2

GBE LAN
GBE_RXD1
BIT_CLK_AUDIO 27 U2 GBE_RXD0 KSO_0/GPIO209 B28

EMBEDDED CTRL
T5 GBE_RXCTL/RXDV KSO_1/GPIO210 A27
ACZ_BCLK R247 33_4 C463 27P/50V_4 R246 10K/F_4 V5 B27
GBE_RXERR KSO_2/GPIO211
P5 GBE_TXCLK KSO_3/GPIO212 D26
M5 GBE_TXD3 KSO_4/GPIO213 A26
ACZ_RST# R241 33_4 P9 C26
ACZ_RST#_AUDIO 27 GBE_TXD2 KSO_5/GPIO214
T7 GBE_TXD1 KSO_6/GPIO215 A24
P7 GBE_TXD0 KSO_7/GPIO216 B25
ACZ_SDIN0 ACZ_SDIN0 27 M7 A25
GBE_TXCTL/TXEN KSO_8/GPIO217
P4 GBE_PHY_PD KSO_9/GPIO218 D24
M9 GBE_PHY_RST# KSO_10/GPIO219 B24
EMI suggestion R257 10K/F_4 V7 C24
GBE_PHY_INTR KSO_11/GPIO220
KSO_12/GPIO221 B23
T103 E23 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222 A23
T131 E24 PS2_CLK/SCL4/GPIO188 EMBEDDED CTRL KSO_14/GPIO223 D22
F21 SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224 C22
T133 G29 FC_RST#/GPO160 KSO_16/GPIO225 A22
KSO_17/GPIO226 B22
D27 PS2KB_DAT/GPIO189
F28 PS2KB_CLK/GPIO190
F29 PS2M_DAT/GPIO191
E27 PS2M_CLK/GPIO192
A A
SB820M A12

PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
SB820-ACPI/GPIO/USB 2/4
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 13 of 43
5 4 3 2 1
5 4 3 2 1

14
SATA PORT 0,1,2,3 IF THERE IS NO IDE, TEST
can support AHCI PLACE SATA AC COUPLING POINTS FOR DEBUG BUS
mode CAPS CLOSE TO SB820 U28B IS MANDATORY
SIDE_PORT_ID2 SIDE_PORT_ID1 SIDE_PORT_ID0
C476 0.01U/16V_4 SATA_TXP0_C AH9
SB800 AH28
29 SATA_TXP0 SATA_TX0P FC_CLK
C479 0.01U/16V_4 SATA_TXN0_C AJ9 Part 2 of 5 AG28 1 0 0 Samsung
SATA1 29 SATA_TXN0 SATA_TX0N FC_FBCLKOUT
AF26
C468 0.01U/16V_4 SATA_RXN0_C FC_FBCLKIN
29 SATA_RXN0 AJ8 SATA_RX0N
C466 0.01U/16V_4 SATA_RXP0_C AH8 AF28
29 SATA_RXP0 SATA_RX0P FC_OE#/GPIOD145
FC_AVD#/GPIOD146 AG29 1 0 1 Hynix
C471 0.01U/16V_4 SATA_TXP1_C AH10 AG26
SATA ODD 31 SATA_TXP1
C473 0.01U/16V_4 SATA_TXN1_C AJ10
SATA_TX1P FC_W E#/GPIOD148
AF27
D 31 SATA_TXN1 SATA_TX1N FC_CE1#/GPIOD149 D
FC_CE2#/GPIOD150 AE29
C480 0.01U/16V_4 SATA_RXN1_C AG10 AF29 0 0 0 No support side port
31 SATA_RXN1 SATA_RX1N FC_INT1/GPIOD144
C481 0.01U/16V_4 SATA_RXP1_C AF10 AH27
31 SATA_RXP1 SATA_RX1P FC_INT2/GPIOD147
AG12 SATA_TX2P FC_ADQ0/GPIOD128 AJ27
PLVDD_SATA-- AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
SATA PLL FC_ADQ2/GPIOD130 AH25
POWER AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
AH23 +3VS5 R252 *10K/F_4 SIDE_PORT_ID0 R419 10K/F_4
FC_ADQ5/GPIOD133
AH14 SATA_TX3P FC_ADQ6/GPIOD134 AJ22 Side port ID H/W setting
XTLVDD_SATA-- SATA PLACE SATA_CAL AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21
crystal power AF21 +3VS5 R256 *10K/F_4 SIDE_PORT_ID1 R421 10K/F_4
RES VERY CLOSE AG14
FC_ADQ8/GPIOD136
AH22
SATA_RX3N FC_ADQ9/GPIOD137

FLASH
TO BALL OF SB820 AF14 SATA_RX3P FC_ADQ10/GPIOD138 AJ23
AF23 +3VS5 R255 *10K/F_4 SIDE_PORT_ID2 R253 10K/F_4
FC_ADQ11/GPIOD139
NOTE: AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
R361 IS 1K 1% FOR 25MHz FC_ADQ14/GPIOD142 AG25
AJ17 AH26 +3VS5 R422 *10K/F_4 BOARD_ID0 R254 10K/F_4
XTAL, 4.99K 1% FOR 100MHz SATA_RX4N FC_ADQ15/GPIOD143

SERIAL ATA
AH17 SATA_RX4P
INTERNAL CLOCK
AJ18 R259 *10K/F_4 BOARD_ID1 R264 10K/F_4
SATA_TX5P R237 *0_4/S
AH18 SATA_TX5N FANOUT0/GPIO52 W5 RF_OFF# 33
W6 R293 *0_4/S
FANOUT1/GPIO53 BT_OFF# 29
AH19 Y9 R405 *0_4 R426 *10K/F_4 BOARD_ID2 R266 10K/F_4
SATA_RX5N FANOUT2/GPIO54 BT_COMBO_EN# 33
AJ19 SATA_RX5P
W7 ODD_PWR
FANIN0/GPIO56
V9 SB_FANIN1
ODD_PWR 31 For Zero ODD R427 *10K/F_4 BOARD_ID3 R267 10K/F_4
FANIN1/GPIO57 T82
C R424 1K/F_4 SATA_CALRP AB14 W8 R407 *0_4/S LCD_BK 23 C
R423 931/F_4 SATA_CALRN SATA_CALRP FANIN2/GPIO58
+1.1V_AVDD_SATA AA14 SATA_CALRN
B6 TEMPIN0 R258 *10K/F_4 BOARD_ID4 R262 10K/F_4
TEMPIN0/GPIO171 T125
A6 TEMPIN1
TEMPIN1/GPIO172 T123
SB_SATA_LED# AD11 A5 MB_THRMDA_SB
SATA_ACT#/GPIO67 TEMPIN2/GPIO173 T124
TEMPIN3/TALERT#/GPIO174 B5 T67
+3V R428 10K/F_4 C7 TEMP_COMM
TEMP_COMM
A3 SIDE_PORT_ID0

HW MONITOR
VIN0/GPIO175 SIDE_PORT_ID1
T1 AD16 SATA_X1 VIN1/GPIO176 B4 ID4 ID3 ID2 ID1 ID0 CONFIG 31- Level BOM Item
A4 SIDE_PORT_ID2
VIN2/GPIO177 BOARD_ID0
VIN3/GPIO178 C5
A7 BOARD_ID1 0 0 0 0 0 UMA 1
VIN4/GPIO179 BOARD_ID2
VIN5/GPIO180 B7
B8 BOARD_ID3
VIN6/GBE_STAT3/GPIO181 BOARD_ID4
T2 AC16 SATA_X2 VIN7/GBE_LED3/GPIO182 A8 0 0 0 1 0 2

0 0 1 0 0 3
J5 SPI_DI/GPIO164 NC1 G27
E2 Y2 0 0 1 1 0 4
SPI ROM

SPI_DO/GPIO163 NC2
K4 SPI_CLK/GPIO162
K9 SPI_CS1#/GPIO165
ROM_RST# G2 0 1 0 1 0 5
T69 ROM_RST#/GPIO161

SB820M A12 0 1 1 1 0 6
+3V

B B
1 0 0 1 0 7
Item Board ID Hardware setting
C689 1 0 1 1 0 8
0.1U/10V_4
1
U26 0 0 0 0 1 SG / Muxless 9
5

TC7SH08FU
2 SB_SATA_LED# 2
33 SATA_LED# 4 0 0 1 0 1 10
1
3
1 0 0 1 1 11
3

4
1 0 1 1 1 12
5

+1.5VSUS 7
+1.5VSUS R172 *2.2K_4

R173 8
2

Q22 *2.2K_4
*MMBT3904
A 3 1 MEM_MA_EVENT# 6 9 A

R170 *2.2K_4
R171 10
*2.2K_4
2

Q21

13 MEM_GEVEN# 3 1
*MMBT3904
MEM_MB_EVENT# 7
11 PROJECT : R22
12
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
SB820-ACPI/GPIO/USB 2/4
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 14 of 43
5 4 3 2 1
5 4 3 2 1

+3.3V_SB_R

VDDQ--3.3V I/O power


PLACE ALL THE DECOUPLING CAPS ON
THIS SHEET CLOSE TO SB AS POSSIBLE.
U28C
Part 3 of 5
VDD-- S/B CORE power

+1.1V_VCC_SB_R
15
R236 *0_8/S
131mA SB800 510mA R265 *0_8/S U28E
+3V AH1 VDDIO_33_PCIGP_1 VDDCR_11_1 N13 +1.1V
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15
Y19 N17 SB800

CORE S0
C460 C472 C474 C497 VDDIO_33_PCIGP_3 VDDCR_11_3 C491 C490 C487 C484 C486
AE5 VDDIO_33_PCIGP_4 VDDCR_11_4 U13 Y14 VSSIO_SATA_1 VSS_1 AJ2
22U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 AC21 U17 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 Y16 A28
VDDIO_33_PCIGP_5 VDDCR_11_5 VSSIO_SATA_2 VSS_2
AA2 V12 AB16 A2

PCI/GPIO I/O
D VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_3 VSS_3 D
AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 AC14 VSSIO_SATA_4 VSS_4 E5
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W 12 CKVDD_1.1V-- AE12 VSSIO_SATA_5 VSS_5 D23
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W 18 Internal clock AE14 VSSIO_SATA_6 VSS_6 E25
AA9 +1.1V_CKVDD AF9 E6
VDDIO_33_PCIGP_10 Generator I/O VSSIO_SATA_7 VSS_7
AF7 VDDIO_33_PCIGP_11 TBDmA power BLM18PG181SN1D(180,1.5A)_6
AF11 VSSIO_SATA_8 VSS_8 F24
1.8V : FLASH MEMORY MODE(DEFAULT) AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 AF13 VSSIO_SATA_9 VSS_9 N15
VDD33_18--3.3V IDE I/O power K29 L48 +1.1V AF16 R13
3.3V: IDE MODE VDDAN_11_CLK_2 VSSIO_SATA_10 VSS_10
R288 *0_8/S
1.8V flash memory I/O power
VDDIO_18_FC
71mA VDDAN_11_CLK_3 J28 AG8 VSSIO_SATA_11 VSS_11 R17
K26 AH7 T10

CLKGEN I/O
VDDAN_11_CLK_4 C505 C507 C512 C498 C530 VSSIO_SATA_12 VSS_12
VDDAN_11_CLK_5 J21 AH11 VSSIO_SATA_13 VSS_13 P10
Delete Cap and change +1.8V to pull low from AF22 J20 1U/10V_4 1U/10V_4 0.1U/10V_4 0.1U/10V_4 22U/6.3V_8 AH13 V11

FLASH I/O
VDDIO_18_FC_1 VDDAN_11_CLK_6 VSSIO_SATA_14 VSS_14
AE25 K21 AH16 U15
AMD command , due to no IDE & flash mode AF24
VDDIO_18_FC_2 VDDAN_11_CLK_7
J22 AJ7
VSSIO_SATA_15 VSS_15
M18
VDDIO_18_FC_3 VDDAN_11_CLK_8 VSSIO_SATA_16 VSS_16
AC22 VDDIO_18_FC_4 AJ11 VSSIO_SATA_17 VSS_17 V19
AJ13 VSSIO_SATA_18 VSS_18 M11
VDDRF_GBE_S V1 AJ16 VSSIO_SATA_19 VSS_19 L12
L71 0_6 L18
+3V
POWER VDDIO_33_GBE_S M10 A9 VSSIO_USB_1
VSS_20
VSS_21 J7

C713 C708 VDDPL_3.3V_PCIE


43mA B10 VSSIO_USB_2 VSS_22 P3
AE28 K11 V4

GBE LAN
2.2U/6.3V_4 *0.1U/10V_4 VDDPL_33_PCIE VSSIO_USB_3 VSS_23
B9 VSSIO_USB_4 VSS_24 AD6
D10 AD4

PCI EXPRESS
+1.1V_PCIE_VDDR VSSIO_USB_5 VSS_25
U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 D12 VSSIO_USB_6 VSS_26 AB7
V22 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 L9 D14 VSSIO_USB_7 VSS_27 AC9
PCIE_VDDR--PCIE I/O power 600mA V26 VDDAN_11_PCIE_3 D17 VSSIO_USB_8 VSS_28 V8
+1.1V L72 0_6 V27 E9 W9
VDDAN_11_PCIE_4 VSSIO_USB_9 VSS_29
V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 F9 VSSIO_USB_10 VSS_30 W 10
V29 VDDAN_11_PCIE_6 VDDIO_GBE_S_2 P8 F12 VSSIO_USB_11 VSS_31 AJ28
C715 C717 C710 C516 C510 W 22 F14 B29
10U/6.3V_8 1U/10V_4 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 VDDAN_11_PCIE_7 VSSIO_USB_12 VSS_32
C W 26 VDDAN_11_PCIE_8 F16 VSSIO_USB_13 VSS_33 U4 C
C9 VSSIO_USB_14 VSS_34 Y18
S5_3.3--3.3v standby power G11 VSSIO_USB_15 VSS_35 Y10
+3VALW_R
93mA

GROUND
F18 VSSIO_USB_16 VSS_36 Y12
+3V L41 VDDPL_3.3V_SATA AD14 32mA D9 Y11
VDDPL_33_SATA R433 *0_6/S VSSIO_USB_17 VSS_37
VDDIO_33_S_1 A21 +3VS5 H12 VSSIO_USB_18 VSS_38 AA11
PBY160808T-221Y-N(220,2A) AJ20 D21 H14 AA12
C489 C488 VDDAN_11_SATA_1 VDDIO_33_S_2 VSSIO_USB_19 VSS_39
AF18 B21 H16 G4

SERIAL ATA
2.2U/6.3V_4 *0.1U/10V_4 VDDAN_11_SATA_4 VDDIO_33_S_3 C692 C696 C695 VSSIO_USB_20 VSS_40
AH20 K10 H18 J4

3.3V_S5 I/O
+1.1V_AVDD_SATA VDDAN_11_SATA_2 VDDIO_33_S_4 *0.1U/10V_4 2.2U/6.3V_6 2.2U/6.3V_6 VSSIO_USB_21 VSS_41
AG19 VDDAN_11_SATA_3 VDDIO_33_S_5 L10 J11 VSSIO_USB_22 VSS_42 G8
AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9 J19 VSSIO_USB_23 VSS_43 G9
AVDD_SATA--SATA phy power 567mA AD18 VDDAN_11_SATA_6 VDDIO_33_S_7 T6 K12 VSSIO_USB_24 VSS_44 M12
+1.1V L45 AE16 T8 K14 AF25
VDDAN_11_SATA_7 VDDIO_33_S_8 VSSIO_USB_25 VSS_45
K16 VSSIO_USB_26 VSS_46 H7
BLM18PG181SN1D(180,1.5A)_6 S5_1.1V--1.1V standby power K18 AH29
C514 C502 C504 C495 C494 VSSIO_USB_27 VSS_47
113mA H19 V10

CORE S5
22U/6.3V_8 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 VDDCR_1.1V R280 *0_6/S VSSIO_USB_28 VSS_48
VDDCR_11_S_1 F26 +1.1VS5 VSS_49 P6
A18 VDDAN_33_USB_S_1 VDDCR_11_S_2 G26 VSS_50 N4
A19 VDDAN_33_USB_S_2 TBDmA C506 C515
Y4 EFUSE VSS_51 L4
For support USB A20 VDDAN_33_USB_S_3 VDDIO_AZ_S M8 +3VS5 VSS_52 L8
AVDDTX--USB Phy +3V_AVDD_USB B18 1U/10V_4 1U/10V_4 D8
wakeup-->3V_S5 VDDAN_33_USB_S_4 VSSAN_HW M
Analog I/O power B19 A11 VDDCR_1.1V_USB
VDDAN_33_USB_S_5 VDDCR_11_USB_S_1
658mA B20 B11 M19 M20
USB I/O
L69 VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 VSSXL VSSPL_SYS
+3VS5 C18 VDDAN_33_USB_S_7
C20 197mA PBY160808T-221Y-N(220,2A)
PBY160808T-221Y-N(220,2A) VDDAN_33_USB_S_8 L68
C687 C690 C688 C686
D18 VDDAN_33_USB_S_9 VDDPL_33_SYS M21 +VDDPL_3.3V 47mA +1.1VS5 P21 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14 H23
D19 VDDAN_33_USB_S_10 P20 VSSIO_PCIECLK_2 VSSIO_PCIECLK_15 H26
10U/6.3V_8 10U/6.3V_8 1U/10V_4 1U/10V_4 D20 L22 +VDDPL_1.1V 62mA M22 AA21
VDDAN_33_USB_S_11 VDDPL_11_SYS_S C684 C682 C683 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16
E19 M24 AA23
PLL

VDDAN_33_USB_S_12 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 VSSIO_PCIECLK_4 VSSIO_PCIECLK_17


B VDDPL_33_USB_S F19 +3VS5 17mA M26 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AB23 B
P22 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19 AD23

L40 VDDAN_1.1V_USB
TBDmA C11 VDDAN_11_USB_S_1 VDDAN_33_HW M_S D6 +VDDAN_3.3VHWM 5mA P24 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 AA26
+1.1VS5 D11 VDDAN_11_USB_S_2 P26 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21 AC26
L20 VDDXL_3.3V T20 Y20
PBY160808T-221Y-N(220,2A) VDDXL_33_S PBY160808T-221Y-N(220,2A) VSSIO_PCIECLK_9 VSSIO_PCIECLK_22
C482 C483
32mA L43
T22 VSSIO_PCIECLK_10 VSSIO_PCIECLK_23 W 21
+3V T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W 20
2.2U/6.3V_4 0.1U/10V_4 SB820M A12 V20 AE26
VSSIO_PCIECLK_12 VSSIO_PCIECLK_25
J23 VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 L21
C500 C496 K20
*0.1U/10V_4 2.2U/6.3V_6 VSSIO_PCIECLK_27
Part 5 of 5
SB820M A12

+3V +VDDPL_3.3V +1.1V +VDDPL_1.1V


+3VS5 +3VS5

L47 L46
PBY160808T-221Y-N(220,2A) PBY160808T-221Y-N(220,2A)

C517 C503 C519 C511


2.2U/6.3V_6 *0.1U/10V_4 2.2U/6.3V_6 *0.1U/10V_4
C475 C679 C513
2.2U/6.3V_6 2.2U/6.3V_6 0.1U/10V_4 Close to pin F19

A +3VS5 +VDDAN_3.3VHWM A

Close to pin M8 L39 *0_6/S

C478
0.1U/10V_4
PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
SB820-PWR/DECOUPLING 4/4
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 15 of 43
5 4 3 2 1
5 4 3 2 1

OVERLAP COMMON PADS WHERE


POSSIBLE FOR DUAL-OP RESISTORS.
intermal have pull
Hi 10K , confirm AMD
ward this pull Hi
not need
16
REQUIRED STRAPS
It must ready
+3VS5
before RSMRST#
D D
+3VS5 +3V +3VS5 +3VS5
INT CLK GEN R276

10K/F_4
R402 R285
R410
R250 10K/F_4 10K/F_4 10K/F_4
*10K/F_4
13 SB_GPIO200
13 ACZ_SDOUT 12 PCI_CLK_TPM 12 PCI_CLK2 12 PCI_CLK3 12 PCI_CLK4 12 LPC_CLK0 12 LPC_CLK1 12,32 RTC_CLK 13 SB_GPIO199

R400 R401 R403 R289


R249
Use RTC CLK pin GPIO199 R275 R283 GPIO200
10K/F_4 10K/F_4 10K/F_4 10K/F_4 10K/F_4 need pull high *2.2K_4 2.2K_4

C C

AZ_SDOUT PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 GPIO200 GPIO199


REQUIRED
STRAPS PULL LOW POWER ALLOW Watchdog USE non_Fusion EC CLKGEN
MODE PCIE Gen2 Timer DEBUG CLOCK MODE ENABLED ENABLED H,H = Reserved
HIGH
DEFAULT Enabled STRAP DEFAULT DEFAULT
H,L = SPI ROM

PULL PERFORMANCE FORCE Watchdog IGNORE FUSION EC CLKGEN L,H = LPC ROM (Default)
LOW MODE PCIE Gen1 Timer DEBUG CLOCK MODE DISABLED DISABLED L,L = FWH ROM
Disabled STRAP
DEFAULT DEFAULT DEFAULT DEFAULT

NB_PWRGD_IN:
RS780/RX780 = 1.8V; RS740 = 3.3V
DEBUG STRAPS Do NOT share it with SB_PWRGD when use Internal Clk Gen
(Need SB PLL initialize firstly)
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
B B

+3VS5 R261 10K/F_4 R260 *0_4/S SB_PWRGD_IN


SB_PWRGD_IN 13

C459 NB/SB POWER GOOD CIRCUIT


*2.2U/6.3V_6 +1.8V

R234
300_4

2 RX780,RS780
36 VRM_PWRGD
3 NB_PWRGD_IN
NB_PWRGD_IN 10

5,20,32 ECPWROK 1

D24
BAT54A

R243 *0_4/S
WD_PWRGD 13

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

PULL USE PCI DISABLE ILA USE FC USE DEFAULT DISABLE PCI AL17SZ17000 IC(5P) NL17SZ17DFT2G(SOT-353) SOT-353
A HIGH PLL AUTORUN PLL PCIE STRAPS MEM BOOT ALUC1G17000 IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5) A
SOT23-5

DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

PULL BYPASS ENABLE ILA BYPASS FC USE EEPROM ENABLE PCI


LOW PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
SB820-STRAPS
NB5/RD2
Date: Wednesday, September 15, 2010Sheet 16 of 43
5 4 3 2 1
5 4 3 2 1

U21A

+1.8V_DPE_VDD18 AG15
U21G

DP E/F POWER

DPE_VDD18#1
DP A/B POWER

DPA_VDD18#1 AE11 +1.8V_DPA_VDD18


17
AG16 DPE_VDD18#2 DPA_VDD18#2 AF11

2.5GT/s bit rate


PEG_TX0 AF30 AH30 C_PEG_RXN0 C258 0.1U/10V_4 +1.0V_DPE_VDD10 AG20 AF6 +1.0V_DPB_VDD10
9 PEG_TX0 PCIE_RX0P PCIE_TX0P PEG_RX0 9 DPE_VDD10#1 DPA_VDD10#1
PEG_TX#0 AE31 AG31 C_PEG_RXP0 C253 0.1U/10V_4 AG21 AF7
9 PEG_TX#0 PCIE_RX0N PCIE_TX0N PEG_RX#0 9 DPE_VDD10#2 DPA_VDD10#2
D D
PEG_TX1 AE29 AG29 C_PEG_RXP1 C259 0.1U/10V_4 AG14 AE1
9 PEG_TX1 PEG_TX#1 PCIE_RX1P PCIE_TX1P C_PEG_RXN1 PEG_RX1 9 DPE_VSSR#1 DPA_VSSR#1
AD28 AF28 C269 0.1U/10V_4 AH14 AE3
9 PEG_TX#1 PCIE_RX1N PCIE_TX1N PEG_RX#1 9 DPE_VSSR#2 DPA_VSSR#2
AM14 DPE_VSSR#3 DPA_VSSR#3 AG1
AM16 DPE_VSSR#4 DPA_VSSR#4 AG6
PEG_TX#2 AD30 AF27 C_PEG_RXP2 C271 0.1U/10V_4 AM18 AH5
9 PEG_TX#2 PCIE_RX2P PCIE_TX2P PEG_RX2 9 DPE_VSSR#5 DPA_VSSR#5
PEG_TX2 AC31 AF26 C_PEG_RXN2 C285 0.1U/10V_4
9 PEG_TX2 PCIE_RX2N PCIE_TX2N PEG_RX#2 9
+1.0V_VGA
PEG_TX3 AC29 AD27 C_PEG_RXP3 C250 0.1U/10V_4 +1.8V_DPE_VDD18 AF16 AE13 +1.8V_DPA_VDD18
9 PEG_TX3 PCIE_RX3P PCIE_TX3P PEG_RX3 9 DPF_VDD18#1 DPB_VDD18#1
PEG_TX#3 AB28 AD26 C_PEG_RXN3 C239 0.1U/10V_4 AG17 AF13
9 PEG_TX#3 PCIE_RX3N PCIE_TX3N PEG_RX#3 9 DPF_VDD18#2 DPB_VDD18#2 1.0V(220mA)

PEG_TX4 AB30 AC25 C_PEG_RXP4 C297 0.1U/10V_4 +1.0V_DPB_VDD10 L59 0_6


9 PEG_TX4 PCIE_RX4P PCIE_TX4P PEG_RX4 9

PCI EXPRESS INTERFACE


PEG_TX#4 AA31 AB25 C_PEG_RXN4 C308 0.1U/10V_4 AF22 AF8
9 PEG_TX#4 PCIE_RX4N PCIE_TX4N PEG_RX#4 9 +1.0V_DPE_VDD10 DPF_VDD10#1 DPB_VDD10#1
AG22 DPF_VDD10#2 DPB_VDD10#2 AF9
C593 C591 C592
PEG_TX5 AA29 Y23 C_PEG_RXP5 C288 0.1U/10V_4 *0.1U/10V_4 *10U/6.3V_8 *1U/10V_4
9 PEG_TX5 PCIE_RX5P PCIE_TX5P PEG_RX5 9
PEG_TX#5 Y28 Y24 C_PEG_RXN5 C295 0.1U/10V_4 R327 0_4 AF23 AF10
9 PEG_TX#5 PCIE_RX5N PCIE_TX5N PEG_RX#5 9 DPF_VSSR#1 DPB_VSSR#1
AG23 DPF_VSSR#2 DPB_VSSR#2 AG9
AM20 DPF_VSSR#3 DPB_VSSR#3 AH8
PEG_TX6 C_PEG_RXP6 C311 0.1U/10V_4
9 PEG_TX6
PEG_TX#6
Y30
W 31
PCIE_RX6P PCIE_TX6P AB27
AB26 C_PEG_RXN6 C321 0.1U/10V_4
PEG_RX6 9 AM22
AM24
DPF_VSSR#4 DPB_VSSR#4 AM6
AM8
Use Muxless need power
9 PEG_TX#6 PCIE_RX6N PCIE_TX6N PEG_RX#6 9 DPF_VSSR#5 DPB_VSSR#5
but low loading
PEG_TX#7 W 29 Y27 C_PEG_RXP7 C327 0.1U/10V_4
9 PEG_TX#7 PCIE_RX7P PCIE_TX7P PEG_RX7 9
PEG_TX7 V28 Y26 C_PEG_RXN7 C335 0.1U/10V_4
9 PEG_TX7 PCIE_RX7N PCIE_TX7N PEG_RX#7 9
R82 150/F_4 AF17 AE10 R99 150/F_4
DPEF_CALR DPAB_CALR
C V30 PCIE_RX8P PCIE_TX8P W 24 C
U31 PCIE_RX8N PCIE_TX8N W 23
+1.8V_DPE_VDD18 AG18 DP PLL POWER AG8 +1.8V_DPA_VDD18
+1.8V_DPE_VDD18 DPE_PVDD DPA_PVDD +1.8V_DPA_VDD18
AF19 DPE_PVSS DPA_PVSS AG7
U29 PCIE_RX9P PCIE_TX9P V27
T28 PCIE_RX9N PCIE_TX9N U26
+1.8V_DPE_VDD18 AG19 AG10 +1.8V_DPA_VDD18
+1.8V_DPE_VDD18 DPF_PVDD DPB_PVDD +1.8V_DPA_VDD18
T30 PCIE_RX10P PCIE_TX10P U24 AF20 DPF_PVSS DPB_PVSS AG11
R31 PCIE_RX10N PCIE_TX10N U23

R29 T26 SEYMOUR-XT


PCIE_RX11P PCIE_TX11P
P28 PCIE_RX11N PCIE_TX11N T27

P30 PCIE_RX12P PCIE_TX12P T24


N31 PCIE_RX12N PCIE_TX12N T23

N29 PCIE_RX13P PCIE_TX13P P27 (Seymour-S3: LVDS mode 240mA@1.0V)


M28 PCIE_RX13N PCIE_TX13N P26 (Seymour-S3: DP mode 220mA@1.0V)
+1.0V_DPE_VDD10 +1.8V_DPA_VDD18 1.8V(300mA)
M30 P24 +1.0V_DPE_VDD10 L19 0_6 +1.8V_DPA_VDD18 L22 0_6
PCIE_RX14P PCIE_TX14P +1.0V_VGA +1.8V_VGA
L31 PCIE_RX14N PCIE_TX14N P23
C254 C279
C232 C203 C221 *0.1U/10V_4 *1U/10V_4 C251
L29 M27 *0.1U/10V_4 *1U/10V_4 *10U/6.3V_6 *10U/6.3V_8
PCIE_RX15P PCIE_TX15P
B
K30 PCIE_RX15N PCIE_TX15N N26 B

(Seymour-S3: LVDS mode 300mA@1.8V)


CLOCK
(Seymour-S3: DP mode 300mA@1.8V)
EXT_GFX_CLKP AK30
12 EXT_GFX_CLKP PCIE_REFCLKP
EXT_GFX_CLKN AK32 +1.8V_DPE_VDD18 L15 0_6
12 EXT_GFX_CLKN PCIE_REFCLKN +1.8V_VGA
C185 C174
C287
CALIBRATION *0.1U/10V_4 *1U/10V_4 *10U/6.3V_8
Y22 M72_PCIE_CALRP R337 1.27K/F_4
PCIE_CALRP
10K/F_4 R372 N10 AA22 M72_PCIE_CALRN R100 2K/F_4 +1.0V_VGA
PW RGOOD PCIE_CALRN

12 PCIE_RST# AL27 PERSTB

SEYMOUR-XT
100MHz (+/-300ppm) input frequency,
0-0.7V single-ended swing

Use Muxless need power DB to SI Change VGA power


but low loading
A A

PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
SEYMOUR-XT PCIE_Interface
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 17 of 43
5 4 3 2 1
5 4 3 2 1

MEM_ID[3:0]
0000
0001
0010
Vendor
Samsung- E die
Hynix- Vega die
Hynix- Vega die
Type
64*16-800MHZ
64*16-800MHZ
128*16-800MHZ
Vendor P/N
K4W1G1646E-HC12
H5TQ1G63DFR-12C
H5TQ2G63BFR-12C T18 AE9
U21B

M93-S3/M92-S2
DVCNTL_0/ DVPDATA_18
TXCAP_DPA3P
TXCAM_DPA3N
AF2
AF4
+1.8V_AVDD_Q

+1.8V_AVDD_Q
1.8V(70mA)
L20
+1.8V_VGA
+A2VDD

+A2VDD
3.3V(65mA)
L13 +3V_DELAY
18
0011 Samsung- C die 128*16-800MHZ K4W2G1646C-HC12 T55 L9
DVCNTL_1 / NC
0100 Micron 128*16-800MHZ MT41J128M16HA-125:D N9 AG3 PBY160808T-121Y-N(120,2.5A) BLM18PG181SN1D(180,1.5A)_6
T51 DVCNTL_2 / NC TX0P_DPA2P
0101 Reserved T21 AE8
DVDATA_12 / DVPDATA_16 DPA TX0M_DPA2N
AG5
0110 Hynix- Vega die 64*16-900MHZ H5TQ1G63DFR-11C AD9 C212 C233 C226 C186 C181 C168
T22 DVDATA_11 / DVPDATA_20
0111 Samsung- E die 64*16-900MHZ K4W1G1646E-HC11 AC10 AH3 0.1U/10V_4 1U/10V_4 10U/6.3V_6 0.1U/10V_4 1U/10V_4 10U/6.3V_8
T30 DVDATA_10 / DVPDATA_22 TX1P_DPA1P
1000 Samsung- G die 64*16-900MHZ K4W1G1646G-BC11 T23 AD7
DVDATA_9 / DVPDATA_12 TX1M_DPA1N
AH1
1001 Reserved T20 AC8
DVDATA_8 / DVPDATA_14
1010 Hynix- Vega die 128*16-900MHZ H5TQ2G63BFR-11C T25 AC7
DVDATA_7 / DVPCNTL_0 TX2P_DPA0P
AK3
1011 Samsung- C die 128*16-900MHZ K4W2G1646C-HC11 T33 AB9
DVDATA_6 / DVPDATA_8 TX2M_DPA0N
AK1
1100 Reserved T29 AB8
DVDATA_5 / DVPDATA_6 +VDDD1
D 1101 Reserved +VDDR4 T32 AB7
DVDATA_4 DVPDATA_4 TXCBP_DPB3P
AK5
+1.8V_A2VDD_Q D
1110 Reserved Memory ID TXCBM_DPB3N
AM3 1.8V(45mA VDD1DI)
1111 Reserved DVO 1.8V(2mA)
R341 *10K/F_4 MEM_ID3 AB4 AK6 +VDDD1 L54
DVDATA_3 / DVPDATA_19 TX3P_DPB2P +1.8V_VGA
R340 *10K/F_4 MEM_ID2 AB2 AM5 +1.8V_A2VDD_Q L18
DVDATA_2 / DVPDATA_21 TX3M_DPB2N +1.8V_VGA
R342 *10K/F_4 MEM_ID1 Y8 DPB PBY160808T-121Y-N(120,2.5A)
R110 *10K/F_4 MEM_ID0 DVDATA_1 / DVPDATA_2 *PBY160808T-121Y-N(120,2.5A)
Y7 AJ7
DVDATA_0 / DVPDATA_0 TX4P_DPB1P C572 C571 C576
AH6
TX4M_DPB1N C223 C294 C207 0.1U/10V_4 1U/10V_4 10U/6.3V_6
MEM_ID[3:0] 31 Level BOM H/W setting
PBY160808T-121Y-N(120,2.5A) 1.8V(150mA DPC_PVDD) AK8 *0.1U/10V_4 *1U/10V_4 *10U/6.3V_8
+1.8V_DPC_PVDD TX5P_DPB0P
0000 TBD TBD +1.8V_VGA TX5M_DPB0N
AL7
L60
0001 TBD TBD C600 C602 C603 M93-S3/M92-S2 Robson-- Install
10U/6.3V_8 1U/10V_4 0.1U/10V_4 W6 Seymour- NC
DPC_PVDD / DVPDATA_11
0010 TBD TBD V6
DPC_PVSS / GND M92-S2/M93-S3 BACO mode -- install
V4
DVPDATA_3/TXCCP_DPC3P
0011 TBD TBD DVPCNTL_2/TXCCM_DPC3N
U5
+1.8V_DPC_PVDD AC6
DPC_VDD18#1/DVPDAT10
0100 TBD TBD AC5
DPC_VDD18#2/DVPDAT23 DVPDATA_7 / TX0P_DPC2P
W3
V2
DVPDATA_1 / TX0M_DPC2N
Y4
DVPCNTL_MV1 / TX1P_DPC1P
AA5 W5
PBY160808T-121Y-N(120,2.5A) DPC_VDD10#1/DVPDAT15 DVPDATA_9 / TX1M_DPC1N
1.1V(110mA DPC_VDD10) AA6
DPC_VDD10#2/DVPDAT17
+1.0V_VGA +1.1V_DPC_VDD10 AA3
L23 DVPDATA_13 / TX2P_DPC0P
Y2
C282 C283 C284 DVPCNTL_1 / TX2M_DPC0N
10U/6.3V_8 1U/10V_4 0.1U/10V_4 U1 AA12
DPC_VSSR#1 / DVPCLK VDDR4 / DPCD_CALR
W1
DPC_VSSR#2 / DVPDAT5
U3
DPC_VSSR#3 / GND
Y6
DPC_VSSR#4 / GND
Access to SCL and SDA is mandatory AA1
DPC_VSSR#5/ DVPCNTL_MV0 DPC
on BACO designs for debug purposes

R350 *4.7K_4 R1
R347 *4.7K_4 SCL
+3V_DELAY R3
SDA I2C
C AM26 C
GENERAL PURPOSE I/O R
AK26
GPIO0 RB
19 GPIO0 U6
GPIO1 GPIO_0
19 GPIO1 U10 AL25
GPIO2 GPIO_1 G
19 GPIO2 T10 AJ25
G_SMBDAT GPIO_2 GB
32 G_SMBDAT U8
G_SMBCLK GPIO_3_SMBDATA
32 G_SMBCLK U7 AH24
GPIO5 GPIO_4_SMBCLK B
19 GPIO5 T9 AG25
GPIO_5_AC_BATT BB
T8
GPIO_6 DAC1
EXT_LVDS_BLON T7 AH26 R328 *10K/F_4
GPIO8 GPIO_7_BLON HSYNC R329 *10K/F_4
19 GPIO8 P10 AJ27
GPIO9 GPIO_8_ROMSO VSYNC
19 GPIO9 P4
+3V_DELAY GPIO10 GPIO_9_ROMSI
T52 P2
GPIO11 GPIO_10_ROMSCK R333 499/F_4
19 GPIO11 N6 AD22
R119 *10K/F_4 GPIO24_TRSTB R120 *10K/F_4 GPIO12 GPIO_11 RSET
19 GPIO12 N5
GPIO13 GPIO_12 +1.8V_AVDD_Q
19 GPIO13 N3 AG24 +1.8V_AVDD_Q
R122 *10K/F_4 GPIO25_TDI T36 HDMI_HP2 GPIO_13 AVDD
Y9 AE22
GFX_CORE_CNTRL0 GPIO_14_HPD2 AVSSQ
38 GFX_CORE_CNTRL0 N1
R355 *10K/F_4 GPIO27_TMS T56 OSC_SPREAD GPIO_15_PWRCNTL_0 +VDDD1
M4 AE23 +VDDD1
T114 VGA_ALERT GPIO_16_SSIN VDD1DI
R6 AD23
R357 *10K/F_4 GPIO28_TDO HPD3 GPIO_17_THERMAL_INT VSS1DI
T42 W10
TEMP_FAIL GPIO_18_HPD3
5 TEMP_FAIL M2
GPIO_19_CTF M92-S2/M93-S3
R354 *10K/F_4 GPIO26_TCK 38 GFX_CORE_CNTRL1 GFX_CORE_CNTRL1 P8 AM12
BB_EN GPIO_20_PWRCNTL_1 R2 / NC
T47 P7 AK12
GPIO22 GPIO_21_BB_EN R2B / NC
19 GPIO22 N8
GPIO_23_CLKREQb GPIO_22_ROMCSB
N7 AL11
GPIO_23_CLKREQB G2 / NC
AJ11
G2B / NC
R152 10K/F_4 GPIO22 AK10
GPIO24_TRSTB B2 / NC
T57 L6 AL9
GPIO25_TDI JTAG_TRSTB B2B / NC
GPIO22(ROMCS#) T53 L5
JTAG_TDI
GPIO26_TCK L3
PD without external VBIOS ROM T54
GPIO27_TMS JTAG_TCK
T58 L1 AH12
GPIO28_TDO JTAG_TMS C / NC
T59 K4
JTAG_TDO DAC2 Y / NC
AM10
TESTEN AF24 AJ9
R112 4.7K_4 G_SMBDAT TESTEN COMP / NC
+3V_DELAY
AB13 BACO MODE:AD19 & AE17
R109 4.7K_4 G_SMBCLK GENERICA DAC2_VSY
W8 AL13 DAC2_VSY 19 & AE20 need with power
B
GENERICC GENERICB H2SYNC DAC2_HSY B
19 GENERICC W9 AJ13 DAC2_HSY 19
GENERICC V2SYNC C581 27P/50V_4 EVGA-XTALI
W7
GENERICD
AD10
GENERICE_HPD4

1
AD19 R319 *0_4 +VDDD1 +VDDD1
VDD2DI / NC R108 *0_4 Y2 R332
R366 *10K/F_4 GPIO_23_CLKREQb
AC14
HPD1 VSS2DI / NC
AC19
27MHZ 10M_6
For Int Clk 27Mhz
+3V_DELAY +1.8V_VGA

2
1.8V+R6043(249R)=1.8V/3=0.6V AE20 R103 *0_4 +A2VDD
R86 499/F_4 A2VDD / NC C582 EVGA-XTALO
AE17 +1.8V_A2VDD_Q +1.8V_A2VDD_Q 27P/50V_4
R130 3K_4 GFX_CORE_CNTRL0 R94 249/F_4 +0.6V_M92_VREFG AC16 A2VDDQ / NC
VREFG
AE19
R132 3K_4 GFX_CORE_CNTRL1 A2VSSQ
Robson-- Install
1.8V(75mA DPLL_PVDD) C242 0.1U/10V_4 AG13 R84 *715/F_4 Seymour-- NC
L50 BLM18PG471SN1D(470,1000MA) R2SET / NC
Add a 3K ohm pull-down resistor +1.8V_VGA
to set the correct VDDC during C577 DDC/AUX
power up. C556 C573 AE6
10U/6.3V_8 1U/10V_4 0.1U/10V_4 PLL/CLOCK DDC1CLK
AE5
+1.8V_DPLL_PVDD DDC1DATA
AF14
DPLL_PVDD
AE14 AD2
DPLL_PVSS AUX1P
AD4
AUX1N
+1.0V_VGA L57 BLM18PG471SN1D(470,1000MA) +1.0V_DPLL_VDDC AD14 AC11
DPLL_VDDC DDC2CLK
AC13
C584 C585 C292 DDC2DATA
1.0V(125mA DPLL_VDDC)
10U/6.3V_8 1U/10V_4 0.1U/10V_4 EVGA-XTALI AM28 AD13
EVGA-XTALO XTALIN AUX2P
AK28 AD11
XTALOUT AUX2N
AC22
NC#2/XO_IN
AB22 AE16
+3V_DELAY NC#1/XO_IN2 DDCCLK_AUX5P
AD16
DDCDATA_AUX5N
PBY160808T-121Y-N(120,2.5A) 1.8V(20mA TSVDD) AC1
DDC6CLK
+1.8V_VGA T4 AC3
R336 L55 DPLUS THERMAL DDC6DATA
T2
DMINUS
*10K/F_4 AD20
C579 C586 C280 NC/DDCCLK_AUX3P
A AC20 A
NC/DDCDATA_AUX3N
R5
10U/6.3V_8 1U/10V_4 0.1U/10V_4 +1.8V_TSVDD TS_FDO
AD17
TESTEN TSVDD
AC17
TSVSS

R97
*10K/F_4
10K/F_4
EXT_LVDS_BLON R123 SEYMOUR-XT
PROJECT : R22
Seymour uninstall
Quanta Computer Inc.
to meet AF24 N/C
If no contact this pin to LVDS need pull low Size Document Number Rev
Custom 1A
SEYMOUR-XT Main
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 18 of 43
5 4 3 2 1
5 4 3 2 1

AA27
AB24
U21E

PCIE_VSS#1 GND#1 A3
A30
U21F

LVDS CONTROL AB11


19
PCIE_VSS#2 GND#2 VARY_BL RECOMMENDED SETTINGS
AB32 PCIE_VSS#3 GND#3 / EVDDQ#2 AA13 DIGON AB12
AC24 AA16 0= DO NOT INSTALL RESISTOR
AC26
PCIE_VSS#4 GND#4
AB10
CONFIGURATION STRAPS-- SEE EACH DATABOOK FOR STRAP DETAILS 1 = INSTALL 3K RESISTOR
PCIE_VSS#5 GND#5
AC27 AB15 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, X = DESIGN DEPENDANT
PCIE_VSS#6 GND#6 / EVDDQ#3
AD25 AB6 NA = NOT APPLICABLE
PCIE_VSS#7 GND#7 THEY MUST NOT CONFLICT DURING RESET
D
AD32 PCIE_VSS#8 GND#8 AC9 TXCLK_UP_DPF3P AH20 D
AE27 PCIE_VSS#9 GND#9 AD6 TXCLK_UN_DPF3N AJ19
AF32 PCIE_VSS#10 GND#10 AD8
AG27 AE7 AL21 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
PCIE_VSS#11 GND#11 TXOUT_U0P_DPF2P
AH32 PCIE_VSS#12 GND#12 AG12 TXOUT_U0N_DPF2N AK20
K28 PCIE_VSS#13 GND#13 AH10
K32 AH28 AH22 TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING
PCIE_VSS#14 GND#14 TXOUT_U1P_DPF1P
L27 PCIE_VSS#15 GND#15 B10 TXOUT_U1N_DPF1N AJ21 0
M32 B12 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED
PCIE_VSS#16 GND#16
N25 PCIE_VSS#17 GND#17 B14 TXOUT_U2P_DPF0P AL23 X
N27 PCIE_VSS#18 GND#18 B16 TXOUT_U2N_DPF0N AK22
P25 B18 RSVD GPIO2 RESERVED 0
PCIE_VSS#19 GND#19 RSVD GPIO8 RESERVED 0
P32 PCIE_VSS#20 GND#20 B20 TXOUT_U3P AK24
R27 PCIE_VSS#21 GND#21 B22 TXOUT_U3N AJ23
T25 PCIE_VSS#22 GND#22 B24
T32 B26 BIF_VGA DIS GPIO9 VGA ENABLED 0
PCIE_VSS#23 GND#23 LVTMDP
U25 PCIE_VSS#24 GND#24 B6
U27 PCIE_VSS#25 GND#25 B8
V32 C1 AL15 RSVD GPIO21 RESERVED 0
PCIE_VSS#26 GND#26 TXCLK_LP_DPE3P
W 25 PCIE_VSS#27 GND#27 C32 TXCLK_LN_DPE3N AK14
W 26 PCIE_VSS#28 GND#28 E28
W 27 F10 AH16 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 0
PCIE_VSS#29 GND#29 TXOUT_L0P_DPE2P
Y25 PCIE_VSS#30 GND#30 F12 TXOUT_L0N_DPE2N AJ15
Y32 PCIE_VSS#31 GND#31 F14
F16 AL17 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 0 0 1
GND#32 TXOUT_L1P_DPE1P
GND#33 F18 TXOUT_L1N_DPE1N AK16
GND#34 F2
F20 AH18 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS (Removed on Seymour/Whistler) 0
GND#35 TXOUT_L2P_DPE0P
M6 GND#56 GND#36 F22 TXOUT_L2N_DPE0N AJ17
N11 GND#57 GND#37 F24
C N12 F26 AL19 RSVD H2SYNC RESERVED 0 C
GND#58 GND#38 TXOUT_L3P
N13 GND#59 GND#39 F6 TXOUT_L3N AK18
N16 F8
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
AUD[1]
AUD[0]
HSYNC
VSYNC
SEE DATABOOK FOR DETAIL
SEE DATABOOK FOR DETAIL
0
0
P6 GND#63 GND#43 G31
P9 G8 SEYMOUR-XT
GND#64 GND#44 RSVD GENERICC RESERVED 0
R12 GND#65 GND#45 H14
R15 GND#66 GND#46 H17
R17 GND#67 GND#47 H2
R20 GND#68 GND#48 H20
T13 GND#69 GND#49 H6
T16 J27 +3V_DELAY
T18
GND#70
GND#71
GND#50
GND#51 J31 NOTE1: AMD RESERVED CONFIGURATION STRAPS
T21 GND#72 GND#52 K11
T6 GND#73 GND#53 K2
GPIO9 R349 *10K/F_4
ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED,
U15 GND#74 GND#54 K22 18 GPIO9
U17 K6 THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET.
GND#75 GND#55 GPIO13 R351 *10K/F_4
U20 GND#76 GND#85 T11 18 GPIO13
U9 GND#77 GND#86 R11
V13 GPIO12 R371 *10K/F_4 GPIO21 H2SYNC GENERICC GPIO8 GPIO2
GND#78 18 GPIO12
V16 GND#79
V18 GPIO11 R370 10K/F_4
GND#80 18 GPIO11
Y10 GND#81
Y15 GND#82
Y17 GND#83 VSS_MECH#1 A32
Y20 GND#84 VSS_MECH#2 AM1
VSS_MECH#3 AM32
For Robson &
B B
Seymour should
SEYMOUR-XT
be NC
+3V_DELAY

Power Up/Down Sequence Memory Aperture size


GPIO0 R343 *10K/F_4
GPIO9 GPIO13 GPIO12 GPIO11 18 GPIO0
GPIO1 R114 *10K/F_4
18 GPIO1
BIOSROM ROMIDCFG2 ROMIDCFG1 ROMIDCFG0 GPIO2 R345 *10K/F_4
18 GPIO2
0 128M 0 0 0 18 GPIO8 GPIO8 R344 *10K/F_4

+VGA_CORE VDDC R115 *10K/F_4


0 256M 0 0 1 18 GENERICC
R325 *10K/F_4
18 DAC2_VSY
0 64M 0 1 0 18 DAC2_HSY
R326 *10K/F_4
+VGA_CORE VDDCI GPIO22 R153 *10K/F_4
0 32M 0 1 1 18 GPIO22
GPIO5 R362 10K/F_4
18 GPIO5

+1.5V_VGA VDDR1 0 512M 1 0 0


A 0 1G 1 0 1 A

+3.3V_Delay VDDR3
0 2G 1 1 0
+1.8V_VGA VDDR4 0 4G 1 1 1 PROJECT : R22
+1.8V_VGA VDD_CT
It is a shared pin strap with CONFIG[2:0] if BIOS_ROM_EN is set to 0.
Quanta Computer Inc.
20ms 20ms Size Document Number Rev
Custom 1A
SEYMOUR-XT GND / LVDS/ Straps
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 19 of 43
5 4 3 2 1
5 4 3 2 1

1.5V ( DDR3, MVDDQ = 1.5V@2.0A)


U21D

MEM I/O
PCIE
PCIE_VDDR--PCI-E I/O power. 1.8 V ± 5%

+1.8V_PCIE_VDDR

1.8V(500mA)
20
PBY160808T-221Y-N(220,2A)
+1.5V_VGA
H13 AB23 +1.8V_PCIE_VDDR L21
VDDR1#1 PCIE_VDDR#1 +1.8V_VGA
H16 VDDR1#2 PCIE_VDDR#2 AC23
H19 VDDR1#3 PCIE_VDDR#3 AD24
C432 C373 C365 C372 C368 C374 J10 AE24 C313 C286 C237 C216 C227 C301 C217 C240
2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 VDDR1#4 PCIE_VDDR#4 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_6
J23 VDDR1#5 PCIE_VDDR#5 AE25
D
J24 VDDR1#6 PCIE_VDDR#6 AE26 D
J9 VDDR1#7 PCIE_VDDR#7 AF25
K10 VDDR1#8 PCIE_VDDR#8 AG26
K23 VDDR1#9
K24 +1.0V_VGA
VDDR1#10
K9 VDDR1#11 PCIE_VDDC#1 L23
C669 C653 C433 C438 C443 C380 C369 C375 C430 L11 L24 +1.0V_PCIE_VDDC
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDR1#12 PCIE_VDDC#2
10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S L12 VDDR1#13 PCIE_VDDC#3 L25 1.0V(2.0A)
L13 L26 +1.0V_PCIE_VDDC L11 0_8
VDDR1#14 PCIE_VDDC#4
L20 VDDR1#15 PCIE_VDDC#5 M22
L21 VDDR1#16 PCIE_VDDC#6 N22
L22 N23 C353 C346 C339 C349 C332 C367 C324 C135
+1.8V_VDD_CT VDDR1#17 PCIE_VDDC#7 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_6
1.8V(110mA VDD_CT) PCIE_VDDC#8 N24
PCIE_VDDC#9 R22
L17 PBY160808T-121Y-N(120,2.5A) +1.8V_VDD_CT T22
+1.8V_VGA LEVEL PCIE_VDDC#10
PCIE_VDDC#11 U22
TRANSLATION V22
C200 C210 C312 C224 C325 PCIE_VDDC#12 +VGA_CORE
Gated 3.3V AA20 VDD_CT#1 VDDC+VDDCI
60mA by L12 0_6 10U/6.3V_6 1U/10V_4 1U/10V_4 1U/10V_4 0.1U/10V_4 AA21 0.85~1.1V(15A peak )( Ripple < 87.2mV)
VDD_CT#2
VDDC AB20 VDD_CT#3 VDDC#1 AA15
+3V_DELAY AB21 CORE N15
VDD_CT#4 VDDC#2
VDDC#3 N17
+3V_VGA 1 3 +3V_DELAY M93-S3/M92-S2 R13 C162 C163 C352 C343 C112 C340 C344 C165
VDDC#4

POWER
R16 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_6
VDDC#5
VDD_R3 --IO power for AA17 VDDR3#1 VDDC#6 R18
3.3 V pins (e.g. R64 Q10 *AO3409 C298 C302 C316 C291 AA18 I/O Y21
2

*100K/F_4 1U/10V_4 1U/10V_4 1U/10V_4 VDDR3#2 VDDC#7


GPIO’s). 3.3 V ± 5% 10U/6.3V_6 AB17 T12
VDDR3#3 VDDC#8
AB18 VDDR3#4 VDDC#9 T15
VDDC#10 T17
V12 VDDR4#1 / VDDR5 VDDC#11 T20
C Y12 U13 C160 C347 C159 C355 C161 C330 C333 C
+VDDR4 VDDR4#2 VDDC#12 1U/10V_4 2.2U/6.3V_4 1U/10V_4 10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4
U12 VDDR4#3 / VDDR5 VDDC#13 U16
VDDC#14 U18
D12 *CH501H-40PT L-F +1.8V_VGA L61 +VDDR4 AA11 V21
Q9 NC#1 / VDDR4 VDDC#15
1 2 T35 Y11 DVCLK / VDDR4 VDDC#16 V15
3

*2N7002E PBY160808T-121Y-N(120,2.5A) C299 C300 C323 V17


10U/6.3V_6 1U/10V_4 0.1U/10V_4 VDDC#17
1.8V(170mA VDDR4) V11 NC#3 / VDDR5 VDDC#18 V20
U11 NC / VDDR5 VDDC#20 Y13
32,37,38 VGACOREON R60 *47K_4 2 Y16 C334 C341 C342 C119 C124 C320
VDDC#21 1U/10V_4 2.2U/6.3V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4
VDDC#22 Y18
VDDC#23 /BIF_VDDC R21
VDDC#19/BIF_VDDC U21
MEM CLK
1

L17 VDDRHA
C122 For Seymour,PCIE_PVDD is PCIE_VDDR
ISOLATED
+3V_DELAY circuit *1U/10V_4 1.8V(40mA PCIE_PVDD)
L16 VSSRHA CORE I/O C108 C117 C106 C166 C123 C109
M13 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
PLL VDDCI#1
VDDCI#2 M15
:Change Power to
DB to SI: +1.8V_PCIE_VDDR AM30 PCIE_PVDD VDDCI#3 M16
+1.8V_PCIE_VDDR AMD Required VDDCI#4 M17
VDDCI#5 M18 Note1.
MPV18 L8 M20
MPV18 VDDCI#6
VDDCI#7 M21 Ra
1.8V(75mA MPV18) N20 BIF_VDDC
VDDCI#8 +VGA_CORE
1.0V_VGA(100mA SPV10) SPV18 H7 R85 *0_4
L67 BLM18PG471SN1D(470,1000MA) MPV18 SPV18
+1.8V_VGA
L26 BLM18PG471SN1D(470,1000MA) +1.0V_VGA_SPV10 H8
+1.0V_VGA SPV10
C633 C634 J7
B
1U/10V_4 0.1U/10V_4 C358 C377 C371 SPVSS B
0.95V~1.1V(2A VDDCI)
10U/6.3V_6 0.1U/10V_4 1U/10V_4 +VDDCI L62 0_8
+VGA_CORE
BACK BIAS
1.8V(90mA SPV18) M11 C363 C361 C354 C337 C611 C338
BBP#1 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
M12 BBP#2
L25 PBY160808T-121Y-N(120,2.5A) SPV18
+1.8V_VGA

C351 C356 SEYMOUR-XT


1U/10V_4 0.1U/10V_4

Support BACO Mode PX_MODE PX_MODE1


SI:change BACO circuit for AMD recommand +5V
+5V
Q19 Q18
R465 *0_4 AO3416 AO3416
+3V +3V R76
R75 1K_4 +1.0V_VGA 1 3 3 1
37 PX_MODE1
1K_4
3

R68 R121 PX_EN## BIF_VDDC


*10K_4 PX_EN#

2
100K/F_4 PX_EN# BIF_VDDC
Q15
3

3
PX_EN 2 Q40 Q16
2N7002 Q20 AO3416 AO3416 C188 C183 C175 C189 C173
38 PX_MODE
2 2N7002 2 Q13 2 Q14 1 3 3 1 10U/6.3VS_6 2.2U/6.3V_4
+VGA_CORE
3

A 2N7002 2N7002 22U/6.3VS_8 10U/6.3VS_6 2.2U/6.3V_4 A


1

2N7002 Q11 +3V


C187

2
3

PX_EN 2 PX_EN##
1

Q28
5

R78 0.1U/10V_4
5,16,32 ECPWROK 2 12,32,37,38 VGA_PWROK 2
4 BACO_EN PROJECT : R22
1

5.1K/F_4 2N7002 PX_MODE 1 Quanta Computer Inc.


U7
1

TC7SH08FU Size Document Number Rev


Custom 1A
SEYMOUR-XT_Power_and_NC
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 20 of 43
5 4 3 2 1
5 4 3 2 1

22
22

22
VMA_ODT0
VMA_ODT1

VMA_RAS0#
VMA_ODT0
VMA_ODT1

VMA_RAS0#
VMA_RAS1#
VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
K27
J29
H30
H32
U21C

DQA_0
DQA_1
DQA_2
MAA_0
MAA_1
MAA_2
K17
J20
H23
G23
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
21
22 VMA_RAS1# DQA_3 MAA_3
VMA_DQ4 G29 G24 VMA_MA4
VMA_CAS0# VMA_DQ5 DQA_4 MAA_4 VMA_MA5
22 VMA_CAS0# F28 DQA_5 MAA_5 H24
22 VMA_CAS1# VMA_CAS1# VMA_DQ6 F32 J19 VMA_MA6
VMA_DQ7 DQA_6 MAA_6 VMA_MA7

MEMORY INTERFACE
F30 DQA_7 MAA_7 K19
22 VMA_WE0# VMA_WE0# VMA_DQ8 C30 J14 VMA_MA8
VMA_WE1# VMA_DQ9 DQA_8 MAA_8 VMA_MA9
D 22 VMA_WE1# F27 DQA_9 MAA_9 K14 D
VMA_DQ10 A28 J11 VMA_MA10
VMA_CS0# VMA_DQ11 DQA_10 MAA_10 VMA_MA11
22 VMA_CS0# C28 DQA_11 MAA_11 J13
VMA_DQ12 E27 H11 VMA_MA12
VMA_CS1# VMA_DQ13 DQA_12 MAA_12 VMA_BA2
22 VMA_CS1# G26 DQA_13 MAA_13/BA2 G11
VMA_DQ14 D26 J16 VMA_BA0
VMA_CKE0 VMA_DQ15 DQA_14 MAA_14/BA0 VMA_BA1
22 VMA_CKE0 F25 DQA_15 MAA_15/BA1 L15
22 VMA_CKE1 VMA_CKE1 VMA_DQ16 A25
VMA_DQ17 DQA_16 VMA_DM0
C25 DQA_17 DQMA_0 E32
22 VMA_CLK0 VMA_CLK0 VMA_DQ18 E25 E30 VMA_DM1
VMA_CLK0# VMA_DQ19 DQA_18 DQMA_1 VMA_DM2
22 VMA_CLK0# D24 DQA_19 DQMA_2 A21
VMA_DQ20 E23 C21 VMA_DM3
VMA_CLK1 VMA_DQ21 DQA_20 DQMA_3 VMA_DM4
22 VMA_CLK1 F23 DQA_21 DQMA_4 E13
22 VMA_CLK1# VMA_CLK1# VMA_DQ22 D22 D12 VMA_DM5
VMA_DQ23 DQA_22 DQMA_5 VMA_DM6
F21 DQA_23 DQMA_6 E3
VMA_WDQS[7..0] VMA_DQ24 E21 F4 VMA_DM7
22 VMA_WDQS[7..0] DQA_24 DQMA_7
VMA_DQ25 D20
VMA_RDQS[7..0] VMA_DQ26 DQA_25 VMA_RDQS0
22 VMA_RDQS[7..0] F19 DQA_26 RDQSA_0 H28
VMA_DQ27 A19 C27 VMA_RDQS1
VMA_DM[7..0] VMA_DQ28 DQA_27 RDQSA_1 VMA_RDQS2
22 VMA_DM[7..0] D18 DQA_28 RDQSA_2 A23
VMA_DQ29 F17 E19 VMA_RDQS3
VMA_DQ[63..0] VMA_DQ30 DQA_29 RDQSA_3 VMA_RDQS4
22 VMA_DQ[63..0] A17 DQA_30 RDQSA_4 E15
VMA_DQ31 C17 D10 VMA_RDQS5

From GPU
VMA_MA[13..0] VMA_DQ32 DQA_31 RDQSA_5 VMA_RDQS6
22 VMA_MA[13..0] E17 DQA_32 RDQSA_6 D6
VMA_DQ33 D16 G5 VMA_RDQS7
VMA_DQ34 DQA_33 RDQSA_7 25mm (max) 5mm (max) 25mm (max)
F15 DQA_34
22 VMA_BA0 VMA_BA0 VMA_DQ35 A15 H27 VMA_WDQS0
VMA_BA1 VMA_DQ36 DQA_35 W DQSA_0 VMA_WDQS1
22 VMA_BA1 D14 DQA_36 W DQSA_1 A27
VMA_BA2 VMA_DQ37 F13 C23 VMA_WDQS2 DRAM_RST R208 10_4 DRAM_RST_M
22 VMA_BA2 DQA_37 W DQSA_2 DRAM_RST_M 22
VMA_DQ38 A13 C19 VMA_WDQS3 R220 51/F_4
VMA_DQ39 DQA_38 W DQSA_3 VMA_WDQS4
C C13 DQA_39 W DQSA_4 C15 C
support 1Gbit VMA_DQ40 E11 E9 VMA_WDQS5
VMA_DQ41 DQA_40 W DQSA_5 VMA_WDQS6 R213 C427
VRAM ( 64M X 16 ) A11 DQA_41 W DQSA_6 C5
VMA_DQ42 C11 H4 VMA_WDQS7
VMA_DQ43 DQA_42 W DQSA_7 5.1K/F_4 120P/50V_4
F11 DQA_43
VMA_DQ44 A9 L18 VMA_ODT0
VMA_DQ45 DQA_44 ODTA0 VMA_ODT1
C9 DQA_45 ODTA1 K16
VMA_DQ46 F9
VMA_DQ47 DQA_46 VMA_CLK0
D8 DQA_47 CLKA0 H26
VMA_DQ48 E7 H25 VMA_CLK0#
VMA_DQ49 DQA_48 CLKA0B
VMA_DQ50
A7
C7
DQA_49
G9 VMA_CLK1
DB to SI:R213 & C427 exchange
VMA_DQ51 DQA_50 CLKA1 VMA_CLK1#
F7 DQA_51 CLKA1B H9 Place all these components very close to GPU (Within
VMA_DQ52 A5
VMA_DQ53 E5
DQA_52
G22 VMA_RAS0# 25mm) and keep all component close to each Other (within
DQA_53 RASA0B
VMA_DQ54 C3 DQA_54 RASA1B G17 VMA_RAS1# 5mm) except Rser2
VMA_DQ55 E1
VMA_DQ56 DQA_55 VMA_CAS0# This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
G7 DQA_56 CASA0B G19
+1.5V_VGA VMA_DQ57 G6 G16 VMA_CAS1# Capacitors and Resistor values are an example only. The Series R and
VMA_DQ58 DQA_57 CASA1B
G1 DQA_58 || Cap values will depend on the DRAM load and will have to be
VMA_DQ59 G3 H22 VMA_CS0#
VMA_DQ60 DQA_59 CSA0B_0 calculated for different Memory ,DRAM Load and board to pass Reset
J6 DQA_60 CSA0B_1 J22
R217 VMA_DQ61 J1
Signal Spec.
VMA_DQ62 DQA_61 VMA_CS1#
J3 DQA_62 CSA1B_0 G13
40.2/F_4 VMA_DQ63 J5 K13
DQA_63 CSA1B_1
MVREFD K26 K20 VMA_CKE0
MVREFDA CKEA0 VMA_CKE1
J26 MVREFSA CKEA1 J17
+1.5V_VGA +1.5V_VGA
R378 243/F_4 J25 G25 VMA_WE0#
B
C429 R212 R161 5.1K/F_4 MEM_CALRN0 W EA0B VMA_WE1# B
K7 NC/TESTEN#2 W EA1B H10

0.1U/10V_4 100/F_4 R228 R126 150/F_4 J8 AB16 PX_EN 20


MEM_CALRP1/DPC_CALR PX_EN
K25 MEM_CALRP0 RSVD#2 G14
40.2/F_4 R377 243/F_4 G20 VMA_MA13
DRAM_RST L10 RSVD#3
MVREFS DRAM_RST
CLKTESTA K8
CLKTESTB CLKTESTA
L7 CLKTESTB
C439 R222
SEYMOUR-XT
0.1U/10V_4 100/F_4
C618 C616
*0.1U/10V_4 *0.1U/10V_4

R353 R352
*51.1/F_4 *51.1/F_4
Can remove it when MP from
AMD review reply

route 50ohms
single-ended/100ohms diff
and keep short
A A
For PARK-S3 only

PROJECT : R22
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
SEYMOUR-XT MEM_Interface
NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 21 of 43
5 4 3 2 1
5 4 3 2 1

VMA_MA[13..0]

22
21 VMA_MA[13..0]
512MB DDR3
21 VMA_DQ[63..0]
21 VMA_DM[7..0] 21 VMA_WDQS[7..0]
21 VMA_RDQS[7..0]
U14 U24 U13 U23

VREFC_VMA1 M9 E4 VMA_DQ20 VREFC_VMA2 M9 E4 VMA_DQ27 VREFC_VMA3 M9 E4 VMA_DQ38 VREFC_VMA4 M9 E4 VMA_DQ48


VREFD_VMA1 VREFCA DQL0 VMA_DQ18 VREFD_VMA2 VREFCA DQL0 VMA_DQ31 VREFD_VMA3 VREFCA DQL0 VMA_DQ32 VREFD_VMA4 VREFCA DQL0 VMA_DQ52
H2 F8 H2 F8 H2 F8 H2 F8
VREFDQ DQL1 VMA_DQ22 VREFDQ DQL1 VMA_DQ25 VREFDQ DQL1 VMA_DQ36 VREFDQ DQL1 VMA_DQ53
DQL2 F3 DQL2 F3 DQL2 F3 DQL2 F3
VMA_MA0 N4 F9 VMA_DQ17 VMA_MA0 N4 F9 VMA_DQ29 VMA_MA0 N4 F9 VMA_DQ34 VMA_MA0 N4 F9 VMA_DQ54
VMA_MA1 A0 DQL3 VMA_DQ23 VMA_MA1 A0 DQL3 VMA_DQ30 VMA_MA1 A0 DQL3 VMA_DQ39 VMA_MA1 A0 DQL3 VMA_DQ49
P8 H4 P8 H4 P8 H4 P8 H4
VMA_MA2 A1 DQL4 VMA_DQ16 VMA_MA2 A1 DQL4 VMA_DQ28 VMA_MA2 A1 DQL4 VMA_DQ33 VMA_MA2 A1 DQL4 VMA_DQ51
P4 H9 P4 H9 P4 H9 P4 H9
VMA_MA3 A2 DQL5 VMA_DQ21 VMA_MA3 A2 DQL5 VMA_DQ24 VMA_MA3 A2 DQL5 VMA_DQ37 VMA_MA3 A2 DQL5 VMA_DQ50
N3 A3 DQL6 G3 N3 A3 DQL6 G3 N3 A3 DQL6 G3 N3 A3 DQL6 G3
VMA_MA4 P9 H8 VMA_DQ19 VMA_MA4 P9 H8 VMA_DQ26 VMA_MA4 P9 H8 VMA_DQ35 VMA_MA4 P9 H8 VMA_DQ55
VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7
P3 A5 P3 A5 P3 A5 P3 A5
D VMA_MA6 VMA_MA6 VMA_MA6 VMA_MA6 D
R9 A6 R9 A6 R9 A6 R9 A6
VMA_MA7 R3 D8 VMA_DQ0 VMA_MA7 R3 D8 VMA_DQ15 VMA_MA7 R3 D8 VMA_DQ43 VMA_MA7 R3 D8 VMA_DQ60
VMA_MA8 A7 DQU0 VMA_DQ5 VMA_MA8 A7 DQU0 VMA_DQ10 VMA_MA8 A7 DQU0 VMA_DQ44 VMA_MA8 A7 DQU0 VMA_DQ58
T9 A8 DQU1 C4 T9 A8 DQU1 C4 T9 A8 DQU1 C4 T9 A8 DQU1 C4
VMA_MA9 R4 C9 VMA_DQ1 VMA_MA9 R4 C9 VMA_DQ13 VMA_MA9 R4 C9 VMA_DQ40 VMA_MA9 R4 C9 VMA_DQ63
VMA_MA10 A9 DQU2 VMA_DQ4 VMA_MA10 A9 DQU2 VMA_DQ9 VMA_MA10 A9 DQU2 VMA_DQ47 VMA_MA10 A9 DQU2 VMA_DQ56
L8 C3 L8 C3 L8 C3 L8 C3
VMA_MA11 A10/AP DQU3 VMA_DQ2 VMA_MA11 A10/AP DQU3 VMA_DQ12 VMA_MA11 A10/AP DQU3 VMA_DQ42 VMA_MA11 A10/AP DQU3 VMA_DQ61
R8 A11 DQU4 A8 R8 A11 DQU4 A8 R8 A11 DQU4 A8 R8 A11 DQU4 A8
VMA_MA12 N8 A3 VMA_DQ7 VMA_MA12 N8 A3 VMA_DQ8 VMA_MA12 N8 A3 VMA_DQ45 VMA_MA12 N8 A3 VMA_DQ57
VMA_MA13 A12/BC DQU5 VMA_DQ3 VMA_MA13 A12/BC DQU5 VMA_DQ14 VMA_MA13 A12/BC DQU5 VMA_DQ41 VMA_MA13 A12/BC DQU5 VMA_DQ62
T4 A13 DQU6 B9 T4 A13 DQU6 B9 T4 A13 DQU6 B9 T4 A13 DQU6 B9
T8 A4 VMA_DQ6 T8 A4 VMA_DQ11 T8 A4 VMA_DQ46 T8 A4 VMA_DQ59
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 M8 M8 M8
A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA

M3 B3 VMA_BA0 M3 B3 VMA_BA0 M3 B3 VMA_BA0 M3 B3


21 VMA_BA0 BA0 VDD#B3 BA0 VDD#B3 BA0 VDD#B3 BA0 VDD#B3
N9 D10 VMA_BA1 N9 D10 VMA_BA1 N9 D10 VMA_BA1 N9 D10
21 VMA_BA1 BA1 VDD#D10 VMA_BA2 BA1 VDD#D10 VMA_BA2 BA1 VDD#D10 VMA_BA2 BA1 VDD#D10
21 VMA_BA2 M4 G8 M4 G8 M4 G8 M4 G8
BA2 VDD#G8 BA2 VDD#G8 BA2 VDD#G8 BA2 VDD#G8
K3 K3 K3 K3
VDD#K3 VDD#K3 VDD#K3 VDD#K3
VDD#K9 K9 VDD#K9 K9 VDD#K9 K9 VDD#K9 K9
N2 N2 N2 N2
VDD#N2 VMA_CLK0 VDD#N2 VDD#N2 VMA_CLK1 VDD#N2
21 VMA_CLK0 J8 CK VDD#N10 N10 J8 CK VDD#N10 N10 21 VMA_CLK1 J8 CK VDD#N10 N10 J8 CK VDD#N10 N10
K8 R2 VMA_CLK0# K8 R2 K8 R2 VMA_CLK1# K8 R2
21 VMA_CLK0# CK VDD#R2 CK VDD#R2 21 VMA_CLK1# CK VDD#R2 CK VDD#R2
K10 R10 VMA_CKE0 K10 R10 K10 R10 VMA_CKE1 K10 R10
21 VMA_CKE0 CKE/CKE0 VDD#R10 +1.5V_VGA CKE/CKE0 VDD#R10 +1.5V_VGA 21 VMA_CKE1 CKE/CKE0 VDD#R10 +1.5V_VGA CKE/CKE0 VDD#R10 +1.5V_VGA

K2 A2 VMA_ODT0 K2 A2 K2 A2 VMA_ODT1 K2 A2
21 VMA_ODT0 ODT/ODT0 VDDQ#A2 VMA_CS0# ODT/ODT0 VDDQ#A2 21 VMA_ODT1 ODT/ODT0 VDDQ#A2 VMA_CS1# ODT/ODT0 VDDQ#A2
21 VMA_CS0# L3 A9 L3 A9 21 VMA_CS1# L3 A9 L3 A9
CS /CS0 VDDQ#A9 VMA_RAS0# CS /CS0 VDDQ#A9 CS /CS0 VDDQ#A9 VMA_RAS1# CS /CS0 VDDQ#A9
21 VMA_RAS0# J4 RAS VDDQ#C2 C2 J4 RAS VDDQ#C2 C2 21 VMA_RAS1# J4 RAS VDDQ#C2 C2 J4 RAS VDDQ#C2 C2
K4 C10 VMA_CAS0# K4 C10 K4 C10 VMA_CAS1# K4 C10
21 VMA_CAS0# CAS VDDQ#C10 VMA_WE0# CAS VDDQ#C10 21 VMA_CAS1# CAS VDDQ#C10 VMA_WE1# CAS VDDQ#C10
21 VMA_WE0# L4 D3 L4 D3 21 VMA_WE1# L4 D3 L4 D3
WE VDDQ#D3 WE VDDQ#D3 WE VDDQ#D3 WE VDDQ#D3
VDDQ#E10 E10 VDDQ#E10 E10 VDDQ#E10 E10 VDDQ#E10 E10
VDDQ#F2 F2 VDDQ#F2 F2 VDDQ#F2 F2 VDDQ#F2 F2
VMA_RDQS2 F4 H3 VMA_RDQS3 F4 H3 VMA_RDQS4 F4 H3 VMA_RDQS6 F4 H3
VMA_RDQS0 DQSL VDDQ#H3 VMA_RDQS1 DQSL VDDQ#H3 VMA_RDQS5 DQSL VDDQ#H3 VMA_RDQS7 DQSL VDDQ#H3
C8 H10 C8 H10 C8 H10 C8 H10
C DQSU VDDQ#H10 DQSU VDDQ#H10 DQSU VDDQ#H10 DQSU VDDQ#H10 C

VMA_DM2 E8 A10 VMA_DM3 E8 A10 VMA_DM4 E8 A10 VMA_DM6 E8 A10


VMA_DM0 DML VSS#A10 VMA_DM1 DML VSS#A10 VMA_DM5 DML VSS#A10 VMA_DM7 DML VSS#A10
D4 DMU VSS#B4 B4 D4 DMU VSS#B4 B4 D4 DMU VSS#B4 B4 D4 DMU VSS#B4 B4
VSS#E2 E2 VSS#E2 E2 VSS#E2 E2 VSS#E2 E2
G9 G9 G9 G9
VMA_WDQS2 VSS#G9 VMA_WDQS3 VSS#G9 VMA_WDQS4 VSS#G9 VMA_WDQS6 VSS#G9
G4 DQSL VSS#J3 J3 G4 DQSL VSS#J3 J3 G4 DQSL VSS#J3 J3 G4 DQSL VSS#J3 J3
VMA_WDQS0 B8 J9 VMA_WDQS1 B8 J9 VMA_WDQS5 B8 J9 VMA_WDQS7 B8 J9
DQSU VSS#J9 DQSU VSS#J9 DQSU VSS#J9 DQSU VSS#J9
VSS#M2 M2 VSS#M2 M2 VSS#M2 M2 VSS#M2 M2
M10 M10 M10 M10
VSS#M10 VSS#M10 VSS#M10 VSS#M10
VSS#P2 P2 VSS#P2 P2 VSS#P2 P2 VSS#P2 P2
T3 P10 DRAM_RST_M T3 P10 DRAM_RST_M T3 P10 DRAM_RST_M T3 P10
21 DRAM_RST_M RESET VSS#P10 RESET VSS#P10 RESET VSS#P10 RESET VSS#P10
VSS#T2 T2 VSS#T2 T2 VSS#T2 T2 VSS#T2 T2
VMA_ZQ1 L9 T10 VMA_ZQ2 L9 T10 VMA_ZQ3 L9 T10 VMA_ZQ4 L9 T10
ZQ/ZQ0 VSS#T10 ZQ/ZQ0 VSS#T10 ZQ/ZQ0 VSS#T10 ZQ/ZQ0 VSS#T10
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% A1 B2 Ohms +-1% A1 B2 Ohms +-1% A1 B2 Ohms +-1% A1 B2
NC VSSQ#B2 NC VSSQ#B2 NC VSSQ#B2 NC VSSQ#B2
T1 B10 T1 B10 T1 B10 T1 B10
R227 NC VSSQ#B10 R382 NC VSSQ#B10 R218 NC VSSQ#B10 R379 NC VSSQ#B10
A11 D2 A11 D2 A11 D2 A11 D2
NC VSSQ#D2 NC VSSQ#D2 NC VSSQ#D2 NC VSSQ#D2
243/F_4 T11 NC VSSQ#D9 D9 243/F_4 T11 NC VSSQ#D9 D9 243/F_4 T11 NC VSSQ#D9 D9 243/F_4 T11 NC VSSQ#D9 D9
E3 E3 E3 E3
VSSQ#E3 VSSQ#E3 VSSQ#E3 VSSQ#E3
J2 E9 J2 E9 J2 E9 J2 E9
NC/ODT1 VSSQ#E9 NC/ODT1 VSSQ#E9 NC/ODT1 VSSQ#E9 NC/ODT1 VSSQ#E9
L2 F10 L2 F10 L2 F10 L2 F10
NC/CS1 VSSQ#F10 NC/CS1 VSSQ#F10 NC/CS1 VSSQ#F10 NC/CS1 VSSQ#F10
J10 G2 J10 G2 J10 G2 J10 G2
NC/CE1 VSSQ#G2 NC/CE1 VSSQ#G2 NC/CE1 VSSQ#G2 NC/CE1 VSSQ#G2
L10 G10 L10 G10 L10 G10 L10 G10
NC/ZQ1 VSSQ#G10 NC/ZQ1 VSSQ#G10 NC/ZQ1 VSSQ#G10 NC/ZQ1 VSSQ#G10
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12

+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA


B B

R386 R202 R384 R205 R231 R223 R381 R376


4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4

R385 R207 R387 R210 R230 R229 R383 R380


4.99K/F_4 C655 4.99K/F_4 C431 4.99K/F_4 C663 4.99K/F_4 C646 4.99K/F_4 C445 4.99K/F_4 C440 4.99K/F_4 C651 4.99K/F_4 C645
.1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4

VMA_CLK0 +1.5V_VGA +1.5V_VGA

R214
56.2/F_4
C425 C426 C452 C441 C434 C424 C422 C666 C640 C638 C664 C421 C667 C656 C637 C635
C436
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
VMA_CLK0_COMM

R221 .01U/16V_4 +1.5V_VGA +1.5V_VGA QCI PN


56.2/F_4
SAMSUNG AKD5LGGT502
VMA_CLK0#
A VMA_CLK1 C670 C668 C658 C446 C449 C451 C661 C665 C642 C641 C639 C649 C650 C652 C442 C448 A
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
HYNIX AKD5LZGTW00
R211
56.2/F_4
+1.5V_VGA +1.5V_VGA
C428
VMA_CLK1_COMM
PROJECT : R22
R215 .01U/16V_4 C662 C643 C455 C457 C454 C644 C654 C657 C648 C453 C456 C450
Quanta Computer Inc.
56.2/F_4 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S 10U/6.3V_6S
Size Document Number Rev
Custom SEYMOUR-XT VRAM(DDR3 BGA96) 3A
VMA_CLK1# NB5/RD2
Date: Wednesday, September 15, 2010 Sheet 22 of 43
5 4 3 2 1
1 2 3 4 5 6 7 8

+VIN
L8 UPB201209T-330Y-N(5A)
+VIN_BLIGHT +12VALW