REFER TO PAGE 5 FOR LOGIC LEVELS, NOTES,

ETC, REFERENCED BY THIS SYMBOL:

+12V
+35 V
F1
E1 +
J15-1
AC MAINS INVERTER
F2 TP11
INPUT BOARD -12V SWITCHING
208-230 VAC REGULATOR CIRCUIT J15-3
DS1 E2 - (U3 AND ASSOCIATED
1 PHASE J15-5
COMPONENTS)

PE J15-6
TO FILAMENT BOARD
EMC CAPACITOR -12 V REFER TO PG 4
BOARD J15-2
+1.2V
+5V
U58 TP30
+5V
J5-5 J5-7 J10-1 J10-3 J5-3 J5-1 +1.2V -35 V
+12 V +12 V REGULATOR
ON / OFF +24V
TP13 J15-4
D7 COMMAND 2
FROM MD-0928
MAIN CONTACTOR DRIVE
FROM MD-0928 D5 J6-1 J11-1 +5V SWITCHING
REGULATOR CIRCUIT
F7 J6-2 J11-2 (U14 AND ASSOCIATED
E16 E15
E1 ** D12 COMPONENTS)
120/240 VAC
E14 TO LOW SPEED
F6 STARTER
MD-0935 +12V

R33

R27
R32
D43 +12 V
K2
F5 R11
+3.3V J7-13
+5V
U64 TP31 TP14
F4 R17
+3.3V +24 V
REGULATOR

R14
+12V J7-19
TO AEC BOARD
J6-12 J11-12
+24V REFER TO PG 4
2 4 J7-17
SOFT-START
CONTACTOR DRIVE SOFT-START
D8 FROM MD-0928 U5 SENSE TO J7-11
+12V SWITCHING
MD-0928 REGULATOR CIRCUIT
(Q8, Q13, U10 AND
BUCKY DRIVE 1 3 J6-6 J11-6 ASSOCIATED -12 V
D13 COMPONENTS)
F8 F9 E7 TO MD-0930
R13 J2-3
TO COIL OF POWER DISTRIBUTION
+35 V RELAY (CUSTOMER-SUPPLIED)
K6 J2-4
J9-1 MAXIMUM 100 MA
E8 +35 V J1-4 J12-6
J9-3 +24 V
J1-5 J12-5 K1
J9-7 E11 E5 F10 F2 J20-13
* C2
E9 J20-15
+24 V +12V
E12 D1 J20-3 TO TOUCHSCREEN
CONSOLE
D5 J20-9
220V J8-5 REFER TO PG 4
0V J20-12
D10 C4
J8-3 J20-14
110V J1-8 J12-2 ON / OFF
COMMAND 1
0V J8-1 J1-9 J12-1 FROM MD-0928
F11
-35 V J3-8
120V 24 VAC TO
MD-0930 F12 +24 V +15V
26V J3-1 F1 24 VDC TO +24 V TO MEMBRANE
MD-0930 TP10 TP9 CONSOLE
208V -35 V +24V
J1-1 J12-9 REFER TO PG 4
0V
J1-2 J12-8 J3-3
240V 1
18V J3-4 F2
R27

C6 TP12
400V +15V SWITCHING
0V J3-3 TP9 REGULATOR CIRCUIT
D3 DS1 (U15 AND ASSOCIATED
480V J1-6 J12-4
18V J3-5 F3 D14 COMPONENTS)
J1-7 J12-3
D4
J3-2 DRAWN DATE
G. SANWALD 14 APR 2008 DC BUS & POWER
CHECKED DISTRIBUTION
JAC 14 AUG 2008
DES.\MFG.\AUTH.
THIS SHEET DEPICTS 1 PH. UNITS. H.V. AUXILIARY BOARD GENERATOR CONTROL BOARD MD-0927 REV E
REFER TO PAGE 2 FOR 3 PH. JAC 14 AUG 2008
208-230V UNITS, AND PAGE 3 * E5, E9, E11, and E12 CONFIGURE THE BUCKY OUTPUTS FOR +24 VDC, 120 VAC, OR 240 VAC. REFER TO CHAPTER 8 FOR DETAILS. Use and disclosure is subject to the restrictions SHEET 1 OF 5
FOR 3 PH. 400/480V UNITS ** E14, E15, E16 CONFIGURE THE LOW SPEED STARTER BOOST VOLTAGE FOR 120 OR 240 VAC. REFER TO CHAPTER 2 FOR DETAILS. on the title page of this CPI document.
 F3
~ +
E1 + +12V

~
AC MAINS +35 V
INPUT F2 INVERTER
BOARD J15-1
208-230 VAC

~
TP11
3 PHASE F1 DS1 E2 - -12V SWITCHING
J15-3
- REGULATOR CIRCUIT
(U3 AND ASSOCIATED
COMPONENTS) J15-5

PE J15-6
EMC CAPACITOR
TO FILAMENT BOARD
BOARD -12 V REFER TO PG 4
J15-2
+1.2V
+5V
U58 TP30
+5V
J5-5 J5-7 J10-1 J10-3 J5-3 J5-1 +1.2V -35 V
+12 V +12 V REGULATOR
ON / OFF +24V
TP13 J15-4
D7 COMMAND 2
FROM MD-0928
MAIN CONTACTOR DRIVE
FROM MD-0928 D5 J6-1 J11-1 +5V SWITCHING
REGULATOR CIRCUIT
F7 J6-2 J11-2 (U14 AND ASSOCIATED
E16 E15
E1 ** D12 COMPONENTS)
120/240 VAC
E14 TO LOW SPEED
F6 STARTER
MD-0935 +12V

R33

R27
R32
D43 +12 V
K2
F5 R11
+3.3V J7-13
+5V
U64 TP31 TP14
F4 R17
+3.3V +24 V
REGULATOR

R14
+12V J7-19
TO AEC BOARD
J6-12 J11-12
+24V REFER TO PG 4
2 4 J7-17
SOFT-START
CONTACTOR DRIVE SOFT-START
D8 FROM MD-0928 U5 SENSE TO J7-11
+12V SWITCHING
MD-0928 REGULATOR CIRCUIT
(Q8, Q13, U10 AND
BUCKY DRIVE 1 3 J6-6 J11-6 ASSOCIATED -12 V
D13 COMPONENTS)
F8 F9 E7 TO MD-0930
R13 J2-3
TO COIL OF POWER DISTRIBUTION
+35 V RELAY (CUSTOMER-SUPPLIED)
K6 J2-4
J9-1 MAXIMUM 100 MA
E8 +35 V J1-4 J12-6
J9-3 +24 V
J1-5 J12-5 K1
J9-7 E11 E5 F10 F2 J20-13
* C2
E9 J20-15
+24 V +12V
E12 D1 J20-3 TO TOUCHSCREEN
CONSOLE
D5 J20-9
220V J8-5 REFER TO PG 4
0V J20-12
D10 C4
J8-3 J20-14
110V J1-8 J12-2 ON / OFF
COMMAND 1
0V J8-1 J1-9 J12-1 FROM MD-0928
F11
-35 V J3-8
120V 24 VAC TO
MD-0930 F12 +24 V +15V
26V J3-1 F1 24 VDC TO +24 V TO MEMBRANE
MD-0930 TP10 TP9 CONSOLE
208V
-35 V +24V
J1-1 J12-9 REFER TO PG 4
0V
J1-2 J12-8 J3-3
240V 1
18V J3-4 F2
R27

C6 TP12
400V +15V SWITCHING
0V J3-3 TP9 REGULATOR CIRCUIT
D3 DS1 (U15 AND ASSOCIATED
480V J1-6 J12-4
18V J3-5 F3 D14 COMPONENTS)
J1-7 J12-3
D4
J3-2 DRAWN DATE
G. SANWALD 14 APR 2008 DC BUS & POWER
CHECKED DISTRIBUTION
JAC 14 AUG 2008
THIS SHEET DEPICTS 3 PH. DES.\MFG.\AUTH.
208-230V UNITS. REFER TO PAGE H.V. AUXILIARY BOARD GENERATOR CONTROL BOARD MD-0927 REV E
JAC 14 AUG 2008
1 FOR 1 PH. UNITS, AND PAGE * E5, E9, E11, and E12 CONFIGURE THE BUCKY OUTPUTS FOR +24 VDC, 120 VAC, OR 240 VAC. REFER TO CHAPTER 8 FOR DETAILS. Use and disclosure is subject to the restrictions SHEET 2 OF 5
3 FOR 3 PH. 400/480 V UNITS ** E14, E15, E16 CONFIGURE THE LOW SPEED STARTER BOOST VOLTAGE FOR 120 OR 240 VAC. REFER TO CHAPTER 2 FOR DETAILS. on the title page of this CPI document.
 F3
~ +
E1 +

~
AC MAINS +12V
F2 +35 V
INPUT * INVERTER
400/480 VAC BOARD J15-1

~
3 PHASE F1 DS1 E2 - TP11
-12V SWITCHING
- REGULATOR CIRCUIT J15-3
(U3 AND ASSOCIATED
COMPONENTS) J15-5
PE
* 50/65/80 KW UNITS USE
EMC CAPACITOR TWO INVERTER BOARDS J15-6
BOARD TO FILAMENT BOARD
-12 V REFER TO PG 4
J15-2
+1.2V
+5V
U58 TP30
+5V
J5-5 J5-7 J10-1 J10-3 J5-3 J5-1 +1.2V
TP10 2 -35 V
+12 V +12 V REGULATOR
ON / OFF +24V
TP13 J15-4
D7 COMMAND 2
TP11 FROM MD-0928

MAIN CONTACTOR DRIVE

D5 J6-1 J11-1 +5V SWITCHING
FROM MD-0928
REGULATOR CIRCUIT
F6 J6-2 J11-2 (U14 AND ASSOCIATED
120/240 VAC
E1 D12 COMPONENTS)
TO LOW SPEED
E16 E15 F7 STARTER
** MD-0935
+12V

R27
R33
E14 R32

K2
F5 R11 D43 +12 V
+3.3V J7-13
F4 R17 +5V
U64 TP31 TP14
+3.3V +24 V
+12V 4 REGULATOR
TP5 3

R14
TP4 J7-19
TO AEC BOARD
J6-12 J11-12
+24V REFER TO PG 4
SOFT-START
2 4 J7-17
CONTACTOR DRIVE
D8 FROM MD-0928
SOFT-START
U5 SENSE TO +12V SWITCHING J7-11
MD-0928 REGULATOR CIRCUIT
F8 F9 (Q8, Q13, U10 AND
BUCKY DRIVE 1 3 J6-6 J11-6 ASSOCIATED -12 V
D13 COMPONENTS)
E7 TO MD-0930
R13 J2-3
J9-5 TO COIL OF POWER DISTRIBUTION
+35 V +35 V RELAY (CUSTOMER-SUPPLIED)
K6 J2-4
J9-1 TP2 MAXIMUM 100 MA
E8 J1-4 J12-6
J9-3 +24 V
J1-5 J12-5 K1
J9-7 E11 E5 F10 F2 J20-13
* C2

R28
E9 J20-15
+24 V +12V
E12 D1 J20-3 TO TOUCHSCREEN
CONSOLE
D5 J20-9
220V J8-5 -35 V REFER TO PG 4
0V J20-12
D10 C4
R29
TP3
J8-3 J20-14
110V J1-8 J12-2 ON / OFF
COMMAND 1
0V J8-1 J1-9 J12-1 FROM MD-0928
F11
J3-8
120V 24 VAC TO
MD-0930 F12 +24 V +15V
26V J3-1 F1 24 VDC TO +24 V TO MEMBRANE
MD-0930 TP1
-35 V TP10 TP9 CONSOLE
208V J1-1 J12-9 +24V
0V REFER TO PG 4
J1-2 J12-8 J3-3
240V 1
18V J3-4 F2
R30

C6 TP12
400V TP12 +15V SWITCHING
0V J3-3 TP9 REGULATOR CIRCUIT
D3 DS1 (U15 AND ASSOCIATED
480V J1-6 J12-4
18V J3-5 F3 D14 COMPONENTS)
J1-7 J12-3
D4
J3-2 DRAWN DATE
G. SANWALD 14 APR 2008 DC BUS & POWER
CHECKED DISTRIBUTION
JAC 14 AUG 2008
THIS SHEET DEPICTS 3 PH. DES.\MFG.\AUTH.
400/480V UNITS. REFER TO H.V. AUXILIARY BOARD GENERATOR CONTROL BOARD MD-0927 REV E
JAC 14 AUG 2008
PAGE 1 FOR 1 PH. UNITS, AND * E5, E9, E11, and E12 CONFIGURE THE BUCKY OUTPUTS FOR +24 VDC, 120 VAC, OR 240 VAC. REFER TO CHAPTER 8 FOR DETAILS. Use and disclosure is subject to the restrictions SHEET 3 OF 5
PAGE 2 FOR 3 PH. 208-230V UNITS ** E14, E15, E16 CONFIGURE THE LOW SPEED STARTER BOOST VOLTAGE FOR 120 OR 240 VAC. REFER TO CHAPTER 2 FOR DETAILS. on the title page of this CPI document.
 +35 V
TP6
J1-1 F2

J1-3

TP2
-12 V
J1-5

FROM J15 GENERATOR J1-6

CONTROL BOARD
PG 1, 2, 3
TP7
J1-2 F1

+12 V
-35 V

J1-4
+24V FILAMENT SUPPLY BOARD
J28-13

J28-15 F3
FROM J20 GENERATOR
CONTROL BOARD TOUCHSCREEN
PG 1, 2, 3 J28-3 CONSOLE
J28-14

FROM J7 GENERATOR REFER TO MD-0936 (AEC) FOR

CONTROL BOARD PINOUTS OF THE +/-12 VDC
TOUCH-SCREEN BOARD
PG 1, 2, 3 AND +24 VDC SUPPLIES

AEC BOARD

FLUORESCENT LAMP

LCD DISPLAY ASSEMBLY

J5-1 J5-5
+5V TP9 5

300 VAC
BACKLIGHT
POWER SUPPLY C36
(Q1, Q2, T1, ETC)
MEMBRANE
+5V CONSOLE
+3.3V
TP7
TP2 +1.2V
+ 5V, + 3.3V, +1.2V TP6
AND - 20V
J8-8 F1 POWER SUPPLY TP14
CIRCUITS
(U12, U18, U20,
FROM J3 GENERATOR D3-D7, L1, ETC.)
CONTROL BOARD TP3
PG 1, 2, 3 TP8
J8-3
-20V

CONSOLE BOARD

DRAWN DATE
G. SANWALD 14 APR 2008 DC BUS & POWER
CHECKED DISTRIBUTION
JAC 14 AUG 2008
DES.\MFG.\AUTH.
MD-0927 REV E
JAC 14 AUG 2008
Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 4 OF 5
 NOTE
REMARKS
REFERENCE
“LOW” (APPROXIMATELY 0 VDC) DISABLES THE +5V, +12V, AND +15V REGULATORS (GENERATOR SWITCHED OFF). “HIGH” (APPROXIMATELY 24V DC) ENABLES THESE REGULATORS
1 (I.E. GENERATOR SWITCHED ON) .
“LOW” (APPROXIMATELY 0 VDC) ENERGIZES THE MAIN POWER CONTACTOR IN THE GENERATOR, (”HIGH”, + 12V DC = NOT ENERGIZED). THIS CONTACTOR IS ENERGIZED AFTER THE MAIN BUS CAPACITORS
2 ARE CHARGED, APPROXIMATELY 10 SECONDS AFTER POWER-ON. (Test point available on 400 / 480V AC units only)

“LOW” (APPROXIMATELY 0V DC) ENERGIZES THE SOFT START CONTACTOR K2 ON THE H.V. AUXILIARY BOARD, (”HIGH”, + 12V DC = NOT ENERGIZED). THIS CONTACTOR IS ENERGIZED FOR A MAXIMUM OF
3
APPROXIMATELY 10 SECONDS AFTER POWER-ON IN ORDER TO CHARGE THE DC BUS CAPACITORS. (Test point available on 400 / 480V AC units only)

4 THE VOLTAGE WAVEFORM AT THIS TEST POINT IS DEPICTED IN FIGURE 1 BELOW. (Test point available on 400 / 480V AC units only)

5 THE VOLTAGE WAVEFORM AT THIS TEST POINT IS DEPICTED IN FIGURE 2 BELOW.

8.33-10 ms
+5 V +5 V

FIGURE 1
0V 0V
EARLY CHARGING NEARLY FINISHED CHARGING

18 s

4V
FIGURE 2

-8 V

DRAWN DATE
G. SANWALD 14 APR 2008 DC BUS & POWER
CHECKED DISTRIBUTION
JAC 14 AUG 2008
DES.\MFG.\AUTH.
MD-0927 REV E
JAC 14 AUG 2008
Use and disclosure is subject to the restrictions SHEET 5 OF 5
on the title page of this CPI document.
 J1-10 J19-10

J1-9 J19-9
X-RAY MINI- OFF
CONSOLE
ON
J1-13 J19-13

MINI-CONSOLE BOARD +24 V

J1-4 J16-4 J28-11 J20-11

D2

OFF
J1-5 J16-5 J28-10 J20-10
*
TOUCHSCREEN * TO CONNECT AN EMERGENCY-OFF SWITCH, REMOVE JUMPER
CONSOLE ON J2-1 J2-2 FROM J2-1 TO J2-2, AND THEN CONNECT THE EMERGENCY OFF
J1-6 J16-6 J28-12 J20-12 SWITCH TO J2-1 AND J2-2.

TOUCH-SCREEN K2
FRONT PANEL BOARD BOARD

ON / OFF
Q4
COMMAND 1
TO MD-0927
J7-16 J8-7 J3-7

ON / OFF

R13
J7-15 J8-6 J3-6 COMMAND 2
Q5
OFF TO MD-0927
MEMBRANE ON TP3 TP9 S2
Q7
CONSOLE J8-3 J3-3
J7-17 OFF

R17
Q6

S1
CONSOLE ON
KEYBOARD ASSEMBLY BOARD

+5 V

U87

R300
J6-12 J11-12 DATA
BUFFER
MAIN CONTACTOR 5
DRIVE TO
MD-0927 SOFT START
SENSE FROM U5
MD-0927

4
J6-6 J11-6
D7

+12 V
+12 V

J6-1 J11-1
D48
J6-2 J11-2
U86
J6-3 J11-3 R294
Q29
J6-4 J11-4
R290

Q28
DATA
U83 LATCH

SOFT-START J6-11 J11-11 DATE

CONTACTOR DRIVE DRIVER DRAWN
G. SANWALD 14 APR 2008
TO MD-0927
CHECKED SYSTEM “ON”
SB 11 SEPT/08
H.V. AUXILIARY BOARD DES.\MFG.\AUTH.
DATA, ADDRESS, &
CONTROL BUS MD-0928 REV A
Use and disclosure is subject to the restrictions L. FOSKIN 11/SEPT/2008
GENERATOR CONTROL BOARD
on the title page of this CPI document. SHEET 1 OF 1
 BUCKY DRIVE +12V
FROM MD-0927

24 VDC, 1
RETURN 120 / 240 VAC K1
D2 TP13
U83 U86
J6-13 J11-13 DATA
J2-10 DRIVER
LATCH
BUCKY RETURN
2 TP14
BUCKY 1 J2-9
R2 ** C3 J6-14 J11-14 +5V
GROUND
1 4
J2-8 +24V

R326
BUCKY 1 OUT
U89
+24V U2
DATA

R5
BUCKY 1 J2-7
BUFFER
START K1 3
1 4 2 3

R3
TP15
J2-6 +5V
J6-15 J11-15
U1
BUCKY 1
READY J2-5

R304
2 3 +24V 4 U89
J2-4 DATA
TP16
+5V BUFFER
INTERLOCK

R7
J2-3 J6-16 J11-16
#1
1 4

R309
J2-2 +12V 5 U89
INTERLOCK #2 / U3
TP19 DATA
TOMO EXPOSURE J2-1 BUFFER
INPUT *
2 3 K3 D6
J4-4 U83 U86
BUCKY RETURN
J6-19 J11-19 DATA
TOMO / BUCKY 2 J4-3 DRIVER
R15 ** LATCH
C10
GROUND
+5V
J4-2
TOMO / BUCKY 2 OUT
24 VAC

R325
TOMO / BUCKY 2 J4-1 6 TP18
FROM U89
START K3
MD-0927 J6-18 J11-18 DATA
1 4 BUFFER
J11-6 24 VDC
24 VAC FROM
OUT J11-5 MD-0927 U6 +5V

+24V 7

R318
J11-2 2 3
24 VDC TP17 U89

R9
OUT J11-1
J6-17 J11-17 DATA
+24V BUFFER
1 4
J4-6 R10
+5V
BUCKY 2 U4
READY J4-5 8

R319
2 3 TP6 U89
J4-10
J6-10 J11-10 DATA
DOOR BUFFER
INTERLOCK J4-9 +24V 1 4
+12V U19
J7-1 R26 R25 U9 DATA
D49 LATCH
THERMAL
SWITCH J7-2
2 3 R295
J6-9 J11-9
+12V Q31 DATA, ADDRESS, &
J11-3 CONTROL BUS

R296
ROOM K7 D11 J6-20 J11-20
LIGHT
J11-4 DRAWN DATE
H.V. AUXILIARY BOARD GENERATOR CONTROL BOARD G. SANWALD 14 APR 2008 ROOM
CHECKED INTERFACE
SB 30 APR 08
REFER TO CHAPTER 3 OF THE SERVICE MANUAL FOR ADDITIONAL DETAILS REGARDING INTERFACING OF BUCKYS, INTERLOCKS, ETC. REFER TO PAGE 2 FOR LOGIC LEVELS, DES.\MFG.\AUTH.
NOTES, ETC, REFERENCED BY THIS SYMBOL: MD-0930 REV C
* THIS IS THE TOMO EXPOSURE INPUT FOR ANY IMAGE RECEPTOR THAT IS PROGRAMMED FOR TOMO OPERATION. THIS L. FOSKIN 06/MAY/2008
INPUT IS AN INTERLOCK FOR ALL REMAINING RECEPTORS THAT DO NOT HAVE TOMO ENABLED. THIS INPUT MUST NORMALLY
BE PROGRAMMED AS INACTIVE ON ALL NON-TOMO RECEPTORS IF THIS IS USED AS A TOMO INPUT ON THE TOMO RECEPTOR. Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 1 OF 2
 NOTE
REMARKS
REFERENCE
1 “LOW” (APPROXIMATELY 0 VDC) = BUCKY 1 START. “HIGH” (APPROXIMATELY +12 VDC) = BUCKY 1 NOT REQUESTED TO START. (Test point available on 400 / 480V AC units only)
2 “LOW” (APPROXIMATELY 0 VDC) = BUCKY 1 READY. “HIGH” (APPROXIMATELY +5 VDC) = BUCKY 1 NOT READY. (Test point available on 400 / 480V AC units only)
3 “LOW” (APPROXIMATELY 0 VDC) = 40” S.I.D. INTERLOCK CLOSED. “HIGH” (APPROXIMATELY +5 VDC) = 40” S.I.D. INTERLOCK OPEN. (Test point available on 400 / 480V AC units only)
4 “LOW” (APPROXIMATELY 0 VDC) = 72” S.I.D. INTERLOCK CLOSED. “HIGH” (APPROXIMATELY +5 VDC) = 72” S.I.D. INTERLOCK OPEN. (Test point available on 400 / 480V AC units only)
5 “LOW” (APPROXIMATELY 0 VDC) = BUCKY 2 START. “HIGH” (APPROXIMATELY +12 VDC) = BUCKY 2 NOT REQUESTED TO START. (Test point available on 400 / 480V AC units only)
6 “LOW” (APPROXIMATELY 0 VDC) = BUCKY 2 READY. “HIGH” (APPROXIMATELY +5 VDC) = BUCKY 2 NOT READY. (Test point available on 400 / 480V AC units only)
7 “LOW” (APPROXIMATELY 0 VDC) = DOOR INTERLOCK CLOSED. “HIGH” (APPROXIMATELY +5 VDC) = DOOR INTERLOCK OPEN. (Test point available on 400 / 480V AC units only)
8 “LOW” (APPROXIMATELY 0 VDC) = THERMAL SWITCH CLOSED. “HIGH” (APPROXIMATELY +5 VDC) = THERMAL SWITCH OPEN. (Test point available on 400 / 480V AC units only)

** THESE RESISTORS MAY NEED TO BE INSTALLED IN SOME APPLICATIONS. REFER TO CHAPTER 3C FOR DETAILS.

Use and disclosure is subject to the restrictions on the title page of this CPI document.
DRAWN DATE
G. SANWALD 11 FEB 2003 ROOM
CHECKED INTERFACE
SB 30 APR 08
DES.\MFG.\AUTH.
MD-0930 REV C
L. FOSKIN 06/MAY/2008

SHEET 2 OF 2
 +5V +5V
+24V

R84

R87
R33
U71 U77
DATA
1 4 BUFFER CPU
5V-3.3V
U7
2 3

X-RAY ENABLE
1 1 4 TO PG 2
TP13 U9
REFER TO PAGE 2 FOR DS6
U83 U86
LOGIC LEVELS, NOTES, J8-5 J3-5 2 3 DATA
DRIVER
ETC, REFERENCED BY LATCH

THIS SYMBOL: 1 4
+3.3V
U17 +24V

R55
J3-1 2 3

R42
2 1 4
TP12 U8
DS5
J8-4 J3-4 2 3
HAND
+3.3V SWITCH
DATA, ADDRESS, &

X-RAY

PREP
COM
CONTROL BUS
U21
R56

X-RAY
FPGA
1 4 J2-3 J2-2 J2-1

U16
J3-3 2 3

J19-11 J1-11
PREP J3-5 X-RAY MINI-
JW2 *
CONSOLE
J19-12 J1-12
HANDSWITCH PREP
JW1 * DATA, ADDRESS, &
ASSY CONTROL BUS X-RAY
J19-14 J1-14

MINI-CONSOLE BOARD
J7-2

J20-7 J28-7 J21-3 J2-3

X-RAY J7-3

J20-8 J28-8 J21-4 J2-4

PREP
PREP TOUCHSCREEN
J7-1
J8-3 J3-3 X-RAY CONSOLE
J20-9 J28-9 J21-5 J2-5

KEYBOARD ASSEMBLY CONSOLE BOARD GENERATOR CONTROL BOARD FRONT PANEL BOARD

* REMOVE JW1 TO DISABLE THE CONSOLE PREP BUTTON, AND JW2

J30-3
TO DISABLE THE CONSOLE X-RAY BUTTON PREP
HAND J30-1
X-RAY DRAWN DATE
SWITCH
J30-5 G. SANWALD 14 APR 2008 X-RAY EXPOSURE
MEMBRANE CONSOLE COM CHECKED
JAC 5 MAY 08
(RADIOGRAPHIC)
TOUCH-SCREEN DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. BOARD
JAC
MD-0931 REV B
28 MAY 08

SHEET 1 OF 3
 J3-9 J9-9

J3-7 J9-7

H.T. TANK X-RAY ENABLE

+5V +5V +5V
FROM PG 1
AND FROM
MD-0926 PG 2

R293

R253
3 6

R91
TP17 TP19

R288

R270
TP18
U65
DATA R282 7
BUFFER Q27
U77 TP16
3.3V-5V R276
DRIVE ENABLE
TO MD-0932
5 PG 1
CPU
TP20
U67
DATA R287
BUFFER Q26
3.3V-5V
R269

+12V +12V
R137

R129
Q22

R151
Q21 R130 RAD INHIBIT
TO MD-0932
R136

PG 1

ADDRESS / DATA
& CONTROL BUS
D0..D7

GENERATOR CONTROL BOARD

DRAWN DATE
G. SANWALD 14 APR 2008 X-RAY EXPOSURE
CHECKED (RADIOGRAPHIC)
JAC 5 MAY 08
DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. JAC
MD-0931 REV B
28 MAY 08

SHEET 2 OF 3
 NOTE
REMARKS
REFERENCE
1 “LOW” (APPROXIMATELY 0V DC) = X-RAY REQUESTED. “HIGH” (APPROXIMATELY +24V DC) = X-RAY NOT REQUESTED.
2 “LOW” (APPROXIMATELY 0V DC) = PREP REQUESTED. “HIGH” (APPROXIMATELY +24V DC) = PREP NOT REQUESTED.
3 “LOW” (APPROXIMATELY 0V DC) = HT TANK CONNECTED. “HIGH” (APPROXIMATELY +5V DC) = HT TANK NOT CONNECTED.
4 “LOW” (APPROXIMATELY 0V DC) = NO FAULT PRESENT. “HIGH” (APPROXIMATELY +5V DC) = FAULT DETECTED, EXPOSURE INHIBITED.
5 “LOW” (APPROXIMATELY 0V DC) = X-RAY REQUESTED. “HIGH” (APPROXIMATELY +5V DC) = X-RAY NOT REQUESTED BY THE CPU.
6 “LOW” (APPROXIMATELY 0V DC) = EXPOSURE REQUESTED. “HIGH” (APPROXIMATELY +5V DC) = EXPOSURE NOT REQUESTED OR REQUEST NOT VALID.
7 “HIGH” (APPROXIMATELY +5V DC) = GATE DRIVE PULSES ENABLED. “LOW” (APPROXIMATELY 0V DC) = GATE DRIVE PULSES NOT ENABLED DUE TO A FAULT OR NO VALID EXPOSURE REQUEST.

DRAWN DATE
G. SANWALD 14 APR 2008 X-RAY EXPOSURE
CHECKED (RADIOGRAPHIC)
JAC 5 MAY 08
DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. JAC
MD-0931 REV B
28 MAY 08

SHEET 3 OF 3
 REFER TO PAGE 3 FOR
LOGIC LEVELS, NOTES, INVERTER “SHOOT THRU” INVERTER “SHOOT THRU”
ETC, REFERENCED BY SENSE, FROM PAGE 2 SENSE, FROM PAGE 2
+5V +5V +12V
THIS SYMBOL: 1 1V = 20 kV OF
R250
H.V. FEEDBACK
TP26 J10-1 J10-3 J16-1 J16-3 R156 - 2
1 R177 J9-6
TP8 + 3
-
U77 U78 U51A

R165
+ T3 T4 R166

R283
R184
DATA U70 C154
CPU TP27 J9-5
BUFFER 2
5V-3.3V - 6
-
R260 R285 7
1 JW15

R128
5 KV FEEDBACK SIGNAL

R272
+
J9-7
FROM PAGE 2
+
U51B 2 125 kV
U75
R193

R289
3 150 kV

R178
INVERTER “SHOOT THRU”
R171 6
DETECTOR CIRCUITS
-
7 R204 J9-8
+ 5
+5V +5V U56B

R202

R183
U77 U78 TP23
DATA - 3
7 R191
CPU BUFFER + 2 GATE DRIVE CIRCUIT J5-1
5V-3.3V FOR MOSFET INVERTER
U55 J5-2
1 JW6

R212
J5-3
2 125 kV Q16 Q19
J5-4
R198 3 150 kV
INVERTER DRIVE SIGNAL
CONTINUED ON PAGE 2
U45 J13-1
R135
A/D J13-2
CONV Q17 Q20
R134

J13-3
R219 J13-4

1V = 15 kV OF TP5
H.V. DEMAND
HV ON
TO MD-0926
R149

- PG 1
-
R243
+ Q25
1 JW16 +
U72A
U72B
2 125 kV
R105

R390 3 150 kV “HV ON” CIRCUIT

RAD INHIBIT C184 TP2 TP3 5

FROM MD-0931 D19
R138 PG 2
U43

R100
R108
D/A 2- ERROR AMPLIFIERS
R144 R112 U26A U27A
CONV 1 2- R131 R123
3+ 1 2
3 - D23 3 2 7
+ - R106 2- 1
U38A + 1
U48A D27 JW7 +
3+
U25A
R150

1 U25B VCO U26B U27B

U33A 5

R119
6 4 5
2 INCLUDES U34, U39, 4
U49, U52, U62, Q23
C69 3 JW7 NOT
USED AT
THIS
C70 TIME
4
TP15
- 3 R218 D33, 36, 38, 42
7 DRIVE ENABLE
2 CURRENT SENSE FROM MD-0931
+
R222

R103

+5V U69 PG 2
R214

R217

T2 T1 1 JW4 *
R228

U77 U78 2
DATA -12V 1 JW5 * R209
CPU BUFFER 3
5V-3.3V 2
R107 3 J6-4 J6-1
DRAWN DATE
G. SANWALD 14 APR 2008 KV CONTROL
DATA BUS H.T. PRIMARY CURRENT SENSE CHECKED & FEEDBACK
FROM PAGE 2 GW MAY 7, 2008
D0..D7
DES.\MFG.\AUTH.
GENERATOR CONTROL BOARD
JAC 27 AUG 2008
MD-0932 REV B
* REFER TO TABLE 1 (SHEET 3) FOR THE SHEET 1 OF 3
Use and disclosure is subject to the restrictions on the title page of this CPI document. JW4 AND JW5 JUMPER POSITIONS
 TO J9-8

kV FEEDBACK TO J9-7
TO PAGE 1
TO J9-5
HV ANODE
T2 J2-1 TO J9-6
TO J16-1 INVERTER BOARD
PART OF INVERTER “SHOOT “SHOOT THRU”
THROUGH” DETECTOR CIRCUIT J2-3
TO J16-3 SENSE, TO PAGE 1
*
E1: 560 to 670 VDC (+)
MOSFET INVERTER J1
(INCLUDES Q1-Q16) ANODE

C S
L

J13-1 J1-1
J3-8
J13-2 J1-2 HV MULT
ASSY +
E3 J3-7 (ANODE)
J13-3 J1-3
J13-4 J1-4 J3-5

J3-6
E4

E9
INVERTER BOARD E2: 560 to 670 VDC (-)
FROM
PAGE 1
T2 J2-1
TO J10-1 INVERTER
PART OF INVERTER “SHOOT “SHOOT THRU” E10
THROUGH” DETECTOR CIRCUIT J2-3
TO J10-3 SENSE, TO PAGE 1
E1: 560 to 670 VDC (+) HV MULT
MOSFET INVERTER
ASSY-
(INCLUDES Q1-Q16)
(CATHODE)

J5-1 J1-1
*
J5-2 J1-2

E3
C L
J5-3 J1-3
S
J5-4 J1-4

HV CATHODE J2
TANK LID CATHODE
E4 BOARD
BOARD

GENERATOR * DEPENDING ON GENERATOR

CONTROL BOARD INVERTER BOARD E2: 560 to 670 VDC (-) MODEL, THE H.T. TRANSFORMERS
MAY USE TWO PAIRS OF SECONDARY
WINDINGS, OR THREE SECONDARIES
AS SHOWN ABOVE
THIS PAGE DEPICTS 50 KW, 65 KW AND 80 KW UNITS (WITH TWO INVERTER ASSEMBLIES.
REFER TO PAGE 3 FOR 32/40KW UNITS THAT USE ONE INVERTER ONLY. H.T. PRIMARY CURRENT TO J6-1 PART OF H.V. OIL TANK
SENSE, TO PAGE 1 TO J6-4

DRAWN DATE
G. SANWALD 14 APR 2008 KV CONTROL
CHECKED & FEEDBACK
GW MAY 7, 2008
DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. JAC 27 AUG 2008
MD-0932 REV B
SHEET 2 OF 3
 T2 J2-1
TO J10-1 INVERTER
PART OF INVERTER “SHOOT “SHOOT THRU”
THROUGH” DETECTOR CIRCUIT J2-3
TO J10-3 SENSE, TO PAGE 1
E1: 325 to 670 VDC (+)
MOSFET INVERTER
(INCLUDES Q1-Q16)
TO E9 AND E10
ON H.V. TANK
(PAGE 2)

FROM J5-1 J1-1

PAGE 1 J5-2 J1-2

E3

J5-3 J1-3
J5-4 J1-4

E4

GENERATOR
CONTROL BOARD INVERTER BOARD E2: 325 to 670 VDC (-)

H.T. PRIMARY CURRENT TO J6-1

SENSE, TO PAGE 1 TO J6-4

NOTE
REMARKS
REFERENCE
A NARROW PULSE WILL BE PRESENT AT THIS TEST POINT IF AN INVERTER “SHOOT THROUGH” HAS BEEN DETECTED. THE VOLTAGE WAVEFORM AT THIS TEST POINT IS DEPICTED IN FIGURE 1 BELOW.
1 THIS PULSE MAY BE VERY DIFFICULT O DETECT, AS THE INVERTER DRIVE WILL BE SHUT DOWN WHEN A “SHOOT THROUGH” IS DETECTED, THUS REMOVING THE FAULT CONDITION.
2 AS PER # 1.
A NARROW PULSE WILL BE PRESENT AT THIS TEST POINT IF KV OVER VOLTAGE HAS BEEN DETECTED (130 KV FOR 125 KV UNITS, 163 KV FOR 150 KV UNITS). REFER TO FIGURE 1. THIS PULSE MAY BE VERY
3 DIFFICULT TO DETECT, AS THE HIGH VOLTAGE WILL BE SHUT DOWN WHEN THE OVER VOLTAGE CONDITION IS DETECTED, THUS REMOVING THE FAULT CONDITION.
A NARROW PULSE WILL BE PRESENT AT THIS TEST POINT IF INVERTER OVER CURRENT HAS BEEN DETECTED. THE VOLTAGE WAVEFORM AT THIS TEST POINT IS DEPICTED IN FIGURE 1 BELOW.
4
THIS PULSE MAY BE VERY DIFFICULT O DETECT, AS THE INVERTER DRIVE WILL BE SHUT DOWN WHEN AN OVER CURRENT CONDITION S DETECTED, THUS REMOVING THE FAULT CONDITION.

5 THE VOLTAGE AT TP2 AND TP3 SHOULD BE A 50% DUTY CYCLE SQUARE WAVE, RANGING IN FREQUENCY FROM APPROXIMATELY 80 kHz TO APPROXIMATELY 250 kHz, DEPENDING ON GENERATOR
OUTPUT POWER. SEE FIGURE 2.

+5 V 32/40 kW 50 kW 32/40 kW 32/40 kW 50 kW 65/80 kW

400/480 VAC 400/480 VAC 208/230 VAC 400/480 VAC 208/230 VAC 400/480 VAC
FIGURE 1 12 VDC 125 kV 150 kV 125 kV 150 kV 150 kV 150 kV
FIGURE 2
JW4 Pins 1-2 Pins 2-3 Pins 2-3 Pins 1-2 Pins 2-3 Pins 2-3
0V 0 VDC
JW5 Pins 1-2 Pins 1-2 Pins 2-3 Pins 1-2 Pins 2-3 Pins 2-3

TABLE 1

DRAWN DATE
G. SANWALD 14 APR 2008 KV CONTROL
CHECKED & FEEDBACK
GW MAY 7, 2008
DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. JAC 27 AUG 2008
MD-0932 REV B
SHEET 3 OF 3
 REFER TO PAGE 3 FOR
LOGIC LEVELS, NOTES, MAXIMUM FILAMENT CURRENT
ETC, REFERENCED BY LIMIT CIRCUIT
THIS SYMBOL: SET MAX
CURRENT ERROR AMPLIFIER, PWM REGULATOR,
JW1 AND FILAMENT CURRENT DRIVERS
3
+
2 6.5 A
-
R76 5.5 A
U1A 1 +35V
1 -12V

TP4
D6

R117
U42 R72 6
Q6 Q12
D/A 6 - R116 J14-6 J2-6 R65 TP3
CONV 7 6- R95 R77 U3
5 +
7 -
U32B 5+
J14-5 J2-5 R66 U1B +

U4B PWM
REGULATOR

R71

R85
Q13
5 Q7
TP2 TP4
C22

R84
L CATHODE
-35V

C L
J5-2 J4-2
S
+12V
4 J5-1 J4-1
+12V 2 TP1 K1 K1
J5-4 J4-4
TP29
D50 J5-3 J4-3
J14-11 J2-11
U77 U67
DATA R299
CPU BUFFER Q30
3.3V-5V S
R297

3 FILAMENT
T1 MOUNTING
TP28 D12, 13
U45 U7 BOARD
D 27, 28
R140 J14-2 J2-2 R69 - U4A
A/D + RMS
CONV +
-
CONVERTER
U2B
R141

J14-10 J2-10
R21

+5V TANK LID

BOARD
R292

U77 U78 Q1
PART OF H.V. OIL TANK
DATA 1.7 V
CPU BUFFER U2A Ref
5V-3.3V -
+

FILAMENT CURRENT SENSE,

RMS CONVERTER, AND
FILAMENT FEEDBACK
DATA BUS
D0..D7

DRAWN DATE
G. SANWALD 14 APR 2008 FILAMENT DRIVE
CHECKED & MA CONTROL
JAC 5 MAY 08
DES.\MFG.\AUTH.
GENERATOR CONTROL BOARD FILAMENT SUPPLY BOARD
JAC
MD-0934 REV A
28 MAY 08
Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 1 OF 3
 U74A
3+ R277
1
2-
1V = 100 mA

R271
OF ANODE
CURRENT R238

R246
TP7
R233
U45

R216
2- A/D
R118
1 CONV
3+
U68A

R122
R257

R237
J1 HV ANODE

R160
ANODE BOARD

S C

R265
L

+5V +5V

R155

R143
J3-1 J9-1 R258 R227 R221 TP25
3-
6- R142 7

R278
7 2
5+ +
U47
J3-2 J9-2 R208 R234 U68B

R148
R239
mA
TEST
E18 JACK
- +5V

R159
R176
U78 U77
-12V TP24
+ DATA
3- BUFFER CPU
E17 7
2+ 5V-3.3V

R169
U50

R185
J3-4 J9-4 R215 R192

2- R170
R266

1
3+
J3-3 J9-3 R213 R199 DATA BUS

R164
U56A
D0..D7
L C

R203
S

J2
CATHODE HV CATHODE TANK LID
BOARD BOARD

PART OF HV OIL TANK GENERATOR CONTROL BOARD

Use and disclosure is subject to the restrictions on the title page of this CPI document.
DRAWN DATE
G. SANWALD 14 APR 2008 FILAMENT DRIVE
CHECKED & MA CONTROL
JAC 5 MAY 08
DES.\MFG.\AUTH.
JAC
MD-0934 REV A
28 MAY 08

SHEET 2 OF 3
 NOTE
REMARKS
REFERENCE
1 1 VOLT AT THIS TEST POINT = 1 AMP OF FILAMENT DEMAND.
2 “LOW” (APPROXIMATELY 0 VDC) ENERGIZES K1 ON THE FILAMENT SUPPLY BOARD (SMALL FILAMENT), “HIGH” (APPROXIMATELY +12 VDC) DE-ENERGIZES K1 (LARGE FILAMENT).
3 0.6 VOLT AT THIS TEST POINT = 1 AMP OF ACTUAL FILAMENT CURRENT.
4 “HIGH” (APPROXIMATELY 5 VDC) = FILAMENT FAULT (FILAMENT CURRENT < 2 A). “LOW” (APPROXIMATELY 0 VDC) = NO FILAMENT FAULT.
5 1 VOLT AT THIS TEST POINT = 1 AMP OF ACTUAL FILAMENT CURRENT.
6 PWM OUTPUT. THE WAVEFORM WILL BE AS PER FIGURE 1 FOR LOW AND HIGH FILAMENT CURRENT DEMAND.
A NARROW PULSE WILL BE PRESENT AT THESE TEST POINTS DURING SEVERE ANODE OR CATHODE OVER CURRENTS (I.E. TUBE OR TANK ARCS). REFER TO FIGURE 2. THESE PULSES MAY BE VERY
7, 8 DIFFICULT TO OBSERVE, AS THE HIGH VOLTAGE WILL SHUT DOWN WHEN A FAULT IS DETECTED, THUS REMOVING THE OVER CURRENT SITUATION.

Approx 25 usec (40 kHz)

+12 V
LOW FILAMENT
DEMAND

0V
FIGURE 1

+12 V
HIGH FILAMENT
DEMAND

0V

+5 V TP25

0V
FIGURE 2
+5 V
TP24

0V

DRAWN DATE
G. SANWALD 14 APR 2008 FILAMENT DRIVE
CHECKED & MA CONTROL
JAC 5 MAY 08
DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. JAC
MD-0934 REV A
28 MAY 08

SHEET 3 OF 3
REFER TO PAGE 2 FOR
LOGIC LEVELS, NOTES,
ETC, REFERENCED BY
THIS SYMBOL:

F7 J7-4
COM
120/240 VAC
R19 C12 J7-6
TO LOW SPEED
STARTER
SHIFT
FROM MD-0927 F6 R20 J7-5
MAIN
R31 J7-3
GROUND

R23

R24
R21

R22
2 1

3 4 +5 V +5 V
2 1
U89
2

R310

R305
3 U8
4
1 TP7

U7 TP8 J6-8 J11-8

DATA
J6-7 J11-7 BUFFER
J6-6 J11-6

3
K5 U83
TP9 U86

J6-5 J11-5
DRIVER
D9
DATA
LATCH

K4 +12 V
TP10 J6-3 J11-3
4
J6-4 J11-4 D48

D7
TP11 +12 V
R294
J6-1 J11-1 Q29

R290
J6-2 J11-2
Q28
DATA, ADDRESS, &
CONTROL BUS

H.V. AUXILIARY BOARD GENERATOR CONTROL BOARD

Use and disclosure is subject to the restrictions on the title page of this CPI document.

DRAWN DATE
G. SANWALD 14 APR 2008 LOW SPEED
CHECKED STARTER
SB 30 APR/08
DES.\MFG.\AUTH.
L. FOSKIN 02/JUN/2008 MD-0935 REV C
SHEET 1 OF 2
 NOTE
REMARKS
REFERENCE
1 MAIN STATOR CURRENT SENSE. IF MAIN CURRENT IS LOW, THIS WILL BE APPROXIMATELY +5V DC. PULSES AT 100 OR 120 HZ WILL BE PRESENT AS SHOWN IN FIGURE 1 AT NORMAL STATOR CURRENT.
2 PHASE-SHIFT STATOR CURRENT SENSE. IF SHIFT CURRENT IS LOW, THIS WILL BE APPROXIMATELY +5V DC. PULSES AT 120 HZ WILL BE PRESENT AS SHOWN IN FIGURE 1 AT NORMAL STATOR CURRENT.
3 “LOW” (APPROXIMATELY 0V DC) FOR APPROXIMATELY 1.8 SEC DURING PREP, THEN PULSED LOW FOR 500 MSEC EVERY 5 SECONDS DURING PREP. REFER TO FIGURE 2.
“LOW” (APPROXIMATELY 0V DC) ENERGIZES K4 ON THE H.V. AUXILIARY BOARD, (”HIGH”, + 12V DC = NOT ENERGIZED). THIS RELAY IS ENERGIZED AFTER THE MAIN BUS CAPACITORS ARE CHARGED,
4
APPROXIMATELY 10 SECONDS AFTER POWER-ON.

+5 V
FIGURE 1
THIS APPROACHES 0 V AS CURRENT INCREASES
0V

PULSE WIDTH INCREASES AS CURRENT INCREASES

+12V K5 DE-ENERGIZED
FIGURE 2

0V K5 ENERGIZED
N/A
APPROXIMATELY 1.8 SEC.

PREP STARTED

Use and disclosure is subject to the restrictions on the title page of this CPI document.

DRAWN DATE
G. SANWALD 14 APR 2008 LOW SPEED
CHECKED STARTER
SB 30 APR/08
DES.\MFG.\AUTH.
L. FOSKIN 02/JUN/2008 MD-0935 REV C
SHEET 2 OF 2
 E10 E9 F2 +5V
CS1 560/650 VDC (+) SW1 * SW2 *
DC BUS VOLTAGE DS1
560/650 VDC
E11 E10 F1 INVERTER
560/650 VDC (-) FAULT 560 / 650 VDC (+)

R24
INVERTER
E12 E11 FAULT
DETECTOR
U10, U11
EMC CAPACITOR BOARD

U17, U18 IGBT IGBT

+12V +12V DRIVER SWITCH SWITCH
U19, U22, U24
CIRCUIT AND (Q2) (Q4)
J18-1 J1-1 FAULT
CURRENT
J18-3 J1-3 LATCH
+12V +12V
J18-5 J1-5 (U1-U9, IGBT IGBT
T1-T4, ETC). SWITCH SWITCH
J18-7 J1-7
(Q1) K4

R317

R324
(Q3)
J18-9 J1-9

R40 TUBE 1
HS PREP
TB2-3 SHIFT
U86 U83 DS10 DS11 J18-6 J1-6 1 5

J18-8 J1-8 U12 DUAL SPEED 560 / 650 VDC (-)

STARTER CPU, K1
2 4
BUFFERS,
DATA DRIVERS
DRIVER
LATCH K1-A
HIGH SPEED K5
SELECT K3 TB2-2 MAIN
D47
R41 Q5
+12V +12V TB2-1 COMM
K6
J18-2 J1-2 1 5 K5

R31
+5V R32
K4
U13
R308

J18-4 J1-4 C22

2 4 K6 K1-B
R302

READY PREP K7
U87 DS9 INITIATED K3
E5 C1 E8

4 1

DATA U88 SHIFT CAPACITOR

+5V
BUFFER ARRANGEMENT
3 2 901297-12, 13
J18-10 J1-10 E7 E6 901298-12, 13
R303

C2 C3 C4
K7
J18-19 J1-19 DUAL SPD DUAL SPD DUAL SPD DUAL SPD DUAL SPD E14
STARTER ASSY STARTER ASSY STARTER ASSY STARTER ASSY STARTER ASSY
901297-02 901297-12 901297-13 901297-15 901297-16
901298-02 901298-12 901298-13 901298-15 901298-16

U45 CAPACITOR VALUE VALUE VALUE VALUE VALUE REMOVE WIRE

R273 J18-12 J1-12 SHIFT
R274 - 6 C1 40 uF 30 uF 25 uF 12.5 uF 25 uF FOR 15.5 uF LS CAPACITOR
A/D 7 R259 C6 (-15 ONLY)
5 C2 N/A 30 uF 25 uF 6 uF 12.5 uF ARRANGEMENT
CONV +
J18-11 J1-11 901297-15, 16
K3
R281

U79B C3 40 uF 15 uF 12.5 uF 6 uF 12.5 uF E5 E8 901298-15, 16

C147 J18-13 J1-13
C4 40 uF 15 uF 12.5 uF 6 uF 12.5 uF C1
J18-15 J1-15
C5 N/A N/A N/A 6 uF 12.5 uF
DATA BUS J18-17 J1-17
C6 N/A N/A N/A 12.5 uF N/A E7 E6
D0..D7
K7 C3 C4
GENERATOR CONTROL BOARD E14
C2 C5

DUAL SPEED STARTER ASSY

901297-02 901297-12 901297-13 901297-15 901297-16

K3 K7 901298-02 901298-12 901298-13 901298-15 901298-16
K3
LOW SPD (1) CLOSED OPEN 36 uF 30 uF 15.5 / 28 uF 31 uF E5 E8
60 uF C1
LOW SPD (2) CLOSED CLOSED 37.5 uF 31 uF N/A 37.5 uF
HIGH SPD (1) OPEN OPEN 6 uF 5 uF 3 uF 6 uF SHIFT CAPACITOR DRAWN DATE
20 uF E7 E6
HIGH SPD (2) OPEN CLOSED 7.5 uF 6 uF 6 uF 12.5 uF ARRANGEMENT G. SANWALD 14 APR 2008 DUAL SPEED
C3 C4 901297-02
K7 CHECKED STARTER
E14 901298-02

REFER TO CHAPTER 2 OF THE SERVICE MANUAL FOR THE DES.\MFG.\AUTH.

DUAL SPEED STARTER BOARD J.B. MD-0924 REV C
PROCEDURE TO SET DIP SWITCH SW1. SW2 IS NOT USED. 26 AUG 2008

SHEET 1 OF 1
Use and disclosure is subject to the restrictions on the title page of this CPI document.
REFER TO PAGE 7 FOR
LOGIC LEVELS, NOTES,
ETC, REFERENCED BY
THIS SYMBOL:

U90 U91
J7-2
CHAMBER 4 SELECT
J7-3
CHAMBER 3 SELECT
J7-4
CHAMBER 2 SELECT
J7-5
DATA CHAMBER 1 SELECT
LATCH DRIVER J7-6
START
J7-7
RIGHT FIELD SELECT
J7-8 TO AEC BOARD.
MIDDLE FIELD SELECT
J7-9
REFER TO SHEETS 2-6
LEFT FIELD SELECT AS APPLICABLE FOR THE
AEC BOARD IN YOUR UNIT
+5V
VOLTAGE
AMPLIFIER
TP21 R264
1 COMPARATOR -
- R245 R232 J7-15
PT RAMP
+
+

U77 U71 U66B J7-10

U73 PT REF

R249
R263

DATA J7-1
CPU BUFFER PT STOP
5V-3.3V
2
TP6
R256
R220

U44
D/A 6-
CONV 7
5+
U38B

U77 U71
DATA R286
CPU BUFFER
5V-3.3V

DATA, ADDRESS, &

CONTROL BUS

GENERATOR CONTROL BOARD

DRAWN DATE
G. SANWALD 14 APR 2008
CHECKED AEC
BZ 29 APR 2008
DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. JAC
MD-0936 REV A
28 MAY 08

SHEET 1 OF 7
 +500V
TP10 LEFT +/-300V
J1-2
+/-300 V AEC CH 1
+12V +12V +12V +12V +12V
6 J11-1
JW8 H.V. J1-1
+12V * 1 +/-300/+500 V

RN6C

RN6D
RN6B

RN6A

RN6E
TP22 2 J1-3
+/-300V +45V +45 V
TP24 H.V. 3 J11-4
START J1-8
DS5 DS1 DS2 DS3 DS4 RIGHT RESET/START
J11-3
MIDDLE J1-10
RN4A JW7 M FIELD SEL
J7-2 J5-2 D6 J11-2
CHAMBER 4 SELECT CH 4 1 L/R J1-9
TP9 2 R FIELD SEL
U3C 3 J11-6
J7-3 J5-3 RN3D CONVERTER R/L J1-11
D5 L FIELD SEL
CHAMBER 3 SELECT CH 3 +12V +24V CIRCUIT J11-5

R66
12 VDC TO 45 VDC TP11 J1-12
U3B R89 CHAMBER O/P
J7-4 J5-4 D12 RN3C AND 300 / 500 VDC 9 J11-9
CHAMBER 2 SELECT CH 2 J1-7
+45V CH 1 GROUND
U3F * INCLUDES U7 AND T1
J7-5 J5-5 D4 RN3A
CHAMBER 1 SELECT CH 1 S1D R90
D16 **
U3D
J7-6 J5-6 D11 RN3B Q1
SET

R79
START STRT
VALUE LEFT +/-300V
J2-2
+/-300 V AEC CH 2
U3E U3A * START J12-1
JW6 H.V. J2-1
1 +/-300/+500 V
2 J2-3
+12V +24V +12V +24V +12V +24V +45V +45 V
3 J12-4
START J2-8
RIGHT RESET/START
J12-3
MIDDLE J2-10
JW5 M FIELD SEL
J5-7
* * * 1 J12-2
L/R
J7-7 J2-9
RIGHT FIELD SELECT 2 R FIELD SEL
D30 D40 D65 3 J12-6
J7-8 J5-8 R/L J2-11
MIDDLE FIELD SELECT Q2 Q3 Q4 L FIELD SEL
J12-5
J7-9 J5-9 TP12 J2-12
LEFT FIELD SELECT * * * R67 CHAMBER O/P
RIGHT MIDDLE LEFT 9 J12-9
J2-7
CH 2 GROUND
FROM
PAGE 1 S1C R68

LEFT +/-300V
J3-2
+/-300 V AEC CH 3
TP18 J13-1
TP17 4 TP20 5 JW4 H.V. J3-1
J7-19 J5-19 CH 1 1 +/-300/+500 V
+24V J3-3
2 +45V +45 V
TP23 - STRT R1 S2A 3 J13-4
START J3-8
-
CH 2 RESET/START
J7-13 J5-13 TP5 TP6 TP7
+
S4 RIGHT
+12V + J13-3
U4A MIDDLE J3-10
FROM J7-17 J5-17 U4B R2 S2B JW3 M FIELD SEL
R32 J13-2
MD-0831 C11 CH 3 1 L/R J3-9
* 2 R FIELD SEL
3 J13-6
TP4 C4 S2C R/L J3-11
R3 L FIELD SEL
CH 4 J13-5
J7-11 J5-11 CH 1 R53 TP13 J3-12
-12V -
R57 CHAMBER O/P
R4 S2D 9 J13-9
S3A
+
J3-7
CH 3 GROUND
U2B
R11 CH 2 S1B R58
TP3 2 TP19 7
S3B
TP2 8
J7-15 J5-15 R54 LEFT +/-300V
J4-2
+/-300 V AEC CH 4
PT RAMP R12 J14-1
RN4C CH 3 JW2 H.V. J4-1
J7-10 J5-10 +/-300/+500 V
PT REF 1
2 J4-3
J7-1 J5-1 S3C +45V +45 V
PT STOP 3 J14-4
START J4-8
R13 CH 4
-
RIGHT RESET/START
+12V D27 - J14-3
R56 + MIDDLE J4-10
+ JW1 M FIELD SEL
S3D U1A 1 J14-2
RN4B U2A L/R J4-9
RN4D

- 3 STRT 2 R FIELD SEL

7 R14 3 J14-6
+ 2 R/L J4-11
L FIELD SEL
J14-5
U6 TP14 J4-12
R35 CHAMBER O/P
SAMPLE 9 J14-9
J4-7
D22 & HOLD CH 4 GROUND

S1A R36
GENERATOR CONTROL BOARD AEC BOARD

THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 734614 DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE
Use and disclosure is subject to the restrictions DRAWN DATE
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 14 APR 2008
on the title page of this CPI document.
CHECKED AEC
THE +/- 12V OUTPUTS ON J1 TO J4 AND J11 TO J14 ARE NOT SHOWN ON DESIGNATES A FACTORY CONFIGURED LOGIC OR SIGNAL LEVEL. AEC BZ 29 APR 2008
THIS DIAGRAM. THESE ARE DETAILED ON THE CONNECTOR PIN OUT BOARDS ARE CONFIGURED AT THE TIME OF ORDER TO BE COMPATIBLE DES.\MFG.\AUTH.
TABLES IN CHAPTER 3D. * WITH THE SPECIFIED AEC CHAMBER(S). FOR EXAMPLE, THE START
JAC
MD-0936 REV A
** SIGNAL TO THE CHAMBER MAY BE FACTORY CONFIGURED TO BE ACTIVE 28 MAY 08
R79 ADJUSTS THE +45V, +300V, AND +500V OUTPUTS FROM THE DC TO DC LOW (0 V), ACTIVE HIGH (+12 V), OR ACTIVE HIGH (+24 V). SHEET 2 OF 7
CONVERTER CIRCUIT. REFER TO CHAPTER 3D FOR DETAILS.
 AEC CH 1 AEC CH 3
LEFT 1 LEFT 1
SELECT SELECT
2 2
JW1 JW5
RIGHT 3 R5 RN1 RN1 RIGHT 3 R6 RN2 RN2
3 6 7 2 J1-2 3 6 7 2 J3-2
SELECT ANODE (R) SELECT ANODE (L)
2 J1-5 2 J3-5
R69 - CATH (R) R70 - CATH (L)
1 RN1 RN1 1 RN2 RN2
3 4 5 8 1 J1-1 3 4 5 8 1 J3-1
ANODE (M) ANODE (M)
+ +
U4A U5A
U2A J1-6 U3A J3-6
CATH (M) CATH (M)

R10

R50
J1-3 J3-3
ANODE (L) ANODE (R)
J1-4 J3-4
CATH (L) CATH (R)
MIDDLE MIDDLE
SELECT J1 (shell) SELECT J3 (shell)
R13 RN7 RN7 GROUND R14 RN8 RN8 GROUND
3 6 7 2 3 6 7 2

R9 - 6 R11 - 6
7 RN7 RN7 7 RN8 RN8
+ 5 4 5 8 1 + 5 4 5 8 1
U4B U5B
U2B U3B

R7

R8
RIGHT 1 J11-5 RIGHT 1 J13-5
ANODE (R) ANODE (L)
SELECT J11-6 SELECT J13-6
2 CATH (R) 2 CATH (L)
JW2 J11-3 JW6 J13-3
3 ANODE (M) 3 ANODE (M)
LEFT R27 RN9 RN9 J11-4 LEFT R28 RN10 RN10 J13-4
3 6 7 2 CATH (M) 3 6 7 2 CATH (M)
SELECT SELECT
2 J11-1 2 J13-1
R22 - ANODE (L) R23 - ANODE (R)
1 RN9 RN9 1 RN10 RN10
3 4 5 8 1 J11-2 3 4 5 8 1 J13-2
CATH (L) CATH (R)
+ +
U4C U5C
U8A J11-7 U9A J13-7

R16

R17
CH 1 CH 3
SELECT U4D SELECT U5D

CH 1 CH 3
OUT OUT
(SHT 4) (SHT 4)

AEC CH 2 AEC CH 4
LEFT 1 LEFT 1
SELECT SELECT
2 2
JW3 JW7
RIGHT 3 R43 RN11 RN11 RIGHT 3 R44 RN12 RN12
3 6 7 2 J2-2 3 6 7 2 J4-2
SELECT ANODE (R) SELECT ANODE (L)
6 J2-5 6 J4-5
R40 -
CATH (R) R41 - CATH (L)
7 RN11 RN11 7 RN12 RN12
5 4 5 8 1 J2-1 5 4 5 8 1 J4-1
ANODE (M) ANODE (M)
+ +
U14A U15A
U8B J2-6 U9B J4-6
CATH (M) CATH (M)
R33

R34
J2-3 J4-3
ANODE (L) ANODE (R)
J2-4 J4-4
CATH (L) CATH (R)
MIDDLE MIDDLE
SELECT J2 (shell) SELECT J4 (shell)
R51 RN13 RN13 GROUND R52 RN14 RN14 GROUND
3 6 7 2 3 6 7 2

R47 - 2 R49 - 2
1 RN13 RN13 1 RN14 RN14
+ 3 4 5 8 1 + 3 4 5 8 1
U14B U15B
U16A U17A
R45

R46
RIGHT 1 J12-5 RIGHT 1 J14-5
ANODE (R) ANODE (L)
SELECT J12-6 SELECT J14-6
2 CATH (R) 2 CATH (L)
JW4 J12-3 JW8 J14-3
3 ANODE (M) 3 ANODE (M)
LEFT R57 RN15 RN15 J12-4 LEFT R58 RN16 RN16 J14-4
3 6 7 2 CATH (M) 3 6 7 2 CATH (M)
SELECT SELECT
6 J12-1 6 J14-1
R55 - ANODE (L) R56 - ANODE (R)
7 RN15 RN15 7 RN16 RN16
5 4 5 8 1 J12-2 5 4 5 8 1 J14-2
U14C
+
CATH (L) U15C
+
CATH (R)
U16B J12-7 U17B J14-7

R54
R53

CH 2 CH 4
SELECT U14D SELECT U15D

CH 2 CH 4
OUT OUT
(SHT 4) (SHT 4)

THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 737992. THIS DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES”
PAGE SHOWS THE INPUT CIRCUITS; THE SIGNAL PROCESSING THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE DRAWN DATE
CIRCUITS ARE CONTINUED ON THE NEXT PAGE. LOGIC LEVEL (0V = OFF, 5V = ON). G. SANWALD 14 APR 2008
CHECKED AEC
BZ 29 APR 2008
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. DES.\MFG.\AUTH.
JAC
MD-0936 REV A
28 MAY 08
Use and disclosure is subject to the restrictions on the title page of this CPI document.
SHEET 3 OF 7
 +5V +5V +5V +5V

8 7 6 5

RN3

RN3

RN3

RN3
1 2 3 4 U6
DS4 DS3 DS2 DS1
J7-2 J5-2 R67 2 18 CH 1 OUT
CHAMBER 4 SELECT CH 4 SELECT (FROM SHT 3)

J7-3 J5-3 R66 3 17

CHAMBER 3 SELECT CH 3 SELECT

J7-4 J5-4 R65 4 16

CHAMBER 2 SELECT CH 2 SELECT

J7-5 J5-5 R64 5 15

CHAMBER 1 SELECT CH 1 SELECT
INVERTING
BUFFER

J7-6 J5-6 D28 6 14

START
J7-7 J5-7 R63 7 13
RIGHT FIELD SELECT RIGHT SELECT
J7-8 J5-8 R62 8 12
MIDDLE FIELD SELECT MIDDLE SELECT CH 2 OUT
J7-9 J5-9 R61 9 11 (FROM SHT 3)
LEFT FIELD SELECT LEFT SELECT

+5V
R15

R36
TP1 10 R18

FROM +12V +5V

PAGE 1 U1 R21
R39
Q2
+5 V TP2 11
REGULATOR
R35
- 2
J7-13 J5-13 1
+ 3
CH 3 OUT
TP6 TP7 U12A (FROM SHT 3)
FROM J7-17 J5-17 R38
MD-0831
J7-11 J5-11 R25
-12V
R42 R29
- 6
7
CH 1 + 5
SELECT U11B

R59 R1
4 TP3 CH 2 6- R32
TP4 7
2 SELECT 5+

R31
C31
R26 U12B
J7-15 J5-15

R37
PT RAMP R60 R2
- 2
J7-10 J5-10 1 CH 3
PT REF + 3 SELECT CH 4 OUT
J7-1 J5-1 (FROM SHT 3)
PT STOP U11A
+12V R3
CH 4
R19

+5V SELECT
R20

SAMPLE
R4 & HOLD
3 D37
R12

R24
TP5
D38 R30
- 3
7
+ 2
U10

GENERATOR CONTROL BOARD AEC BOARD

THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 737992. THIS DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES”
PAGE SHOWS THE SIGNAL PROCESSING CIRCUITS; THE INPUT THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE DRAWN DATE
CIRCUITS ARE SHOWN ON THE PREVIOUS PAGE. LOGIC LEVEL (0V = OFF, 5V = ON). G. SANWALD 14 APR 2008
CHECKED AEC
BZ 29 APR 2008
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS.
DES.\MFG.\AUTH.
JAC
MD-0936 REV A
28 MAY 08
Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 4 OF 7
 LEFT AEC CH 1
+5V +5V +5V +5V SELECT
JW8 NO CONNECTION N/C
+5V 1
J1-2

R51
R49

R50

R52
2 LEFT/RIGHT
3 J1-6
U6 RIGHT RIGHT/LEFT

R39
DS1 DS2 DS3 DS4 SELECT MIDDLE J1-3
R61 +12V JW7 MIDDLE
J7-2 J5-2 2 18 SELECT
CHAMBER 4 SELECT +12V
CH 4 SELECT START/ 1 J1-4
START RESET/START
2
R62 R40 D12 3 TP1 J1-8
J7-3 J5-3 3 17 Q5 +12V
CHAMBER 3 SELECT CH 3 SELECT 9
R1 J1-5
START CHAMBER O/P
J7-4 J5-4 R63 4 16
CHAMBER 2 SELECT CH 2 SELECT R38 CH 1 J1-7
Q4 SELECT -12V
J7-5 J5-5 R64 5 15 J1-9
CHAMBER 1 SELECT GROUND
CH 1 SELECT U1D R2
INVERTING -12V
BUFFER
LEFT AEC CH 2
SELECT
J7-6 J5-6 D20 6 14 JW6 NO CONNECTION N/C
START
R66 1
J7-7 J5-7 7 13 J2-2
RIGHT FIELD SELECT 2 LEFT/RIGHT
R67 3 J2-6
J7-8 J5-8 8 12 RIGHT/LEFT
MIDDLE FIELD SELECT RIGHT
J7-9 J5-9 R68 9 11 SELECT MIDDLE J2-3
LEFT FIELD SELECT JW5 MIDDLE
SELECT
+12V
1 J2-4
START RESET/START
2
+12V +12V +12V 3 TP2 J2-8
9 +12V
R3 J2-5
CHAMBER O/P
+12V +5V D11 D10 D9
CH 2 J2-7

R37

R36

R35
U3 LEFT MIDDLE RIGHT SELECT -12V
SELECT SELECT SELECT J2-9
+5 V GROUND
FROM U1C R4 -12V
REGULATOR Q3 Q2 Q1
PAGE 1

J7-13 J5-13
LEFT AEC CH 3
SELECT
TP11 TP12 JW4 NO CONNECTION N/C
1
J7-17 J5-17 J3-2
FROM 2 LEFT/RIGHT
MD-0831 TP7 13 CH 1 SELECT 3 J3-6
RIGHT RIGHT/LEFT
J7-11 J5-11 SELECT MIDDLE J3-3
-12V - R11 JW3 MIDDLE
CH 2 SELECT SELECT
START/ +12V
+
1 J3-4
START RESET/START
U4A 2
R12 3 TP3 J3-8
CH 3 SELECT 9 +12V
* R5 J3-5
CHAMBER O/P
R13 CH 3
CH 4 SELECT J3-7
SELECT -12V
-
J3-9
+ R14 GROUND
TP9 4 TP8 U1B R6 -12V
2 U8B

J7-15 J5-15 R30 - LEFT AEC CH 4

PT RAMP + TP5 12 SELECT
J7-10 J5-10 TP6 JW2 NO CONNECTION N/C
PT REF U4B
7 1
J4-2
J7-1 J5-1 2 LEFT/RIGHT
PT STOP +5V +12V 3 J4-6
- RIGHT RIGHT/LEFT
-
SELECT
R32

R31

+ MIDDLE J4-3
JW1 MIDDLE
R69

R34

+
SELECT
U7A +12V
U8A 1 J4-4
START/ START RESET/START
3 2
D25 3 TP4 J4-8
R33 +12V
TP10 9
R7 J4-5
CHAMBER O/P
D27 3
7
-
SAMPLE CH 4 J4-7
+ 2 & HOLD SELECT -12V

U9 J4-9
GROUND
U1A R8 -12V

GENERATOR CONTROL BOARD AEC BOARD

THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 737998 DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE DRAWN DATE
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 14 APR 2008
CHECKED AEC
BZ 29 APR 2008
DES.\MFG.\AUTH.
JAC
MD-0936 REV A
28 MAY 08
Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 5 OF 7
 +5V LEFT +12V
+5V +5V AEC CH 1
+12V JW8
1 J1-8
+12 V

R39
2

R49

R50
D29 3 J1-2
LEFT/RIGHT
U6 STRT RIGHT J1-6
DS1 DS2 INVERTED RIGHT/LEFT
R40 JW7
J7-2 J5-2 R61 2 18 R71 Q5 J1-4
CHAMBER 4 SELECT Q7 1 START RESET/START
+12V +12V 2 J1-3
R62 3 MIDDLE MIDDLE
J7-3 J5-3 3 17
CHAMBER 3 SELECT J1-11
D28 D12 9 PORTRAIT PORTRAIT
TP1 J1-13
J7-4 J5-4 R63 4 16
CHAMBER 2 SELECT CH 2 INVERTED INVERTED
PORTRAIT START CH 1
R2 R1 J1-5
R64 R70 R38 CHAMBER O/P
J7-5 J5-5 5 15 Q6 Q4 U1D
CHAMBER 1 SELECT CH 1 J1-7
INVERTING -12 V
BUFFER J1-9
GROUND
-12V
J7-6 J5-6 D20 6 14
START
J7-7 J5-7 R66 7 13 LEFT +12V
RIGHT FIELD SELECT AEC CH 2
J7-8 J5-8 R67 8 12 JW6
MIDDLE FIELD SELECT 1 J2-8
R68 +12 V
J7-9 J5-9 9 11 2
LEFT FIELD SELECT 3 J2-2
LEFT/RIGHT
+12V +12V +12V
RIGHT J2-6
RIGHT/LEFT
JW5
D11 D10 D9 J2-4
1 START RESET/START

R37

R36

R35
J7-19 J5-19 2 J2-3
+24V LEFT MIDDLE RIGHT 3 MIDDLE MIDDLE
J2-11
J7-13 J5-13 Q3 Q2 Q1 9 PORTRAIT PORTRAIT
+12V TP11 TP12 TP2 J2-13
FROM FROM INVERTED INVERTED
J7-17 J5-17 CH 2
PAGE 1 MD-0831 R4 R3 J2-5
CHAMBER O/P
U1C J2-7
J7-11 J5-11 -12 V
-12V
J2-9
GROUND
5 TP7 -12V

STRT

R11 S2B
TP8 4 CH 1
TP9 2
U2A
J7-15 J5-15 R30 R12
PT RAMP CH 2
J7-10 J5-10 R32 -
PT REF U2B
+ R4
U8B

TP6 7
+5V TP5 12
R69

-
J7-1 J5-1 -
+
PT STOP +
U4A
U4B -
+12V D27 -
+
+
U7A
D25 R33 U8A STRT
R34

R31
- 3
7
+ 2
SAMPLE
U9 & HOLD

TP10 3
GENERATOR CONTROL BOARD AEC BOARD

THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 739389 DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE DRAWN DATE
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 14 APR 2008
CHECKED AEC
BZ 29 APR 2008
DES.\MFG.\AUTH.
JAC
MD-0936 REV A
28 MAY 08
Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 6 OF 7
 NOTE
REMARKS
REFERENCE
1 GENERATES A PULSE PER FIGURE 1 WHEN THE AEC RAMP IS APPROXIMATELY 5 % OF THE AEC REFERENCE IF THE AEC RAMP IS ON THE CORRECT TRAJECTORY.
2 AEC REFERENCE VOLTAGE, 0 TO +10 VDC, DEPENDING ON AEC TECHNIQUE. THE LENGTH OF THE AEC EXPOSURE IS PROPORTIONAL TO THE AEC REFERENCE VOLTAGE.
3 AEC STOP (PT STOP) SIGNAL. THIS IS NORMALLY HIGH (APPROXIMATELY +5 VDC), SWITCHING LOW WHEN THE AEC RAMP = THE AEC REFERENCE VOLTAGE. REFER TO FIGURE 1.
4 AEC RAMP. THIS IS A SIGNAL RAMPING FROM 0 TOWARD +10 VDC, THE ACTUAL MAGNITUDE WILL DEPEND ON THE AEC TECHNIQUE. REFER TO FIGURE 2.
5 AS PER # 4.
6 PWM OUTPUT. THIS WILL BE VARIABLE WIDTH PULSES (PULSE WIDTH INCREASING AT INCREASING LOAD), UP TO A MAXIMUM OF 50% DUTY CYCLE. REFER TO FIGURE 4.
7 AEC RAMP OR DC VOLTAGE. THIS IS A RAMP OR DC VOLTAGE, DEPENDING ON AEC CHAMBER TYPE (INTEGRATING OR NON-INTEGRATING). REFER TO FIGURE 3.
8 AS PER # 7, EXCEPT THAT THE RAMP OR DC VOLTAGE WILL BE POSITIVE GOING AND NOT OF THE SAME MAGNITUDE.
9 THE VOLTAGE AT THIS TEST POINT IS THE OUTPUT OF THE AEC CHAMBER. REFER TO THE AEC CHAMBER MANUFACTURERS DOCUMENTATION FOR DETAILS.
10 THIS IS THE START SIGNAL. “HIGH” (5 VDC) = START = ANALOG SWITCHES CLOSED, “LOW” (0 VDC) = START = ANALOG SWITCHES OPEN.
11 THIS WILL BE A POSITIVE DC VOLTAGE. THE MAGNITUDE OF THE DC VOLTAGE IS DEPENDENT ON THE AEC TECHNIQUE IN USE.
12 AS PER # 7, EXCEPT THAT THE POLARITY WILL BE POSITIVE.
13 THE POLARITY AND MAGNITUDE OF THE RAMP AT THIS POINT SHOULD BE APPROXIMATELY THE SAME AS THE PT RAMP OUTPUT. NOTE REFERENCE 4.

+5 V
FIGURE 1
0V
AEC STOP
<10 VDC
FIGURE 2
0V

0V
FIGURE 3 OR
< -10 VDC

INTEGRATING NON-INTEGRATING
AEC CHAMBERS AEC CHAMBERS

200 kHz

12 VDC
FIGURE 4
0 VDC

DRAWN DATE
G. SANWALD 14 APR 2008
CHECKED AEC
BZ 29 APR 2008
DES.\MFG.\AUTH.
JAC
MD-0936 REV A
28 MAY 08
Use and disclosure is subject to the restrictions on the title page of this CPI document.
SHEET 7 OF 7
 +3.3V +3.3V

R242
+5V +5V +5V +5V +5V +5V +5V +5V

R11
DS2 DS3 DS2 DS3 DS4 DS12 DS7 DS8
DS1 TXD RXD DS1
1 Hz TXD RXD AUX2 AUX2 AUX AUX
U21 1 TXD RXD U77

R361

R362
U8 RXD TXD 1 Hz

R19

R20

R81

R94

R69

R61
RS-232
U4 TP10 TP11
U6
U71
DATA R23 J8-1 J3-1 R41
BUFFER DATA
3.3V-5V R54 BUFFER
U14 5V-3.3V

DATA R24 J8-2 J3-2 U65

BUFFER R40
5V-3.3V DATA
FPGA R37 BUFFER
3.3V-5V

U95
J21-2 R365

J21-8 R366

RS-232
+5V +5V COM PORT J21-3 R363
(AUX 2) CPU
J21-7 R364
DS4 DS5
RXD TXD J21-5 U13
U71
R59
DATA
R21

R22
R73 BUFFER
RS-232 5V-3.3V
U11
RS-232 J4
U4 U65
R25 R68
DATA 3 TXD DATA
BUFFER R26 R56 BUFFER
3.3V-5V 7 RTS 3.3V-5V
U14
R27
DATA 2 RXD
BUFFER R28
5V-3.3V 8 CTS

5
DATA BUS
D0..D7
CONSOLE BOARD (MEMBRANE CONSOLE)

J28-1 J20-1

J28-2 J20-2 DATA BUS

TO INTERNAL D0..D7
COMMUNICATION J28-4 J20-4
CIRCUITS
J28-5 J20-5

TOUCH-SCREEN BOARD (TOUCHSCREEN CONSOLE)

J22-2

J22-8
RS-232 J22-7
COM PORT
(AUX) J22-3

1 A PULSE TRAIN WILL BE OBSERVED AT TP10, TP11 DURING J22-5

CONSOLE - GENERATOR COMMUNICATION. THE TXD AND RXD
LEDs ON THE CONSOLE BOARD AND GENERATOR CONTROL BOARD GENERATOR CONTROL BOARD
WILL FLASH TO INDICATE THE PRESENCE OF THESE PULSES.

DRAWN DATE
G. SANWALD 14 APR 2008 SERIAL
CHECKED COMMUNICATIONS
J.B 28 AUG 2008
DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. MD-0937 REV C
J.B 28 AUG 2008
SHEET 1 OF 1
 +15V

F1

R10
Q2

R8

R15
Q3
J4-1
SWITCHED +15V

R11
U19 U20
R353 J4-6
TEST +15V
J4-7
TEST +15V
DATA J4-2
DRIVER + DOSE
LATCH
J4-3 DAP
- DOSE
+5V +5V J4-4
CHAMBER
OPTO
J4-5
RELAY

R5

R6
J4-8
U1 GROUND
U77 U78
J4-9
DATA GROUND
RS-485
CPU BUFFER
TRANCEIVER
5V-3.3V

+5V

R4
R3
Q1

R2

D1
1 JW14

2 Opto-coupler

3 Direct

+5V

DATA BUS 5 6 1
D0..D7

U94 D55

4 3

GENERATOR CONTROL BOARD

DRAWN DATE
G. SANWALD 14 APR 2008
CHECKED DAP
GW 7 MAY 2008
DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. L. FOSKIN 07/MAY/2008
MD-0938 REV B
SHEET 1 OF 1
 U5 U4 +24V

F3 J25-3
J25-22
J25-1
DATA
LATCH DRIVER J25-20
J25-2
J25-21

J25-4
J25-23
J25-5

R355

R356
J25-24

R357
J25-6

R358
J25-25

R359
+24V +24V +24V +24V +24V +24V +24V +24V +24V +24V

+24V

R360
+24V

R29

R30

R31

R32

R53

R50
9 J25-7
4 8
6 10 J25-26
5 Q9 Q10 Q11 Q12 Q14 Q15
U37C J25-29
U37B OUTPUTS TO

R22

R23

R24

R25

R48

R49
U37D
U40 DIGITAL IMAGING
12 11 D7 D8 D9 D10 D16 D11 SYSTEM
HV ON MONOSTABLE
13 TIMER
FROM MD-0932
PG 1 U31
J25-34
DIFFERENTIAL
DATA J25-16
BUFFER

U35
J25-33
DIFFERENTIAL
DATA J25-15
BUFFER
U30
EXPOSURE ENABLE J25-32
DIFFERENTIAL
TO PG 2 DATA J25-14
BUFFER
U28
J25-31
DIFFERENTIAL
DATA J25-13
BUFFER
U21
J25-30
DIFFERENTIAL
DATA J25-12
BUFFER
U19 U20

DATA +12 V
LATCH DRIVER

J19-1 J1-1

J19-2 J1-2 DS1 DS3

RAD PREP
EXP X-RAY MINI-
LS1 LS2 CONSOLE

DATA, ADDRESS, J19-4 J1-4

AND CONTROL BUS J19-3 J1-3
J19-7 J1-7
J19-8 J1-8

GENERATOR CONTROL BOARD MINI-CONSOLE BOARD

THIS SHEET SHOWS THE DIGITAL OUTPUTS. DRAWN DATE

G. SANWALD 14 APR 2008 DIGITAL
CHECKED INTERFACE
Use and disclosure is subject to the restrictions on the title page of this CPI document. GW 8 MAY 2008
DES.\MFG.\AUTH.
MD-0926 REV A
J.B. 26 AUG 2008
SHEET 1 OF 2
 +5V +5V +5V +5V +5V +5V +5V +5V

R55

R58

R60

R64

R67

R72

R82

R80
U18

DATA U46
BUFFER J25-36
DIFFERENTIAL
DATA J25-18
BUFFER

+24V +24V +24V +24V J25-11

J25-10
4 1 4 1 4 1 4 1 4 1

R95
U12 U16 U17 U22 U36

R86
3 2 3 2 3 2 3 2 3 2 4 1
U29

R121
4 1
R63

R66

R76

R79
3 2 U23
3 2

R96
R62

R65

R75

R78

R92
INPUTS FROM
DIGITAL IMAGING
SYSTEM
X-RAY ENABLE
TO MD-0931
1 4 PG2
Mfg / Design Engineering
U11
2 3

EXPOSURE ENABLE
FROM PG 1
J25-35
J25-17
J25-28
J25-9
J25-27
J25-8

DATA, ADDRESS,
AND CONTROL BUS

GENERATOR CONTROL BOARD

THIS SHEET SHOWS THE DIGITAL INPUTS.

DRAWN DATE
Use and disclosure is subject to the restrictions on the title page of this CPI document. G. SANWALD 14 APR 2008 DIGITAL
CHECKED INTERFACE
GW 8 MAY 2008
DES.\MFG.\AUTH.
MD-0926 REV A
J.B. 26 AUG 2008
SHEET 2 OF 2
 FAN VOLTAGE J26-1
REGULATOR
& J26-3
CONTROL
CIRCUIT
100mV / deg C
+5V
TP34 +12V
+12V

R396
R162

R393
R377 U97

R320
2- R395
R279 1
3+
J1-3 J17-3
2-
INVERTER J1-2 J17-2 R291 R280 1
3+ R394

R391
TEMP
SENSOR J1-1 J17-1 U79A

R162
R284
C158 U45

A/D
CONV

R163
THERMAL SENSOR
BOARD
(LOCATED ON
INVERTER HEAT SINK)

+5V +5V +5V

R313

R323

R307
U87

DATA
BUFFER
JW12 1 JW2 1 JW13 1

No fan 2 Normal 2 125 kV 2

Fan 3 Upgrade 3 150 kV 3

DATA BUS
D0..D7

GENERATOR CONTROL BOARD

DRAWN DATE
G. SANWALD 14 APR 2008 TEMP SENSOR /
CHECKED PROG JUMPERS
GW 8 MAY 2008
DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document. MD-0925 REV B
JAC 27 AUG 2008
SHEET 1 OF 1
 STATOR OUTPUT
(LOW SPEED STARTER)
SEE MD-0935

BUCKY 1 IN/OUT, SEE MD-0927

THERMAL SWITCH INPUT
BUCKY 2 IN/OUT, INTERLOCK I & 2 SHEET 1, 2, 3
SEE MD-0930
DOOR INTERLOCK INPUTS
SEE MD-0930 SEE MD-0930
“SOFT START” BUS
AC MAINS FROM VOLTAGE TO DC
LINE FUSES BUS CAPACITORS
J4 J2 J7
PRIMARY OF
AUXILIARY TRANSFORMER J9 J8
SEE MD-0927 SHEET 1, 2, 3
24 VAC & 24 H.V. AUXILIARY BOARD
VDC OUT, ROOM J5
J11
LIGHT OUT
SEE MD-0930 J10
SECONDARY OF 12 VDC DRIVE FOR MAIN
J6
AUXILIARY TRANSFORMER J3 POWER CONTACTOR
J1
SEE MD-0927 SHEET 1, 2, 3 SEE MD-0927 SHEET 1, 2, 3

FOR CPI
USE ONLY
TO TOUCHSCREEN CONSOLE
SEE MD-0927 AND MD-0937 SEE NOTE
BELOW

J4
FROM DAP J20 J3
J19 J2
CHAMBER J4
J12 J15
SEE MD-0938 J8 INTERNAL SYSTEM
J21 J22 GROUNDS
J2 J1
J3
DIGITAL INTERFACE J25
SEE MD-0926 TO X-RAY MINI-CONSOLE J26
SEE MD-0926
X-RAY TUBE
J5 HOUSING GROUND
HT TANK
CONTROL BOARD
FILAMENT SUPPLY
J13 BOARD

J6

J10

J14
J9 J16
INVERTER J5
J23 J24 J7 J18 J11 J17 TEMP SENSOR
SEE MD-0925

FOR CPI
USE ONLY
DRAWN DATE
G. SANWALD 14 APR 2008
INTERCONNECT
CHECKED
DIAGRAM
SB 11 SEPT/08 (CMP 200 R )
DES.\MFG.\AUTH.
NOTE: J2 CONNECTS TO AN EXTERNAL EMERGENCY POWER-OFF SWITCH AND ALSO SUPPLIES POWER FOR MD-0939 REV D
Use and disclosure is subject to the restrictions L. FOSKIN 11/SEPT/2008
AN INSTALLER-SUPPLIED POWER DISTRIBUTION RELAY. REFER TO MD-0927 SHEETS 1-3, MD-0928, AND TO
on the title page of this CPI document. SHEET 1 OF 3
CHAPTER 2 OF THE SERVICE MANUAL FOR DETAILS.
 ALTERNATE CONNECTION:
CANON SINGLE CONSOLE
J4

J2
J4 J3
J20 J3
J2
J21 J12 J15
J8
J22 J19
RESONANT E10
J25 RS-232 PORT (AUX) INVERTER BOARD INDUCTOR &
SEE MD-0937 J26 E9
CAPACITOR
J1
RS-232 PORT (AUX 2) J5
SEE MD-0937 HT TANK

J13
E17 E18
CONTROL BOARD
J6
mA/mAs PORT

J10

J14
J9 J16

J23 J24 J7 J18 J11 J17

THIS APPLIES TO UNITS WITH ONE INVERTER BOARD (32 / 40 kW). SEE PAGE 3 FOR UNITS WITH TWO INVERTER BOARDS (50 / 65 / 80 kW UNITS)

J1

TO RS-232 PORT TO
HAND SWITCH LAPTOP COMPUTER E11
SEE MD-0931 SEE MD-0937 DUAL SPEED
J3 J4
J8 STARTER BOARD
(OPTIONAL)

STATOR OUTPUT FROM EMC

TB2 (DUAL SPEED STARTER) CAPACITOR
SEE MD-0924 BOARD
SEE MD-0924
E10

E9

CONSOLE BOARD DATE

DRAWN INTERCONNECT
G. SANWALD 14 APR 2008
CHECKED
DIAGRAM
SB 11 SEPT/08 (CMP 200 R )
DES.\MFG.\AUTH.
L. FOSKIN
MD-0939 REV D
11/SEPT/2008

Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 2 OF 3
 J2

J4
J20 J3
J2
J21 J12 J15 J4
J8 INVERTER BOARD
J22 J19

J1 J3
J25
J26

J5
RESONANT / SHARING
INDUCTOR & RESONANT E10
CONTROL BOARD CAPACITOR E9
J13

J6 HT TANK

J10
E17 E18
J14
J9 J16 J2
mA/mAs PORT
J23 J24 J7 J18 J11 J17

INVERTER BOARD

J1

AEC BOARD (OPTIONAL)

REFER TO MD-0936
AND CHAPTER 3D
OF SERVICE MANUAL

J5
THIS APPLIES TO UNITS WITH TWO INVERTER BOARDS (50 / 65 / 80 kW). SEE PAGE 2 FOR UNITS WITH ONE INVERTER BOARD (32 / 40 kW UNITS)

DRAWN DATE
G. SANWALD 14 APR 2008
INTERCONNECT
CHECKED
DIAGRAM
SB 11 SEPT/08 (CMP 200 R )
DES.\MFG.\AUTH.
L. FOSKIN
MD-0939 REV D
11/SEPT/2008

Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 3 OF 3