Experiments performed

Part 1

Lab 3

Logic inverter (using MOS)

As given in the lab sheet, the circuit for inverter circuit was made on bread board. Also it was observed
that delay time ie.t PHL and tPLH increases when a load capacitor of 150 pF was put in parallel at the
output side

LED driver (Frequency response)

Here R2 was taken as 500 ohm and frequency of input signal was varied and time taken for it
was observed that beyond 25-30 Hz frequency , it could no longer be distinguished as blinking and it
appeared to be glowing with constant intensity.

Automatic Shutoff Switch

The delay time was observed for 2 values of capacitances namely 0.033uF and 0.0033uF respectively.
And the times obtained were 34s and 3.32 s respectively. Thus we can give an estimate for reverse bias
current to be around 0.033*5*1e-6/34= 4.98 nA in first case and 0.0033*5*1e-6/3.32= 4.96 nA in
second case.
This observation was made for diode 1N4148.

Lab 4A

Inverter switch

Again the principal observation made in this case was that delay times namely .t PHL and tPLH increase
when a capacitive load was put in parallel at the output terminal.

VCO oscillator circuit

In this part three MOS were connected to generate an oscillation and frequencies were recorded on IC
CD 4007(NMOS).

The graph of frequency(MHz) vs . Vdd (in V)

Frequency vs Vdd measurment

12
Frequency in MHz

10
8
6
4
Series1
2
0
0 2 4 6 8 10 12
Vdd in V
 Part 2

LAB 3

The experiment was performed with R1= 14.4k and R2=9.6k, R=17.2 k

Observations : One output terminal (1) was observed to produce rectangular waveform with duty cycle
of 50% with maximum and minimum values of 15V and -15V. The triangular waveform(2) was observed
to have a peak value of 10V and -10V which is quite close to theoretical value of R2/R1 *Vcc.

a) C=0.1uF

We can calculate time period of the waveform to be (R2/R1)*4*R*C which can be calculated to be
4.32ms where as the observed time period was 3.44 ms.

Possible reason for the difference: Maybe the value of capacitance was not very accurate leading to this
discrepancy.

b) C=0.33uF

We can calculate expected time period to be 17 ms where as observed time period to be 17ms.

Possible reason for the difference: Maybe the value of capacitance was not very accurate leading to this
discrepancy.

Second part: Duty cycle adjustment with Vext

 Duty cycle
0.6

0.5

0.4
Duty cycle

0.3

0.2 Duty cycle

0.1

0
0 2 4 6 8 10 12
Vext in V

This observed relation is very close to calculated formula Duty cycle= ½(1-Vext/Vcc)

Lab 5

Frequency response of butter worth filter

In this filter R1=R2=R3 = 12k ohms along with C2=0.02uF and C3=0.005 uF .The observed
frequency response is shown in graph below.
 log (gain)
0
0 1000 2000 3000 4000
-0.2

-0.4
log (gain)

-0.6

-0.8 log (gain)

-1

-1.2

-1.4
Freq in Hz

Using this filter, square pulses of frequency around 1kHz could be converted into sine waves of around
same frequency.

Expt which did not work as expected:

However “sample and hold “ part did not work when the gate voltage was moved to low input voltage
which made the output voltage fall down to zero rather than staying at the value at which it was when
sampled