SXoM Reference Manual B.01

REFERENCE MANUAL
SXoM-C5 Reference Manual
Revision B.01
Date: 30.04.2015
Author: T. Ritter, S. Heider, M. Schetter, Dr. R. Tzschoppe

Table of Contents
ABOUT THIS DOCUMENT 5

HISTORY 5
RELEASES 5
AUTHORS 5
REFERENCED DOCUMENTS 6
LIST OF ABBREVIATIONS 6
1. INTRODUCTION 7
1.1 PURPOSE OF THE BOARD 7
1.2 FEATURE LIST 7
2. ARCHITECTURE 8
2.1 LAYOUT 8
2.2 BLOCK DIAGRAM 9
2.3 ELECTRICAL DESCRIPTION 9
2.4 MECHANICAL DESCRIPTION 10
2.5 T HERMAL CONCEPT 11
3. FEATURES 12
3.1 OVERVIEW 12
3.2 DDR3 MEMORY FOR THE CPU 13
3.3 DDR3 MEMORY FOR THE FPGA 14
3.4 QSPI FLASH 15
3.5 PCI EXPRESS (PCIE) 16
3.6 HIGH-SPEED CAMERA INTERFACE 17
3.7 GENERAL PURPOSE GIGABIT T RANSCEIVER 18
3.8 CSI-2 / HISPI 19
3.9 USB HOST (ULPI) 19
3.10 USB DEVICE (VIA USB-TO-SERIAL UART/FIFO IC TO COMPANION FPGA) 20
3.11 ETHERNET 10/100/1000 (RGMII) 21
3.12 24-LCD INTERFACE 23
3.13 SDIO 24
2
3.14 I S 24
3.15 CAN 25
3.16 SPI 25
3.17 UART 26
2
3.18 I C 27
3.19 JTAG 28
3.20 GPIO 29
Revision B.01 Page 2 of 39 30.04.2015

3.21 WATCHDOG SIGNAL 29

3.22 LEDS 30
3.23 BOOT OPTIONS 31
3.24 SMARC CONNECTOR 32
3.25 CLOCK CIRCUITRY 37
3.26 POWER SUPPLY 38
3.27 RESET 39
List of Figures
Figure 1: SXoM-C5 Rev. B, top side layout..........................................................................................8
Figure 2: SXoM-C5 Rev. B, bottom side layout ....................................................................................8
Figure 3: SXoM-C5 block diagram .......................................................................................................9
Figure 4: SXoM-C5 mechanical description from [4] .......................................................................... 10
Figure 5: Maximum heights under and above the module from [4] ..................................................... 10
Figure 6: Debug LEDs on top side of the SXoM-C5 ........................................................................... 30
Figure 7: Standard clock configuration .............................................................................................. 37
Figure 8: Power supply architecture .................................................................................................. 38
List of Tables
Table 1: History ...................................................................................................................................5
Table 2: Releases ...............................................................................................................................5
Table 3: Authors .................................................................................................................................5
Table 4: Referenced Documents .........................................................................................................6
Table 5: List of Abbreviations ..............................................................................................................6
Table 6: Features overview ............................................................................................................... 12
Table 7: Assignment of signals of the DDR3 memory (for the CPU) to Cyclone V SoC pins ............... 13
Table 8: Assignment of signals of the DDR3 memory (for the FPGA) to Cyclone V SoC pins ............. 14
Table 9: Assignment of signals of the QSPI flash to Cyclone V SoC pins (CPU part) ......................... 15
Table 10: Assignment of PCIe signals of the PCIe switch to Cyclone V SoC pins .............................. 16
Table 11: Pin assignment of the first PCI Express interface on the SMARC connector ....................... 16
Table 12: Pin assignment of the second PCI Express interface on the SMARC connector ................. 16
Table 13: Pin assignment of the high-speed camera interface ........................................................... 17
Table 14: Assignment of general purpose Gigabit transceiver signals to SoC and SMARC pins ......... 18
Table 15: Available general purpose Gigabit Transceiver signals depending on PCIe / CSI0 usage ... 18
Table 16: Assignment of pins for the CSI-2 / HiSPi interface from the SoC to the companion FPGA .. 19
Table 17: Assignment of USB PHY signals of the ULPI interface to Cyclone V SoC pins ................... 19
Table 18: Assignment of USB host interface signals to SMARC connector pins ................................. 19
Table 19: Assignment of transceiver CPEN signal to companion FPGA pin ....................................... 20
Table 20: Assignment of power switch signal from companion FPGA pin to SMARC connector pin ... 20
Table 21: Assignment of USB client interface signals to SMARC connector pins ............................... 20
Table 22: Assignment of UART/FIFO transceiver signals to companion FPGA pins ........................... 20
Table 23: Pin assignment of the Ethernet (RGMII) interface of the SoC ............................................. 21
Table 24: Pin assignment of the link signals to the companion FPGA from the Ethernet transceiver .. 21
Table 25: Pin assignment of the link signals to the companion FPGA from the Ethernet transceiver .. 21
Table 26: Pin assignment of the Gigabit Ethernet interface of the SMARC connector ........................ 22

Table 27: Pin assignment of the 24-bit LCD interface to the SoC ....................................................... 23
Table 28: Pin assignment of the SDIO interface ................................................................................ 24
Table 29: Pin assignment of the SDIO signals to the companion FPGA ............................................. 24
2
Table 30: Pin assignment of the I S interface .................................................................................... 24
Table 31: Pin assignment of the CAN interfaces ................................................................................ 25
Table 32: Pin assignment of the first SPI master interface ................................................................. 25
Table 33: Pin assignment of the second SPI master interface............................................................ 25
Table 34: Pin assignment of the UART0 interface of the CPU............................................................ 26
Table 35: Pin assignment of the UART0 interface of the companion FPGA........................................ 26
Table 36: Pin assignment of the UART interface of the FPGA ........................................................... 26
Table 37: Pin assignment of the I2C interface of the CPU for CSI-2 ................................................... 27
2
Table 38: Pin assignment of the I C interface of the CPU for General Purpose .................................. 27
2
Table 39: Pin assignment of the I C interface of the FPGA for the LCD ............................................. 27
Table 40: Pin assignment of the I2C interface of the FPGA for the Power Management ..................... 27
2
Table 41: Pin assignment of the I C interface of the companion FPGA for the
on-board clock generator and the PCI Express switch .................................................................. 27
Table 42: Pin assignment of the JTAG interface of the FPGA ............................................................ 28
Table 43: Pin assignment of the JTAG interface of the CPU .............................................................. 28
Table 44: Pin assignment of the JTAG interface of the CPU .............................................................. 29
Table 45: Pin assignment of the watchdog interface .......................................................................... 29
Table 46: Debug LEDs for board status indication ............................................................................. 30
Table 47: Boot options of the SoC ..................................................................................................... 31
Table 48: Boot-select interconnection between SMARC connector and companion FPGA ................. 31
Table 49: Companion FPGA and SoC pins for the CPU_POR_N signal............................................. 31
Table 50: Pin assignment of the SMARC connector .......................................................................... 36
Table 51: Reset signals..................................................................................................................... 39

About this Document

This document has been written to provide system engineers and FPGA designers the required
information about how to use Solectrix’ SXoM-C5 system-on-module. Prior knowledge of Altera’s
Cyclone V SoC [1], [2], [3] and the SMARC specification [4] and SMARC design guide [5] are
assumed.
History
Rev. Author / Date Description / Change / Comments

A.01 T. Ritter / First Draft
18.2.2014
A.02 M. Schetter, Adapted to new Solectrix layout, replaced module drawings with photos
S. Heider, of final product, review and subsequent changes / additions
Dr. R. Tzschoppe /
16.12.2014
A M. Schetter, / Prepared for release as preliminary version A.
16.12.2014
B.01 M. Schetter, / Updated document for SXoM-C5 hardware revision B
30.04.2015
Table 1: History
Releases
Rev. Created / Date Signature Checked / Date Signature Released / Signature

Date
A M. Schetter, Dr. R. Tzschoppe, S. Schütz,
16.12.2014 16.12.2014 16.12.2014
B
C
D
Table 2: Releases
Authors
Section Name E-Mail Telephone

Document Thomas Ritter thomas.ritter@solectrix.de +49 (0)911 / 309 161-21
Document Stephan Heider stephan.heider@solectrix.de +49 (0)911 / 309 161-59
Document Michael Schetter michael.schetter@solectrix.de +49 (0)911 / 309 161-23
Document Dr. Roman Tzschoppe roman.tzschoppe@solectrix.de +49 (0)911 / 309 161-55
Table 3: Authors

Referenced Documents
No. Title Description Author Version Date

[1] Cyclone V Device Altera CV-5V2 22.07.2014
Device Handbook Corporation
Handbook –
Volume 1: Device
Interfaces and
Integration
[2] Cyclone V Device Altera CV-5V3 30.09.2014
Handbook –
Volume 2:
Transceivers
[3] Cyclone V Device Altera cv_5v4 30.06.2014
Handbook –
Volume 3: Hard
Processor
System
Technical
Reference
Manual
[4] Smart Mobility Hardware Standardization V1.1 29.05.2014
ARChitecture – Specification Group for
Hardware Embedded
Specification Technologies
(SGET)
[5] Smart Mobility Design Guide Standardization V1.0 09.07.2013
Architecture – Group for
Design Guide Embedded
Technologies
(SGET)
Table 4: Referenced Documents
List of Abbreviations
Abbreviation Description
Table 5: List of Abbreviations

1. Introduction
1.1 Purpose of the Board

The SXoM-C5 is a high-performance system-on-module based on Altera’s Cyclone V SX SoC. Fully
compliant with the SMARC specification [4], it offers a very flexible processing system with a vast
number of interfaces for various purposes on a minimum of space.
1.2 Feature List


1
SoC: Altera Cyclone V SX , package: U672, supported member codes: C2 , C4, C5, C6
o CPU: Dual core Cortex A9 @ 800 MHz
o FPGA: Cyclone V up to 110 Logic Cells
 Companion FPGA: Lattice MachXO2 LCMXo2-1200HC
 Peripherals:
2
o CPU DDR3 memory: 8 Gbit @ 400 MHz 32-bit wide
2
o FPGA DDR3 memory: 8 Gbit @ 400 MHz 32-bit wide
o QSPI flash memory: 256 Mbit
 Interfaces (on SMARC connector)
o 1x Ethernet 10/100/1000
o 1x USB 2.0 Host
o 1x USB 2.0 Device
o 2x UART
o 2x SPI master
o 4x I2C
o 1x I2S
o 2x CAN
o SDIO
o CSI-2 / HiSPi
o 2x JTAG (separate for FPGA and CPU)
o 24 bit parallel LCD
o 2x PCIe Gen2 (up to 5 GT/s) x1
o 12x GPIO
o 4 Rx/Tx 3.125 Gbps Transceiver
 Power Monitoring
 Clock circuitry
o 24 MHz @ 3.3 V for USB PHY
o 25 MHz @ 3.3 V for Ethernet PHY
o 25 MHz @ 3.3 V for PCIe Refclk PLL
o 50 MHz @ 3.3 V for companion FPGA
o 25 MHz @ 1.8 V for CPU part of the SoC
o 100 MHz @ 1.5 V for FPGA part of the SoC
o 148.5 MHz @ 1.8 V for HiSPi interface of the SoC
o External Clock for the Gigabit transceivers via SMARC connector
 Power supply
o Single supply from carrier board with 3.0 V to 5.25 V over 10 pins (5 A in total)
For more detailed information about the offered features please refer to chapter 3.
1
Cyclone V SE SoCs are supported as an option.
2
Other memory sizes are available as an option.

2. Architecture
2.1 Layout
Figure 1 shows the top side of the SXoM-C5, hardware revision B.
Figure 1: SXoM-C5 Rev. B, top side layout
Figure 2 shows the bottom side of the SXoM-C5, hardware revision B.
Figure 2: SXoM-C5 Rev. B, bottom side layout

2.2 Block Diagram

A block diagram of the main components of the SXoM-C5 and its interfaces offered via the SMARC
connector is depicted in Figure 3.
UART
Altera Cyclone V SoC QSPI
256 Mb
DDR3
x32
SDRAM
DDR3
2x 4Gb x32
FPGA Dual Core SDRAM
Fabric CPU 2x 4Gb
Altera Cyclone V ARM Cortex-A9
FPGA I²C
Lattice
MachXO2
I²C
1x PCIe I²C 2x I²C
MGMT USB 2 PCIe I²S 2x SPI Power
Gen1 x2
JTAG UART
USB 2 GbE
GPIOs FIFO Switch CSI-2 (4 lanes) JTAG PHY Supply
PHY
UART Client Host 24-bit LCD 2x CAN Host 3.0 – 5.25 V
4x Tx/Rx SDIO
2x PCIe (3.125 Gbps)
Gen2 x1
SMARC Edge Fingers
Figure 3: SXoM-C5 block diagram
2.3 Electrical Description

All necessary voltages are generated on the module from a single voltage. This voltage is brought in
from the carrier board over ten VDD_IN pins. The supply voltage has to be in the range from 3.0 V to
5.25 V.
Except for the SDIO interface, which works with 3.3 V, and for the differential pairs of the high speed
links, all I/O signals have a nominal voltage of 1.8 V.

2.4 Mechanical Description

Figure 4 shows the module dimensions. The drillings are used to mount the SXoM-C5 on the carrier
board and also to mount a heat spreader on the module, to which a heat sink can be attached.
Figure 4: SXoM-C5 mechanical description from [4]
Figure 5 illustrates the maximum heights under and above the module for a 1.5 mm stack height
carrier connector. The SXoM-C5 follows the mechanical restrictions given by the SMARC specification
[4].
Figure 5: Maximum heights under and above the module from [4]
There shall not be any component on the carrier board top side in the module region when using a
1.5 mm stack height connector. Furthermore, there should be no PCB traces on the carrier board top
side in the module region when such a connector is employed. If components are required in this
region, they have to be placed on the bottom side of the carrier board, or alternatively a connector with
a larger stack height has to be employed (e.g., 2.7 mm, 3.0 mm, or 5.0 mm).
For further information about the mechanical aspects of the board, the reader is referred to the
SMARC hardware specification [4].

2.5 Thermal Concept

It is recommended to use either a heat sink directly mounted on the module, or a heat spreader that is
thermally connected both to the module and to a heat sink or a metal case.
Due to the large amount of components on the SXoM-C5, there are no separate thermal attachment
points on the module. The module mounting holes (cf., Figure 4) serve to fix the module on the carrier
board as well as to fix the heat sink (or heat spreader) to the module.

3. Features
This chapter provides detailed information about the features of the SXoM-C5 module. It further
describes the interconnection of the Altera SoC and the Lattice companion FPGA.
3.1 Overview
Feature Assignment Description Chapter

8 Gbit DDR3 (32-bit) CPU DDR3 memory for CPU part of the SoC 3.2
8 Gbit DDR3 (32-bit) FPGA DDR3 memory for FPGA part of the SoC 3.3
256 Mbit QSPI Flash CPU Configuration device for the SoC 3.4
PCI Express FPGA (via PCI Express Gen2 (up to 5 GT/s) x1 interfaces 3.5
PCIe switch)
High-speed camera FPGA Camera interface with Gigabit transceiver 3.6
interface
General Purpose FPGA User configurable Gigabit transceiver 3.7
Gigabit Transceiver
CSI-2 / HiSPi FPGA Camera Serial Interface CSI-2 / 3.8
High Speed Serial Pixel Interface (HiSPi)
Also usable as a configurable LVDS interface
USB (ULPI) CPU USB interface to the CPU 3.9
USB (via USB-to- Companion USB slave interface 3.10
Serial UART/FIFO IC) FPGA
Gigabit Ethernet CPU 1000/100/10Base-T interface to the CPU 3.11
(RGMII)
LCD FPGA 24 bit parallel LCD display interface 3.12
SDIO CPU SDIO interface to support SD card or eMMC chip 3.13
on the carrier board
I 2S FPGA Audio interface to the FPGA 3.14
CAN CPU CAN interfaces to the CPU 3.15
SPI CPU Serial interface to the CPU 3.16
UART CPU Serial interfaces to the CPU 3.17

2
IC CPU / FPGA / 2
I C for LCD interface, camera interface, general 3.18
Companion purpose and power management, on-board
FPGA clock generator and PCI Express switch
JTAG CPU / FPGA Debug interface for the SoC 3.19
GPIO Companion User specific GPIOs 3.20
FPGA
Watchdog CPU Watchdog function of the CPU 3.21
LEDs FPGA / Indication for stable power and configured FPGA 3.22
Companion and companion FPGA
FPGA
Boot Options Companion Configuration options for the boot source 3.23
FPGA / CPU
SMARC Connector - SMARC interface to the carrier board 3.24
Clock Circuitry Companion Clock supply architecture for the system 3.25
FPGA
Power Supply - Power supply architecture for the system 3.26
Table 6: Features overview

3.2 DDR3 Memory for the CPU

In the default configuration, two 4 Gbit DDR3 memory chips are connected to the CPU. It is also
possible to order the SXoM-C5 with other configurations, e.g., with two 8 Gbit DDR3 memory chips.
Table 7 shows the assignment of signals of the DDR3 memory (for the CPU) to Cyclone V SoC pins.
Signal SoC Pin Signal SoC Pin

A0 C28 DQ19 U28
A1 B28 DQ20 N26
A2 E26 DQ21 N27
A3 D26 DQ22 R27
A4 J21 DQ23 V27
A5 J20 DQ24 R26
A6 C26 DQ25 R25
A7 B26 DQ26 AA28
A8 F26 DQ27 W26
A9 F25 DQ28 R24
A10 A24 DQ29 T24
A11 B24 DQ30 Y27
A12 D24 DQ31 AA27
A13 C24 DQS0_P R17
A14 G23 DQS0_N R16
BA0 A27 DQS1_P R19
BA1 H25 DQS1_N R18
BA2 G25 DQS2_P T19
DQ0 J25 DQS2_N T18
DQ1 J24 DQS3_P U19
DQ2 E28 DQS3_N T20
DQ3 D27 DM0 G28
DQ4 J26 DM1 P28
DQ5 K26 DM2 W28
DQ6 G27 DM3 AB28
DQ7 F28 CLK_P N21
DQ8 K25 CLK_N N20
DQ9 L25 RESET_N V28
DQ10 J27 RAS_N A25
DQ11 J28 CAS_N A26
DQ12 M27 WE_N E25
DQ13 M26 ODT0 D28
DQ14 M28 CKE0 L28
DQ15 N28 CS0_N L21
DQ16 N24 ODT1 (optional) G26
DQ17 N25 CKE1 (optional) K28
DQ18 T28 CS1_N (optional) L20
Table 7: Assignment of signals of the DDR3 memory (for the CPU) to Cyclone V SoC pins

3.3 DDR3 Memory for the FPGA

In the default configuration, two 4 Gbit DDR3 memory chips are connected to the FPGA. It is also
possible to order the SXoM-C5 with other configurations, e.g., with two 8 Gbit DDR3 memory chips.
Table 8 shows the assignment of signals of the DDR3 memory (for the FPGA) to Cyclone V SoC pins.
Signal SoC Pin Signal SoC Pin

A0 AH6 DQ19 AH18
A1 AH5 DQ20 AD20
A2 AG5 DQ21 AE20
A3 AH4 DQ22 AG19
A4 AE12 DQ23 AG20
A5 AD12 DQ24 AF21
A6 AH3 DQ25 AF22
A7 AH2 DQ26 AG21
A8 AD11 DQ27 AH21
A9 AE11 DQ28 AF23
A10 AE8 DQ29 AG23
A11 AF9 DQ30 AH23
A12 AE7 DQ31 AH24
A13 AF8 DQS0_P U14
A14 AD10 DQS0_N U13
BA0 AF7 DQS1_P W14
BA1 AF11 DQS1_N V13
BA2 AF10 DQS2_P AA19
DQ0 AF13 DQS2_N AA18
DQ1 AG13 DQS3_P AD23
DQ2 AG8 DQS3_N AE22
DQ3 AH8 DM0 AG11
DQ4 AE15 DM1 AH17
DQ5 AF15 DM2 AF20
DQ6 AG10 DM3 AG24
DQ7 AH11 CLK_P T13
DQ8 AG16 CLK_N T12
DQ9 AF17 RESET_N AG18
DQ10 AH12 RAS_N AF6
DQ11 AH13 CAS_N AF5
DQ12 AE17 WE_N AE4
DQ13 AD17 ODT0 AG9
DQ14 AG15 CKE0 AH14
DQ15 AH16 CS0_N T11
DQ16 AD19 ODT1 (optional) AH9
DQ17 AE19 CKE1 (optional) AG14
DQ18 AF18 CS1_N (optional) U11
Table 8: Assignment of signals of the DDR3 memory (for the FPGA) to Cyclone V SoC pins

3.4 QSPI Flash

The Quad SPI flash can be used as a boot device for the Cyclone V and offers a flexible way of
booting the SoC. By storing all necessary files (preloader, U-Boot, FPGA configuration file, kernel
image, and file system) on the QSPI flash, you can boot the SoC completely from QSPI flash. Or you
could just boot into U-Boot from QSPI flash and load the file system from a separate boot device (like
a carrier board SD card or eMMC flash).
To boot the preloader from the QSPI flash you have to choose boot option 2. For more information
about boot options, please refer to chapter 3.23, Boot Options.
Table 9 shows the assignment of signals of the QSPI flash to Cyclone V SoC pins.
Signal SoC Pin

CLK C14
CS_N A6
D0 A8
D1 H16
D2 A7
D3 J16
Table 9: Assignment of signals of the QSPI flash to Cyclone V SoC pins (CPU part)

3.5 PCI Express (PCIe)

Although the Cyclone V SoC only supports PCIe Gen1 x2, the SXoM-C5 provides two PCIe Gen2 x1
links via the SMARC connector. This is possible by employing a switch supporting PCIe Gen2 (up to
5 GT/s) in between.
Table 10 depicts the assignment of PCIe signals of the PCIe switch to Cyclone V SoC pins.
Signal SoC Pin

REFCLK_P V5
REFCLK_N V4
RX0_P AF2
RX0_N AF1
RX1_P AB2
RX1_N AB1
TX0_P AD2
TX0_N AD1
TX1_P Y2
TX1_N Y1
Table 10: Assignment of PCIe signals of the PCIe switch to Cyclone V SoC pins
The reference clock for the SoC is generated by a clock IC.

Table 11 and Table 12 provide the assignments of the PCIe signals from the switch to the SMARC
connector pins. The PERST signals are driven by the same source, the companion FPGA.
Signal SMARC Pin Termination

PCIE_0_REFCLK_P P83 -
PCIE_0_REFCLK_N P84 -
PCIE_0_RX_P P86 -
PCIE_0_RX_N P87 -
PCIE_0_TX_P P89 100 nF in series
PCIE_0_TX_N P90 100 nF in series
PCIE_PERST_N P75 PU (47k) to 3.3 V
PCIE_0_PRSNT_N P74 PU (47k) to 3.3 V
Table 11: Pin assignment of the first PCI Express interface on the SMARC connector

PCIE_1_REFCLK_P S84 -
PCIE_1_REFCLK_N S85 -
PCIE_1_RX_P S87 -
PCIE_1_RX_N S88 -
PCIE_1_TX_P S90 100 nF in series
PCIE_1_TX_N S91 100 nF in series
PCIE_PERST_N S76 PU (47k) to 3.3 V
PCIE_1_PRSNT_N P73 PU (47k) to 3.3 V
Table 12: Pin assignment of the second PCI Express interface on the SMARC connector

3.6 High-Speed Camera Interface

A customer-specific high-speed camera interface may be realized by employing two Rx of the Gigabit
transceivers. They are connected to the “CSI0” interface of the SMARC connector. It can be used to
link a second camera to the Cyclone V for 3D applications (the first camera can be connected via the
CSI-2 / HiSPi interface). But it is also possible to use these Gigabit receivers for other applications.
The lanes are routed with a differential impedance of about 90–100 Ω to support a wide range of
applications.
Table 13 shows the pin assignment of the high speed camera interface.
Signal SoC Pin SMARC Pin Termination

CSI0_CLK_P P8 S8 -
CSI0_CLK_N N8 S9 -
CSI0_D0_P P2 S11 -
CSI0_D0_N P1 S12 -
CSI0_D1_P F2 S14 -
CSI0_D1_N F1 S15 -
Table 13: Pin assignment of the high-speed camera interface

3.7 General Purpose Gigabit Transceiver

The Cyclone V SX device in U672 package provides six Gigabit transceiver pairs (Tx/Rx). Two
transceiver pairs are employed for implementing two lanes of PCIe, see chapter 3.5, PCI Express
(PCIe), and two Rx are reserved for implementing the high-speed camera interface, see chapter 3.6.
The remaining four Tx and two Rx of the Gigabit transceivers can be used for general purposes. They
are connected to the differential AFB pins of the SMARC connector, except for “GT_TX0_P” and
“GT_TX0_N”, which are linked to “PCIE_C_TX+” (SMARC pin S81) and “PCIE_C_TX-” (SMARC pin
S82).
The lanes are routed with a differential impedance of about 90–100 Ω to support a wide range of
applications.
The assignment of the general purpose Gigabit transceiver signals to SoC and SMARC pins is shown
in Table 14.

GT_RX0_P K2 S71 -
GT_RX0_N K1 S72 -
GT_RX1_P V2 S74 -
GT_RX1_N V1 S75 -
GT_TX0_P H2 S81 100 nF in series
GT_TX0_N H1 S82 100 nF in series
GT_TX1_P D2 S62 100 nF in series
GT_TX1_N D1 S63 100 nF in series
GT_TX2_P T2 S65 100 nF in series
GT_TX2_N T1 S66 100 nF in series
GT_TX3_P M2 S68 100 nF in series
GT_TX3_N M1 S69 100 nF in series
Table 14: Assignment of general purpose Gigabit transceiver signals to SoC and SMARC pins
NOT ICE
If the PCI Express core of the SoC is used, only three Tx pairs and one Rx pair remain available. The
GT_RX0_P/N and GT_TX0_P/N lines are then used for the PCI Express interface. If both the PCI
Express core and the “CSI0” interface are used, none of the Tx and Rx pairs remain available.
PCIe CSI0 GT_RX0 GT_RX1 GT_TX0 GT_TX1 GT_TX2 GT_TX3

used? used? available? available? available? available? available? available?
       
3 3
       
       
       
Table 15: Available general purpose Gigabit Transceiver signals depending on PCIe / CSI0 usage
3
Only either GT_RX1 or GT_TX2 can be used in this case because they use the same transceiver.

3.8 CSI-2 / HiSPi

Beside the high-speed camera interface (see chapter 3.6), the CSI-2 / HiSPi interface is the other
option to stream video data to the Cyclone V SoC. It is also usable as a configurable LVDS interface.
The CSI-2 / HiSPi interface is routed directly to the SMARC pins. The lanes are routed with a
differential impedance of about 90–100 Ω to support a wide range of applications.
Table 16 shows the assignment of pins for the CSI-2 / HiSPi interface from the SoC to the SMARC
pins.

CSI1_SOC_CLK_P Y13 P3 -
CSI1_SOC_CLK_N AA13 P4 -
CSI1_SOC_D0_P V11 P7 -
CSI1_SOC_D0_N W11 P8 -
CSI1_ SOC_D1_P V12 P10 -
CSI1_ SOC_D1_N W12 P11 -
CSI1_ SOC_D2_P U10 P13 -
CSI1_ SOC_D2_N V10 P14 -
CSI1_ SOC_D3_P U9 P16 -
CSI1_ SOC_D3_N T8 P17 -
Table 16: Assignment of pins for the CSI-2 / HiSPi interface from the SoC to the companion FPGA
3.9 USB Host (ULPI)

The USB host interface is realized with an ULPI link to the PHY. In order to support the power enable
and overcurrent detection function, the “CPEN” pin is routed through the companion FPGA to the
“USB_EN_OC_N” pin of the SMARC connector.
Table 17 illustrates the assignment of USB PHY signals of the ULPI interface to Cyclone V SoC pins.
Signal SoC Pin

D0 C10
D1 F5
D2 C9
D3 C4
D4 C8
D5 D4
D6 C7
D7 F4
CLK G4
STP C5
DIR E5
NXT D5
Table 17: Assignment of USB PHY signals of the ULPI interface to Cyclone V SoC pins
Table 18 illustrates the assignment of the USB host interface signals to SMARC connector pins.

USB_HOST_DP P65 -
USB_HOST_DM P66 -
Table 18: Assignment of USB host interface signals to SMARC connector pins

The control signal for a power switch on the carrier board is implemented in the companion FPGA.
The CPEN pin (enable for power switch) from the USB transceiver is routed to the companion FPGA.
The combinatorial pin for power switch enable and the overcurrent state indication of the power switch
of the SMARC connector are also routed to the companion FPGA.
Table 19 shows the assignment of the transceiver CPEN signal to companion FPGA pin.
Signal Companion
FPGA Pin
CPEN C2
Table 19: Assignment of transceiver CPEN signal to companion FPGA pin
Table 20 depicts the assignment of the power switch signal from companion FPGA pin to SMARC
connector pin.
Signal Companion SMARC Pin Termination

FPGA Pin
USB_HOST_EN_OC_N E1 P67 PU (47k) to 3.3 V
Table 20: Assignment of power switch signal from companion FPGA pin to SMARC connector pin
3.10 USB Device (via USB-to-Serial UART/FIFO IC to Companion FPGA)

The USB device (client) interface is realized via a USB-to-Serial UART/FIFO transceiver (FTDI
FT2232D) which supports data transfer rates up to 1 MByte/s to the companion FPGA.
Table 21 shows the assignment of the USB client interface signals to SMARC connector pins.

USB_CLIENT_DP P60 -
USB_CLIENT_DM P61 -
Table 21: Assignment of USB client interface signals to SMARC connector pins
Table 22 illustrates the assignment of UART/FIFO transceiver signals to companion FPGA pins.
Signal Companion FPGA

D0 M3
D1 N5
D2 M5
D3 P8
D4 M8
D5 P7
D6 N7
D7 M10
RXF_N P11
TXE_N M11
RD_N P12
WR P9
Table 22: Assignment of UART/FIFO transceiver signals to companion FPGA pins

3.11 Ethernet 10/100/1000 (RGMII)

The Ethernet interface is realized with a RGMII link to the PHY, which supports a link up to 1000Base-
T. It is downward compatible to 100Base-T and 10Base-T.
The following table shows the pin assignment of the RGMII interface on the SoC to the Gigabit
Ethernet PHY.
Signal SoC Pin

TXD0 A16
TXD1 J14
TXD2 A15
TXD3 D17
TX_CLK J15
TX_CTL A12
RXD0 A14
RXD1 A11
RXD2 C15
RXD3 A9
RX_CLK J12
RX_CTL J13
MDC A13
MDIO E16
Table 23: Pin assignment of the Ethernet (RGMII) interface of the SoC
The Ethernet transceiver also controls the LEDs for indication of link activity and speed. Due to the
different signal function of the transceiver and the SMARC specification, the companion FPGA is used
to translate between them.
The following tables show the pin assignments of the Ethernet link signals.
Signal Companion FPGA

LINK_ACT_N G3
LINK_SPEED_N H2
Table 24: Pin assignment of the link signals to the companion FPGA from the Ethernet transceiver
Signal Companion FPGA SMARC Pin Termination

GBE_LINK_ACT_N G14 P25 -
GBE_LINK100_N J12 P21 -
GBE_LINK1000_N J14 P22 -
Table 25: Pin assignment of the link signals to the companion FPGA from the Ethernet transceiver

The next table illustrates the pin assignment of the Gigabit Ethernet interface of SMARC connector.
Signal SMARC Pin

GBE_MDI0P P30
GBE_MDI0N P29
GBE_MDI1P P27
GBE_MDI1N P26
GBE_MDI2P P24
GBE_MDI2N P23
GBE_MDI3P P20
GBE_MDI3N P19
GBE_LINK_ACT_N P25
GBE_LINK100_N P21
GBE_LINK1000_N P22
Table 26: Pin assignment of the Gigabit Ethernet interface of the SMARC connector

3.12 24-LCD Interface

The 24-bit LCD interface can be used to connect a display to the SXoM-C5. It is left up to the carrier
board designer into what type of interface he transforms the LCD interface (e.g., VGA or HDMI).
The table below shows the pin assignment of the 24-bit LCD interface.

LCD_D0 Y4 S93 -
LCD_D1 V15 S94 -
LCD_D2 Y8 S95 -
LCD_D3 Y17 S96 -
LCD_D4 Y18 S97 -
LCD_D5 AB23 S98 -
LCD_D6 AA4 S99 -
LCD_D7 AB4 S100 -
LCD_D8 Y5 S102 -
LCD_D9 W8 S103 -
LCD_D10 AC24 S104 -
LCD_D11 AD26 S105 -
LCD_D12 Y16 S106 -
LCD_D13 AE26 S107 -
LCD_D14 V16 S108 -
LCD_D15 AD4 S109 -
LCD_D16 AA24 S111 -
LCD_D17 AA23 S112 -
LCD_D18 Y19 S113 -
LCD_D19 AE6 S114 -
LCD_D20 AD5 S115 -
LCD_D21 AE25 S116 -
LCD_D22 AA20 S117 -
LCD_D23 AF26 S118 -
LCD_VS AA11 S121 -
LCD_HS AC4 S122 -
LCD_PCK Y11 S123 -
LCD_DE D11 S120 -
Table 27: Pin assignment of the 24-bit LCD interface to the SoC

3.13 SDIO
The SDIO interface is implemented with four data signals and shall be connected to a SD card slot on
the carrier board as the boot device for the CPU in boot option 1.
The following table illustrates the pin assignment of the SDIO interface.

SDIO_D0 C13 P39 -
SDIO_D1 B6 P40 -
SDIO_D2 B11 P41 -
SDIO_D3 B9 P42 -
SDIO_CK B8 P36 -
SDIO_CMD D14 P34 -
SDIO_PWR_EN A5 P37 -
SDIO_WP B4 P33 -
SDIO_CD_N H12 P35 -
Table 28: Pin assignment of the SDIO interface
The “card detect” and “write protect” signals are also routed to the companion FPGA to be able to
have an influence on the boot option.
The table below shows the pin assignment of these two signals to the companion FPGA.
Signal Companion
FPGA Pin
SDIO_WP F3
SDIO_CD_N H1
Table 29: Pin assignment of the SDIO signals to the companion FPGA
3.14 I2S
In order to support the output of audio data, an I2S interface is implemented. It uses separate signals
for serial data input and output.
The next table displays the pin assignment for the I2S audio interface.

2
I S_SDI W20 S41 -
2
I S_SDO AB26 S40 -
2
I S_SCK AB25 S42 -
2
I S_WS AA26 S39 -
2
Table 30: Pin assignment of the I S interface
NOT ICE
2
The I S interface would not be available on SMARC modules equipped with a C2 or C4 type SoC!

3.15 CAN
There are two CAN interfaces implemented on the SXoM-C5. Both interfaces are connected to the
CPU. One of the two CAN interfaces is connected to GPIO pins of the CPU and internally routed
through the FPGA fabric to the CAN controller of the CPU.
The serial data lines have to be transformed with a transceiver on the carrier board to “CAN high” and
“CAN low”.
The following table depicts the pin assignment of the CAN interface that is connected to the CPU.

CAN0_TX B14 P143 -
CAN0_RX C21 P144 -
CAN1_TX J18 P145 -
CAN1_RX A20 P146 -
Table 31: Pin assignment of the CAN interfaces
3.16 SPI
The SXoM-C5 offers two SPI master interfaces. Both have two chip select signals to be able to
connect two independent slaves to each master. For more slaves use a daisy-chained SPI bus on the
carrier board.
The table below shows the pin assignment for the two SPI master interfaces.

SPI0_MISO B18 P45 -
SPI0_MOSI C17 P46 -
SPI0_CLK A18 P44 -
SPI0_CS0_N J17 P43 -
SPI0_CS1_N A17 P31 -
Table 32: Pin assignment of the first SPI master interface

SPI1_MISO B19 P57 -
SPI1_MOSI B16 P58 -
SPI1_CLK C19 P56 -
SPI1_CS0_N C16 P54 -
SPI1_CS1_N H17 P55 -
Table 33: Pin assignment of the second SPI master interface

3.17 UART
For low-level communication with the SoC and the companion FPGA there are two UART ports that
can be accessed from the CPU of the SoC.
UART0 is directly connected to CPU pins and routed over the companion FPGA. The handshake
signals (RTS and CTS) of UART0 are only implemented between the companion FPGA and the
SMARC connector.
The UART1 interface is routed through the FPGA within the SoC, but externally available directly via
the CPU pins of the SoC regardless.
The next table shows the pin assignment of the UART0 interface between the CPU and the
companion FPGA.
Signal SoC Pin Companion Termination

FPGA Pin
UART0_RX A22 K12 -
UART0_TX B21 J13 -
Table 34: Pin assignment of the UART0 interface of the CPU
The table below illustrates the pin assignment of the UART0 interface between the companion FPGA
and the SMARC connector. The handshake signals (RTS and CTS) are only routed to the companion
FPGA.

FPGA Pin
UART0_RX M13 P130 -
UART0_TX L14 P129 -
UART0_RTS K13 P131 -
UART0_CTS K14 P132 -
Table 35: Pin assignment of the UART0 interface of the companion FPGA
The next table shows the pin assignment of the UART1 interface which is connected to the CPU GPIO
pins of the SoC.

UART1_RX C6 P135 -
UART1_TX D15 P134 -
Table 36: Pin assignment of the UART interface of the FPGA

3.18 I2C
2
There are five I C interfaces implemented on the SXoM-C5. Two of them are connected to the CPU,
two to the FPGA and another one to the companion FPGA. Through internal re-routing, the FPGA-
connected interfaces can also be controlled by the CPU as a master.
The I2C interfaces for the camera interface and general purpose are connected to the CPU and the
others for LCD support and for the power management are attached to the FPGA.
2
The following tables depict the pin assignment of the I C buses that are connected to the CPU.

2
I C_CAM_SDA A19 S7 PU (2k) to 1.8 V
2
I C_CAM_SCL C18 S5 PU (2k) to 1.8 V
2
Table 37: Pin assignment of the I C interface of the CPU for CSI-2

I2C_GP_SDA A21 S49 PU (2k) to 1.8 V
I2C_GP_SCL K18 S48 PU (2k) to 1.8 V
2
Table 38: Pin assignment of the I C interface of the CPU for General Purpose
The following tables depict the pin assignment of the I2C buses that are connected to the FPGA.

I2C_LCD_SDA C12 S140 PU (2k) to 1.8 V
I2C_LCD_SCL D12 S139 PU (2k) to 1.8 V
2
Table 39: Pin assignment of the I C interface of the FPGA for the LCD

2
I C_PM_SDA E8 P122 PU (2k) to 1.8 V
2
I C_PM_SCL D8 P121 PU (2k) to 1.8 V
2
Table 40: Pin assignment of the I C interface of the FPGA for the Power Management
NOT ICE
The power management I2C bus is connected twice to the companion FPGA. Pins B8 / C8 are used for
programming and to supply the EEPROM for the power management required by the SMARC
specification. Pins D1 (SDA) / B2 (SCL) can be used for general purpose communiation between the
SoC and the companion FPGA.
2
The companion FPGA uses I C addresses 0x40..0x43 on the Power Management bus.
Another I2C interface connects the companion FPGA with the I2C configuration interface of the on-
board clock generator and the PCI Express switch IC.
Signal Companion
FPGA Pin
I2C_CG_SDA D1
2
I C_CG_SCL B2
2
Table 41: Pin assignment of the I C interface of the companion FPGA for the on-board clock generator and the PCI Express switch
NOT ICE
Reconfiguration of the on-board clock generator can cause malfunctions of the module. Solectrix takes
no responsibility for any damage due to the reprogramming of the clock PLL.

3.19 JTAG
The JTAG interfaces for the FPGA and CPU are tied to separate pins on the SMARC connector to
have independent access to each. It is also possible to connect them to a chain on the carrier board.
The table below illustrates the pin assignment of the JTAG interface that is connected to the FPGA.

JTAG_FPGA_TDI W10 S24 PU (25k)
JTAG_FPGA_TDO Y9 S18 -
JTAG_FPGA_TCK AB5 S56 PD (25k)
JTAG_FPGA_TMS AC7 S55 PU (25k)
Table 42: Pin assignment of the JTAG interface of the FPGA
NOT ICE
If the JTAG interface is used, it is recommended that the carrier board designer adds a pulldown resistor
(1k) to JTAG_FPGA_TCK and pull-up resistors (1k - 10k / 2.5 V) to JTAG_FPGA_TDI and
JTAG_FPGA_TMS.
The table below illustrates the pin assignment of the JTAG interface that is connected to the CPU.

JTAG_CPU_TDI D22 S20 PU (25k)
JTAG_CPU_TDO B23 S19 -
JTAG_CPU_TCK K19 S21 PD (25k)
JTAG_CPU_TMS C23 S22 PU (25k)
JTAG_CPU_TRST_N C22 S23 PU (25k)
Table 43: Pin assignment of the JTAG interface of the CPU
NOT ICE
If the JTAG interface is used, it is recommended that the carrier board designer adds a pulldown resistor
(1k – 10k) to JTAG_ CPU_TCK and pull-up resistors (1k - 10k / 2.5 V) to JTAG_ CPU_TDI, JTAG_
CPU_TMS and JTAG_CPU_TRST_N.

3.20 GPIO
There are twelve general purpose IO pins on the SMARC connector that are linked to the companion
FPGA. These pins do not have any specific functionality and can be used for any purpose the user
wants.
The following table shows the pin assignment and termination of the GPIOs that are connected to the
companion FPGA.

FPGA Pin
GPIO0 A10 P108 PU (470k) to 1.8 V
GPIO1 C11 P109 PU (470k) to 1.8 V
GPIO2 A11 P110 PU (470k) to 1.8 V
GPIO3 B12 P111 PU (470k) to 1.8 V
GPIO4 A12 P112 PU (470k) to 1.8 V
GPIO5 C12 P113 PU (470k) to 1.8 V
GPIO6 M12 P114 PU (470k) to 1.8 V
GPIO7 M14 P115 PU (470k) to 1.8 V
GPIO8 F13 P116 PU (470k) to 1.8 V
GPIO9 D12 P117 PU (470k) to 1.8 V
GPIO10 E12 P118 PU (470k) to 1.8 V
GPIO11 E14 P119 PU (470k) to 1.8 V
Table 44: Pin assignment of the JTAG interface of the CPU
3.21 Watchdog Signal

The watchdog signal can be triggered from the CPU. It is generated by a GPIO pin from the CPU part
of the SoC.
The following table shows the pin assignment of the watchdog signal.

WDT_OUT_N E4 S145 -
Table 45: Pin assignment of the watchdog interface

3.22 LEDs
There are two dual LEDs on the board for debugging purpose. The “PWR OK” LED and the yellow
part of the “FPGA OK” LED are connected to the companion FPGA. The green part of the “FPGA OK”
LED is connected to the Altera FPGA.
Figure 6: Debug LEDs on top side of the SXoM-C5
NOT ICE
The control function for the “FPGA OK” LED has to be implemented in both FPGAs.
Table 46 illustrates the pin assignment and the status the two LEDs are indicating.
LED Pin Board Status

PWR_OK - Green: All voltages are supplied
Red: At least one voltage is not in range
FPGA_OK SoC AA15 Green: Altera FPGA is fully configured
Companion FPGA H12 Yellow: Lattice FPGA is fully configured
Table 46: Debug LEDs for board status indication

3.23 Boot Options

There are two boot options that can be selected over the BOOT_SEL pins of the SMARC connector.
The FPGA part of the Cyclone V SoC is always configured by the CPU. Therefore, the MSEL[4..0]
pins of the Cyclone V SoC have a fixed value of “01010” (FPP×32 configuration scheme, see FPGA
Manager section in [3] for more information).
To avoid unsupported BOOT_SEL pin configurations, the BOOT_SEL pins from the SMARC
connector are connected to the companion FPGA. The companion FPGA is able to detect
unsupported boot configurations and to prevent the Cyclone V SoC from booting by pulling the
CPU_POR_N pin (active-low power-on reset) of the Cyclone V SoC low.
Table 47 shows the supported boot options and the necessary BOOT_SEL pin configuration on the
carrier board.
BOOT_SEL2_N BOOT_SEL1_N BOOT_SEL0_N Boot Option

CPU loads preloader from
GND GND FLOAT
carrier board SD card
CPU loads preloader from
FLOAT GND GND
module QSPI flash
Table 47: Boot options of the SoC
NOT ICE
Please note that for selecting the boot source module QSPI flash, the SMARC standard [4] describes a
different pin configuration (#7). This pin configuration is not supported.
NOT ICE
Please note that instead of an SD card, an eMMC flash (operating in 4-bit mode) may also be connected
to the SDIO interface at SMARC pins P39 – P42. If this is the case, the first entry in the above table for
SD card has to be chosen and not the boot selection for eMMC flash provided in the SMARC standard
[4].
Table 48 shows the interconnection of the boot select pins between the SMARC connector and the
companion FPGA.
Signal SMARC Pin Companion Termination

FPGA Pin
BOOT_SEL0_N P123 A6 PU (47k) to 1.8 V
BOOT_SEL1_N P124 C13 Internal PU of the
companion FPGA
(5.8k to 60k) to 1.8 V
BOOT_SEL2_N P125 B4 Internal PU of the
companion FPGA
(5.8k to 60k) to 1.8 V
Table 48: Boot-select interconnection between SMARC connector and companion FPGA
Table 49 shows the interconnection of the POR_N pins between the companion FPGA and the SoC.
Signal Companion SoC Pin

FPGA Pin
CPU_POR_N A4 H19
Table 49: Companion FPGA and SoC pins for the CPU_POR_N signal

3.24 SMARC Connector

This connector and its pin assignment are conforming to the SMARC specification [4].
Table 50 shows the pin assignment of the SMARC connector.
Signal (Top Side) Connected SMARC Signal (Bottom Connected SMARC

to Pin Side) to Pin
NC P1 NC S1
GND P2 NC S2
CSI1_CLK_P Companion P3 GND S3
FPGA
CSI1_CLK_N Companion P4 NC S4
FPGA
NC P5 I2C_CAM_SCL CPU S5
NC P6 NC S6
2
CSI1_D0_P Companion P7 I C_CAM_SDA CPU S7
FPGA
CSI1_D0_N Companion P8 CSI0_CLK_P FPGA S8
FPGA
GND P9 CSI0_CLK_N FPGA S9
CSI1_D1_P Companion P10 GND S10
FPGA
CSI1_D1_N Companion P11 CSI0_D0_P FPGA S11
FPGA
GND P12 CSI0_D0_N FPGA S12
FPGA
CSI1_D2_N Companion P14 CSI0_D1_P FPGA S14
FPGA
GND P15 CSI0_D1_N FPGA S15
FPGA
CSI1_D3_N Companion P17 NC S17
FPGA
GND P18 JTAG_FPGA_TDO FPGA S18
GBE_MDI3N Ethernet PHY P19 JTAG_CPU_TDO CPU S19
GBE_MDI3P Ethernet PHY P20 JTAG_CPU_TDI CPU S20
GBE_LINK100_N Companion P21 JTAG_CPU_TCK CPU S21
FPGA
GBE_LINK1000_N Companion P22 JTAG_CPU_TMS CPU S22
FPGA
GBE_MDI2_N Ethernet PHY P23 JTAG_CPU_TRST_N CPU S23
GBE_MDI2_P Ethernet PHY P24 JTAG_FPGA_TDI FPGA S24
GBE_LINK_ACT_N Companion P25 GND S25
FPGA
GBE_MDI1_N Ethernet PHY P26 NC S26
GBE_MDI1_P Ethernet PHY P27 NC S27
NC P28 NC S28
GBE_MDI0_N Ethernet PHY P29 NC S29
GBE_MDI0_P Ethernet PHY P30 NC S30


to Pin Side) to Pin
SPI0_CS1_N CPU P31 NC S31
GND P32 NC S32
SDIO_WP CPU / P33 NC S33
Companion
FPGA
SDIO_CMD CPU P34 GND S34
SDIO_CD_N CPU / P35 NC S35
Companion
FPGA
SDIO_CK CPU P36 NC S36
SDIO_PWR_EN CPU P37 NC S37
GND P38 NC S38
2
SDIO_D0 CPU P39 I S_WS FPGA S39
2
SDIO_D1 CPU P40 I S_SDO FPGA S40
2
SDIO_D2 CPU P41 I S_SDI FPGA S41
2
SDIO_D3 CPU P42 I S_SCK FPGA S42
SPI0_CLK CPU P44 NC S44
SPI0_MISO CPU P45 NC S45
SPI0_MOSI CPU P46 NC S46
GND P47 GND S47
2
NC P48 I C_GP_SCL CPU S48
2
NC P49 I C_GP_SDA CPU S49
GND P50 NC S50
NC P51 NC S51
NC P52 NC S52
GND P53 NC S53
SPI1_CS1_N CPU P55 JTAG_FPGA_TMS FPGA S55
SPI1_CLK CPU P56 JTAG_FPGA_TCK FPGA S56
SPI1_MISO CPU P57 NC S57
SPI1_MOSI CPU P58 NC S58
GND P59 NC S59
USB_CLIENT_DP USB-to-FIFO P60 NC S60
transceiver
USB_CLIENT_DM USB-to-FIFO P61 GND S61
transceiver
NC P62 GT_TX1_P FPGA S62
NC P63 GT_TX1_N FPGA S63
NC (with PU to 3.3V) P64 GND S64
USB_HOST_DP USB PHY P65 GT_TX2_P FPGA S65
USB_HOST_PM USB PHY P66 GT_TX2_N FPGA S66
USB_HOST_EN_OC_N Companion P67 GND S67
FPGA


to Pin Side) to Pin
GND P68 GT_TX3_P FPGA S68
NC P69 GT_TX3_N FPGA S69
NC P70 GND S70
GND P71 GT_RX0_P FPGA S71
NC P72 GT_RX0_N FPGA S72
PCIE_1_PRSNT_N PCIe switch P73 GND S73
PCIE_0_PRSNT_N PCIe switch P74 GT_RX1_P FPGA S74
PCIE_PERST_N PCIe switch P75 GT_RX1_N FPGA S75
NC P76 PCIE_PERST_N PCIe switch S76
NC P77 NC S77
NC P78 NC S78
GND P79 NC S79
NC P80 GND S80
NC P81 GT_TX0_P FPGA S81
GND P82 GT_TX0_N FPGA S82
PCIE_0_REFCLK_P PCIe switch P83 GND S83
PCIE_0_REFCLK_N PCIe switch P84 PCIE_1_REFCLK_P PCIe switch S84
GND P85 PCIE_1_REFCLK_N PCIe switch S85
PCIE_0_RX_P PCIe switch P86 GND S86
PCIE_0_RX_N PCIe switch P87 PCIE_1_RX_P PCIe switch S87
GND P88 PCIE_1_RX_N PCIe switch S88
PCIE_0_TX_P PCIe switch P89 GND S89
PCIE_0_TX_N PCIe switch P90 PCIE_1_TX_P PCIe switch S90
GND P91 PCIE_1_TX_N PCIe switch S91
NC P92 GND S92
NC P93 LCD_D0 FPGA S93
GND P94 LCD_D1 FPGA S94
NC P101 GND S101
GPIO0 Companion P108 LCD_D14 FPGA S108
FPGA


to Pin Side) to Pin
FPGA
GPIO2 Companion P110 GND S110
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
GPIO11 Companion P119 GND S119
FPGA
GND P120 LCD_DE FPGA S120
2
I C_PM_SCL FPGA P121 LCD_VS FPGA S121
2
I C_PM_SDA FPGA P122 LCD_HS FPGA S122
BOOT_SEL0_N Companion P123 LCD_PCK FPGA S123
FPGA
BOOT_SEL1_N Companion P124 GND S124
FPGA
BOOT_SEL2_N Companion P125 NC S125
FPGA
RESET_OUT_N P126 NC S126
RESET_IN_N P127 NC S127
NC (with PU to 1.8V) P128 NC S128
UART0_TX Companion P129 NC S129
FPGA
UART0_RX Companion P130 GND S130
FPGA
UART0_RTS Companion P131 NC S131
FPGA
UART0_CTS Companion P132 NC S132
FPGA
GND P133 NC S133
UART1_TX CPU P134 NC S134
UART1_RX CPU P135 NC S135
NC P136 GND S136
NC P137 NC S137
NC P138 NC S138


to Pin Side) to Pin
NC P139 I2C_LCD_SCL FPGA S139
2
NC P140 I C_LCD_SDA FPGA S140
NC P141 NC S141
GND P142 NC S142
CAN0_TX CPU P143 GND S143
CAN0_RX CPU P144 NC S144
CAN1_TX CPU P145 WDT_OUT_N FPGA S145
CAN1_RX CPU P146 NC S146
VDD_IN P147 VDD_RTC S147
VDD_IN P148 NC (with PU to 1.8V) S148
VDD_IN P150 VIN_PWR_BAD_N S150
VDD_IN P154 CARRIER_PWR_ON S154
NC (with PU to 1.8V) S157
GND S158
(VDD_IO_SEL_N)
Table 50: Pin assignment of the SMARC connector

3.25 Clock Circuitry

Figure 7 shows the standard configuration for the on-board clock PLL.
25 MHz
Ethernet PHY
24 MHz
USB PHY
50 MHz
FPGA
100 MHz
Oscillator Clock PLL
25 MHz
100 MHz
148.5 MHz
SoC
100 MHz
25 MHz RefClk
PLL
100 MHz
PCIe Switch
Figure 7: Standard clock configuration
The clock PLL can be reprogrammed via an I2C interface on the companion FPGA. Reprogramming
can be done from the CPU of the SoC. Only the clocks for the companion FPGA and for the SoC shall
be reprogrammed if necessary.
NOT ICE
Do not reprogram the clocks for the USB PHY, Ethernet PHY and PCIe Refclk PLL! This would cause
malfunctions on the module. Solectrix takes no responsibility for any damage due to reprogramming the
clock PLL.
There are two clock sources for the Gigabit transceivers of the SoC. The first option is a 100 MHz
HCSL Refclk for PCIe which is generated on-board. The second is externally sourced from the CSI-2
interface on the SMARC connector.

3.26 Power Supply

All power converters are fed from the “VDD_IN” supply voltage on the SMARC connector.
NOT ICE
The module supports only I/O level VDD_IO of 1.8 V!
Because of the current limit of 5 A, it is recommended to supply the module with 5 V instead of a lower
voltage to get a higher power budget for the Cyclone V.
The carrier board designer is responsible for the final calculation for the power consumption of the
module. This is also important for selecting a thermal concept and dimensioning the thermal
dissipation components.
Figure 8 shows the architecture of the power supplies.
DC/DC
1.1 V
SoC
DC/DC
1.5 V
FPGA
VDD_IN (3.0 V – 5.25 V)
LDO 2x DDR3
0.75 V
SMARC
DC/DC QSPI Flash

2.5 V
USB PHY
DC/DC
1.8 V
Ethernet PHY
LDO
1.2 V
DC/DC PCIe Switch

1.0 V
DC/DC Clock PLL

3.3 V
DC/DC
USB to FIFO
5.0 V
Figure 8: Power supply architecture

3.27 Reset
The companion FPGA acts as the reset master, controlling separate reset signals for the CPU and the
FPGA part of the SoC.
Signal Companion SoC Pin Termination

FPGA Pin
SOC_CPU_RST_N A2 A23 PU (1k) to 1.8 V
SOC_FPGA_RST_N C6 AF25 PU (1k) to 1.5 V
Table 51: Reset signals
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REFERENCE MANUAL

SXoM-C5 Reference Manual

Author: T. Ritter, S. Heider, M. Schetter, Dr. R. Tzschoppe

ABOUT THIS DOCUMENT 5

Revision B.01 Page 2 of 39 30.04.2015

3.21 WATCHDOG SIGNAL 29

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About this Document

Rev. Author / Date Description / Change / Comments

Rev. Created / Date Signature Checked / Date Signature Released / Signature

Section Name E-Mail Telephone

Revision B.01 Page 5 of 39 30.04.2015

No. Title Description Author Version Date

Table 5: List of Abbreviations

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1.1 Purpose of the Board

1.2 Feature List

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Figure 1: SXoM-C5 Rev. B, top side layout

Figure 2 shows the bottom side of the SXoM-C5, hardware revision B.

Figure 2: SXoM-C5 Rev. B, bottom side layout

Revision B.01 Page 8 of 39 30.04.2015

2.2 Block Diagram

SMARC Edge Fingers

Figure 3: SXoM-C5 block diagram

2.3 Electrical Description

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2.4 Mechanical Description

Figure 4: SXoM-C5 mechanical description from [4]

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2.5 Thermal Concept

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Feature Assignment Description Chapter

UART CPU Serial interfaces to the CPU 3.17

Revision B.01 Page 12 of 39 30.04.2015

3.2 DDR3 Memory for the CPU

Signal SoC Pin Signal SoC Pin

Revision B.01 Page 13 of 39 30.04.2015

3.3 DDR3 Memory for the FPGA

Signal SoC Pin Signal SoC Pin

Revision B.01 Page 14 of 39 30.04.2015

3.4 QSPI Flash

Signal SoC Pin

Revision B.01 Page 15 of 39 30.04.2015

3.5 PCI Express (PCIe)

Signal SoC Pin

The reference clock for the SoC is generated by a clock IC.

Signal SMARC Pin Termination

Signal SMARC Pin Termination

Revision B.01 Page 16 of 39 30.04.2015

3.6 High-Speed Camera Interface

Signal SoC Pin SMARC Pin Termination

Revision B.01 Page 17 of 39 30.04.2015

3.7 General Purpose Gigabit Transceiver

Signal SoC Pin SMARC Pin Termination

PCIe CSI0 GT_RX0 GT_RX1 GT_TX0 GT_TX1 GT_TX2 GT_TX3

Revision B.01 Page 18 of 39 30.04.2015

3.8 CSI-2 / HiSPi

Signal SoC Pin SMARC Pin Termination

3.9 USB Host (ULPI)

Signal SoC Pin

Signal SMARC Pin Termination

Revision B.01 Page 19 of 39 30.04.2015