Stop syn(pin)the clock signal should not propagate after reaching that point

Exclude pins : all non clock ip such Dpin of FF or combo input

Float pin:it like stop but inter clock latency of that in taken during CTO building.

Sanity checks: floating pins, unconst raise pins, undriven inputs unloaded output ports pin direction
mismatches, multi driven

What are optimization techchique:

Cell sizeing, vt swapping buffering logical restructing pin swapping

Floorplan guidliness:

Group macros as per instance names or module hierarchy

Highly communicating module better to place closer

Macro placement is dependent on its module communicaton with I/O ports

Place on edge avoid zig sagging across macro

Avoid logic cell/Fop being placed into isolated packets

Focus to have homogenous standard cell area with macro aligned

Allow spacing between macros and tile edges

Macro pin connection and orientation

For design that have horizontal overflow to increase utilization cell row separation is increased
which in turn helps increase horizontal routing resources

Macro pins should face towards corea area

Place end cap

Place well tap

Placement:

Pre-place , inplace, post-placement:

What to expect during placement:

Placement of logic gate and flops in corea area

Placement based on inter connectivity of cells modules macros and IO’s

Placement based on timing power , congestion

Alignment of cells placement to placement grid

Placement result wil initial picture on utilization, timing ,routing congestion, placement density

QOR Result: congestion utilization

Post placement not to high <80%

Congeston Map ;should not be any major hot sports:

QOR: causes of timing / congestin:

Floorplan issues:

Crowded I/o pins

Macros that need many wires routed over than

Placement issues: high density area

Connectivity Isuuses: tomany wires crossing an area , macro placed far apart causing extra wiring.

Logic connection: logic wired in as cross bar fashion:

Strategic to fix congestion:

Adjust cell density in congestion area, Add modify blockages, cell padding, create groups and
regions

Modify the FP:

Change macro locations

Change tile shapes/size(feedback to PD integration Team)

Cell Pading: OAI/AOI WILL HAVE MORE PINS and require more routing resource.

Cell padding leves more spacing around cell.

Group and region :the place timing critical logic cells close to each other to help timing and
congestion .( create group may soft,hard exclusive)

Objective of CTS:

Insertion delay, skew balance, meet hold violation

Clock N/W IS MAJOR consume of power

SKEW: timing and hold violations

Trans/slew: cycle varation and short ckt power

Insertion delay: ocv sucespectibilty

Number of buffers: PVT impact leaker power

Switching power: Total power consumption:

Clock N/w is sensitive the

OCV

SI

CYCLE TO CYCLE VARATIOINS