HWTestPart15(WhatIsBaudRate) 


bus = core/2 


Baud Rate = Bus Clock/ Baud Rate Divisor


Baud Rate Divisor = (SPIBR_[4:6]+1) x 2^(SPIBR_[0:2]+1)

NOTE: This problem will screw with you, because MHz is
10^6, but kb is 2^10.

1: A 9S12 has a core clock frequency of 5.5 MHz. What is the SPI0 Baud Rate (in
kb/s to one decimal places) given the following register settings?

SPIBR0 = 0x41;

SPICR10 = 0XD2;

SPICR20 = 0X20; Answer: 134.3



 


HWTest16(DACLevels)


#
N = Number of conversion bits


This one’s a little fun. N (round up) = log(base 2) [(voltage span)/increments] 


//round up means 12.1 -> 13 cause reasons

For the next problem -> N = log(base 2) [(11.1+4.7)/(.002)] = 12.947 = 13

Second problem type (max voltage) > Maximum Output = V(REF) Resolution
where Resolution = V(REF) /(2^N)

If Bipolar: Resolution = V(REF) /(2^(N-1))

Voltage Range = V(REF)

Smallest Voltage = V(REF)/(2^N) **if bipolar subtract 1 from N**

1. If we need to produce voltages from 4.7 to 11.1 Volts, in increments of 2 mV,

what’s the fewest number of bits that our DAC input must have?

13

2. If a 9bit bipolar DAC has a reference voltage of 12.8 Volts, what is the
maximum voltage ( in Volts to four decimal places) that can be produced?
Bipolar > double tres prior to output calc 12.7500

 


HWTest18(ADCPRS)

This one’s a little tricky. You need to solve 

T(sample) = 2x(PRS+1)/fBus x (n(SMP) +12)) 

n(SMP) = 2^(SMP+1) [SMP ranges from 0 to 3]



PRS = (( (T(sample)*fBus)/(2^(SMP+1)+12))/2)-1

1. Given the 9S12 Bus clock frequency ADC SMP value below what
must the value of PRS in ATDCTL4 need to be to give the ADC
sample time given?

fBus = 7.8 MHz


SMP = 1

ATD0 Sample Time = 97.834 micro s

HWTest17(ADCLevels)

Pretty much the same formula as the last problem.


Solve Resolution = V(REF)/2^N, with N being the number of bits.

Clock Frequency = f(BUS)/(2*(PRS+1))
 (Bipolar -> V(REF)/2^(N-1)) -

Sample Time = [2x(PRS+1)/f(BUS)] x (2 + 2^(SMP+1) + 10)
 LOGbase2(V(Ref)/resolution Voltage) = N 

Sample time = 2*(PRS+1)*(12+2^(SMP+1))/f(BUS)
 V(REF) = sample max - sample low if not given

sample time = (1/clock_freq )* (12+2^(SMP+1))


1. If we need to sample voltages from 0 to 11.1 Volts, with a resolution of 47 mV, what’s
the fewest number of bits that our ADC output must have?

PRS = ATD_CTL4[4:0] 
 8

SMP = ATD_CTL4[6:5]



(5.5*10^6) / 2*(0+1) = 2750000 Hz = 2.75 MHz

Using the first Sample Time Equation: 

(2*(0+1) / (5*5*10^6)) * (2+2+10) = 5.091 us
See ADCPRS for formula, simply solve for SMP this time.


# For ease of use... 


LogBase2( (Sample time*fBus) / (2 (PRS+1) ) ) -12)-1 = SMP
log2[(Time * fBus) / ( 2*(PRS+1)) -12] -1 = SMP

 HWTest19(ADCForSequence)

V(ref) = span from Vrl to Vrh

10/8 bits bit 7 of ATD_CTL4 (0/1) A pattern that works:

Left/Right bit 7 of ATD_CTL5 (0/1) SCAN 0 if it says stop, 1 if it says “...”

Un/Signed bit 6 of ATD_CTL5 (0/1)
MULT 0 if all the channels are the same, 1 otherwise

FIF0 0 sets the registers of the conversion per sequence back to 0, 1 just lets the
For the problem below:
 registers keep incrementing until it reaches 7. If SCAN is 1 then the register is
ATDDR = 0110 0011 1100 0000
 automatically reset. Sam Park

10 bits, from the left, then convert to CCBCA The 1st Channel in the list. For example, in the problem below = 6

decimal (399). Resolution for 10 bits S8Cs4CS2CS1C # of unique registers I believe this should # of total channels (Shil)
is V(ref)/1024, 8 bits is V(ref)/256 S8CS4CS2CS1C the conversion per sequence in the registers.

Multiply ATDDR’s decimal by the
resolution, then

If signed, take average of Vrl and Vrh, HWTest21(SCIWhatIsBaud)
 HWTest21(SCIWhatIsSCIBD)


and add answer to that. If unsigned, Solve:
 Same formula as before, just reversed: BRD = f(BUS)/(16*BR)

add answer to lower value (Vrl).
 BAUD RATE = f(BUS)/(16*BAUD RATE DIVISOR)
Remember that BDL can only store up to 256, and overflow goes into the
1. Given the 9S12 register settings 5 lowest bits of BDH.

below and the reference values given,
BAUD RATE divisor = decimal value of SCI0BDH/BDL
[12:0]

Please note: SCI0BDL can only hold values up to 256, and Given the following Bus Clock frequency, provide the hex values for SCI0BDH
the total storage of the two does not exceed 8191 (2^131)
 and SCI0BDL to produce the given Baud Rate for SCI0.

Vrl = 0.00, Vrh = 5.12

To find the Baud Rate Divisor, stick the first 5 bits of low fBus = 1.95 MHz

onto the left side of high.
 Baud Rate = 30.461 bits/s

ATDCTL4 = 0x5D ATDCTL5 = 0x54
Given the following Core Clock frequency and register Answer:

settings for the 9S12, what is the Baud Rate for SCI0 (to

SCI0BDH = 0x0F SCI0BDL = 0xA1

two decimal places)?

ATDDR = 0x63C0

fCore = 21.80 MHz

What voltage is represented by the value in ATDDR?
Answer: Voltage = 4.555
SCI0BDH = 0x00 SCI0BDL = 0x29 Answer: 16615.85