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10-LINE-TO-4-LINE SN54/74LS148
AND 8-LINE-TO-3-LINE SN54/74LS748
PRIORITY ENCODERS
The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoders. They
provide priority decoding of the inputs to ensure that only the highest order 10-LINE-TO-4-LINE
data line is encoded. Both devices have data inputs and outputs which are
AND 8-LINE-TO-3-LINE
active at the low logic level.
The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied
PRIORITY ENCODERS
decimal zero condition does not require an input condition because zero is LOW POWER SCHOTTKY
encoded when all nine data lines are at a high logic level.
The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By
providing cascading circuitry (Enable Input EI and Enable Output EO) octal
expansion is allowed without needing external circuitry.
The SN54 / 74LS748 is a proprietary Motorola part incorporating a built-in
J SUFFIX
deglitcher network which minimizes glitches on the GS output. The glitch
CERAMIC
occurs on the negative going transition of the EI input when data inputs 0 – 7 CASE 620-09
are at logical ones. 16
The only dc parameter differences between the LS148 and the LS748 are 1
that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on
the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a
fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148.
The only ac difference is that tPHL from EI to EO is changed from 40 to N SUFFIX
45 ns. PLASTIC
16 CASE 648-08
SN54 / 74LS147
(TOP VIEW) 1
VCC NC D 3 2 1 9 A D SUFFIX
16 15 14 13 12 11 10 9 SOIC
16
1 CASE 751B-03
D 3 2 1 9
4 A ORDERING INFORMATION
5 6 7 8 C B
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
1 2 3 4 5 6 7 8 SN74LSXXXD SOIC
4 5 6 7 8 C B GND
INPUTS OUTPUTS
SN54 / 74LS148
SN54 / 74LS748
(TOP VIEW)
OUTPUTS INPUTS OUTPUT
VCC EO GS 3 2 1 0 A0
16 15 14 13 12 11 10 9
EO GS 3 2 1 0
4 A0
5 6 7 EI A2 A1
1 2 3 4 5 6 7 8
4 5 6 7 E1 A2 A1 GND
INPUTS OUTPUTS
SN54 / 74LS148
SN54 / 74LS147 SN54 / 74LS748
FUNCTION TABLE FUNCTION TABLE
INPUTS OUTPUTS INPUTS OUTPUTS
1 2 3 4 5 6 7 8 9 D C B A EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
H H H H H H H H H H H H H H X X X X X X X X H H H H H
X X X X X X X X L L H H L L H H H H H H H H H H H H L
X X X X X X X L H L H H H L X X X X X X X L L L L L H
X X X X X X L H H H L L L L X X X X X X L H L L H L H
X X X X X L H H H H L L H L X X X X X L H H L H L L H
X X X X L H H H H H L H L L X X X X L H H H L H H L H
X X X L H H H H H H L H H L X X X L H H H H H L L L H
X X L H H H H H H H H L L L X X L H H H H H H L H L H
X L H H H H H H H H H L H L X L H H H H H H H H L L H
L H H H H H H H H H H H L L L H H H H H H H H H H L H
H = HIGH Logic Level, L = LOW Logic Level, X = Irrelevant
(11) (10)
1 0 (15)
EO
(12) (11) (14)
2 (9) 1
A GS
(13) (12)
3 2
(8)
A0
(1) (13)
4 3
(7)
(2) B (1)
5 4
(7)
(3) (2) A1
6 5
(5) (4)
8 7 (6)
A2
G31
(10)
0 G13 (15)
EO
(11) (14)
1 GS
G2 G29
(12) G9
2
G3 (9)
A0
(13) G18
3
G4
4 (1) G10
G5
G11 (7)
(2) A1
5
G23
G6
(3) G12
6
G7
(4) (6)
7 A2
G8
G28
(5)
EI
G1
SN54 / 74LS748
VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
SN54 / 74LS148
SN54 / 74LS748
From To Limits
S b l
Symbol (Input) (Output) W
Waveform
f Min Typ Max U i
Unit T
Test C
Conditions
di i
tPLH In-phase
p 14 18
1 thru 7 A0 A1
A0, A1, or A2 ns
tPHL output 15 25
tPLH Out-of-phase
p 20 36
1 thru 7 A0 A1
A0, A1, or A2 ns
tPHL output 16 29
tPLH Out-of-phase
p 7.0 18
0 thru 7 EO ns
tPHL output 25 40
CL = 15 pFF
pF,
tPLH In-phase
p 35 55
0 thru 7 GS ns RL = 2.0 kΩ
tPHL output 9.0 21
tPLH In-phase
p 16 25
EI A0 A1
A0, A1, or A2 ns
tPHL output 12 25
tPLH In-phase
p 12 17
EI GS ns
tPHL output 14 36
tPLH 12 21
In-phase
tPHL EI EO 28 40 ns (LS148)
output
30 45 (LS748)