2009 Third International Conference on Genetic and Evolutionary Computing
Research on Phase-Locked Control Strategy for Three-Phase Combined Inverters
Zhang Xianjin1
Institute of Electronic Engineering
Huaihai Institute of Technology
Lianyungang, China
E-mail: zxjb0703113@yahoo.cn
Abstract—A novel control strategy for three-phase combined
inverters is proposed based on phase-locked loop (PLL)
technology. Phase synchronous signal is easily disturbed in the
process of signal transmission for conventional combined
inverters with control-wire connection, which is solved by
demodulation of a certain output voltage. The proposed
concept is simple, and easy to implement. And good
symmetrical three-phase output voltage could be achieved
under unbalanced loads, even with inverters of different
topologies and controllers combined together. It demonstrates
almost the same high performance as that in stand-alone
operation mode. Experimental results of 3.6-kVA three-phase
combined inverter prototypes are presented to verify the
validity and feasibility of this scheme.
Keywords-voltage source inverters(VSI);phase-locked
loop(pll);combined inverter
I. INTRODUCTION
Three phase voltage source inverters (VSI) are
commonly applied in high power or three-phase-four-wire
power systems. The most popular configurations are three-
phase full bridge, three-phase half bridge, three-phase four-
leg, and modular combined inverters [1]. The first three need
universal controller that are not fit for modular design and
manufacture except the last one. However, conventional
combined inverters require communication (control-wire
connection) between modules at a cost as Fig.1 depicted.
When modules are allocated far from each other, noisy
signals interfere with normal signals unavoidably in process
of signal transmission. And additional phase deflection
occurs inevitably, especially with unbalanced loads [2].
In order to get symmetrical output voltage, phase-locked
loop (PLL) concept is introduced to combined inverters
from gird-connected inverter and active power factor
rectifier field [3]. This paper presents a novel control scheme
derived from PLL technology for combined inverters that
solves the signals interference problem of existing structure.
The paper is organized as follows. The novel concept is
presented in Section II along with an analysis of its basic
working principles. Applications of the proposed control
strategy are demonstrated in Section III with two types of
978-0-7695-3899-0/09 $29.00 © 2009 IEEE
DOI 10.1109/WGEC.2009.17
Wang Jianhua2
College of Automation Engineering
Nanjing University of Aeronautics & Astronautics
Nanjin, China
different inverters combined together. Experimental results
are also presented in Section IV to verify the concept and
the analysis results.
Fig.1 Structure of conventional combined inverters
II. THEORETICAL ANALYSIS OF PROPOSED PLL
STRATEGY
Generally, three-phase modular combined inverter is
composed of three independent modules. In order to obtain
three-phase symmetrical voltage, reference voltages vref
must have same magnitude and frequency. And it is easy to
implement using the same clock signal or crystal oscillator
that matches very well. However, the most challenging issue
is to guarantee three references are separated accurate 120°
between each other, which usually needs control-wire
connection for phase synchronization. Not only clock signal
but also synchronous signal is weak signal, hence easily to
be disturbed.
From another prospective, inverter not only convert dc
voltage into ac voltage vo from input to output terminal, but
also modulates input voltage following reference signal like
signal procession circuit: clock signal vclk→ reference
square wave synchronous signal vsyn → reference sine wave
voltage vref → inverter bridge middle point voltage
→sinusoidal wave output voltage vo. So ac voltage vo
contains same information from vref and vreset. In perspective
of signal demodulation as an inverse process above, clock
and synchronous signals could be reproduced from vo. And
fortunately a PLL circuit is the one to generate signal which
is synchronous to input signal [4].
III. MODELING AND ANALYSIS OF PLL ISSUE
The PLL generates a signal as a tracking signal that is an
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exact duplicate of the input fundamental component when He(s) = s/ (s+ kd·kv·F(s)/(s·N)) (3)
the system is in steady state (i.e. identical frequency, With final value theorem of Laplace transform theory,
amplitude, and phase). Under disturbance conditions, the θe (∞) = lim sθi ( s) H e ( s ) (4)
frequency, amplitude, and/or phase variations of the input s →0

signal are detected by the PLL and then the tracking signal Considering two kinds of possible input in practice:
is adjusted to match the input fundamental component. Fig.2 phase step and frequency step signals,
provides a simplified block diagram illustrating the Phase step input:
operation of the PLL, which is composed of a phase detector θi(s)= △φ/(s) (5)
(PD), a loop filter (LF), a voltage- controlled oscillator 2
s ⋅ ∆φ
(VCO) and divider. θ e (∞ ) = lim 2 =0 (6)
s →0 s + k ⋅ k ⋅ F ( s ) / N
d v

Input signal f in
PLL Circuit

Magnitude / dB

Phase / 
A Phase Detector Loop Filter Voltage Controlled Oscillator
B
(PD) C important D (VCO) f out 180
Feedback signal Phase difference DC voltage −20dB / dec
f out Output siganl
90 Kv ⋅ K p
N f out
fc =
2π ⋅ N
f out
0 0
N 1
Frequency Divider −90
N
Frequency Generation Circuit

Fig.2 Block of PLL circuit fc Frequency/Hz

The phase difference between the input and the expected Fig.4 Open-loop transfer function of PLL
signals is measured using PD and passed through a LF. The
error signal drives a VCO which generates the output signal.
The output signal is divided by a divider and feedbacked as
the expected signal. It is apparent that the PLL is a negative
feedback closed loop system. The concept of crossover
frequency and phase margin are the same as that in
converter’s design.Fig.3 shows small signal model of PLL
circuit.
Input signal f in (a)
Phase Detector Loop Filter PLL Circuit
θi vd vc θv
Kd F ( s) Kv
θo
vd = K d (θ i − θ o ) vc = F ( s )Vd Kv
f out θv = vc
Feedback signal s
N

θv
θo = 1
N Frequency Divider
N
1
N

Fig.3 Small signal model of PLL

Open-loop transfer function:

(b)
T(s) =kd·kv·F(s)/(s·N) (1)
Fig.5 Loop filter：(a) 1st order passive RC loop filter,(b) 2nd order
Where kd is the gain of PD, kv/s is the transfer function of
active loop filter
VCO, F(s) is the transfer function of LF, and 1/N is the gain
of divider. Fig.4 shows it’s bode plots. Equation (6) shows that any phase error will be
In order to regulate a phase error signal to zero, at least a eliminated by PLL. However, when frequency step input
pole must be added using loop filter. And 1st order passive occurs, steady error will be an inevitable issue.
RC network is the simplest one to implement, compared Frequency step input:
with active loop filter as Fig.5 shown. At this time, Loop θi(s)= △ω/(s2) (7)
filters transfer function:
∆ω
F(s) = 1/(s τ +1), τ =RC (2) θ e (∞) = lim
s →0 s + k ⋅ k ⋅ F ( s) / N
It is apparent that F (0) =1, so dc gain of open-loop d v (8)
transfer function is quite low, then steady error may occurs. ∆ω
=
Detail discussions are expanded as follows: k d ⋅ kv ⋅ / N
Error transfer function:

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 Fortunately, the frequency step input steady error stays
in a certain range and it is easy to compensate and
unnecessary to go into detail. If it is possible, high order
active loop filter would be a good solution like that in Fig.5
(b).
In actual application, output voltage voa of any module is
transmitted to other inverters, where synchronous signal is
demodulated from strong ac voltage. And the PLL circuit
immune to wide band stationery or non-stationery noise,
harmonics/inter-harmonics, and disturbances. So this
approach overcomes the disadvantage due to noisy signals
mentioned above. The most attractive advantage is that good
symmetrical output voltage could be obtained in this way
even with inverter modules of different topologies and
controllers combined together. However, the proposed PLL
control strategy indicates that three phase combined
inverters are composed of master and slave units, at the
expense of the independence lost of slave modules.
IV. USING THE TEMPLATE
The 28-VDC/115-VAC, 400-Hz, 3.6-kVA two-stage
three-phase combined inverter modules are developed as
prototypes. The front converter is duty-cycle control push-
pull-forward converter, and the inverter is hysteretic current
control half bridge dual buck inverter [5] in Fig. 6.
Fig.8 shows synchronous signal v400syn and clock signal
vclk of slave unit is obtained from voa of master unit, and
Fig.9&10 shows symmetrical three-phase reference and
output voltages, which are all under full load condition.
Even in the case that two modules are made of different
topologies and controllers, as illustrated in Fig. 11, where
inverter b from Avionic Instruments, INC is unloaded as the
master unit and the other prototype a is 2/3 uneven loaded as
the slave unit. The phase deflection is ≯ 2°, which fits
GJB-181A-2003 well. And there is little performance
degradation of slave unit with THD≯1.5%, compared with
its stand alone operation mode. Fig.12 shows the physical
construction, showing the compact design that was achieved.
−voa (200V / div )
v400 sqr (20V / div)
v400 syn (10V / div )
vclk (10V / div)
500µs/div
Fig.8 synchronous and clock signal

vrefa (4V / div) vrefc (4V / div) vrefb (4V / div)

Fig.6 Half bridge dual buck inverter topology 500µs/div

Fig.9 Reference voltage waveforms of three identical inverters combined

voa (100V / div) voc (100V / div) vob (100V / div)

500µs/div
Fig.7 Bode plots of PLL circuit Fig.10 Output voltage waveforms of three identical inverters combined

The prototypes employ PLL IC CD4046 and Frequency

v400 syn (10V / div)
Divider CD40103 for 400Hz synchronous and 7.2kHz clock
signal generation, with 1st order passive RC loop filter used: v400 reset (5V / div)

R=68kohm,C=100nF.The following major components of voa (100V / div)

inverter are selected: output inductor Lfac1= vob (100V / div)

Lfac2=550µH,output capacitor Cf=6.6µF and dc bus capacitor

C1= C2=470µF.
Fig.7 shows bode plots of PLL circuit with 1st order loop
filter. The crossover frequency is 27Hz with 50°phase 500µs/div
margin, which proves good stability and dynamic Fig.11 Waveforms of two different inverters combined
performance.

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(a) (b)
Fig.12 Photos of prototype: (a) single inverter, (b) combined inverter
V. CONCLUSION
In this paper, the essence of phase signal communication
in three-phase combined inverters is analyzed. A novel
control strategy is proposed based on PLL technology,
which overcomes noisy signal interference by using
conventional control-wire connection. It is simple, reliable
and easy to implement. Moreover, with this control scheme,
even inverters with different topologies and controllers
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could be combined together, making it of great importance
in application.
REFERENCES
[1] Daolian Chen, Xu Li, “Conbined three-phase inverters with high
frequency pulse dc link,” in Records of IEEE Power Electronic
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[2] Min Chen, “Research and design of 9kVA three-phase combined
inviter,” Master Dissertation, Nanjing University of Aeronautics &
Astronautics, China, February 2002.
[3] H. Shokrollah, Timorabadi and F.P.Dawson, “A three-phase
frequency adaptive digital phase locked loop for measurement,
control, and protection in power systems,” in Records of IEEE Power
Conversion Conference, 2007,pp.183-190.
[4] Floyd M. Gardner, Phaselock Techniques, 3rd ed. Wiley-Interscience,
2005, pp. 73-74.
[5] Stanley G. R. ,K. M. Bradshaw , “Precision dc-to-ac power
conversion by optimization of the output current waveform-the half
bridge revisited,” IEEE Transactions on Power Electronics,vol.14
no.2, 1999,pp.373-380.