HIGH SPEED DATA ACQUISITION SYSTEM USING

FPSLIC
Mamta V. Patel Aarti G. Yadav

Abstract:In this paper we propose an integrated hardware/software design methodology for the
implementation of High Speed Data Acquisition System. We map this architecture on Atmel;s innovative
processor + FPGA chip (FPSLIC) where the acquisition of the data is implemented by FPGA part and
processing is done through AVR processor. The emphasis is the development of a method to enhance the
reusability of HW and SW in the co design process using languages like C and VHDL.

Keyboard: FPSLIC (Field Programmable System Level Integrated Circuit), FPGA (Field Programmable
Gate Array), AVR (Advance RISC Controller)

1. INTRODUCTION
There are different approaches to design High speed 1.1.1 FPSLIC:
data acquisition system but the advantage of The heart of the system is FPSLIC. The FPSLIC family
implementing SOC using FPGA is its is a combination of Atmel’s AT40K series SRAM
reprogrammability, flexibility, low cost and low power. based FPGAs and the high performance Atmel AVR 8-
Because FPGA is reprogrammable its removes the NRE bit
(Non Recurring Engineering) cost from prototyping and
testing new designs. Once a design is created,
simulation routine can be done on a PC to debug any
hardware or timing issues. Lastly FPGA allows the
platform to be reconfigured for future design. LCD PC- DISPLAY
RESULT IN VB6 MAX 232
1.1 System description

The High speed data acquisition system using FPSLIC FPSLIC

consists of following main parts.
1. 16 i/p channels DUAL
2. Multiplexer AT10K AVR
PORT
3. Flash type ADC
4. PGA (Progrmmable Gain Amplifier) FPGA SRAM uC
5. FPSLIC
Selection
It acquires 16 channels of real time data (Any type of lines
analog channel). The channels are multiplexed down to CD4067 D0-D7
1 channel using 16 to 1 Mux. The selection of each 4x4
channel is done by FPGA. Once the channel is selected 16:1 PGA ADC KEYBO
then data from particular channel is given to PGA MUX 0820 ARD
whose gain is selected by FPGA. The output of PGA is
given to flash type ADC whose control inputs are GAIN CONTROL
provided by FPGA. As soon as ADC completes SELECT I/P’s
conversion an interrupt is generated and given to FPGA 16
then the digital data from ADC is stored in SRAM of i/p’s
FPSLIC. The stored data in SRAM is accessed by AVR Figure1. Block diagram
microcontroller & processing is done on it. The RISC microcontroller with standard peripherals. Figure
processed data is taken from AVR microcontroller 2 presents a block diagram of the FPSLIC architecture.
using serial communication and is displayed on PC Between the FPGA and the AVR re-sides up to 36K of
using Visual Basic as a front-end. 15ns dual port SRAM. The memory space of this
SRAM is divided into the program that is accessible
only by the AVR microcontroller (the data and the
address bus are 16-bit wide) and the data memory space
that is accesible by the FPGA user logic and the AVR
(the data bus is 8-bit wide while the address bus is 16-
bit wide for both sides). Structurally, this internal
SRAM is divided into three blocks: 10K X 16 dedicated
program SRAM, 4K X8 dedicated data SRAM, and 6K
X 16 or 12K X 8 configurable SRAM, which may be
swapped between the program and data memory spaces
in 2K X 16 or 4K X 8 portions.The AVR sees the
FPGA matrix as a set of 16 peripheral ports which it
controls through 16 interrupt and 16 I/O select lines.
The data exchange between the FPGA and the AVR is
handled by two 8-bit data buses: ADOUT and ADIN.
Also, the AVR sends to the FPGA two clock
signals,GCLK5 and GCLK 6, for synchronization
purposes.

1.1.2 Multiplexer: The first block is 16 channel

multiplexer (74HC4067) which will allow only one
channel to pass at a time. The selection inputs (S0-S3)
are provided by FPSLIC that will give selection input
as per the key pressed by the user. So selection of
channel depended on the key pressed by the user. If the
user presses key number one FPSLIC will give
selection input(0001) so that only the input connected Figure 2. FPSLIC architecture
on channel one will be passed through the multiplexer. through FPGA is that it can be used to display very
1.1.3 ADC: The ADC used in application is useful data i.e. if you are using sixteen bit counter and
(AD0820) which is flash type ADC and does the if you want to know the current count of your designed
conversion in nibble mode means it first provides lower counter you can directly display the count value using
nibble and then provides higher nibble. The conversion I/O lines of FPSLIC.
time of ADC is 1.5us and power dissipation is 75mW.
The function of adc is to perform the analog to digital 1.1 .6 PC: The use of PC in the application is to
conversion of the input being selected by the display the graph of the variations in input signals.
multiplexer. It works in two mode (1)read mode (2) For this purpose the programming language Visual
write mode. We have put it in write mode. The control Basic 6.0has been used.So to display the waveform
inputs (RD,WR and CS) to ADC have been provided by the program is written in VB that helps to display
the FPGA so ADC is synchronized with FPGA that is graph of the input channel being selected by the
as ADC converts analog input into digital one it gives user.
interrupt (INT) to FPGA and FPGA fetches the data
and stores it into SRAM at particular location specified 1.1.7 FPGA-AVR Interface
in software. At each and every interrupt address is
incremented by one.

1.1.4 Keyboard : The use of 4X4 matrix keyboard is

for channel selection. The keyboard has been interfaced
through Port E of AVR microcontroller and its program
is executed only when there is interrupt on the INT0 pin
of FPSLIC.

1.1.5 LCD: The 16X2 LCD has been used and it has
been interfaced by FPGA. The lcd receives all the data
(d0-d7) and the control inputs (RS,RW,EN) from
FPGA. The advantage of interfacing lcd
Figure 3. FPGA-AVR Interface
Figure 3 provides details on the AVR and FPGA
interface, showing how peripheral functions
implemented in the FPGA can be directly mapped into
the address space of the AVR microcontroller. Again, 2.SOFTWARE FOR APPLICATION:
because the AVR microcontroller and FPGA interface
logic is “hardwired” into the FPSLIC device, the
effective utilization of the FPGA logic gates is
significantly higher. The result of these features is to
increase the efficiency of the FPGA, improve START
performance, and simplify the design process.

The AVR data bus interface directly into the

FPGA busing resources, effectively treating INITIALIZE LCD
the FPGA as large I/O devices. INITIALIZE AVR PORT FOR

Up to 16 decoded address lines are provided MATRIX KEYBOARD
into the FPGA.

Up to 16 interrupts are available from the IF ANY KEY IS PRESSED
FPGA to AVR.
EXTERNBAL INT=LOW

The AVR can reprogram the FPGA during
operation to create a dynamic reconfigurable
system (cache logic). EXTERNAL INTERRUPT
ROUTINE
SELECTION =KEY PRESSED
1.2 Software Environment IOSELECT=1 ,FIOWE=1
Atmel ‘system designer 3.0 includes the HDL Plannner, FPGA-AVR DATABUS=KEY
synthesis tool (Leonardo Spectrum), Place and route tool
(Figaro IDS) as well as simulation tool Modelsim, FPGA INITIALIZATION=
bitstream generation and download tool. For software SRAMCLOCK=CLOCK 4 MHz
development we use AVR studio or IAR workbench. The SRAM IN WRITEMODE WE=1
following procedure is followed for downloading program into
FPSLIC.
For FPGA:
1. Writing code in HDL Planner. RISING
2. Simulation of VHDL code in ModelSim. EDGE
3. Synthesis of Code by Leonardo spectrum which CLK?
generates .edif file.
4. Routing by Figaro IDS which generates YES
bitstream(.Bst) file.

For AVR:
1. Writing code either using C or assembly AVR-FPGA
Language in Codevision AVR. INTERFACE
2. Compiling the code in AVR studio and
generates .hex file. YES

System Designer 3.0 has FPGA-AVR interface facility

as mentioned in Fig.3 which is used provide internal
MUX SEL=DATA
connection between FPGA and AVR so that they can DATA FROM AVR
communicate with each other. Final bitstream file is DATABUS TO FPGA
generated by it and the same is loaded into FPSLIC by
using ATDH2225 cable. Process data is transferred
through serial port to PC. Here draw the graph for real
time and also display min and max value at particular
time period. This data is also stored into MS ACCESS
B
for future use..
 AVR Microcontroller that makes execution
faster.
3. HW/SW both are reprogrammable so it
reduces NRE cost as well as time to market.
4. Partial dynamic reconfiguration is also
B possible which means user can modify
software program in running mode also.
5. AVR Microcontroller has 1Mips/MHz .
SRAM ADDRESS=60H
6. 1More than 120 instructions which are
executed in single clock.
7. In our application , we require simultaneously
acquisition of data through FPGA as well as
processing of data through AVR controller.
Speed is a major concern which can be
RISING achieved by FPSLIC.
EDGE
CLOCK
4.CONCLUSION:

It can be concluded that the use of FPSLIC gives faster

DATA FROM CHANNEL TO SRAM. scanning rate than any other microcontrollers can
AT THE SAME TIME PROCESS provide. Further in FPSLIC there is an inbuilt 8-bit
DATA INTO AVR .INITIALIZE microcontroller that makes processing of data very easy
SERIAL PORT.TRANSFER PROCESS and due to internal interfacing between FPGA and AVR
DATA TO PC Microcontroller the power consumption is very low.
Reconfiguration of hardware is very easy.
ADDRESS=ADDRESS+1

5. REFERENCES:
NO [01] Ayala, K.J., “8051 Microcontroller”, Second Edition,
Penaram International.
ADDR.=3FFFh [02] Mazidi, M. Ali and Mazidi J.G. “ The 8051
Microcontroller and Embedded Systems”, First
Edition,Pearson Edition.
YES [03] J. Bhasker “A VHDL Primer”, Third Edition
[04] Sudhaker Yalamanchali “VHDL from
Simulation to Synthesis”, Second edition
RESET SRAM ADDRESS
[05] M. Morris Mano “Digital Logic and Computer
Design”, Prentice Hall Of India
[06] www.atmel.com
[07] www.xilinx.com
3. RELATIVE COMPARISON [08] www.honeywell.com
The reason behind specifically using FPSLIC compared [09] www.datasheetarchieve.com
to any other device (Xilinx FPGA, Altera, PIC [10] www.philips.com
Microcontroller etc.) is as follows.

1. As FPSLIC is a monolithic device which is

having internal FPGA and AVR
Microcontroller with internal interfacing
between them, user need not to select device
separately and don’t need to do interfacing
which makes power consumed by FPSLIC
very low (20mW) as most of the power is
consumed in interfacing circuitry.
2. FPSLIC has 36K dual port SRAM which can
simultaneously be accessed by both FPGA and