Microelectronics Reliability 80 (2018) 68–78

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Threshold voltage peculiarities and bias temperature instabilities of SiC T

MOSFETs
⁎
Thomas Aichingera, , Gerald Rescherb, Gregor Pobegenb
a
Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach, Austria
b
KAI GmbH, Europastraße 8, 9524 Villach, Austria

A R T I C L E I N F O A B S T R A C T

Keywords: Silicon carbide (SiC) based metal-oxide semiconductor-field-effect-transistors (MOSFETs) are increasingly ent-
SiC MOSFET ering the high power device market. Besides all the well-known benefits which come along with these new
Threshold voltage hysteresis generations of switches, the nature of the wide bandgap material and the different properties of the semi-
BTI conductor-dielectric interface involve some natural peculiarities in threshold voltage variation and bias-tem-
Device preconditioning
perature-instability (BTI) which differ from comparable silicon (Si) MOSFET counterparts and which need to be
Vendor analysis
understood and assessed. The target of this paper is to highlight such differences, explain their relation to the
semiconductor material, challenge their relevance for the application and define their consequences with regard
to datasheet specifications. Most of the new effects can be understood by means of simple physical models and do
not compromise the reliability of the device. However, it turns out that the standard test procedures typically
used to characterize threshold voltage and threshold voltage drifts for Si devices need to be adapted for SiC
MOSFETs. A new measure-stress-measure procedure for BTI evaluation of SiC MOSFETs is proposed which al-
lows distinguishing between reversible threshold voltage hysteresis and more permanent threshold voltage drift
(BTI). The measurement pattern is then used to assess the VTH stability of recently launched SiC MOSFET parts.
The tested devices differ considerably in BTI drift amplitude and drift variation. The differences are attributed to
variations in device processing and device design.

1. Introduction
High voltage switches based on silicon carbide (SiC) are becoming
mainstream. In particular for voltage classes above 600 V, SiC tech-
nologies promise considerably enhanced performance compared to si-
licon based metal-oxide-semiconductor-field-effect-transistors
(MOSFETs) [1,2]. SiC MOSFETs provide significantly reduced static and
dynamic losses and can be operated at higher temperature, higher
power density and higher frequency. These features have clear system
benefits. Operation at higher frequencies with lower losses allows
shrinking passive components of inverter integrated circuits (ICs) as
well as heat sinks making full SiC system solutions much lighter, more
compact, cheaper and more efficient [3,4]. Despite of all those well-
known benefits it took 10 years after successful market launch of SiC
diodes in 2001 by Infineon [3] until the first productive SiC MOSFETs
were launched by Rohm and Cree (today Wolfspeed) in 2011/2012.
Between 2012 and 2016 several other device manufacturers such as ST
Microelectronics, Microsemi and others have further enriched the
portfolio of SiC MOSFET technologies on the market. These first
generation devices were all planar n-channel DMOS technologies based
on 4H-SiC with the SiC/SiO2 interface at the Si-face of the (0001) plane.
Since very recently Rohm and Infineon have launched the first SiC
trench-MOSFET devices [5,6]. The trench technology allows for higher
packing density and smaller pitch size. Furthermore, it was shown that
the vertical crystal planes of 4H-SiC provide higher channel mobilities
in comparison to the planar (0001) planes [7]. Both advantages im-
prove device performance and reduce the on-resistance times active
area ratio (RON × Aact). Thus, despite higher fabrication complexity it is
very likely that trench topologies are the future of SiC MOSFETs.
One could wonder why it took more than 15 years until SiC
MOSFETs have evolved into a mature productive technology. One
reason can be surely found in SiC specific manufacturing challenges.
Examples are enhanced wafer roughness and wafer bow, smaller wafer
diameter, transparency and hardness of the material as well as the need
for developing new fabrication processes such as high temperature
doping activation anneals, ohmic contact formation and new interface
passivation schemes. Furthermore, before a product can be launched, it
has to be proven that the technology meets industrial and/or

⁎
Corresponding author.
E-mail address: thomas.aichinger@infineon.com (T. Aichinger).

https://doi.org/10.1016/j.microrel.2017.11.020
Received 9 August 2017; Received in revised form 22 November 2017; Accepted 22 November 2017
0026-2714/ © 2017 Elsevier Ltd. All rights reserved.
T. Aichinger et al.
automotive reliability standards. To accomplish a successful qualifica-
tion, certain new “not silicon-like” features of SiC MOSFETs had to be
understood and assessed, many issues had to be solved and several bugs
fixed. A number of SiC specific challenges are somehow linked to gate
oxide reliability, i.e. (i) early gate oxide breakdown and (ii) threshold
voltage instabilities.
With regard to the first challenge, early gate oxide breakdown, the
most important difference between SiC and Si MOSFETs is the 3–4 or-
ders of magnitude higher extrinsic defect density of SiC MOS structures
at the end of the process. This much higher defect density is most likely
linked to substrate defects, metallic contaminations and particles.
Today it is possible to get SiC MOSFETs down to the same low failure
rate as Si-MOSFETs or IGBTs, by applying smart screening measures
[8]. The enabler for efficient gate oxide screening is a much thicker gate
oxide than what is typically needed to fulfill intrinsic lifetime targets. In
this way an extrinsic reliability threat can be transferred to yield loss. A
detailed discussion on intrinsic and extrinsic gate oxide reliability of SiC
MOS structures can be found in Ref. [9].
The second challenge, threshold voltage instabilities, is in general
not linked to macroscopic defects or impurities. One has to distinguish
between intrinsic and extrinsic threshold voltage instabilities. Extrinsic
threshold voltage instabilities are due to ionic contaminations such as
sodium or potassium which could enter the gate oxide either during
device fabrication or from outside during normal device operation.
Both the origin and the effect of extrinsic threshold voltage instabilities
are basically the same for Si and SiC MOSFETs. The procedures to
prevent mobile ions from entering the gate oxide or to get rid of them
during device processing are very well established for Si MOS tech-
nologies. The know-how and experience for detection and elimination
can be directly applied to SiC MOSFETs. Intrinsic threshold voltage
instabilities, on the other hand, are rather linked to the physical
properties of the interface, i.e. the density of interface states and border
traps and their ability to exchange charge carriers with the semi-
conductor substrate. Despite the fact that SiC is the only wide bandgap
semiconductor that possesses a high quality native oxide, the SiC/SiO2
interface is still very different from the Si/SiO2 interface. This is not
only due to the wider bandgap and the narrower band offsets to the
dielectric but also a result of vacancies and carbon related point defects
which only exist in SiC [10,11,12]. To passivate those new defect types,
alternative post oxidation passivation schemes (other than forming gas)
had to be developed. Naturally, different interface properties cause new
features in the transfer characteristics of SiC MOSFETs which will be
discussed in detail in the following sections. Most of these new features
can be understood by means of simplified physical models which allow
a better understanding of process dependencies and help to properly
setup and assess the results of lifetime tests.
One target of this paper is to highlight and help to understand new
features and peculiarities in threshold voltage variations of SiC
MOSFETs. We will discuss differences and similarities in origin, effect
and relevance of threshold voltage instabilities in Si and SiC MOSFETs.
Furthermore, a measurement procedure will be suggested allowing the
assessment of application relevant components in the total VTH drift in a
defined and reproducible manner. In the last section of the paper the
procedure is used to compare VTH instabilities of recent productive
technologies of three different SiC MOSFET manufactures.
2. Relevance of BTI for Si and SiC MOSFETs
In view of the operation of a MOSFET, intrinsic BTI may affect the
device performance in two different ways: (i) BTI causes a parallel shift
of the transfer characteristics and (ii) BTI degrades the slope of the
transfer characteristic.
Independent of the technology (Si or SiC), the consequences for n-
channel MOSFETs are the following
(i) Electron trapping during positive BTI stress causes a positive drift in
69
Microelectronics Reliability 80 (2018) 68–78
threshold voltage thereby reducing the drain current in the on-
state. On the other hand, hole trapping during negative BTI stress
causes a negative drift in threshold voltage which may lead to
parasitic turn-on of the device in the off-state.
(ii) If precursor sites are depassivated during BTI stress they may act as
additional charge trapping and/or scattering centers. Consequently,
the channel mobility can be reduced which degrades the drain
current in the on-state.
For Si devices it is known that n- and p-channel MOSFETs show
different BTI. This causes particular problems for complementary MOS
(CMOS) circuits where both device types are used at the same time in
one system. BTI and transconductance degradation ultimately affect the
operating frequency and lead to a speed reduction of CMOS circuits and
ring oscillators [13,14]. In sub-22 nm technology nodes SiO2 has been
replaced by alternative dielectrics such as SiON or high-k materials.
Such insulators are known to show enhanced BTI. In these fields (and
some other niche applications) BTI is still a serious reliability concern
even for Si MOSFETs.
The applications of SiC MOSFETs are very different to logic IC Si
devices. Typical application fields of SiC MOSFETs are motor drives,
inverters, converters, switch mode power supplies, induction heating
systems and photovoltaics. All these applications require high power
densities and blocking voltages beyond 600 V. Today this market is
dominated by Si device technologies such as CoolMOS™ and IGBT
which hardly show any intrinsic BTI. However, in the near future some
of these applications will be served by hybrid and/or full SiC solutions
to increase performance and reduce system costs. In order to accom-
plish a smooth transition from Si to SiC technologies, it is important to
assess the impact and relevance of BTI for such applications and un-
derstand differences between SiC and Si technologies. In the following
it will be discussed how BTI induced threshold voltage drifts could
possibly affect the reliability and performance of high power devices
and integrated systems:
i. High power devices are often connected in parallel in modules to
enhance the maximum current. The efficiency of parallelization
depends on the matching of the on-resistance and threshold voltage
of the individual devices. Irregular VTH degradation due to BTI may
lead to inhomogeneous current distributions within the system. As a
result, the commutation efficiency degrades and the module tem-
perature increases.
ii. A gradual positive drift of the threshold voltage reduces the
overdrive in the on-state. As a consequence, the channel resistance
of single devices is increased which degrades the efficiency and
enhances static losses and the module temperature.
iii. A gradual negative drift of the threshold voltage may shift the VTH
of the device below a critical value. A too low threshold voltage can
then cause parasitic turn-on during fast switching, thereby enhan-
cing switching losses and device/module temperature.
To relax the first threat (i) one has to make sure that devices which
see the same mission profile during application show a similarly narrow
and predictable VTH drift. This is typically the case for intrinsic BTI.
Problems only arise if the interface and gate oxide quality of individual
devices show large variations, i.e. due to process inhomogeneity. Ionic
contaminations within devices or packages may also degrade paralle-
lization. However, as already mentioned previously, the effects of ex-
trinsic BTI in Si and SiC technologies are similar and need to be pre-
vented anyhow.
The second threat (ii) describes a degraded RON due to a positive
drift of the threshold voltage. In high power MOSFETs the RON is ty-
pically a composition of essentially three major components
RON = R ch + RJFET + R epi (1)
In (1) Rch is the channel resistance of the device, RJFET is the
T. Aichinger et al.
junction-field-effect-transistor (JFET) resistance and Repi is the epitaxial
layer resistance of the drift region. In a first order approximation, the
channel resistance of a MOSFET is given as
L L
R ch = ≈ ,
Wμn qninv Wμn Cox (VG, use − VTH ) (2)
where W is the width of the channel, L is the length of the channel, μn is
the free electron mobility, q is the elementary charge, ninv is the in-
version charge density at the interface, VG, use is the gate use voltage,
VTH is the threshold voltage of the device and Cox is the gate oxide
capacitance. The inversion charge density is proportional to the
overdrive (VG, use − VTH). A significantly increased threshold voltage
due to BTI reduces the overdrive and therefore degrades the channel
resistance.
In Si power devices the RON in (1) is dominated by the JFET and
drift zone resistance. The MOS channel itself contributes only a small
fraction to the total device resistance because the inversion channel
mobility of Si MOSFETs is high and the interface state density is low.
Thus, a drift in VTH due to BTI will cause only a very small change in the
RON and is therefore uncritical for the device performance. In this point
there is an important difference between Si and SiC MOSFETs. In SiC
MOSFETs the channel resistance can make up to 50% of the total device
resistance due to lower inversion carrier mobility at the SiC/SiO2 in-
terface and because of depletion of inversion charge density due to
enhanced electron trapping [15]. Also, for the same voltage class, the
relative contribution of JFET and drift zone resistance is smaller due to
the much higher blocking capability of SiC. As a consequence, the RON
of a SiC MOSFET is more sensitive to a reduction in overdrive, increase
in VTH respectively. Due to this higher sensitivity it is crucial to cor-
rectly assess BTI for particular mission profiles of SiC MOSFETs and
take it into account when rating the maximum RON of the device.
The third threat (iii) imposes a hard specification limit to the
minimum allowed VTH rating of the MOSFET. The limit needs to be
tailored to the expected maximum negative VTH drift during application
to prevent parasitic turn-on. SiC MOSFETs exhibit a strong negative
temperature gradient of the VTH and an enhanced drain induced barrier
lowering (DIBL) effect. Thus, it is crucial to correctly assess the BTI
induced negative VTH drift for particular mission profiles of SiC
MOSFETs and take it into account when rating the minimum VTH of the
device.
From the discussion above one can conclude that SiC power
MOSFETs react more sensitively to threshold voltage drifts than Si
power MOSFETs. Nevertheless, BTI is no imminent reliability risk pro-
vided the VTH drift is
(i) Minimized by means of optimized device processing and interface
passivation (i.e. not related to contamination etc.),
(ii) Narrowly distributed,
(iii) Predictable and
(iv) Correctly considered in the ratings of the device.
In the next paragraph some basic features of intrinsic BTI of SiC
MOSFETs will be discussed and compared to Si MOSFETs.
3. Intrinsic VTH instabilities in Si and SiC MOSFETs
In the introduction section it was pointed out that the SiC/SiO2
interface is more complex than the Si/SiO2 interface because of (i) the
involvement of carbon and (ii) the wider bandgap (3.3 eV instead of
1.1 eV).
(i) The involvement of carbon related defect species requires alter-
native passivation schemes. In SiC/SiO2 systems state-of-the-art defect
passivation is achieved by either direct oxide growth in nitric oxide
(NO), nitrous oxide (N2O) or by nitric oxide or ammonia (NH3) post
oxidation anneals (POAs) at temperatures above 1100 °C
[16,17,18,19,20]. Most publications report that standard forming gas
70
Microelectronics Reliability 80 (2018) 68–78
Fig. 1. Schematic drawing of the band offsets between Si/SiO2 and 4H-SiC/SiO2.
anneals or anneals in H2 is not very effective in SiC [21,22,23] while
they provide very efficient interface state passivation in Si/SiO2 systems
[24].
(ii) The wider bandgap of SiC provides a larger range for point
defects with energy levels between the conduction and the valance
band edges of 4H–SiC. An illustration of the band diagrams of Si and
SiC with respect to the SiO2 dielectric is given in Fig. 1.
To better understand threshold peculiarities of SiC MOSFETs, it is
expedient to make a discrete distinction between (i) short-term and (ii)
long-term effects. It will be argued in this paper that short-term effects
are mainly due to interface trapped charge and long-term effects are
mainly due to border traps. The nomenclature is in close agreement to
what has been the consensus for the Si/SiO2 system [25,26]. In the
following we are linking the terms interface trapped charge and border
traps to their electrical properties and response time.
We define interface trapped charges as point defects at the semi-
conductor-dielectric interface which are located energetically within
the semiconductor bandgap and which may exchange carriers with the
semiconductor substrate according to Shockley-Read-Hall (SRH) theory
[27,28]. Trapping and detrapping of carriers in interface states is trig-
gered by the position of the trap level (Et) and the Fermi level (EF) at the
interface. Another attribute of interface states is their invariant trap
level energy which means they do not undergo relaxation upon cap-
turing or emitting carriers. Interface states are often related to dangling
bond-like or vacancy-like centers [29,30]. A classical characterization
technique for fast interface states is charge pumping [31,32].
As opposed to interface states, border traps are traps within the SiO2
close to the semiconductor-dielectric interface. Charge exchange be-
tween the semiconductor substrate and border traps is an inelastic
tunneling process triggered not only by the substrate Fermi level posi-
tion but also by a thermodynamic energy barrier (Δ E). The barrier may
be widely distributed and is typically different for trapping and de-
trapping [33,34,35]. Border traps may undergo a relaxation upon
capturing or emitting carriers thereby stabilizing the charge state of a
trap for much longer times [33,36]. Border traps are often linked to
oxygen vacancies [37], interstitials, carbon-dimers [38], hydroxyl E′
centers [39,40] or silicon‑oxygen bonds with wide OeSieO angles and
elongated bond length [41,42].
Note that in reality the distinction between interface trapped charge
and border traps is not that sharp. In particular, border traps with very
shallow energy barriers may have similar attributes as interface states
and therefore may also contribute in fast transient measurements such
T. Aichinger et al.
as charge pumping [43]. Nevertheless, to get the basic idea on their
individual role in BTI, we will treat interface states and border traps as
separate groups which differ mainly in response time upon gate bias
(Fermi level) switches.
In the next two sub-sections we will argue that interface states cause
fully reversible threshold voltage variations while border traps are most
likely responsible for more permanent drift and long-term recovery
phenomena. Fully reversible means that the number of (near-) interface
trapped and emitted carriers during one gate voltage switching period
is constant even for billions of consecutive switching events, c.f. Ref.
[44]. This is also consistent with Ref. [45] where it was shown that
short-term threshold voltage instabilities and hysteresis effects in SiC
MOSFETs correlate with the recombination current in a charge
pumping experiment. In applications such as inverter circuits or motor
drives charging and discharging of traps at the SiC/SiO2 interface are
triggered in each high phase (on-state) and low phase (off-state) of the
AC gate driver signal. Because of their periodicity and invariability
threshold voltage variations due to interface trapped charges cannot be
considered as real instabilities but rather as controllable variables ad-
justable by proper device preconditioning in BTI testing and by the gate
driver levels in the application.
3.1. Threshold voltage hysteresis due to interface states
Using advanced oxide passivation, one may achieve today interface
state densities (Dits) in the range of 1011–1012 defects/eVcm2 in SiC/
SiO2 systems [46,47] while typical Dits in Si/SiO2 systems are in the
range of 109–1010 defects/eVcm2 [48,49]. It will be shown that Dits in
the range of 1011–1012 defects/eVcm2 naturally cause a measureable
hysteresis in the threshold voltage, which is especially visible in the
subthreshold regime and results in varying stretch-out of the sub-
threshold slope depending on the sweep direction [50]. When turning
an n-channel device on (sweep from accumulation to inversion), the
upward sweep threshold voltage (VTHUP) is typically lower than the
downward sweep threshold voltage (VTHDOWN) which is measured when
turning the same device off (sweep from inversion to accumulation), cf.
Fig. 2. We call the difference between VTHDOWN and VTHUP threshold
voltage hysteresis (Δ VTHHYST)
HYST DOWN UP
∆VTH = VTH − VTH . (3)
The hysteresis is caused by a non-steady state (thermal non-
(a) (b)
71
Microelectronics Reliability 80 (2018) 68–78
equilibrium) between the charge state of the interface states and the
Fermi level position in the semiconductor. The effect exists in SiC
MOSFETs but is not known for Si MOSFETs. There are two reasons why
a VTH hysteresis is typically not observed in Si MOSFETs: (i) the low Dit
makes the effect very small in amplitude and (ii) the narrow bandgap
causes a fast disappearance of the effect.
The hysteresis is due to the fact that interface traps are charged
positively within a certain fraction of the semiconductor bandgap when
measuring VTHUP in the upward sweep and charged neutrally when
measuring VTHDOWN in the downward sweep
HYST Qit qDit ∆EVTH tox
∆VTH = = .
Cox εr ε0 (4)
In (4) Qit is the total non-equilibrium interface trapped charge
stored within the energy range Δ EVTH, q is the elementary charge, εr is
the relative dielectric constant of SiO2, ε0 is the vacuum permittivity
and tox is the gate oxide thickness. Assuming an oxide thickness of
70 nm and by setting Δ EVTH for simplicity equal to the band gap of the
semiconductor, (4) yields a maximum hysteresis between 3.6 mV and
36 mV for a Si MOSFET (Δ EVTHmax =1.1 eV; Dit = 109 − 1010defects/
eVcm2) and a maximum hysteresis of 1.07 V and 10.7 V for a SiC
MOSFET (Δ EVTHmax = 3.3 eV; Dit = 1011 − 1012defects/eVcm2). It will
be demonstrated in the next two sub-sections that the width of the
energy range Δ EVTH and therefore the amplitude of the hysteresis effect
depends not only on the Dit but also on the time delay and on the Fermi
level position of the VTH readout.
3.1.1. VTH of the upward sweep – lower limit of Δ EVTH
The following discussion is illustrated in Fig. 3(a)–(c). In deep ac-
cumulation the Fermi level is pinned to the valance band, the interface
is positively charged and the system is in thermal equilibrium. As the
gate bias is switched from accumulation to inversion, where VTHUP is
measured, the Fermi level quickly moves across nearly the entire SiC
bandgap which drives the interface into a non-steady state. After the
bias switch the system slowly goes toward thermal equilibrium by
electron capture from the conduction band as well as hole emission into
the valence band.
Hole emission into the valance band defines the lower boundary of
Δ EVTH (EVTH, ep) in (4). The time constant for hole emission is given as
Fig. 2. Schematic illustration of the threshold
voltage hysteresis. The gate bias upward
sweep and downward sweep are depicted in
(a) and the corresponding drain currents are
sketched in (b).
T. Aichinger et al. Microelectronics Reliability 80 (2018) 68–78

(a) Fig. 3. Schematic illustration of restoration

of thermal equilibrium after a gate bias
switch from accumulation to the threshold
voltage. The gate bias switch is illustrated in
(a), the band diagram and gradual charging
of interface states in (b) and the corre-
sponding time-dependent upward sweep
threshold voltage in (c). In (b) positively
charged interface states are indicated as full
circles, neutral interface states are illu-
strated as open circles.

(b)

(c)

1 E − EV certain gate bias level is thus a direct measure of the inversion charge
τep = exp ⎛ t ⎞.
vth σNV ⎝ kT ⎠ (5) density

In (5) vth is the thermal drift velocity, σ is the capture cross section
and NV is the effective density of states in the valence band. The lower
boundary of Δ EVTH is then given as
EVTH , ep = EV + kTln (vth σNV tD, VTH ). (6)
In (6) tD, VTH is the delay time between the bias switch and the VTH
measurement. With increasing delay time, EVTH, ep moves closer toward
mid-gap making the energy range Δ EVTH narrower. The upper boundary
of Δ EVTH corresponds to the Fermi level position at the gate bias at
which VTHUP is measured. Within Δ EVTH positively charged interface
states are continuously neutralized by electron capture. The time con-
stant for electron capture is given as
1 interface approaches thermal equilibrium. From (7) and (8) and con-
τcn = . sistent with Fig. 4 it is obvious that the time to restore thermal equi-
vth σninv (7)
The larger the inversion charge density, the less time it takes to
restore thermal equilibrium. In a MOSFET device, the inversion charge
density is controlled by the gate bias. The drain-source current at a
IDS =
W
μ qninv VDS .
L n (8)
In (8) IDS is the drain-source current and VDS is the drain-source
voltage. Fig. 4 shows VTHUP transients of a SiC MOSFET extracted at
different drain current levels. Readouts were taken for 1000s at room
temperature after biasing the device for 100 ms in deep accumulation
(VGS = −15 V). To measure VTHUP over time, we have operated the
MOSFET in the gated diode biasing scheme which means we have
shorted gate and drain terminals (VGS = VDS) and connected the source
to ground. The tested device has a steady-state threshold voltage of
around 4 V at a drain current of 1 mA. Due to hole emission and elec-
tron capture one observes a time dependent increase of VTHUP as the
librium is indirectly proportional to the current level at which the
threshold voltage is extracted. This means that at a current level of
100 μA restoration of thermal equilibrium takes approximately 10
times longer than at a current level of 1 mA. Having realized that, one

72
T. Aichinger et al.
Fig. 4. VTHUP extracted on a SiC MOSFET device at different current levels after biasing
the device in deep accumulation for 100 ms. The higher the current level the larger is the
inversion carrier density and the faster thermal equilibrium is restored due to electron
capture.
Fig. 5. Universal VTHUP curve for 1 mA. The curve is extracted from the transients in
Fig. 4 scaling the actual time delays at certain current levels to the current level of 1 mA,
c.f. (9).
can calculate for different readouts at different current levels an
equivalent time at 1 mA (tD, 1mA′) and scale all curves in Fig. 4 to one
universal VTHUP transient curve, c.f. Fig. 5.
R ch,1mA IDS, i [mA]
tD′ ,1mA = tD, i ≈ tD, i
R ch, i 1 [mA]
In (9) tD, i is the delay time at the current IDS, i, Rch, 1mA is the channel
resistance at 1 mA and Rch, i is the channel resistance at the current IDS,
i. Note that the total device resistance is essentially identical to the
channel resistance at current levels at and below 1 mA. At 1 mA it takes
roughly 0.1–1 s until the device is in a steady state. The channel re-
sistance at 1 mA is around 4 kΩ. Considering that the rated RON of the
same device at the nominal gate voltage (e.g. + 15 V) is about 5 orders
of magnitude lower (40mOhm), we can extrapolate the time to restore
thermal equilibrium at the nominal gate voltage to below 1 μs.
3.1.2. VTH of the downward sweep – upper limit of Δ EVTH
The following discussion is illustrated in Fig. 6(a)–(c). In deep in-
version the Fermi level is pinned to the conduction band edge and the
system is in thermal equilibrium. As the gate bias is switched from the
nominal gate bias in deep inversion (e.g. + 15 V) to the threshold
voltage, where VTHDOWN is measured, the Fermi level position changes
only slightly. Thermal equilibrium is restored by electron emission into
the conduction band. Note that there is no hole capture because the
interface is inverted when measuring VTHDOWN. The time constant for
electron emission is given as
Microelectronics Reliability 80 (2018) 68–78
1 E − Et
τen = exp ⎛ C ⎞.
vth σNC ⎝ kT ⎠ (10)
In (10) NC is the effective density of states in the conduction band.
In the downward sweep thermal equilibrium by electron emission is
restored almost immediately as the trap levels above EF are located
energetically close to EC. Thus, VTHDOWN does not show similar long
recovery transients as VTHUP. Fig. 7 shows VTHDOWN transients of a SiC
MOSFET extracted at different drain current levels for 1000s at room
temperature after biasing the device for 100 ms in deep inversion
(+ 15 V). Independent of the current level VTHDOWN is immediately
stable within the measurement window. The small remaining constant
recovery slope of roughly 10 mV/dec is due to a small number of border
traps which become charged during the deep inversion phase and emit
their trapped carriers with long recovery time constants after the bias
switch.
From the discussion above we conclude that the threshold voltage of
the upward sweep (VTHUP) strongly depends on the delay time tD, VTH
and on the gate bias (Fermi level position) at which it is extracted. The
threshold voltage of the downward sweep (VTHDOWN), on the other
hand, is hardly altered by interface state charging and is almost im-
mediately stable after the bias switch.
In summary, in SiC MOSFETs a threshold voltage hysteresis effect is
observed when switching the device between deep accumulation and
deep inversion (e.g. from −15 V to + 15 V). We argue that this is be-
cause the interface gets positively charged before the upward sweep
and is neutralized before the downward sweep. The effect is much
weaker and even disappears if the device is switched only between
depletion and deep inversion (e.g. 0 V to +15 V) [45]. In depletion
there are no holes to get trapped and therefore the interface does not
charge up positively prior to the upward sweep. In general, the am-
plitude of the measured hysteresis depends on the current level at
which the VTH is extracted, the switching speed and measurement delay
as well as on the density of interface states. A large hysteresis is typi-
cally seen
(i) in the subthreshold regime of the MOSFET, at drain current levels
in the nano-ampere range, where the time constants for electron
capture (c.f (7)) are long [45] or,
(ii) in the threshold voltage regime of the MOSFET, at drain current
levels in the milli-ampere range, when performing fast gate bias
switches and measure VTHUP and VTHDOWN with time delays in the
micro-seconds regime [44].
(9)
It was reported in [45] that devices with the MOS channel on a
vertical crystal plane of 4H-SiC (e.g. the a-plane) show a larger hys-
teresis effect than devices with the MOS channel at the planar crystal
plane of 4H-SiC (e.g. the Si-face of the of the (0001) plane). Never-
theless, the former devices show better channel mobility. It was argued
that this is because of a lower Dit close to the conduction band and a
higher Dit around mid-gap. A lower Dit close to the conduction band
reduces electron tapping at gate voltages higher than the threshold
voltage of the device while a higher Dit around mid-gap increases
charge trapping in the subthreshold regime of the MOSFET.
We want to emphasize again that the reported VTH hysteresis is not
classical BTI and cannot be considered as degradation. It is a fully re-
versible and reproducible feature of SiC MOSFETs [44]. In the appli-
cation the VTH hysteresis may have the following effects:
(i) it may reduce switching losses because it actively supports turn-on
and turn-off of the transistor;
(ii) it may cause a drain current overshoot when using high dV/dt
slopes. This overshoot is due to a temporary higher overdrive and a
lower channel resistance at the very beginning of the high phase of
the gate pulse.
73
T. Aichinger et al. Microelectronics Reliability 80 (2018) 68–78

(a) Fig. 6. Schematic illustration of restoration

of thermal equilibrium after a gate bias
switch from deep inversion to the threshold
voltage. The gate bias switch is illustrated in
(a), the band diagram and gradual dischar-
ging of interface states in (b) and the cor-
responding time-dependent downward
sweep threshold voltage in (c). In (b) posi-
tively charged interface states are indicated
as full circles, neutral interface states are
illustrated as open circles.

(b)

(c)

To the best of our knowledge the reported VTH hysteresis has no

negative effect on the performance and on the reliability of SiC
MOSFETs. Nevertheless, it needs to be considered and understood in
order to include the effect into simulation and to correctly perform and
assess threshold voltage measurements and BTI.

3.2. Threshold voltage drift due to border traps

It was already mentioned in the introduction of this section that

border traps may exchange carriers with the semiconductor substrate
via a thermodynamic energy barrier (Δ E). The finite barrier height
stretches the capture and emission time constants allowing for longer
stress and recovery transients.
Fig. 7. VTHDOWN extracted on a SiC MOSFET device at different current levels after ∆E
biasing the device in deep inversion for 100 ms. The threshold voltage is stable within the ′ = τcn exp ⎛ cn ⎞
τcn
⎝ kT ⎠ (11)
measurement window independent of the current level at which it is extracted. There is
only a very small remaining recovery of roughly 10 mV/dec due to carrier emission from
∆E
border traps. ′ = τen exp ⎛ en ⎞
τen
⎝ kT ⎠ (12)

In (11) and (12) τcn′ ′

and τen are stretched electron capture and

74
T. Aichinger et al. Microelectronics Reliability 80 (2018) 68–78

(a) 3.3. Application relevant BTI testing of SiC MOSFETs using device
preconditioning

The best way to characterize the impact of BTI on a specific appli-

cation or system would be to run long-lasting switching tests under
normal operation conditions (10–100 kHz) and evaluate VTH and RON
drifts over time. It is very challenging to realize such a test because
single devices in packages or integrated systems are sometimes not
accessible and it is hard to resolve small drifts on-the-fly during ap-
(b)
plication. Nevertheless, it is worth the effort because the result can be
used to correctly assess and calibrate the outcome of a much simpler
productive BTI test which is typically performed using accelerated DC
stress conditions and accepting longer time delays between end of stress
and read-out. The target of this section is to suggest a reliability re-
levant BTI test for SiC MOSFETs which fulfills the following three cri-
teria:

Fig. 8. Schematic evolution of the threshold voltage during application. The gate signal is (i) reproducible;
sketched in (a); the response of the threshold voltage is depicted in (b). We assume that (ii) shows worst case application relevant drift;
interface states are mainly responsible for the hysteresis (ΔVTHHYST). They are fully
(iii) largely invariant against stress-measure time delays;
charged and discharged in every single switching cycle. Border traps are responsible for
time dependent drift of the threshold voltage (ΔVTHBTI). They may be increasingly
charged during long-term operation/stress leading to a gradual device degradation. Criterion (i) guarantees that the test can be used for quality mon-
itoring, (ii) assures that the result is representative for the application
and (iii) allows stressing multiple devices in parallel and afterwards
emission time constants. Δ Ecn and Δ Een are the barrier heights for
characterizing those in-series without being bound to strict guidelines
electron capture and emission.
for stress-measure time delays. Our test procedure is illustrated in
It was shown in Refs [33,34,35]. that a wide distribution of barrier
Fig. 9. The basic idea behind the proposed measure-stress-measure se-
energies can explain the power-law dependence of Δ VTH(tS) of BTI as
quence is to exclude the fully-reversible hysteresis effect from the ex-
well as the logarithmic log(trec) transients in BTI recovery. As opposed
tracted VTH drift by restoring a defined charge state at the interface
to interface states which are fully charged and discharged in every
before each threshold voltage read-out. This is achieved by using a
single switching cycle (ΔVTHHYST), border traps may be increasingly
100 ms negative preconditioning gate pulse before measuring VTHUP
charged during long-term operation/stress leading to a gradual drift in
and a 100 ms positive preconditioning gate pulse before measuring
VTHUP and VTHDOWN with stress time (Δ VTHBTI(t)). The issue is sketched
VTHDOWN. The amplitudes of the preconditioning pulses must be high
in Fig. 8, experimental verification is given in Ref. [44]. The actual
enough to charge the interface fully positive in the negative half-period
amplitude of the BTI drift during AC operation depends on a dynamic
of the gate pulse (deep accumulation) and fully negative in the positive
balance between stress and recovery, trapping and detrapping respec-
half-period of the gate pulse (deep inversion), e.g. −15 V / +15 V. In
tively. The details of the model are explained in the concept of capture-
this case the result is largely independent of the preconditioning time,
emission-time (CET) maps [35,51].
c.f. Fig.5 in Ref. [44]. For practical reasons we recommend a pre-
As discussed in Section 2, a gradual degradation of the threshold
conditioning time between 1 ms and 1 s. The voltage dependence of the
voltage in the application can be a reliability concern for SiC MOSFETs.
preconditioning is shown in Fig.3 of Ref. [45]. After an initial read-out
In order to limit BTI induced threshold voltage drifts, the SiC/SiO2 in-
(VTH, 0UP, VTH, 0DOWN), BTI stress is performed at elevated gate bias and
terface needs to be optimized not only for channel mobility but also
temperature with increasing stress times. In between the stress cycles
with respect to intrinsic bias-temperature stability. A reliable SiC
read-outs are performed at room temperature (or at stress temperature)
MOSFET needs to be designed in a way that both VTH and RON remain
using the same preconditioning procedure (VTH, iUP, VTH, iDOWN). The
within the specified ratings during the entire projected lifetime. Typi-
drift in VTHDOWN corresponds to the actual BTI degradation
cally, this requirement is secured via accelerated lifetime testing and
DOWN DOWN DOWN BTI
extrapolation to use-conditions. This is not straight-forward for SiC ∆VTH ,i = VTH ,i − VTH ,0 = ∆VTH , i. (13)
MOSFETs because the measurement of BTI-induced threshold voltage
A drift in the hysteresis (ΔΔ VTH, iHYST) would be given as an increase
drifts (Δ VTHBTI(t)) can be distorted by the hysteresis effect if not per-
of the difference between VTHDOWN and VTHUPwith stress time
formed correctly. In the next section a proper configuration of a mea-
sure-stress-measure procedure will be suggested for SiC MOSFETs in HYST
∆∆VTH DOWN
, i = (VTH , i
UP
− VTH DOWN
, i ) − (VTH ,0
UP
− VTH HYST HYST
,0 ) = ∆VTH , i − ∆VTH ,0 .
order to differentiate properly between threshold voltage hysteresis and
(14)
real BTI.
The result of such a test is shown in Fig. 10. We have used a stress

Fig. 9. Measure-stress-measure procedure suggested to evaluate

BTI for SiC MOSFET. Before threshold voltage readout a defined
charge state at the interface is generated by negative and positive
preconditioning.

75
T. Aichinger et al.
Fig. 10. BTI induced threshold voltage drifts as a function of stress time using the mea-
sure-stress-measure pattern illustrated in Fig. 10. The stress bias was + 35 V and the
stress temperature was 150 °C. The readout temperature was 30 °C and the delay time
between stress and readout was in the range of 1 h ± 15 min.
temperature of 150 °C and a stress voltage of +35 V. Readout was
performed at +30 °C. Note that the used stress voltage is 20 V higher
than the recommended gate voltage of the tested device (+15 V). The
time delay between stress and readout (tD, RO) was in the range of 1 h
( ± 15 min). This time is needed to cool down the device and perform
the readout sequence. During the delay time tD, RO the device was
floating. Fig. 10 shows that the BTI drift of the tested SiC MOSFET is
only about 350 mV after 160.000 s (45 h) accelerated DC stress. There
is only a very small drift in the hysteresis (ΔΔ VTHHYST) indicating a
negligible BTI induced increase in short-time VTH variations which we
attribute to the generation of interface states.
Fig. 11 shows the dependence of Δ VTHDOWN on the delay time (tD,
RO). Cooldown under bias has been used in order to achieve delay times
in the seconds regime. Within one decade in time Δ VTHDOWN recovery is
less than 10 mV. This means that Δ VTHDOWN is largely delay time-in-
variant if readouts are always performed within one decade in time
after termination of stress (e.g. between 1 h and 10 h or between
10 min and 100 min). A more detailed discussion on different test
procedures and cool down sequences can be found in Ref. [52]. In the
next section the same procedure will be applied to an ensemble of SiC
MOSFETs of different manufactures in order to compare their BTI.
3.4. Analysis of commercially available devices
Due to the benefits of SiC devices for power applications, the vendor
landscape of SiC MOSFETs is continuously growing. Several manu-
facturers are already on the market with their 2nd or 3rd device gen-
erations. To get an overview on BTI of recent SiC MOSFET technologies,
Fig. 11. BTI induced threshold voltage drift of the downward sweep as a function of delay
time tD, RO between stress and measurement. Shown are the results for two different stress
times, 1 h and 10 h. The stress bias was +35 V and the stress temperature was 150 °C.
The readout temperature was 30 °C. In order to achieve stress-measure delay times in the
seconds regime, we have used cool down under applied gate bias.
76
Microelectronics Reliability 80 (2018) 68–78
Fig. 12. Relative threshold voltage drift (ΔVTHDOWN/VTH, 0DOWN) of SiC MOSFET devices
of three different manufacturers. Up to 200 devices per manufacturer were stressed for
500 h at 150 °C using positive and negative stress biases between + 20 V and − 20 V. The
stress biases are indicated in the fig. M1 is a DMOSFET device, M2 and M3 are TMOSFET
devices.
we have subjected the latest device generations of three different
manufacturers to a 500 h BTI stress at 150 °C using positive and ne-
gative stress voltages between +20 V and −20 V. For all devices the
measure-stress-measure procedure illustrated in Fig. 9 was applied. To
gain some statistics, we have stressed between 28 and 200 devices of
each manufacturer. The extracted relative threshold voltage drifts are
illustrated in Fig. 12. Note that manufacturer M1 is a DMOSFET device,
while manufacturer M2 and M3 are trench MOSFET (also called
UMOSFET) devices. Fig. 12 shows that there is quite some variation in
VTH drift. The largest instabilities are seen in the trench MOSFET de-
vices of manufacturer M2. M2 shows positive and negative VTH drifts up
to 25% of its initial value as well as a large variation in the drift range
which is unfavorable for parallelization. The DMOSFET device of
manufacturer M1 shows up to 7% VTH drift in positive and up to 8% VTH
drift in negative direction when stressed with +19 V, −8 V respec-
tively. The negative drift of M1 is less than M2, however, one has to
consider the much lower stress voltage of only − 8 V. The range in VTH
drift of M1 is larger than the one of M3. The overall best performing
device in this test was the trench MOSFET device of manufacturer M3.
Despite of the largest range in stress voltages (+ 20 V/−20 V), the
devices of M3 show a very narrow drift range, which is good for par-
allelization. Furthermore, the drift of M3 at negative stress bias is al-
most negligible. The drift of M3 at positive stress voltage is very narrow
and below 10%. We believe that the large deviations in BTI of current
SiC MOSFET hardware is due to different interface passivation schemes
used to optimize the device performance. It is known, for example, that
excess nitrogen incorporated during nitric-oxide passivation may lead
to enhanced BTI [53]. Further possible reasons for the observed dis-
crepancies are different gate oxide thicknesses and crystal planes used
for the MOS channel.
3.5. Conclusions
In this paper we have highlighted peculiarities of threshold varia-
tions in SiC MOSFETs and discussed their relevance for the application
of high power devices. We have pointed out that SiC MOSFETs exhibit a
fully reversible hysteresis effect which is due to charging and
T. Aichinger et al.
discharging of interface traps. A similar threshold voltage hysteresis is
typically not seen in Si MOSFETs because of the much lower density of
interface states and due to the narrower bandgap. Even though the
hysteresis is no reliability threat, it needs to be considered while per-
forming a BTI stress test. To separate the hysteresis effect from the
actual BTI, a proper preconditioning needs to be applied prior to the
VTH readout. The purpose of the preconditioning is to bring the inter-
face into a well-defined and reproducible charge state before the
measurement. To assess the actual BTI of SiC MOSFETs, we have sug-
gested a measure-stress-measure procedure which allows determining
worst case application relevant drift and is largely invariant against
stress-measure time delays. The proposed BTI stress procedure was then
applied to an ensemble of SiC MOSFET devices of the latest device
generations of three different manufacturers. It was found that devices
differ considerably in VTH drift amplitude and drift variation. The dif-
ferences were attributed to deviations in device processing and device
design. The best device (M3) showed a very narrow drift range, almost
no BTI drift after 500 h at 150 °C and −20 V gate voltage and less than
10% increase in VTH after 500 h BTI stress at 150 °C and + 20 V gate
voltage.
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