MATLAB® and Simulink® for

Embedded System Design

© 2007 The MathWorks, Inc.

Pieter J. Mosterman
pieter.mosterman@mathworks.com
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592 rtb_either = power_window_con_B.passenger_control_b Senior Research Scientist
593 || power_window_con_B.passenger_control_a; The MathWorks, Inc.
594
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596 * Inport: '<Root>/driver_up'
597 * Logic: '<S13>/overrule'
598 */
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Introduction

 Increasing complexity of embedded systems

 Complexity
– Intricacy
– Size
 Raising the Level of Abstraction
 Compilers to handle the complexity because of
size

2
Agenda

 The System Design Challenge

 Software Design Flow
 Hardware Design Flow
 Summary

3
 The System Design Challenge
 We design, simulate, and MATLAB® and Simulink®
validate system models and Algorithm and System Design
algorithms in MATLAB®
and/or Simulink®

 How can we implement and

verify designs on DSPs and
GPPs?

 How can we implement and

verify designs on FPGAs and C HDL
ASICs?
MCU DSP FPGA ASIC

4
 Integrated Design Flow for
Embedded Software and Hardware
 Design, simulate, and validate MATLAB® and Simulink®
system models and algorithms in Algorithm and System Design
MATLAB and Simulink
Real-Time Workshop Simulink HDL Coder
 Automatically generate C and Embedded Coder, Link for ModelSim
HDL Targets, Links Link for Cadence Incisive

Generate

Generate
 Verify hardware and software
implementations against the

Verify

Verify
system and algorithm models

C HDL

MCU DSP FPGA ASIC

5
Agenda

 The System Design Challenge

 Software Design Flow
 Hardware Design Flow
 Summary

6
Integrated Design Flow for
Embedded Software
 Implementation with
automatic C code generation MATLAB® and Simulink®
Algorithm and System Design
 Implementation Real-Time Workshop Simulink HDL Coder
– Floating- and fixed-point code Embedded Coder,
Targets, Links
Link for ModelSim
Link for Cadence Incisive
– Integration with downstream
IDEs and tools

Generate

Generate
– Links to verification

Verify

Verify
– Device drivers
– Optimization options

C HDL

MCU DSP FPGA ASIC

7
Representative Application – Video
 Video system design and implementation Embedded Software
– Encapsulates challenges: complexity, Case Study:
convergence, time-to-market Video Edge Detection
on a DSP
– Sophisticated algorithms
– Floating- and fixed-point issues
– DSP or FPGA/ASIC implementations
 Design flows and steps shown directly
applicable to other signal processing
applications
Live
MATLAB
Demo
8
Example: Video Edge Detection
 Floating point video edge detection system based on
Prewitt algorithm
 Compositing original image with detected edges
 Utilizes blocks from Video and Image Processing Blockset

9
Converting to Fixed-Point
 Polymorphic blocks capable of floating- and fixed-point
operation
 8-bit input datatype – blocks inherit fixed-point data
 Simulink Accelerator provides fast fixed-point simulation

8-bit fixed-point input

10
Automatic Code Generation
for Implementation on GPPs and DSPs

Code generation
options
and preferences
Fixed-point model

Select target or flavor

of generated code

11
 Code Generation Report

HTML report

Links to code files

from HTML report Links to Simulink
model from
generated code
Readable,
commented code
12
Video Edge Detection
Embedded Software System on TI 6000TM
TCP/IP Blocks

13
Target Code Generation Options

High-Speed RTDX Inline Signal Processing

Blockset functions

Incorporate
DSP/BIOS

14
Code Execution on Target and Profiling
 Build and execute
– Auto-generate C and ASM

– Integrate RTOS and

scheduler
– Create full CCS project
– Invoke compiler, linker, and
download code
– Run on target

 Profile code performance

System profiling
includes entire DSP Subsystem profiling
application code
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 Code Optimization Options
 Utilize target-specific blocks
– C-callable assembler libraries
– Simulate bit-true in Simulink
– Generate calls to hand-optimized
assembler libraries
– Highly optimized implementation
of core functionality
– C62x and C64x fixed-point DSPs

 Manual optimization by user

16
Design Verification and Visualization:
MATLAB as software test bench

Visualize and debug embedded

software with MATLAB

Captured
Input video
video

MATLAB script
(test bench) 17
 Design Verification and Visualization:
Simulink as software test bench

Processor and hardware-in-the-

loop testing, simulation,
visualization, and verification of
embedded software with Simulink

Simulink test bench

Device or design
under test (DUT)

Simulink system design

embedded on DSP
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Review: Integrated Design Flow for
Embedded Software
 Drive system development
with an executable
specification
Real-Time Workshop
 Quickly create complete
working code base
MATLAB® and Simulink®
Algorithm and System Design
Simulink HDL Coder
Embedded Coder, Link for ModelSim
Targets, Links
Link for Cadence Incisive

Generate

Generate
 Use code profiles to identify
and optimize bottlenecks

Verify

Verify
 Verify code with Links to
IDEs and processors C HDL

MCU DSP FPGA ASIC

19
Agenda

 The System Design Challenge

 Software Design Flow
 Hardware Design Flow
 Summary

20
Integrated Design Flow for Hardware
(FPGA and ASIC)
 Design elaboration MATLAB® and Simulink®
Algorithm and System Design

 Implementation Real-Time Workshop Simulink HDL Coder

Embedded Coder, Link for ModelSim
– HDL code generation Targets, Links Link for Cadence Incisive
(VHDL and Verilog)

Generate

Generate
– test bench generation
– Links to verification

Verify

Verify
– Integration with
synthesis tools
C HDL

MCU DSP FPGA ASIC

21
What We Will Show In This Case Study
 Behavioral modeling and simulation Hardware Case Study:
 Fixed-point modeling and simulation Video Edge Detection
 Design elaboration on an FPGA
 HDL generation
 Co-simulation using Link for ModelSim

Live
MATLAB
Demo
22
Executable Specification

23
Design Elaboration

Automatically generate
Verilog or VHDL code from
elaborated models

24
HDL Code Generation Using GUI

Select subsystem, target

language, directory

Select output options

Check model for errors Generate HDL Code

25
More Code Generation Options

Select reset and

clock options

Set language-specific
options: input/output
datatypes, timescale
directives, …

26
Automatically Generate Test Bench

Self-checking HDL test bench compares

Simulink results to HDL results

27
 Co-simulate Generated HDL

Link for ModelSim

HDL code executing on

ModelSim simulator 28
Review:
Integrated Design Flow for Hardware
 Drive system development
with an executable MATLAB® and Simulink®
Algorithm and System Design
specification
Real-Time Workshop Simulink HDL Coder
Embedded Coder, Link for ModelSim
Targets, Links Link for Cadence Incisive
 Quickly create complete
working HDL code base

Generate

Generate
and test benches

Verify

Verify
 Verify code with Links to
RTL simulators and C HDL
synthesis tools
MCU DSP FPGA ASIC

29
Agenda

 The System Design Challenge

 Software Design Flow
 Hardware Design Flow
 Summary

30
Summary
 Accelerate development using MATLAB® and Simulink®
Model-Based Design Algorithm and System Design
– Generate
Real-Time Workshop Simulink HDL Coder
• Real-Time Workshop Embedded Coder, Link for ModelSim
Targets, Links Link for Cadence Incisive
• Simulink HDL Coder
– Verify

Generate

Generate
• Link for Cadence

Verify

Verify
Incisive

 Design and verify software C HDL

and hardware from MATLAB
and Simulink MCU DSP FPGA ASIC

31