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Business end of standards
VOLUME 3 NUMBER 5 Duncan Young

SEPT/OCT 2007 Small form factors
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it WWW.MIL-EMBEDDED.COM
FPGA vs. DSP? Pr

Together is ge
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betterorS
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Industry execs
weigh in:
Aitech, Intel, LynuxWorks,
Themis
©2007 OpenSystems Publishing. Not for distribution.

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Ethernet
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Military
FEATURES
Systems: DSP vs. FPGA – peaceful coexsistence
12 FPGA coprocessing architectures for military
applications
By J. Ryan Kenny and Bryce Mackin, Altera Corporation
EMBEDDED SYSTEMS
w w w. m i l - e m b e d d e d . c o m
16 FPGA/DSP hybrid architectures: Satisfying the
reconfigurability requirements of the military
September/October Volume 3 Number 5 By Ron Huizen, BittWare, Inc.
20 New design methodologies offer easier path

Columns to custom DSP hardware
By Shawn McCloud, Mentor Graphics
Industry Analysis
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7 The business end of standards 26 Implementation trade-offs of digital FIR filters
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By Jerry Gipper By Ed Rocha, Quickfilter Technologies
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8 Small form factor embedded subsystems Mil Tech Trends: Industry execs weigh in
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By Duncan Young
36 Focus on SWaP, energy management, and QoS
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Crosshairs Editorial
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An exclusive interview with Bill Kehret, founder
and CEO of Themis
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62 The “A’s” have it By Chris A. Ciufo, Editor
By Chris A. Ciufo, Editor
depaRTMENTS
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40 Guest editorial: Intel commits to embedded,
communications
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By Anthony Neal-Graves, Intel
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10 Daily Briefing: News Snippets 42 Linux meets the needs of security-critical, CM
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By Sharon Schnakenburg, Assistant Editor network-centric computing MY
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By Dr. Inder M. Singh, LynuxWorks
56 Editor’s Choice Products
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44 The costs of doing business in the new CMY
61 Advertiser Index RoHS world K
By Doug Patterson, Aitech Defense Systems, Inc.
E-LETTER www.mil-embedded.com/eletter Special feature: PowerPC still tops for defense

48 Advantages of Power Architecture technology
Hardware-based solution aids: Design for military applications
assurance for airborne systems By Katie Butler, Freescale Semicondutor
By Irene Sysenko, PhD, Aldec, Inc., and Ravi Pragasam, Actel Corporation
52 Product Guide: PowerPC products
MILS: Protecting our most vital systems
By Rance J. DeLong, LynuxWorks, Inc.
Multilevel security in tightly coupled military WEB RESOURCES

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Industry Analysis
The business end of standards
By Jerry Gipper
New computer technology specifications emerge every day that However, in many cases, the business side is weak or even non-
become potential candidates for standardization through the existent. All too often, no one is there to catch and run with the
efforts of existing standards organizations. The primary reason ball as a standard pops out. Even worse, most consortia do not
these specifications strive for standard status is to make devel- have a strong group that can gather and analyze market problems
opers and users confident that the specification will not change before the technical teams start their work. Sometimes an influ-
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without due process and that it will be widely used, thus driving ential individual or company provides some guidance, but as the
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down costs. If this is not a goal, then staying at specification individual moves on or the companies shift strategies, business
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status is just fine. leadership falters.
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Organizations such as the Institute of Electrical and Electronics
Engineers, Inc. (IEEE) and the American National Standards
I propose that a better job could be done to create standards if
more marketing was done at the beginning. A product lifecycle-
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Institute (ANSI) have rigorous processes in place to ensurelike process should be in place to force the steps needed to build
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that the approved specification has been through a thoroughand justify a business case. A much more rigorous data gathering
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vetting process. The resulting documents have been revised and
and analysis process should be in place. A business case should
improved upon through the work of many concerned parties. be developed, reviewed, and approved by the governing board
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Anyone who has been involved in the standards process knowsof a consortia or standards body before any standards work is
the immense amount of time and energy required to make it to
expended. The typical process used by many groups requires that
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the approved stage. three or more companies sponsor a
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proposal for a working group to be
What appears to be missing is adequate established. This process is very
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justification to expend all the neces- inadequate. The sponsors need to
… In many cases, the
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sary effort to convert a specification be called to the mat to demonstrate
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to a standard. My observation is that a business case. Processes similar
business side is weak or
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launching a standards development to what an investor or venture
effort appears too easy. The business capitalist follows before making an
side needs more representation to jus- even nonexistent. All too investment demonstrate the type of
tify the tremendous amount of effort it rigor that should be followed for a
takes to develop a ratified standard. often, no one is there to major endeavor.
From the IEEE Standards Associa- catch and run with the ball The effort in launching most stan-
tion (IEEE-SA) operations manual, dards should be as consistent as
“Approval of a standard by the IEEE- as a standard pops out. the effort to launch a major new
SA signifies that the IEEE believes the product line. The market problems
document to be consistent with good being addressed by the specifica-
engineering practice and that it rep- tion should be researched and
resents a consensus of representatives from materially affected understood. The market potential and adoption plan should be
industries, governments, or public interests.” This is consistent presented. A plan for evangelizing and marketing the standard
with most other standards bodies’ operations procedures, but it should also be included, and a budget and sources for the budget
only addresses the results of the technical standards develop- should be considered.
ment effort. It does not address the potential business and market
impact of the standard. No basic requirements are established for The industry and consumers would then benefit from better
meeting good business goals. choices, and developers would be able to focus on efforts that
stand a much greater chance of sticking and reaching levels of
Many consortia and standards bodies have both a technical and success. The success level of any individual standard should
business structure. There is usually a team of engineers working increase and the confusion factor with conflicting standards
on technical challenges and issues; meanwhile, the marketing should decrease if the homework is done before launching a
and public relations types sit in a separate room, trying to under- significant standards effort.
stand what the technical side is working on or how to position
and message the technical side’s output. Usually the technical I would love to hear your opinion on this topic.
side is a strong team that is excellent at coming up with solu-
tions, creating a draft specification, and pushing it through the For more information, contact Jerry at jgipper@opensystems-
standards process. publishing.com.
Military EMBEDDED SYSTEMS September/October 2007 / 7

Field Intelligence
Small form factor

embedded subsystems
By Duncan Young
The drive toward battlefield digitization configured from them will be quite bulky will be no conditioned air or pumped
plus the effects of ongoing conflicts for some of the new rapid upgrade pro- liquids available. Baseplate or natural
around the world are driving the military grams. For example, it is much harder to convection are the most feasible methods
to upgrade existing vehicle fleets as a pack even a small number of these bulky of cooling, thus steering shoebox designs
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higher priority than introducing wholly boxes into light helicopters, Unmanned to be fully enclosed and use only the
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new fleets, as envisaged by the Future Aerial Vehicles (UAVs), and wheeled outside surfaces of the box for cooling
Combat Systems (FCS) program. This vehicles than it would be if using larger and connector space. The selection of the
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is ramping up demand for quick-turn numbers of much smaller box sizes. form factor and box size most suited to an
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applications using new communications With electronics miniaturization taking application can be complex, but there are
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bandwidth. These new applications are such strides, the larger board sizes may two simple relationships that help:
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often not critical to a fleet’s war-fighting also contain too much functionality and
capability but are targeted toward greater performance for convenient modulariza- performance = watts = size
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information exchange, data presentation, tion for these types of relatively simple ruggedness = weight
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training, and general purpose tools for the add-on capabilities.
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crew. Many of these new capabilities are For example, an embedded PC based on
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being added on top of existing systems, Embeddable PCs are widely used in the PC/104-Plus form factor will offer
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rather than being fully integrated, creating industrial control systems, displac- relatively low-end performance, limited
a new phenomenon: the shoebox-sized, ing many earlier VMEbus systems. by its small size and hence its ability to
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rugged embedded PC, which is easy They can be custom built for very dissipate a lot of heat. PC/104-Plus is not
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and familiar to use and small enough to specialized systems or, more frequently, inherently rugged but can be made so by
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be mounted almost anywhere that panel configured from one of the many adding weight in the form of supporting
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space is available. industry-standard form factors. Table 1 structures and enclosures. Where top-end
lists the characteristics of some of the performance is required, larger size and/
Systems for new platforms will continue most commonly used varieties, all of or more efficient cooling such as conduc-
to be implemented using well-developed which either have been or could be used tion will be required. Conduction cooling
open architecture embedded comput- as the basis of a rugged embeddable PC. also provides much additional stiffening
ing standards such as VMEbus, VPX, to a module, making it the ideal choice
and CompactPCI. These will allow the There is room in the market for many for prolonged operational use in the
configuration of very powerful, fully different solution sets based around the harshest military environments.
network-enabled, integrated systems that concept of a self-contained, fully func-
will be maintainable and upgradeable in tional PC running Windows or Linux. GE Fanuc Embedded Systems’ MAGIC-1
the field over the life of each vehicle fleet. As these are add-on units, the vehicle to is an example of a fully ruggedized, pre-
However, as these standards are generally which they will be fitted is unlikely to configured embeddable PC. Based on the
6U in size (233.4 x 160 mm), a subsystem have any provision for cooling. So there conduction-cooled 3U VPX (VITA 46)
Form factor Real estate Conduction Network support PCI Express and
Board type PCI
mm cm2 cooling (Ethernet) fabric support
PC/104-Plus 96 x 90 86 x   x
EPIC 115 x 165 190 x   x
EBX 203 x 146 297 x   x
3U VPX 160 x 100 160  x  
MicroTCA single 74 x 182 134 proposed x  
MicroTCA double 149 x 182 270 proposed x  
ETX Express 95 x 125 119 x x  
Table 1

PCI/104-Express
with CoreTM2 Duo
PCI Express
Applications with
two displays
video streaming
HD-videos
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MICROSPACE® MSM945
incl. SMX945
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form factor, MAGIC-1 (Figure 1) is As lessons learned from ongo-
_ PCI/104-Express baseboard
optimized for graphical applications. It ing conflicts percolate down into
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uses a 2 GHz Intel Core Duo processor urgent operational requirements, the _ Intel® CoreTM Duo LV L2400 /
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Intel® Celeron® M ULV423
with a 16-lane PCI Express interface to military COTS market is developing
an NVIDIA G73 graphics processing unit new directions and creating new standards _ 1.0GHZ to 2x 1.6GHz
to achieve its high-performance goals. with innovative technology solutions. _ i945GM-PCI Express chipset
Flagship applications for the more mature _ CRT, SDVO, 224MB VRAM
Embedded training systems located in 6U form factors still abound, particularly
_ KB/MS, FD, 1x P-ATA, 2x S-ATA
active fighting vehicles are an excellent in new build platforms where the real 2x COM RS232, LPT1, 8x USB 2.0,
example of an application area that such benefits of fully integrated applications 1x LAN 10/100 BASE-T,
an embeddable PC with high-resolution, and reduced levels of maintenance can AC97-7.1 HDA
truly realistic graphics performance is be achieved. However, existing platforms _ DDR2-RAM 256 – 2048MB
targeted toward. Training exercises – – many of which were introduced into _ IDE
particularly in multisensor, cooperative active service prior to the COTS era –
_ Watchdog
environments – are designed to develop are, of necessity, rapidly evolving in an
more intuitive and interpretive skills incremental manner to counter new and _ Power 5W / typ 10-20W
than the traditional action-reaction type more demanding threats. To satisfy this _ Smart cooling concept
of training. This does not require an demand, cycle times for new subsystems _ -25°C to +60°C
exact real-time mimic of actual equip- from design to deployment must be (Option -40°C to +70°C)
ment operation, hence hard-deadline, reduced dramatically. And it is in these
real-time performance parameters are applications that the new breed of small,
DIGITAL-LOGIC AG offers reliable
less critical. But because the training is rugged, preconfigured PCs will be so Embedded Computers in PC/104,
performed in the deployed environment, successful. 3.5”, EPIC, EBX, smartModule,
embedded training systems must be fully COM Express and other formats.
ruggedized. Another typical application To learn more, e-mail Duncan at
Further information at:
for this kind of preconfigured subsystem young.duncan1@btinternet.com.
could be to drive a large-screen display
www.digitallogic.com
for planning or briefing troops inside
expeditionary armored vehicles.

Daily Briefing: News Snippets
By Sharon Schnakenburg,
Schnakenburg Assistant Editor www.mil-embedded.com/dailybriefing
A (life)time to achieve Headache-eliminating

It’s that time of year, and Frost & Sullivan is at it again.
This time, the organization, which hands out beaucoup
partnership
Engineering departments can
awards annually, has announced that Quantum3D, Inc.’s
now eliminate the hassle of
cofounder and president Ross Q. Smith is one of its 2007
sending their test and mea-
Lifetime Achievement Award winners. Frost & Sullivan’s
surement instruments back to
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director of production events Caryn Brown says Smith
several different manufacturers
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was nominated for several reasons: His role as a “pioneer”
for calibration: Sypris Test &
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in PC-based real-time visual computing, his service as a
Measurement and Tektronix
“driving force” in the movement to turn the embedded
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recently formed a one-stop-shop
visual computing and visual simulation/training markets
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partnership where customers
into COTS/open architectures, and his “strategic vision”
can receive onsite, single-source calibration services for
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of watershed real-time visual computing products. Smith –
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about 80,000 different instruments (nearly 90 percent of
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along with honorees from other industries including
those typically used, according to Sypris), no matter who
healthcare, automotive and transportation, and financial
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the manufacturer is. The major motivations behind the union
services, among others – is honored at the 3rd Annual
reportedly include cutting customers’ costs, increasing cus-
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Growth Innovation and Leadership 2007: A Frost &
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tomer convenience, and eliminating the inconsistency that
Sullivan Executive Congress on Corporate Growth in
can arise when dealing with many different vendors.
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Monterey, Sept. 16-18.
FPGAs: Up in space
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The U.S. Army has a new addi-
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How well do FPGAs tion (or is that a new edition?):
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and “mission-critical” Boeing’s new CH-47F Chinook
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really blend together helicopter was recently pro-
in space? Very well, nounced combat ready by Army
according to repre- officials and has joined the
sentatives of the Actel ranks for service to its country.
Boeing photo taken by Fred Troilo
Corporation, whose The helicopter – assigned to the

RTAX1000S-CQ352 7th Battalion, 101st Aviation
FPGA device flew Regiment (Air Assault), based
out of the stratosphere at Ft. Campbell, Ky. – derives
at NASA’s Phoenix its power from two 4,868-
Mars mission launch horsepower Honeywell engines and travels at speeds in
at Cape Canaveral Aug. 4. Actel’s RTAX-S FPGA is part of excess of 175 mph. The CH-47F comprises a BAE Digital
the spacecraft’s Meteorological Station (MET) instrument, Advanced Flight Control System (DAFCS), a Rockwell
designed to gather, process, and send pressure and tempera- Collins Common Avionics Architecture System (CAAS),
ture data back to Earth-stationed researchers. Actel’s high- and a “modernized” airframe. It also includes the Robertson
reliability, high-density RTAX-S family includes 250,000 Aviation Extended Range Fuel System – which provides
to 4 million equivalent system gates, along with usable a 400+ nautical mile mission radius – and “improved
error-corrected onboard memory, Single-Event Upset (SEU) survivability features” such as Improved Countermeasure
hardened flip-flops, and large amounts of user-defined I/O. Dispenser Systems and Common Missile Warning.
Semiconductor sales: Moving up in the world

In the common vernacular, “It’s all good.” Well, at least most of the recent semiconductor sales news is, according to a report by
the Semiconductor Industry Association (SIA). Tallies indicate that worldwide semiconductor sales reached $20.3 billion in May
2007, representing a 2.4 percent growth hike from $19.8 billion in May 2006. NAND flash and microprocessors experienced the
largest sales volume gains, likely contributing to the nearly 10 percent increase in PC and cell phone market unit sales; meanwhile,
DRAM experienced strong price pressures, resulting in total DRAM sales revenue losses of 8 percent even though unit shipments
were 7 percent higher. While admitting to a “sequential decline” this past April, SIA president George Scalise remains optimistic
about this year’s semiconductor sales overall, citing a 3.1 percent increase in the first five months of 2007 as compared to the same
time frame in 2006.

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FPGA coprocessing architectures

for military applications
By J. Ryan Kenny and Bryce Mackin
Military electronic equipment
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manufacturers at one time were military market for high-performance ules can be added to processor memory
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categorized into two fairly distinct processing is expanding rapidly, though subsystems to offload specific hardware
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design types: hardware based and there are currently few application- pipeline functions. The advantages of
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software based. Each offered significant specific (tailored application) coprocess- these approaches have been explored by
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advantages and disadvantages in speed ing FPGA solutions available. Altera Corporation and applied in some
and flexibility. Newer, more flexible cases by FPGA users. Many significant
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war-fighter support systems today With the proliferation of distributed and advantages to sensor signal processing
take advantage of both hardware and multicore processing computers, com- problems can be examined with three
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software using hardware acceleration plex signal processing applications can sample layouts: two example architecture
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with FPGAs. be accelerated with distributed functions. sets for multicore processing and one
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The processing cores, however, are still architecture for single-core processing.
Hardware acceleration with FPGAs is limited by cache size and coherency,
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important in military sensor applications memory bandwidth, and in some cases, Potential algorithmic returns
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for three reasons. First is to reduce system power and cooling. Hardware acceleration using an FPGA
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latency so that defensive systems can react as a coprocessor is intended to offer 10x
faster to enemy threats, such as jamming One approach to improving processing to 100x speed improvement for tailored
or blinding. Second, as military threats power and efficiency in single-core and algorithms, and anywhere from 3x to
have become more elusive and blend in multicore processors is to use FPGAs as 50x speed improvement for the user
with urban settings, systems are constantly application-specific coprocessors. These application. These target numbers are
under pressure to increase sensor resolu- devices can be designed to fit into Intel based on commercial applications such
tion. And lastly, as military threats become Xeon and Advanced Micro Devices as financial analysis, data warehousing,
more tactical, the Size, Weight, and Power (AMD) Opteron sockets to replace one and biosciences.
(SWaP) of a system must be reduced. of the processors with pipelined FPGA
Application Processor Only FPGA Coprocessing Speed Up
(1) Hough and inverse Hough processing 12 minutes processing time Pentium 4-3 GHz 2 seconds of processing time @ 20 MHz 370x faster
(2) Spatial Statistics (Two Point Angular Correlation 3,397 CPU Hours with 2.8 GHz Pentium
36 hours (exact solution) 96x faster
Cosmology) (Approximate Solution)
(2) Black-Scholes (Financial Application (single

2.3M experiments/sec with a 2.8 GHz processor 299M experiments/sec 130x faster
precision floating point 2M points))
(1) Smith Waterman ssearch34 from FASTA 6,461 sec processing time (Opteron) 100 sec FPGA processing 64x faster
(3) Prewitt Edge Detection (compute-intensive 327M Clks

131K Clks @ .33 MHz 83x faster
video and image processing) (1 GHz processing power)
(1) Monte Carlo Radiative Heat Transfer 60 ns processing time (3 GHz processor) 6.12 ns of processing time 10x faster
(1) BJM Financial Analysis (5M paths) 6,300 sec processing time (Pentium 4-1.5 GHz) 242 sec of processing @ 61MHz FPGA 26x faster
Table 1

Several selected algorithms taken from 14.4 GBps
useful for delivering sensor data directly
these commercial applications have been sustained payload to the user logic chips.
implemented and tested on FPGA copro- (7.2 GBps per pair)
cessors for evaluation. These are shown MAP The division of the user’s program
in Table 1. SDRAM SDRAM between the microprocessor and program-
1 GB 4.2 Controller 4.2 1 GB
GBps GBps
mable logic is accomplished using the
In addition to the performance advantages 14.4 GBps Carte high-level language programming
of hardware acceleration, replacement of environment. This allows programmers to
either an Intel or AMD processor signifi- User Logic 1 4.8 GBps User Logic 2 use ANSI C and FORTRAN to generate a
55 Mgates 55 Mgates
cantly reduces power consumption and single executable program that will con-
19.2 GBps (2.4 x8)
heating in a system. This is a result of the trol both FPGAs and the microprocessor.
streamlining of software and hardware Eight Banks Onboard Memory
This allows the division of logic between
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functions where they are best suited. Ini- (64 MB SRAM) hardware and software to be performed by
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tial benchmarks on the expected power a single architect.
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savings are algorithm dependent. 12 GBps
Performance gains of this coprocessing
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Figure 1
Single-core coprocessing approach have been demonstrated to
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architecture several government customers, resulting
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The majority of military systems utilize between sensor and microprocessor with in orders of magnitude improvement over
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single-core CPU architectures. Migrat- minimal latency. This is performed with a stand-alone 2.8 GHz Xeon processor.
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ing to higher-performance processing user logic chips diagrammed (Figure 1) in These applications include military imag-
systems, while still meeting government generic blocks. The controller is an FPGA ing, radar signal processing, and image
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software code reuse objectives, is a that performs several functions including target recognition. Benchmark results for
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problem that can be solved by offloading virtual to physical address conversion and the complete application including data
software functions into FPGA hardware. DMA packet generation. The SDRAMs movement time are shown in Figure 2.
n
i
shown are part of a 64-bit global shared
S
Some signal processing problems are address space that includes the micro- Some military applications may be more
fairly simple, involving a single sensor processor memory. The direct execution advanced, utilizing multiple sensors,
r
with a single data processor. In order to logic that implements the user’s program sensors in multiple modes, or rapid sys-
o
optimize the data flow and computational resides in the two user logic FPGAs. tem reconfiguration. For these systems
F
bandwidth in this system, the coprocess- These can perform up to sixteen 64-bit where the user is willing to pursue a
ing problem is very straightforward. Large references per clock cycle to the 8 SRAM more difficult segmentation of logic in
functions that can be mathematically banks. In addition to the connection to the pursuit of higher performance, multicore
isolated and pipelined are performed out- DIMM bus, data may also be received or processing is one of the latest trends in
side a processor using a systems analysis sent using the GPIO port. This port is very high-performance computing.
process.
One such process utilizes a hardware 357

350
and software architecture called
Performance Speedup: MAP vs 2.8 GHZ Xeon mP
IMPLICIT+EXPLICIT. It can be used 304

300
with single or multiple microprocessor 280
boards. This architecture combines an 250 240
FPGA-based reconfigurable proces-
206
sor, MAP, in a peer relationship with a 200
microprocessor. This peer relationship is
150
achieved by connecting programmable 150
logic to the microprocessor using the
microprocessor’s memory DIMM slots. 100 75
FPGAs are used to implement pipelined 50
direct execution logic to perform func- 50
tions such as DSP logic. This can acceler-
ate sensor processing, allowing for less 0
Cosmology
Backprojection
SPAM
3DES
Visual/IR
Image Processing
3DES/Med.
Filter and Edge
Det./3DES
Radar
Signal
Processing
Target
Recognition
power consumption and greater sensor

resolution.
Another processing challenge in sensor Figure 2

systems is moderating the information

Multicore coprocessing
architecture
Multicore processing is utilizing multi-
ple CPUs to execute code in parallel on
the same algorithm, but separate process
threads. Multicore processing require-
ments are being significantly pushed
by military applications in imaging and
data processing where performance gains
in single-core processors are becom-
ing marginal. Providers of both Intel and
AMD based architectures are being asked
y
for their solutions.
Accordingly, the goal of multicore
nl Figure 3
O
coprocessing is the same as single core:
t
to identify and isolate math functions that
can be efficiently offloaded from software
n
i
into hardware in order to accelerate sen-
r
sor system performance. A set of notional
P
coprocessing architectures for the Intel
Xeon Quad Core (Figure 3) and AMD
e
l
Opteron (Figure 4) layouts are shown.
g
Figure 5 shows a representative system
n
developed by XtremeData that utilizes
i
an FPGA on an XDI module. In all three
S
layouts, FPGAs are placed in CPU sock-
r
ets and require application hardware to
best utilize the FPGA logic.
Fo
In the Xeon architecture, a processor and
a coprocessor are connected using the
Intel Front Side Bus (FSB) architecture.
A Northbridge (information available
from Intel) is used to connect each FSB
to one another. These are the normal
pathways used by multicore CPU instruc-
tions. Access to front side bus interface
standards is becoming more widely
available to developers.
Figure 4
The AMD Opteron architecture uses direct
HyperTransport interconnects between power available in the FPGA. This copro- Implementation
each processor/coprocessor socket. This cessor solution offloads high-resolution In addition to the FPGA design and
32-bit packetized data connection is DSP algorithms in military imaging drop-in module, an application engineer
similar to 2.5 V LVDS and can easily be systems and performs Black-Scholes has the task of modifying the application
integrated using available HyperTransport simulations for financial modeling. software to exercise the FPGA coproces-
FPGA cores. sor for tailored hardware operations.
The motherboard plugs into a standard There are several approaches to this
The Xtreme Data architecture is an imple- commercial enterprise rack or blade process, which can be logically broken
mentation currently in use in the several server. It utilizes a low-latency, high- out into two steps.
nonmilitary markets. It utilizes a multi- bandwidth HyperTransport interface to
processor motherboard with an AMD and the other processor. The FPGA uses all First, a systems engineer needs to deter-
Intel socket-compatible module interface resources intended for a CPU – power mine which functions in the system will be
for the FPGA and other components. This supply, heat sinks, HyperTransport links – offloaded into the FPGA for accelerated
multisocket architecture allows the appli- and is programmed with on-chip memory processing. This can be accomplished by
cation to take advantage of the processing controllers. using traditional software profiling tools.

72485_v3 US Milit Emb Systems.aiPage 1 9
Figure 5
y
Second, the application engineer must Engineers will then have a new challenge:
l
identify the function calls and interfaces balancing tailored performance versus
n
for coprocessing, as well as the task distri- code reuse.
O
bution among the remaining processors.
t
In the case of the Carte Programming J. Ryan Kenny is technical
Environment, users have equated this marketing manager in
n
i
effort as comparable to the effort required Altera’s military and aero-
r
to convert a uniprocessor application into space business unit. He is
P
an MPI application. responsible for creating
FPGA-based technical
e
l
As multicore processing becomes more solutions for the military data and signal
g
prevalent, software tools will become processing market. He joined Altera in
n
available to help designers parallelize March 2007 and has more than 10 years
i
and compile their systems for N hardware of experience in space and defense elec-
S
nodes from other vendors. Function calls tronics in the U.S. Air Force and at
r
can be translated from C to efficient HDL Lockheed Martin. He graduated from the
using proprietary tools offered by FPGA
o
U.S. Air Force Academy and completed
providers. This application tailoring an MSEE and MBA from California State
F
requires only basic FPGA knowledge, University Northridge and Santa Clara
allowing the system designer to build University respectively. He can be
algorithm architectures confidently with- contacted at rkenny@altera.com.
out a full FPGA development staff.
Bryce Mackin is the strate-
Simplifying coprocessing gic marketing manager in
Using design software developed by Altera’s computer and stor-
FPGA providers and hardware partners, age business unit.
hardware acceleration is evolving from a His focus is on FPGA
specialized engineering effort into a pow- coprocessors for the high-
erful systems design tool. It is accessible performance computing market. Bryce
to software designers today, and will only has been in the computer and storage
become more accessible in the future. market for more than 10 years. Prior to
joining Altera, he served as a strategic
The next generation of embedded compu- marketing manager for Xilinx, worked at
tation for military applications is likely Adaptec in several product marketing
to involve strong design partnerships be- roles, and held the position of marketing
tween providers of software and pipe- chairman for the Storage Networking
lined hardware. More of these will be Industry Association (SNIA) IP Storage
seen in the future as holistic development Forum. Bryce has a degree in Industrial
tools allowing simple partitioning of Engineering from California State Uni-
applications into the processor domain versity in San Jose. He can be contacted
that better suits their execution. at bmackin@altera.com.
As computing architectures become opti- Altera Corporation

mized for military applications, code port- 408-544-7000
ability and supportability may suffer. www.altera.com

FPGA/DSP hybrid architectures:

Satisfying the reconfigurability
requirements of the military
By Ron Huizen
ny
l
Many signal processing applications
in the military require reconfigurability
ensuring that the system will support
future, more advanced requirements. On
O
coupled with the speed and dynamic the other hand, applications that require
t
range of a floating-point DSP. The enough flexibility to be easily updated
n
solution is a hybrid architecture that and modified usually rely on FPGAs,
i
employs an onboard FPGA framework which, in recent years, have also gained
r
to create a seamless transition between the ability to provide embedded signal
P
I/O, FPGAs, and DSPs. processing. When an application requires
e
both the flexibility of an FPGA and the
l
Embedded signal processing applications advanced signal processing capabilities of
g
in the evolving modern-day military a floating-point DSP, the problem arises of
n
increasingly require flexibility, adaptabil- which technology to use.
i
ity, and reprogrammability. The ability
S
to modify a military system in real time FPGAs are extremely effective for well-
r
based on what is happening in the real defined, straightforward, high-speed,
o
world – adapting to weather conditions, repetitive problems requiring data flexibil-
F
new threats, mission changes – is crucial. ity and parallelism, the type of processing
When this is coupled with the require- that is very often needed at the front end
ments of floating-point signal processing of the signal processing system. They can
– low latency, high throughput, extended provide reconfigurable interfacing, with
precision, and dynamic range – the ability many of the newly released FPGAs able
to properly satisfy all requirements using to implement switch fabrics such as Serial
one processing technology diminishes. RapidIO and PCI Express, making them
ideal for on- and off-board data transfer.
Many times, a design that includes both They have been touted as do-everything
FPGAs and DSPs – a hybrid architecture silicon, able to perform high-end pro-
– provides the best solution. The challenge cessing and provide the dynamic range
then becomes one of integrating two quite required by many military signal process-
different technologies efficiently and effec- ing applications.
tively so that the end system functions as
one entity. A software control framework In practice, though, difficulty in program-
that can successfully merge the two tech- ming these devices for floating point can
nologies, allowing the system to play on greatly increase time-to-market, making
the strengths of each, is a necessity. them unlikely candidates for high-end
signal processing at any point in the
Leveraging strengths, mitigating near future. Another drawback of these
weaknesses devices is power inefficiency, a common
Embedded signal processing applications trade-off with flexibility. A similar func-
that require sustained, low latency, high- tion implemented in an FPGA might take
throughput data processing traditionally two to three times as much power versus
rely on DSPs. When additional dynamic a DSP. Note, however, this inefficiency
range is needed, a floating-point DSP may be an acceptable trade-off for the
has been the processor of choice, also sake of flexibility.

Floating-point DSPs, on the other hand, high throughput, and data control, all
are much better at implementing a broad within a reasonable power budget. This
range of highly complex algorithms that type of system also has a higher amount
require floating-point math and have the of inherent flexibility, providing repro-
tendency to change frequently. Any appli- grammability for bug fixes and giving
cation that requires some sort of decision system designers the ability to support
making or adaptive processing, where the a different application in a very short
next processing step is dependent upon amount of time.
the current result, requires a floating-point
DSP. They are better in terms of power The FPGA framework solution
consumption and have the benefit of pro- While the benefits of hybrid design are
gramming in C, decreasing development many, along with these benefits come
y
time. What they cannot do efficiently is some significant design issues. A suc-
l
handle the repetitive, straightforward cessful hybrid design needs to be able
n
processing that is many times required to properly allocate data bandwidth
O
on the front end of the signal process- (including memory and I/O) among the
t
ing application; they can actually waste FPGA(s) and DSP(s), easily connect the
large amounts of processing efforts on onboard data options while retaining the
n
i
these types of tasks, translating to a less ability to modify them, and last but not
r
efficient and more costly system. It’s not least, successfully integrate the FPGA
P
uncommon for an FPGA implementation processing with the DSP so that each
of a straightforward, parallel, repetitive compute element is handling the part
e
l
task to require two to five times as many of the problem it is most proficient at.
g
DSPs to complete the same task. A software framework that can handle
n
each of these is essential. The framework
i
Given the strengths and weaknesses then functions as two separate entities:
S
of each, it makes sense to use them as an I/O interfacing and routing device
r
complementary technologies, mitigating and a configurable FPGA pre-, post-,
the risks and weaknesses of each tech- or co-processing engine. One example
o
nology when used on its own. A hybrid implementation is BittWare’s integrated
F
architecture can intelligently combine system framework ATLANTiS, shown in
the two, providing efficient performance, Figure 1.
ATLANTiS FPGA
User User
I/0 Interface(s) Processing User Interface
Processing
ATLANTiS Interconnect Fabric

Memory
Inter-Processor Standard Multiport

Comms (IPC) Processing Memory Arbiter
Additional
FPGA(s)
-or-
Programmable
DSP(s)
Figure 1

Data interfacing and routing be instantly modified for an immediate at 128 bits per I/O. The bandwidth can be
Given that FPGAs are better at the need, while also retaining the ability to allocated to any or all data inputs by 32
repetitive, well-defined, straightforward be updated for future modification and configuration registers that evenly divide
processing – as well as being known for expansion. This is achieved via the main the bandwidth slots into 62.5 MBps and
their flexibility – it makes sense that the framework switch, shown in Figure 2, can be changed “on the fly.”
board’s onboard entry and exit points which controls all connectivity and band-
reside on the FPGA, and that the entire width allocation. Configurable FPGA processing engine
software framework handling this data Should the signal processing application
also resides on the FPGA. This FPGA The switch is configured via registers by in question require the FPGA to provide
framework can then handle all data the host or any of the onboard DSPs and some of the signal processing, the FPGA
transfer on and off the board and between comprises two smaller switches, each framework also needs to enable the user
itself and the DSP(s), acting as a software with eight inputs and eight outputs. The to add FPGA processing blocks into the
y
programmable cable and enabling the switch connectivity is defined by the data flow at any time while the applica-
l
dynamic connection of every tion is running. This can also
n
I/O to any other I/O, where The ability to easily connect (and disconnect) be achieved through register-
O
connections can be created controlled data routing
the external data sources to each other, to between all modules within
t
and broken without the need to
recompile or change cables. The IP processing modules within the FPGA, and the FPGA, enabling the inser-
n
i
options for data interfacing can to the onboard DSPs creates an incredibly tion of FPGA processing mod-
r
include: digital I/O (LVDS or ules at any point. As discussed
single ended), general purpose flexible system that can be instantly modified in the previous section, the
P
I/O, flags, interrupts, link ports,
e
for an immediate need… framework’s memory space
l
high-speed serial links, rear is accessible by the onboard
g
panel connectors, off-board connectors, specific FPGA load and is controlled by DSPs or the host via either a peripheral
n
board-to-board links, cluster-to-cluster the configuration registers, which allow bus or a cluster bus and is accessible to
i
links, and multiport memories. source and destination time slices. This the designer via a GUI that provides a
S
is all controlled by the system designer graphical representation of all possible
r
The ability to easily connect (and discon- via a Windows navigator, command source and destination I/Os. This enables
nect) the external data sources to each scripts, or C functions. Each switch DSP or host control and status, and R/W
o
other, to IP processing modules within accommodates single point, multipoint, access to all of the frameworks resources;
F
the FPGA, and to the onboard DSPs cre- or broadcast switching amongst any of its the most important resource is the main
ates an incredibly flexible system that can eight inputs at up to 125 MHz clock rate framework switch. Access to the memory
Output Output Output Output Output Output Output Output

0 1 2 3 4 5 6 7
128 128 128 128 128 128 128 128
Configuration
8X8
Registers
Switch
Control Bus
128 128 128 128 128 128 128 128
Input Input Input Input Input Input Input Input

0 1 2 3 4 5 6 7
Figure 2

ny
l
tO
rn
i Figure 3
e P
space enables instant I/O routing changes example of this architecture. The board
l
and the ability to insert standard and/or combines the Altera Stratix II GX FPGA
g
custom FPGA processing blocks into the with Analog Devices TigerSHARC
n
queue at any point during data transfer. TS201 DSPs, creating an intelligent and
i
flexible system with an easy path for
S
When the user configures the framework future enhancements and upgrades.
r
for a specific load, the master switch is
o
programmed, defining source and des- Ron Huizen is
F
tinations for each I/O from all available VP of technology at
connections; the 32 configuration registers BittWare, where he
are memory mapped by a DSP or the host. focuses on technology
Should a different load be required, the direction and new prod-
framework is reset and then configured uct concept definition.
with the next load. FPGA IP blocks can be In a previous role at
added into the switch to provide additional BittWare, Ron oversaw all aspects of
processing at any point during the data product development. Before joining
flow. The result is the efficient integration BittWare, he held various roles in
of two different technologies. With the electronic product development at
FPGA framework handling all data rout- Amirix Systems. During his tenure at
ing, as well as providing any pre- or post- Amirix, Ron started Cabotel Systems, a
processing, the onboard DSPs are freed to spin-off company focused on developing
handle the highly complex signal process- semi-custom electronic products. Prior
ing for which they have been designed. to Amirix, he worked at Nortel Networks
for several years on SS7 switching sys-
A flexible, high-end signal tems. He holds a Bachelors of Computer
processing system Science from Acadia University and
Many of today’s military signal process- a Masters of Computer Science from
ing applications require the flexibility Carleton University. He can be con-
and reprogrammability of an FPGA com- tacted at rhuizen@bittware.com.
bined with the ease-of-use and floating-
point processing provided by DSPs. The BittWare, Inc.
solution is a hybrid architecture that effi- 603-226-0404
ciently and effectively combines both by www.bittware.com
way of an FPGA framework. BittWare’s
GT-3U-cPCI, shown in Figure 3, is one

New design methodologies

offer easier path to custom DSP hardware
By Shawn McCloud
ny
l subsystems designed into modern mil/
O
aero applications. In recent years, sys-
t
tem designers have increasingly looked
n
i
beyond programmable DSPs toward
r
dedicated hardware solutions, such as
P
FPGAs and ASICs that deliver increased
levels of performance.
ge
l However, manually implementing DSP
algorithms in hardware can be an expen-
n
i
sive, time-consuming process. Hand-
S
coding hardware descriptions in RTL can
take a design team weeks or months, with
r
verification and optimization doubling
o
or even tripling the total time required to
F
implement complex DSP algorithms (see
For years, system designers have The processing performance required for sidebar). This effort and expense meant
weighed the trade-offs between the next-generation compute-intensive appli- that ASICs and FPGAs were only used
programming flexibility of discrete cations, including wireless communica- in demanding niche applications. Now, a
DSPs against the performance, area, tion and image processing, has created new class of algorithmic synthesis design
and power benefits of custom hardware. a gap between off-the-shelf DSP per- tools makes it faster and easier to imple-
The effort involved in creating DSP formance and market needs. More and ment DSP algorithms in hardware and put
hardware was a major deterrent for more, discrete DSP devices fall short of within easy reach hardware implementa-
all but the most performance-hungry performance requirements for leading- tions that are optimized for performance,
applications. However, a new design edge communications and multimedia area, or power consumption.
methodology called algorithmic
synthesis makes it easier to create high-
performance dedicated DSP hardware.
With this methodology, designers can
automatically create Register Transfer RTL: DSP algorithms the hard way
Level (RTL) implementations in seconds,
compare multiple microarchitectural Using traditional Register Transfer Level (RTL) methodologies to create hard-
options, and quickly achieve designs ware implementations for complex DSP algorithms, design teams had to iterate
through several steps, including microarchitecture definition, hand-coding
that are optimized for the performance,
the RTL, and area/speed/power optimization through iterative RTL synthesis.
area, and power consumption needs This manual process was, and still is, slow and error-prone, introducing up to
of systems as diverse as a land-based 60 percent of the bugs found in RTL through design misinterpretation from
surveillance system, an airborne original specification. In the final result, both the microarchitecture and tech-
reconnaissance system, and a personal nology characteristics become hard-coded into the RTL description. This effect
night-vision system. With these severely limits the notion of RTL reuse or retargeting for real applications and
capabilities, designers find themselves leads to inefficient, overbuilt designs and wasted silicon.
seriously rethinking their overall design
flow for implementing DSP algorithms.

Algorithmic synthesis moves hardware synthesis to the traditional DSP software At this point in the traditional flow,
design decisions to a higher level of programming flow. In both flows, algo- software developers use a compiler to
abstraction. As a point of reference, one rithm designers develop a floating-point automatically compile the C code for an
could compare the automated C-to-RTL model of an algorithm, then convert that off-the-shelf DSP. With algorithmic syn-
design flow (Figure 1) used in algorithmic to a fixed-point model, typically in C++. thesis, a hardware designer uses an algo-
rithmic synthesis tool to automatically
create an RTL description of DSP hard-
ware that is tuned for a specific ASIC or
FPGA technology platform, dramatically
shortening the design hardware design
flow. In fact, the technology-independent
ANSI C++ description enables the algo-
y
rithmic synthesis tool to target either
l
ASIC or FPGA implementations.
On Algorithmic synthesis enables designers

to tune the design to exactly match the
t
performance required for a specific appli-
n
i
cation, including latency, throughput,
r
power consumption, and frequency, help-
P
ing designers avoid the common problem
of overbuilt hardware, for example, hard-
e
l
ware that exceeds performance require-
g
ments at the cost of increased silicon size
Figure 1
n
and/or power consumption. Since the
i
POWERMP-178X124-NEWPHOTO-UK.qxd 20/03/07 10:12 Page 1 C representation is completely abstracted
rS
o
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from the final implementation, designers can later use

the constraints in the algorithmic synthesis tool to
easily retarget the same representation for different
microarchitectures and ASIC/FPGA implementations.
Abstraction: The key to greater exploration

and optimization
Algorithmic synthesis based on pure ANSI C++ speeds
the hardware design process 10-100x. By nature, an
ANSI C++ source is a purely functional description of
the algorithm and therefore independent of the target
architecture and technology. Lower levels of abstrac-
y
tion necessarily include more information on hardware
l
structure, which limits the freedom a designer has when
n
exploring alternative microarchitectures. In addition,
O
automating the painstaking RTL creation process means
t
designers have more time to consider architectural deci-
sions that can have a tremendous impact on design per-
n
i
formance, area, and power consumption. The user can
r
apply synthesis constraints to specify the target technol-
P
ogy (ASIC or FPGA), the amount of parallelism, and
desired performance. These constraints, combined with
e
l
increased productivity, give the designer both the ability
g
and time to explore different trade-offs, resulting in a
n
wider optimization scope for their design (Figure 2). Figure 2
Si
or
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Contact us - www.ces.ch

These factors enable designers to create Typically, the ability to influence factors algorithmic synthesis. Used to restore
hardware designs more tightly tuned to a like power consumption, performance, signal clarity in transmission systems,
specific application than traditional RTL and area is much greater at higher levels the FIR filter is one of the most common
methods. For example, the same pixel- of abstraction. Unfortunately, accuracy of components used in signal processing
pipe algorithm for video might be used power, performance, and area estimation applications. This example will evaluate
in a land-based surveillance system, an is inversely proportional to a design’s trade-offs for an eight-tap FIR filter with
airborne reconnaissance system, and a abstraction level (Figure 3). However, a performance requirement of 400 MHz,
personal night-vision system, but each the ability to compare power consump- targeted at a 90 nm ASIC technology.
implementation would look very differ- tion estimates for the various algorithms
ent. Trade-offs to achieve these different or microarchitectures within an algorithm One of the most common structures of a
implementations can be made using a gives designers an invaluable advantage FIR filter is the literal implementation or
variety of constraints within an algorith- and allows them to have a much greater the direct form implementation, where the
y
mic synthesis tool. These constraints can impact on power-related decisions earlier data is moved through a shift-register based
l
include loop unrolling or pipelining, loop in the design process. delay line and each register’s output is
n
merging, RAM, ROM, and FIFO array multiplied with corresponding coefficients.
O
mapping, memory resource merging, and Case study: Finite Impulse Response The resulting outputs of all the multipliers
t
memory bit-width resizing. Using this (FIR) are summed up to create the filter’s output.
methodology, hardware designers can Using a FIR as an example (Figure 4), Typically, this implementation delivers
n
i
easily perform “what if” trade-offs evalu- let’s look at how this simple algorithm can the highest throughput. As most FIR filter
r
ating area, latency, power consumption, be implemented in multiple ways using coefficients are symmetrical, this tradi-
P
throughput, and clock frequency for each
microarchitecture, all the while leaving
e
l
the original pure ANSI C/C++ source
g
unchanged.
n
i
Example: Power optimization
Ability to Quantify
Ability to Impact Design

S
The increasing number of battery-powered
r
military applications that rely on power-
efficient algorithms – such as wireless
o
communications, portable data devices, Fut
F
ure
and video systems – has made power opti- Pre
sen
mization a higher priority. Well-known t
tactics like clock gating, optimizing Pas
t
memory accesses, controlling clock rates,
and changing state machine encoding,
for example, are typical RTL methods
for power-efficient design. Most of these
design techniques are available through Physical Gate RTL Behavoioral Algorithmic System
algorithmic synthesis tools. Design Level Level level
Figure 3
Figure 4

tional architecture could also be optimized tap number is the structure wherein the Using an advanced algorithmic synthesis
by folding the structure, thus reducing the taps are rotated through a shift register tool, such as Catapult C Synthesis from
number of multipliers required. Folding with only the end tap being indexed. This Mentor Graphics, one can rapidly create
is a common optimization strategy that implementation typically results in a lower various microarchitectures for any given
helps reduce area utilization by reusing area structure. Figure 6 shows a schematic algorithm. For example, a traditional or
the same area hardware components view of a register-based rotate implemen- direct form implementation of the FIR
(such as multipliers) for multiple streams tation of a four-tap FIR filter. Of course, filter can be designed with minimal
of data. Folding involves a trade-off there are many other logically equivalent resources or as a parallel fully pipelined
between the area utilization of the hard- popular FIR implementations such as a system. Though similar in functionality,
ware and the higher clock rate required transpose format or circular buffer using the effect on performance – especially
to maintain similar data rates. Figure 5 memory (for a larger number of taps); it with respect to power – for each of these
shows an RTL schematic view of a pipe- is up to the designer to choose one that implementations is quite different and
y
lined implementation of a direct form FIR best fits performance needs. In this article, can be clearly seen (Figure 7). The fully
l
filter. we will experiment with the direct form pipelined solution runs with the highest
n
and register-based rotate implementations throughput rate, but also has larger area
O
Another FIR filter implementation of the FIR filter and examine them with and higher estimated power usage.
t
typically used when the filter has a low respect to power consumption.
rn
i
e P
gl
Sn
i
or Figure 5
Figure 6
Figure 7

Similar experimental implementations Shawn McCloud has He holds a BS in Electrical and Com-
can be created for the register-based been the product line puter Engineering from Case Western
rotate version of the FIR filter algorithm. manager and director Reserve University in 1986. E-mail him
As expected, this algorithm’s imple- for Mentor Graphics’ at shawn_mccloud@mentor.com.
mentation uses less area compared to high-level synthesis
the shift-register based version and also technology for the past Mentor Graphics
consumes less power. four years. Prior to that, his positions at 503-685-7000
Mentor Graphics included technical and www.mentor.com
Verification benefits product marketing focused on RTL and
Another important benefit derived from high-level synthesis. From 1986 to 1994,
algorithmic synthesis is the greatly en- Shawn worked for Motorola as a senior
hanced quality of the RTL code. Since systems engineer responsible for RISC-
y
the lower-level RTL code is automatically and CISC-based microprocessor design.
l
generated from the system specification,
n
there are fewer bugs introduced into the
O
design – up to 60 percent less. By elimi-
t
nating errors that invariably crop up dur-
ing manual RTL generation, algorithmic
n
i
synthesis shortens the verification effort,
r
thereby moving a design to completion
P
faster.
e
l
For those bugs that stem from design-
g
related decisions, the same algorithmic
n
source description used to generate the
i
design can be used to automatically cre-
S
ate a consistent verification environment
r
including high-speed system models.
Advanced algorithmic synthesis tools
o
automatically create SystemC wrappers,
F
allowing designers to rapidly verify their
designs 20-100x faster than traditional
RTL. A test bench can also be generated
that automatically compares the ANSI C/
C++ input to the RTL output, providing
debug information for specific synchroni-
zation points in the case of a simulation
mismatch.
Rapidly implementing algorithms

in hardware
Even with an automated approach such
as algorithmic synthesis, the hardware
design process is a departure from the
traditional DSP software programming
flow. For companies that simply must
achieve higher performance, lower power
consumption, or more efficient imple-
mentations, algorithmic synthesis is a
cornerstone design technology. Algorith-
mic synthesis based on pure ANSI C++
eliminates the manual effort involved
in hardware creation, helping design-
ers explore more design options in less
time, plus reduce overall design time by
10-100x.

Implementation trade-offs
of digital FIR filters
By Ed Rocha
ny
l
tO U.S. Air Force photo taken by Tech. Sgt. Jason Tudor
rn
i
High-precision FIR filters are used in myriad medical, military, a microcontroller with a built-in hardware multiplier and enough
P
and high-volume consumer applications. However, given the data RAM to store data samples to be used in the computation.
choice of stand-alone Microcontroller Units (MCUs), DSPs, The major benefits are that this is a small, low-power implemen-
e
l
FPGAs, or dedicated Finite Impulse Response (FIR) ICs, only tation. It is also highly integrated. The microcontroller not only
the latter balances cost, power, size, and precision performance. implements the FIR filter, but can also function as the overall
g
system controller. The disadvantage is that a microcontroller,
n
i
FIR filters form the basis of wireless systems in medical devices, even after adding a hardware multiplier on-chip, still has very
S
industrial control, consumer electronics, and cellular infrastructure. limited computational abilities and is only a viable solution for
In fact, they are one of the most common types of digital filters. relatively simple FIR filters at low sample rates. Also, adding
r
These linear time-invariant style filters rely solely on current and resources to a microcontroller like a hardware multiplier and
o
past input samples and not on past outputs, making the resultant memory significantly increases the cost of the chip.
F
signal directly proportional to the number of taps (summation
series) and a coefficient set used to calculate the output. The second implementation is that of a DSP. The major benefit
of using a DSP is that it provides a large amount of computation
FIR filters can be calculated relatively easily using several dif- horsepower and a virtually infinite amount of flexibility in design
ferent IC implementations, including microcontrollers, general and algorithm choices. The DSP can also handle medium to large
purpose DSP chips, FPGAs, and purpose-built dedicated FIR FIR filters up to very high sample frequencies. The downside of
devices. While each type has advantages and disadvantages, in using DSPs, though, is that they are large devices that burn a
systems requiring the combination of high precision, low cost, lot of power. They are also relatively expensive and possibly
reasonable size, and power, purpose-built FIRs plus low-cost overkill in systems that run at lower sample frequencies.
MCUs represent the best of all worlds. Let’s examine each
option in detail. The third choice is that of an FPGA. The major benefit of an
FPGA is the ability to implement algorithms in hardware without
Implementation comparison losing versatility. FPGAs can support an almost infinite number
Several implementation choices are available to designers. Each has of algorithmic choices and provide the highest performance of
its benefits and risks (Table 1). The first implementation is that of all. The downside of using FPGAs is that they are also large
FIR basis Pro Con

Implements only simple FIR, limited computation, cost
Microcontroller (MCU) SWaP, integration, CPU decision making
increases with complexity
Flexibility, nearly limitless horsepower, implements large Power hungry, expensive, often overkill in some
Dedicated DSP
FIRs and high sample rates systems
H/W implementation yet still versatile, Large and power hungry, requires skilled IC designers,
FPGA
very flexible algorithms and cost per chip is high
Purpose-built FIR chip
Fast time-to-market, programming ease, low cost Fixed functionality, requires host controller
(such as the SavFIRe)
Table 1

devices that burn more power than any of Example FIR filter for comparison
the other alternatives. They also require To make a reasonable comparison
skilled engineers and considerable design between the different platforms for
time to implement. The cost per chip is implementing the FIR filter, it helps to
PC/104 Can-Tainer
the highest of all competing solutions for have an example. This way we can not
a single filter such as the one described only compute the ability of each platform
earlier. to perform the task, but also estimate
comparisons between the platforms’ size,
The final implementation choice is a power, and cost.
Simple and Versatile FIR Engine or
SavFIRe. The dedicated FIR chip is the The FIR filter we will design is a notched
CT1
easiest to program and represents the low-pass filter and has the specifications 04
y
quickest time-to-market of all solutions. shown in Figure 1.
l
Rugged anodized aluminum PC/104 enclosure
It is the least expensive of all the solu- designed for harsh environments.
n
tions and is by far the smallest and most »» System sample frequency = 1 KHz Isolating shock mount and an internal stack
»» Notch center frequency = 60 Hz vibration mount provides maximum protection
O
power-efficient method discussed. The from high frequency vibrations and low
downside of using this part is that it is a »» Top notch BW = 50 Hz frequency G-forces.
t
dedicated FIR filter and cannot be reused »» Bottom notch BW = 38 Hz
n
»» Notch attenuation = 60 dB
i
or reconfigured to be anything else. Using
r
SavFIRe requires some sort of host con- »» Pass-band upper frequency = 250 Hz 108 Watt PC/104+ Power Supply
»» Pass-band lower frequency = 260 Hz
P
troller to run the system. However, an
MCU with filter data storage can cost as »» Pass-band ripple = 0.1 dB
e
»» Stop-band attenuation = 60 dB
l
low as $1. The combination of an inex-
g
pensive, low-power microcontroller along
n
with the SavFIRe chip represents the best The approximate number of taps for this
i
total system solution in terms of power, filter is 467.
HE1
S
04+
size, time-to-market, and cost. DX
r
+3.3V, +5V, +12V & -12V DC output
o
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Extended temperature: -40OC to +85OC
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6V to 40V DC input range
PC/104 size and mounting holes
Built in temperature sensor
www.tri-m.com info@tri-m.com
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HEAD OFFICE: VANCOUVER
tel: 604.945.9565 fax: 604.945.9566
Figure 1

Microcontroller implementation
A good example of a microcontroller that
can handle a considerable FIR load is
Folded FIR Filter: High-level Conceptual Diagram
Texas Instruments’ MSP430F169. It has Data Store A Data Store B
both a built-in MAC unit and multiple
DMA channels to assist in moving data
and coefficients to and from data mem-
ory. Another significant specification is
its 2 KB of memory. This is important 2
because the microcontroller must have X(n) 1 N
enough memory to buffer data samples
equal to the number of taps.
Write In
Figure 2 shows the data flow of the FIR
filter. The steps needed to calculate each
ny
l
Read Out
N = max number of taps
O
output of the FIR filter are as follows:
t
Coef Store
»» Get input sample from ADC
n
coef MAC Y(n)
i
»» Loop N-1 times: Move two input
r
samples from memory to MAC;
P
move coefficient from memory to
MAC; perform MAC operation
e
l
»» Retrieve output from MAC and
g
store to memory
Figure 2
n
i
0883_TW_1-4-AZ_USA_OPVerlag 03.08.2006 12:32 Uhr Seite
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Table 2 represents some benchmarks
for the MSP430F169. Using the data in Number of Max Sampling Rate (KHz)
Number of Taps, N
the table, we can estimate the number CPU Clocks (100% CPU loading)
of clock cycles needed to calculate a
467-tap filter. After some interpolation, we 32 310 25
come up with about 3,200 clock cycles.
This indicates a maximum sample rate 50 410 19
of 2,500 Hz. We are only sampling at
1,000 Hz. If we add a bit of overhead to re- 100 730 11
trieve samples and deliver results to mem-
Table 2
ory or perform any type of analysis on the
samples, it is fair to assume that our filter
y
will result in approximately a 50 percent
l
loading on the CPU. Table 2 specifies
n
the benchmarks of the MSP430F169.
O
The MSP430 family only has a 16 x 16
t
multiplier in its MAC unit. This means
n
i
that designers are limited to 16-bit
r
data and 16-bit coefficients if they
P
are to achieve the performance just
mentioned. In many systems, both
e
l
data and coefficients can be larger than
g
16 bits, which could easily result in a per-
formance degradation of 10x or more.
DSP implementation
Sn
i
The steps involved in FIR calculations
r
are very similar for a DSP compared to a
o
microcontroller. Differences occur in the
F
memory usage where the DSP treats the
memory as a circular buffer with pointers
that automatically update. Also, because of
the high amount of parallelism and pipelin-
ing in a DSP, most DSPs can execute the
entire MAC operation including fetching
and storing data in one clock cycle per
MAC operation. There is a slight bit of
overhead associated with the beginning
and end of the computation loops, but this
is negligible for a large number of taps.
Using a Texas Instruments lower-end,

fixed-point DSP, the TMS320C55x,
let’s look at our previous filter design.
This DSP is capable of 160 MIPS
with one 32 x 32 multiply each clock
cycle. This equates to 160M/467 taps
per sample = 342 KSps at full speed; this
is more than adequate for our example
application.
FPGA implementation
The available hardware resources in any
given FPGA vary widely depending on
the FPGA vendor, part family, and the
size of the device chosen.

CTRL
Registers
For the 467-tap FIR in our example, let’s use the smallest FPGA
in the Cyclone II family from Altera. The EP2C5 has about DCLK 5
Data RAM
7 SCLK
DDS / FIR Filter
4.6 K logic elements, 26 M4K blocks (4 Kb RAMs), and 13 embed- DIN 4
Data Fmt / Averager 512 Tap SPI 8 SDI
Control M = 1-256 Max
ded multipliers that are each 18 x 18 bits wide. To implement the DSEL 3
Intfc
9 CS _N
467-tap filter in our example, there are many different architec-

Coefficient
tural choices available using the resources in the FPGA. Clk Gen
(ring osc )
clk _sys RAM
6 SDO
The simplest architecture is to use a single multiplier and run it

467/2=234 times for each input sample. The sample rate in this RVDD33 15
VREG
1.8v Core 3.3v I/O
example is only 1 KHz, which implies that our multiplier would RGND 16
have to run at:

14 12 10 11 13 2
y
RVDD18 VDD18 GND VDD33 TST RST_N
1 KHz * 467/2 = 234 KHz
l
Figure 3
,OWERTHE2ISK
On This is easily achievable in today’s FPGAs
t
and represents a minimal hardware
resource usage.
rn
i The multipliers in most low-cost FPGAs
P
are 18 x 18 as mentioned earlier. That
means to process larger than 18-bit data
e
l
or 18-bit coefficients or both, designers
g
will need to use four of these multipliers
n
to create a 36 x 36 multiplier.
S i Let’s assume a typical industry worst
r
case of 24-bit data words and 32-bit
o
coefficients. For a 467-tap filter, there must
be enough memory to buffer up 467 data
F
samples and to store 467/2 coefficients.
Ignoring some of the implementation
details of the FPGA RAM architecture,
this implies that a data RAM of 12 Kb and
a coefficient RAM of 8 Kb are needed.
Translating this into the M4K blocks of the
Cyclone II FPGAs would mean a total of
five M4K blocks.
'3S BIT!$#
SavFIRe implementation
'3S BIT$!# Quickfilter Technologies has developed
a SavFIRe chip that is a dedicated FIR
#/433OLUTIONSFOR%7AND2!$!2 filter, supporting up to 512 taps with
!CQIRIS THE INDUSTRY REFERENCE FOR HIGH SPEED DATA CONVERSION 32-bit coefficients and anywhere from
ANDPROCESSINGCOMBINESSTATEOFTHEARTPROCESSINGENGINESWITH 12- to 24-bit data words. The QF1D512
ADVANCEDPROPRIETARYTECHNOLOGYINAMODULARSCALABLEFAMILYOF supports sample rates from 1 Hz up to
6-%683 6)4! PRODUCTSFOREMBEDDEDAPPLICATIONSSUCHAS 500 KHz. A block diagram of the chip is
RADARANDELECTRONICWARFARE
provided in Figure 3.
4HIS CONCEPT BRINGS A NEW VISION FOR LIFECYCLE SUPPORT WITH
TECHNOLOGY INSERTION TOGETHER WITH HIGHER INTEGRATION LOWER The main advantages that come from a
POWERCONSUMPTIONANDGREATERRELIABILITY dedicated IC all stem from the ability to
&ORMOREINFORMATION
design a chip specifically for the purpose
ON6-%683MODULES in mind and optimize all of the associ-
CALLUSAT ORVISIT ated characteristics of the device. For
WWWAGILENTCOMlNDACQIRIS example, this device is 3 x 3 mm in size;
!CQIRISISNOWPARTOF!GILENT 16 of these will fit in the same footprint

ny
l
tO
rn
i
e P
gl
Sn
i
or
F

RTD Embedded Technologies, Inc.
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y
l
Featuring the new edition ZFx86
FailSafe® Embedded PC-on-a-Chip
fully optimized for the function at hand. consumption for SavFIRe running a
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Dual watchdog timers, Phoenix
467-tap filter at 1 KHz is about 50 µW.
BIOS and FAILSAFE Boot ROM The disadvantage of using an IC tailored This is orders of magnitude lower than
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Extended temperature -40°C to 85°C
for a specific function like FIR filters is any competing solution. The power scales
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that it is not very flexible for use in appli- directly with the sample rate, giving an
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cations outside of FIR filtering. Another equivalent power of 0.5 mW at 10 KHz
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requirement is that SavFIRe cannot be and 5 mW at 100 KHz.
used autonomously in a system. There
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must be some sort of host controller to Implementation comparison
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PC/104 VersaTainer configure the chip and run sample data We have outlined four popular choices for
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through it. implementing a high-precision digital FIR
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filter. All of these implementations have
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For comparison to the other implementa- their bright spots as well as their down-
tion methods, let’s use the same 467-tap falls, which are summarized in Table 3.
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FIR example from above. This filter can Again, the SavFIRe choice appears to
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VT-
104 be created with 32-bit coefficients and come out ahead.
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The VT104 VersaTainer is a rugged aluminum
use from 12- to 24-bit data samples with
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enclosure that can be used as either a PC/104, the current architecture in SavFIRe. Also, Ed Rocha is a
PC/104+ or EBX enclosure.
The solid one-piece extruded body provides dual
1 KHz is no problem since SavFIRe consultant and the
internal shock and vibration protection. works from 1 Hz to 500 KHz. owner of Ed Rocha
Consulting. He
So what about design effort? There is also consulted on the
a development package, QF1D512-DK, architecture and
comprising a development board and soft- development of Quickfilter’s software
ware development tool. The software tool development tools for both the QF1D512
75 Watt High Efficiency PC/104
enables a designer to design a filter by and QF4A512. He can be contacted at
simply specifying the filter parameters. erocha@quickfilter.net.
Once the parameters are entered, the
software generates all the filter coeffi- Quickfilter Technologies
cients and necessary register values to get 214-547-0460
HE
10
the chip up and running, making design www.quickfiltertech.com
4-7
5W
time absolutely minimal. It literally takes
75 Watt output
minutes for an inexperienced designer to
+5V, +12V, -12V outputs design a high-precision filter.
6V to 40V Dc input range
PC/104 compliant Compute Time-to-
Flexibility Size Power Cost
Power Market
Micro-
 
controller
www.tri-m.com info@tri-m.com
1.800.665.5600
DSP  
FPGA  
HEAD OFFICE: VANCOUVER
SavFIRe     
tel: 604.945.9565 fax: 604.945.9566
Table 3

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Mil Tech Trends: Industry execs weigh in
Focus on SWaP,
energy management, and QoS
An exclusive interview with Bill Kehret, founder and CEO of Themis
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EDITOR’S FOREWORD
On
Regretfully, my time with Bill Kehret ended all too soon. This edited and excerpted Q&A is so chock full o’ technical
goodness that I hated to leave anything out. But sadly, we had a space budget. However, this one is a must-read for anyone
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dealing with boards, software, power, multicore, or fabrics. Uh, pretty much all embedded applications. – Chris Ciufo
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MIL EMBEDDED: I think of Themis mostly as a SPARC server systems and applications evolved in a high clock rate, uniproces-
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provider. How’s this processor working for you? sor environment. This is especially true of real-time OSs that
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rely on a simple hardware model.
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KEHRET: First, let me say that we also field innovative, multicore
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Power-64 architecture products, as well as Intel and AMD multi- For our traditional SPARC market, customers using Solaris are
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socket, multicore products; we’re not all about SPARC. accustomed to running SMP, whether it is implemented over mul-
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tiple sockets or as a single socket with multiple cores. This class
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Specifically, regarding your question about SPARC servers, I’d of customers will make the move to multicore and multithreading
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like to point out that SPARC had the first SIMD instruction set over a shorter timeframe than those whose experience is limited
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enhancements, the first dual core processors, and now the first to uniprocessor environments. It is a natural consequence that all
eight-core SMP chips. Sun’s latest chip multithreading effort has Themis technology platforms have multicore variants.
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industry-leading floating point as well as hardware support for
up to 64 threads. MIL EMBEDDED: Which switched fabrics are having the great-
est impact on your customers? Why?
Themis has been a pioneer
in bringing these innova- KEHRET: Switched Ethernet,
tions to the embedded mar- … SPARC had the first SIMD instruction InfiniBand, and PCIe are the
ketplace, having deployed set enhancements, the first dual core standards being deployed by
many thousands of SPARC our customers. Our OEM
and Solaris “seats.” We processors, and now the first eight-core customers are coming up
continue to innovate with to speed on the use of these
SMP chips.
all of these technologies for fabrics, as they move from
ecosystems as diverse as “stovepipe” solutions, to
VME, ATCA [AdvancedTCA, a PICMG specification] and their the end customer’s computing needs, to more open and scalable
variants, as well as rack-mounting blade servers. We’ve even architectures. Customers and users alike perceive Ethernet as
deployed blade solutions integrated with storage and InfiniBand the standard solution to their system interconnect requirements.
switching, complete with flow-through liquid cooling. Sensor I/O is making a change to support Ethernet as opposed to
the more traditional serial or 1553 connections. Since there are
MIL EMBEDDED: How are multicore processors [AMD, Intel, many legacy interfaces in service, the move to fabrics for I/O
IBM] affecting your market? will come slowly.
KEHRET: Multicore is the right answer for SWaP-constrained Also, we’re increasingly seeing intersystem communication
applications. Sun probably got that right first, though it’s moving to 10 GbE along with the emergence of 10 GbE MACs,
rarely credited with those innovations. Multicore provides an with TOE [TCP/IP Offload Engine] and HW encryption support.
energy-efficient alternative to scaling core speed and can be a For TOE and encryption, SoC [System-on-Chip] processing
cost-effective way of fitting SMP onto a small platform. The platforms will surely accelerate this trend. For the future, the
solutions provided by AMD, Intel, and IBM vary greatly. For choice will depend on whether the application can tolerate the
embedded applications, the adoption of multicore is lagging protocol stack latency as well as the nonpredictable delivery of
behind the commercial enterprise because embedded operating data over the network.

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MIL EMBEDDED: Can you contrast the market for air-cooled, MIL EMBEDDED: What are the technology trends you’re see-
rack-mount equipment versus embedded, rugged, deployed ing, looking out three to five years?
equipment? What are the trends?
KEHRET: Connectivity, both in terms of hardware and software
KEHRET: If the distinction is a choice between rack-mounting infrastructure, will scale vertically and horizontally by two
COTS chassis, including “blade servers” and more robust bus- powers of 2. By this I mean that endpoint-pair bandwidths will
based board ecosystems such as VME and ATCA, then I’d have double twice and the number of switch endpoints will double
to say that the market for generic COTS boxes is growing at and possible quadruple. Entities under management will scale
the expense of all of the board-based ecosystems. But there is a equivalently. Applications will continue to be virtualized, to sup-
SWaP and cost penalty to be paid for “cocooning” lightly rug- port the scaled number of “clients.”
gedized COTS boxes, which can typically handle less than half
the “g” loads of average VMEbus boards, with vibration modal Security will be pushed further into the IT fabric and processor
frequencies significantly lower than for a VME ecosystem. chips so that multilevel security will be supported on operat-
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ing systems as well as data links, making networks and IT
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MIL EMBEDDED: “Mission critical” describes many applica- centers more impervious to malicious attack. Service Oriented
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tions today. What are the technical issues to consider in a Architectures [SOA] will fuel the demand for scaling processor
mission-critical environment? cores and threads and the virtualization of OS and application
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instantiations on those processing resources. Automatic comput-
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KEHRET: Regardless of how robust we make the hardware and ing resource management and policy languages will become as
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software, redundancy is necessary to achieve truly high levels commonplace as high-level hardware definition languages and
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of availability. The only question is how to size and control the “silicon compilers,” as required to cope with the avalanche of
overhead. Fully redundant systems are a luxury few applications computing complexity.
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can afford, so the trick is turning over-provisioned resources into
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productive resources. Real-time computing resource management MIL EMBEDDED: As processors and attendant systems have
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is critical to achieving contracted Application Quality of Service become more powerful, there is a need to develop clever
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[AQoS] for true mission-critical computing. Flexible policies cooling techniques. What are today’s challenges, and how
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determine the priority of applications loaded on the system. The are Themis and other companies addressing the problems?
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system’s mission drives those policies. Real-time automated con-
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trol is the only way to wring out all of the available performance KEHRET: We think there’s lots more life left for air-cooled sys-
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for a given amount of computing resources and application load. tems, and conduction cooling is a key to extending the life of
air-cooled systems. The question is where to put the heat sink.
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We like to use as much of the board surface area as possible for
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Serial Data Recorder the heat exchanger (heat sink) on our high power density boards.
We pioneered four-way SMP servers in the VME form factor,
Logs RS-232 data to CompactFlashTM using discretionary pins and 12 V power to get the power into
solid-state storage without a PC the slot and wall-to-wall heat sinks that slid into the VME board
card guides. Interestingly, VITA 46/48 takes a page out of this
saves power book and adds liquid flow-through cooling in the bargain.
saves hassle The trouble with bus and board open standards is the freedom that
saves money vendors have for interpretation. ATCA especially suffers from
all the choices of how to use cooling air channels on the board.
Our industry likes to go crazy with modularity. The downside of
this is that cooling air channels get messed up by a proliferation
of AMCs [Advanced Mezzanine Cards].
At the level of the shelf or chassis, there is very little effort made
to regulate the available slot-to-slot inlet air pressure, so much
of the touted power density headroom is fiction. These problems
put a special burden on the system integrator and can, in part,
be mitigated by the ecosystem vendor. However, that means the
vendor that builds the high power density boards also needs to
design the shelf/chassis and its cooling system.
DataBridge SDR-CF
TM Bill Kehret has been active in the embedded computing
industry for more than 30 years and CEO of Themis since it
was founded in 1989.
Acumen Instruments Corporation
www.acumeninstruments.com Themis
(515) 296-5366 510-252-0870
www.Themis.com
Quarter Page Ad - Swiss 721 BT.pub... ©2007

Thursday, OpenSystems
May 31, 2007 17:05 Publishing. Not for distribution.
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Guest editorial:
Intel commits to embedded,
communications
By Anthony Neal-Graves
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EDITOR’S FOREWORD
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I’m often asked if pure commercial telecom and communications equipment applies to the defense and aerospace markets.
It most certainly does. This question is usually posed by someone with a “hidden agenda” hoping to cast aspersions on
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vendors and supporters of telecom markets. Pure commercial telecom equipment – such as that found at the edge of the
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cloud in special-purpose systems such as packet shapers, voice-to-text-to-voice systems, and other specialty applications –
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has direct applicability to the military. This equipment forms the backbone of the non-classified sections of the Global
Information Grid, reachback installations, and provides interoperability with the rest of the civilian “POTS” world.
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And no company has been more involved with these telecom markets than Intel.
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To address those naysayers who say COTS suppliers don’t have a long-term commitment to telecom (and hence to A&D),
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I present this letter from Intel showing the company’s strong commitment to these applications, and to telecom in general.
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Intel prepared this statement exclusively for our readers at my request. – Chris Ciufo
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Intel is completely committed to the embedded and communica- such as PICMG to ensure that Intel Architecture based solutions
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tions markets, as demonstrated by its 30 year history supporting are available on ATCA and MicroTCA for customers in all these
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products for long lifecycles of at least 5 to 7 years, and that it market segments.
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continues to align its product roadmap with real customer needs
for performance and power. This could not be possible without Anthony Neal-Graves, General Manager
the rich array of hardware and software providers in Intel’s Modular Communications Platform Division, Intel
ecosystem. Intel first launched an ecosystem program in 1998,
named the Intel Communications Alliance (ICA) in 2002. Intel
and its ICA currently support over 3,000 customers in more than
30 market segments – a testament to Intel’s commitment to work
with industry developers to bring new solutions and standards to
wide adoption.
For example, real world deployments and adoption by leading

Telecom Equipment Manufacturers (TEMs) and service providers
worldwide have made AdvancedTCA (ATCA) the de facto plat-
form for the fastest growing IP services and wireless segments, such
as IPTV and IP services. In 2006, Intel saw a doubling in volumes
of ATCA products shipped to the communications market. Intel’s
recently released fifth generation ATCA Single Board Computer
(SBC) brings to market all the performance and performance
per watt benefits of the Dual-Core Intel® Xeon® Processor 5100
Series to these customers. With a wide variety of ATCA products
currently deployed on Intel Architecture, IA is clearly the lead-
ing architecture of choice for ATCA.
In addition, in the embedded industry, Intel is starting to see

momentum pick up in market segments such as Military and
Government. These customers have the same requirements for
rugged, reliable and long life systems as the telecommunications
market – and ATCA and MicroTCA are a natural fit. Intel con-
tinues to work closely with its ecosystem and standards bodies

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Linux meets the needs of security-critical,

network-centric computing
By Dr. Inder M. Singh
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The flexibility and availability of Linux applications provide the best way to manage costs, leverage commercial technologies,
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and provide flexibility in the military’s emerging network-centric computing systems. Separation kernel technology provides
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the framework for meeting the critical security requirements of these systems.
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The information age dramatically changed
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the modern battlefield. The U.S. military
has been deploying a new network-centric
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framework characterized by information
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sharing – shared situational awareness
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and knowledge of the commanders’ intent
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throughout the force, regardless of the in-
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dividual’s or unit’s precise location. Un-
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der the direction of the U.S. Department
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of Defense’s (DoD’s) Office of Force
Transformation (www.oft.osd.gov), all ad-
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vanced weapons platforms, sensor sys-
tems, and command centers are to be
linked via the Global Information Grid
(GIG). Still in its burgeoning phase, Net-
work Centric Operations (NCO), also
known as network-centric warfare, has al-
ready proven that networked forces can be
more effective than those using traditional
means of communication.
Implementation of the DoD’s massive Benefits of Linux Moving toward security

NCO systems will be the most ambi- Linux has played a major role in the The difficulty in transferring information
tious application of the network-centric development of networking, and it is between networks with different security
computing concept ever attempted, and it widely used across the Internet infra- classifications makes designing the NCO
is likely to become a model for building structure. The wide availability of Linux tricky. While conventional wisdom once
many large security-critical, network- applications for defense systems, com- stated that open source software ran the
centric systems in the commercial market bined with other benefits of using open
as well. source technology, can help to reduce Subsystems in Network Centric Operations
the cost and time for building large, Weapons systems
Designing an extended network on this complex applications. Many of the sub- Sensors
Controls
scale is obviously a massive undertaking. systems involved in NCO (see Table 1) Servers
The military recognizes that designing use embedded processors and software, Workstations
its “system of systems” to leverage the and some are used in other parts of these Personal computers
Handheld terminals
flexibility and availability of Linux appli- network-centric systems. Linux is unique
Table 1
cations is the best way to manage costs, in its scalability across this large range of
leverage commercial technologies, and available hardware.
provide flexibility in the network.

risk of malicious developers inserting code system, secure separation kernels parti- As part of these efforts, LynuxWorks has
developed LynxSecure, an embedded
that would make networks vulnerable to tion data and system resources, providing
secure separation kernel that will be cer-
attack or misuse, today the tables have dependable data isolation between parti-
tifiable to Common Criteria EAL 6+ and
turned. In fact, open source Linux is a bet- tions, controlling information flow among
DO-178B Level A. Its approach to certi-
ter match for mission-critical applications the partitions, and enforcing policy for fication, correct by construction, provides
than other proprietary COTS operating how partitions can communicate. the most cost-effective approach to certi-
systems, as its power and flexibility lie in fying a secure kernel and minimizing the
the robust code that anyone can view and The future of Linux networks costs of sustaining engineering throughout
improve upon. Many companies and organizations – such a program’s life.
as the nonprofit Network Centric Opera-
However, the security requirements of tions Industry Consortium (NCOIC) at Dr. Inder M. Singh,
mission-critical military systems that www.ncoic.org – are working toward LynuxWorks chairman,
served as CEO until
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handle multilevel classified data cannot bringing Linux to the forefront in secure,
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be met by any existing operating system, network-centric operations, integrating 2006. He has founded
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including Linux. Security has often been open standards into a global framework and led numerous
addressed by placing application guards based on a common set of principles and companies including
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and security functions at appropriate processes to facilitate the global deploy- Exelan and Kalpana.
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places in the network, thereby continu- ment of network-centric applications. He was formerly board chairman and
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president for the Embedded Linux Con-
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ing to leverage Linux’s flexibility while
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sortium. He holds PhD and M. Phil.
addressing security requirements. But ad With its international roster of defense
degrees in Computer Science from Yale
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hoc solutions of this kind are not easily contractors such as General Dynamics,
University, and an MSEE from Polytech-
scalable to the large, ambitious systems Boeing, and Lockheed Martin, as well as
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nic Institute of New York. He can be con-
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envisioned in NCO. A more powerful others in security-sensitive industries, the tacted at inside@lnxw.com.
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solution is provided by separation kernel NCOIC is working to develop a secure
technology. Secure separation kernels information management architectural
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LynuxWorks
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offer the ability to sequester the Linux framework for collaboration and projects 800-255-3969
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kernel in a separate partition, separate such as the GIG and others. www.lynuxworks.com
from highly trusted software that pro-
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vides the mission-critical security func-
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tionality. These secure separation kernels
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are designed to meet the highest levels of
embedded software security.
Separation kernels enable one operating

system (the “guest” operating system)
to run within the same environment as
another, supporting multiple operating
system environments on the same physi-
cal hardware. With a separation kernel,
security-related functions can be run
in separate, highly trusted partitions,
isolated from the Linux partitions, so that
the security of the system is not depen-
dent on the operating system. At the same
time, legacy Linux applications software
can be run unmodified, saving dollars and
staff years in programming time.
Combining separation kernels and hard-

ware virtualization technologies such as
Intel’s VT provides high-performance
operation of “guest” operating systems
running on separation kernels, compa-
rable to running the operating system
directly on the hardware. Unlike tradi-
tional security kernels, which perform all
trusted functions for a secure operating

The costs of doing business

in the new RoHS world
By Doug Patterson
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In addition to the design flaws and increased system failure rate it has produced, the inane RoHS compliance mandate has
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cost multiple industries millions of dollars in new development and remediation costs. Many questions still remain as to the
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usefulness of this directive in view of the performance sacrifices manufacturers and end users have had to endure.
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Adapting to change and assuming risk are generally considered In a presentation at the IEEE’s 2005 Microelectronics Reliability
costs of doing business. As industries and technologies shift and & Qualification Workshop in Manhattan Beach, California,
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new challenges present themselves, businesses must be ready for Northrop Grumman noted several satellite programs from 1998
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these costs. However, when an irrational and politically moti- to 2002 that completely or partially failed, including the Galaxy 3,
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vated change within an industry forces companies to assume Solidaridad 1, and HS 601. With this known problem of tin
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potentially detrimental risks without proof of a truly meaningful whisker growth, the reason why the RoHS directive is being so
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benefit, it becomes something more than just the cost of doing adamantly upheld must be questioned. Without any plan in place
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business. It becomes the costly way of doing business. to identify an alternative solution, RoHS eliminates an essential
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element (lead) in compounds that helps lessen the formation of
The new way of doing business tin whiskers.
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Within a very short time frame and with seemingly utter disre-
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gard for the lasting impact it will have on the reliability of critical The same 2005 IEEE presentation identified some potential miti-
embedded systems, the RoHS directive has forced our industry gation techniques (Table 1), but nothing proved reliable enough to
to adopt what is touted to be a more environmentally safe alterna- entirely eliminate tin whisker formation. In fact, industry research
tive – the elimination of lead (Pb) in electronic components. shows that conformal coating hasn’t stopped whisker growth. In
a 2000 paper entitled “Effects of Conformal Coat on Tin Whisker
But, time and again, we continue to see far more negative con- Growth,” Unisys and NASA documented that tin whiskers con-
sequences than perceived environmental benefits. Research tinued to develop even with a Uralane 5750 conformal coating in
dating back several decades has documented cases of tin (Sn) place. The study tracked the whisker development over a six-month
whiskers causing failures in several mission- and life-critical period and a one-year period, with both instances indicating that
applications. Missile and satellite programs, medical devices growth was continuing and coating penetration was inevitable.
like pacemakers, consumer electronics, and
the nuclear power generation industry have Lead-free tin whisker mitigation techniques*
all documented and suffered from the detri- Technique Result/Status
mental effects of tin whiskers. Wasn’t this
problem one of the reasons tin-lead solder Matte tin (dull finish) Proved more resistant to whiskering than bright tin
alloys came into play in the first place?
Annealing tin Reduces some stresses in plating that contribute
The price to be lead-free to growth
The RoHS directive has already incurred
Soldering or solder dipping with Proved useful for most components, but 100 percent
astronomical costs. The University of lead-tin solder coverage is mandatory. Only robotic solutions shown
Maryland’s Center for Advanced Life Cycle reliable to date.
Engineering (CALCE) has documented
several ongoing failures within electronics Stripping finishes; replating with May be possible for some components
lead-tin solder
systems specifically related to tin whisker
growth. A 2002 report on these failures states Conformal coatings Can be applied with some degree of success
that one particular recall within a missile pro-
gram cost taxpayers upwards of $5 million, *No technique has been proven effective in a long-term high-stress environment.
and that was more than five years ago. Presented at the December 2005 Microelectronics Reliability & Qualification Workshop
Table 1

Lead-free alloys tested
Effects on manufacturing
Alloy Soldering Advantagesa Disadvantagesa
and beyond
method
And what about the costs to
develop and manufacture Sn-3.9Ag-0.6Cu b (SAC) Wave • M.pt < SnAg • Cost and supply of Ag for
two component product lines Reflow • Good mechanical properties wave soldering
– one lead-free version and Manual • Better wetting than SnAg • Component thermal damage
another that includes a tin- Sn-0.7Cu-0.05Ni c Wave • Supply of material • M.pt > SnAg
lead alloy? Next, consider the Manual • Lower cost for use in • Component thermal damage
costs to companies that pur- wave soldering • Lower creep resistance
chase these components while Sn-3.4Ag-1.0Cu-3.3Bi d (SACB) Reflow • M.pt < SnAg and SnAgCu • Potential for weak joints
providing the next higher- Manual • Promising long-term with Pb
level subassemblies that now reliability • Commercial availability
must maintain segregated
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Control alloy: Sn37Pb
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stock and run separate pro- a Adapted from “Lead-free Electronics” (2004) for general alloy family; pros and cons may not apply for exact alloy shown
cesses – one RoHS compliant,
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b NEMI-tested alloy
the other compliant with c SN100C from NIHON Superior
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the waivers and exemptions d NCMS-tested alloy
Source: BAE Systems 2005 testing of lead-free solder or high-reliability applications
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allowing tin-lead alloys.
Table 2
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And how much lead are we sav-
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ing with RoHS? Are the costs really justifiable? Texas Instruments the power-generation industry, the U.S. Nuclear Regulatory
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has estimated that its conversion to lead-free will save the equiva- Commission has documentation dating back to 1999 from
lent of just 10 automobile batteries annually on a worldwide scale The Foxboro Company of Foxboro, Massachusetts, indicating
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– a minuscule amount when you consider the millions of dollars that nuclear reactors had to perform a SCRAM (an emergency
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and hours spent scrambling for compliance and trying to counter nuclear reactor shutdown) because of tin whisker growth embed-
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the effects of using lead-free components. ded deep within the control electronics. A tin whisker was also
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the reported cause of a 2005 plant shutdown at the Millstone
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RoHS seems to be here to stay, which means tin whiskers aren’t Power Station in Millstone, Connecticut.
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going away either, until new, cost-effec-
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tive soldering alloys and compounds are
found. Even though tin whiskers were
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discovered several decades ago, no one
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clearly understands what makes them
grow. CALCE proposes several funda-
mental questions aimed at discovering
the root cause of whiskers:
»» How much mechanical or

environmental stress is needed
to initiate growth?
»» Does temperature cycling or
steady-state temperature aging
worsen growth?
»» Could passivation (or surface oxide)
layers reduce tin whiskers?
To date, more than 11 months after the

RoHS directive was put into full effect,
the industry has not yet produced an effec-
tive, standard replacement for the tin-lead
alloy. However, some companies have
tried to find a solution. BAE Systems
researched three tested alternatives, but
none proved to match the caliber of tin-
lead (Table 2).
Feeling the full effect

This lead-free issue affects many other
businesses besides those in the medi-
cal, communications, and defense and
aerospace industries. For example, in

LOCATING...
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solutions partner with: o Semiconductor products for specific
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White Electronic Designs has expertise and
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experience in constructing extended environment,
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on time – over time – every time.
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Proceed directly to:
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www.whiteedc.com/Delivers
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Alternate routes include info@whiteedc.com
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or 602.437.1520.
WWW.WHITEEDC.COM

Doug Patterson is VP of worldwide sales and
marketing for Aitech Defense Systems, Inc.
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Doug has more than 20 years of experience in
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marketing, business development, and product
management, including technical and commu-
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nications accomplishments in telecommunica-
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tions and harsh environment electronics.
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Currently, he serves on VITA’s board of direc-
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tors. He also holds three patents in advanced metered mailing
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systems and nonvolatile memory redundancy mapping. Doug
holds a BSEE from BEI/Sacred Heart University. He can be
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contacted at dpatterson@rugged.com.
This tin whisker problem is not a new one. Not only
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has it reared its ugly head before, but it also has been exacer- Aitech Defense Systems, Inc.
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bated by electronics’ decreasing geometries and smaller device
i
888-248-3248
size. Components are now physically closer together on densely www.rugged.com
S
packed circuit boards, and the distance
r
a tin whisker must cover before reach-
o
ing another component and causing a
F
short, or in some instances, a catastrophic
system failure, is decreasing.
The negative effects of RoHS are not

limited to tin whiskers. Additional rev-
elations continue to surface. Last January,
researchers at Ford Automotive’s Lincoln
Design Center identified the cause of mal-
functioning computers – lead-free solder
that corroded when it came in contact with
modeling clay that contained high levels
of sulfur. The older computers with the
traditional 60/40 tin-lead solder were unaf-
fected. What other risks inadvertently cre-
ated by this transition await us down the
road, and what will the real costs be?
To mandate a directive with known and

unknown consequences within such a short
time period seems an extremely expensive
and haphazard way of doing business.
Change can be good, and taking risks helps
businesses and industries grow. But, it is
also necessary to find a balance so that the
cost of doing business does not exceed the
expenses needed to maintain compliance
with changes of dubious benefit.

Special Feature: PowerPC still tops for defense
Advantages of Power Architecture

technology for military applications
y
By Katie Butler
nl
The PowerPC and the subsequent development of the complete was a new breed of superscalar RISC microprocessor that offered
O
Power Architecture technology family have become synonymous very high levels of performance with relatively modest clock
t
with military embedded computing applications, powering rates. Its performance was achieved through more efficient forms
n
many high-profile programs from the M1-A2 Abrams main of pipelining and branch prediction than previous processor archi-
i
battle tank to the F/A-18E/F. We look at its evolution and how tectures, resulting in improved performance per watt of power
r
it has maintained a technological advantage over competitive dissipation. Since then Power Architecture technology vendors
P
processing architectures. have continually improved and innovated new microprocessor
solutions, contributing to the architecture’s success in embedded
e
l
Power Architecture technology was first introduced as the PowerPC computing markets such as automotive, telecommunications,
g
core by Motorola and IBM in the early 1990s. The PowerPC core aerospace, and defense.
Sn
i
or
F
Figure 1

The stringent selection criteria required by embedded systems Power Architecture technology based devices such as Freescale’s
deployed on military front lines are reflected in the choice of single and dualcore version of the MPC8641 (Figure 1) have
processor that can be used for each application. Key selection comprehensive processing subsystems all in the same device, and
characteristics include the following: yet still maintain an overall power dissipation of no more than
.30 W. This compares favorably to earlier Power Architecture
»» High processor performance for compute-intensive and based devices such as the MPC7447/7448 which, when configured
embedded applications with external devices of equivalent functionality, would typically
»» High levels of integration to reduce supporting device dissipate similar power for only one processor device.
real-estate and power dissipation
»» Vector processing unit for high-performance digital signal High performance and integration
processing applications MIPS used to be the primary indicator of a processor’s perfor-
mance, as it is a measurement of the instruction rate of a particu-
»» Power dissipation as low as possible. Power translates lar device. However, the MPC8641’s high degree of integration
into space and weight, which are premium commodities in
y
shows that overall system performance, instead of just core
l
military platforms.
instruction rate, is becoming the industry’s key metric.
»» Software compatibility between
On
generations for spiral development
and long-term sustainability
nt
Power Architecture technology ad-
i
r
dresses these criteria by having a broad
product portfolio from a variety of
P
vendors to balance the performance-
e
versus-power trade-off. Furthermore,
l
many of the products are targeted for
g
long embedded application life cycles.
n
For example, the MPC603e PowerPC
i
device from Freescale, which was intro-
S
duced in 1996, is still shipping in the
r
industry today. By meeting the selection
criteria of high-performance processors
o
with a wide temperature range and an
F
embedded power envelope, Power
Architecture technology has become
one of the de facto processor archi-
tectures in the aerospace and defense
market today.
Power Architecture technology

evolution
The first generation of PowerPC core
based processors comprised general
purpose execution and arithmetic units
only, requiring external support for
caches, memory controllers, bus inter-
faces, and I/O interfaces to create a
complete embeddable general purpose
processing subsystem. As semicon-
ductor process technology improved
and transistors became smaller, many
of the functions were absorbed into
the processor itself. One example was
Freescale’s PowerQUICC family of
processors, which integrated a commu-
nications offload engine able to perform
stack processing and thereby offload the
CPU. This was a pointer to the future
of processor architecture development,
as today many functions have been
integrated in hardware.

Special Feature: PowerPC still tops for defense
In today’s systems an execution unit will rarely have

its instruction and data queues full and imme-
diately available for
processing at the
maximum instruc-
tion rate. There are
exceptions to this,
such as some classes
of digital signal processing, but Figure 2
these are unusual. System perfor-
mance is affected by external and oper-
ating system-generated events – context on-chip caches and memory
switching, interrupts, timers, protocol stack controllers. This provides a massive
y
processing, buffer management, and the applica- system-level performance boost when
l
tion itself. All of this causes the processor core to be compared to less integrated processing devices.
n
idle for part of the time waiting for data or instructions.
System performance comprises all these plus the bandwidth AltiVec technology based vector processor
O
and management of the data paths and memory such that optimal Integration has become one of the defining technology inno-
t
processing performance, I/O processing, network performance, vations of Power Architecture technology devices. One such
n
and data flows can be achieved without compromise. example is the AltiVec technology, which revolutionized mili-
ri
tary digital signal processing and floating point applications,
Incorporating all this functionality onto a single device has been first integrated into Freescale’s family of processors contain-
P
made possible by improved process technologies yielding more ing PowerPC cores in 1999. Operating in parallel with the
e
transistors per die. The current process allows the inclusion of PowerPC’s execution unit, AltiVec technology is a SIMD vec-
l
hardware implementations of many I/O and communications tor processor with thirty-two 128-bit registers supporting many
g
subsystems such as multiple Ethernet controllers, Serial RapidIO data types and complex instructions. This makes it highly
n
interconnect, and PCI Express expansion cards in addition to suitable for applications such as image, sonar, and radar pro-
i
cessing. AltiVec technology was recently enhanced to include
S
out-of-order execution to increase its efficiency when working
r
with multiple data streams.
o
Digital signal processing applications require specialized
F
architectures that support scalability and rapid data movement
from the sensors and between many processing nodes. The
MPC8641D, with its dual cores and support for Serial RapidIO
interconnect, makes an ideal basis for such a signal processing
system. Serial RapidIO provides a high-speed, peer-to-peer
switched fabric with very low latency, which can be configured
in many different topologies to provide the bandwidths required
between multiple processing nodes.
An example of how the Power Architecture technology’s inte-

grated features and AltiVec technology can be harnessed is the
Curtiss-Wright Controls Embedded Computing CHAMP-AV 6
advanced multicomputer for digital signal processing applica-
tions, shown in Figure 2. This platform, based on the new VPX
(VITA 46) standard, integrates quad MPC8641D devices, each
with its own 1 GB DDR2 memory subsystem, for a total of
eight processor cores and a high-speed Serial RapidIO fabric to
distribute data between processor nodes.
Power dissipation
Another key issue in processor architecture today is power
dissipation. Much in the way that overall performance mea-
surements have changed from just core clock frequency, the
ways of describing processor power dissipation have changed,
especially with complex power management schemes. Many
devices in consumer markets benefit from power management
schemes where parts of the device can be powered down when
not in use, or clocks can be slowed to reduce power drain.

However, many embedded applications cannot handle reduced
performance to counteract an overheated processor. A primary
flight control computer for a single-seat aircraft cannot operate
more slowly just because it gets warm. Therefore, it is important
that maximum power dissipation is always stated at maximum
performance and maximum temperature. This allows designers
to properly characterize their embedded systems within their
operational limits.
Software compatibility
Beyond evaluating hardware platform performance, system
designers must also evaluate the available software solutions.
Aerospace and defense vendors make a significant investment in
y
software. Because military platforms such as warships, aircraft,
l
and ground vehicles have a very long service life, companies
n
must invest in architectures that have software compatibility
across platforms. Power Architecture technology vendors such
O
as Freescale Semiconductor offer software compatibility across
t
their Power Architecture cores and products, making it very
n
i
easy to scale platforms. Preservation of the integrator’s software
r
investment is key to the success of these programs, along with a
P
commitment to long-term supply.
e
The future of Power Architecture technology
l
The future of Power Architecture technology lies in Power.Org
g
(www.power.org), an open forum focused on promoting the
n
architecture and bringing together the current Power Architec-
i
ture technology specifications to the open community. Both
S
Freescale Semiconductor and IBM participate in Power.Org, and
r
recently the organization announced the Power ISA 2.03, which
o
merges previous versions of the Instruction Set Architecture.
This merger results in more consistency and compatibility across
F
platforms based on Power Architecture technology, a significant
benefit for software and system designers. Power.Org works
to ensure the future compatibility of new Power Architecture
technology products and the continued growth of the supporting
ecosystem of developers and suppliers.
Power Architecture technology has become one of the prominent

processor architectures in the military and aerospace industry
today. Its historic reputation for low power and high performance,
as well as its strength in software compatibility and embedded
life cycles, has resulted in highly integrated products that will
continue to serve the market.
Katie Butler is the aerospace and defense

product marketer for the networking com-
puter systems group within Freescale. She
supports aerospace and defense customers
that integrate PowerPC and PowerQUICC
products into their solutions. Katie received
her Bachelors and Masters degrees in
Electrical Engineering from the Massachusetts Institute of
Technology, where her graduate research work was focused on
power dissipation in optical networking. She can be contacted
at katie.butler@freescale.com.
Freescale Semiconductor
512-996-5370
www.freescale.com

Product Guide: PowerPC products
Rugged
Company name Form factor Model number Processor/Frequency Version(s) Description
available
Aitech Defense Systems A rugged 3U CompactPCI single-slot SBC in

www.rugged.com
3U CompactPCI C903 IBM 750L, 600 MHz  conduction- and air-cooled versions
GE Fanuc Embedded Systems

www.gefanucembedded.com
3U CompactPCI IMP1A-571 Blade PowerPC 7410  A single-slot software radio blade
GE Fanuc Embedded Systems PowerPC 8641D, A single board computer featuring x8 PCI Express
3U VPX SBC330
1.5 GHz  fabric, 2 GB memory, and two GbE ports
y
l
General Micro Systems Ultra low-cost single board computer with power
www.gms4vme.com
6U CompactPCI C512 Freedom AMCC PPC, 800 MHz  consumption as low as 7 W
Interface Concept
www.interfaceconcept.com
On
6U CompactPCI IC-e6-cPCIb
MPC7448 PowerPC,
1.4 GHz (2 optional) 
A high-performance board in standard, extended,
and rugged grades
Motorola Inc., Embedded

Communications Computing
n
it6U CompactPCI
CPCI-6190
IBM 750GX, 1 GHz
A universal-mode SBC with IPMI system
r
Processor Board management support (PICMG 2.9)
www.motorola.com/computing
P
Motorola Inc., Embedded CPCI-6106
A CompactPCI high-performance universal
Communications Computing 6U CompactPCI Universal IBM 750GX, 1 GHz
e
processor board
l
www.motorola.com/computing Processor Board
g
IBM 750GX, 1 GHz or
Orion Technologies
6U CompactPCI CPC7520 IBM 750FX,  A PowerPC 6U single board computer
n
www.otisolutions.com
i
600/800 MHz
S
Orion Technologies PowerPC IBM 750FX/GX, A hot-swappable, high-availability PowerPC
6U CompactPCI CPC7510 
r
www.otisolutions.com 1 GHz 6U SBC
o
Performance Technologies AMCC High Performance A high-availability NAS or SAN storage blade
6U CompactPCI CPC5900
F
www.pt.com PowerPC supporting 800 GB of storage
Actis ACTIS-VSBC- PowerQUICC II A PowerQUICC II SBC based on the

6U VME
www.actis-computer.com 6848 MPC8248E, 400 MHz MPC8248 processor
CES A family of reconfigurable PowerPC-based 6U VME

www.ces.ch
6U VME RIO4 Family PowerPC G4  2eSST computers for harsh environments
GE Fanuc Embedded Systems PowerPC 7447 G4+,

6U VME PPC8A-572 Blade A single-slot blade system
www.gefanucembedded.com 1.2 GHz
A combined C102 SBC processor and M222

Aitech Defense Systems Dual-Process flash memory PMC to help solve data throughput
www.rugged.com
6U VME64x
SBC
7448 RISC  problems and provide lower power dissipation and
large mission data mass storage
A versatile AdvancedTCA mezzanine card

Extreme Engineering MPC7448 PowerPC, carrier that can be factory configured to
AdvancedTCA XCalibur1210
www.xes-inc.com 1.7 GHz (2) support any combination of PrPMC, XMC,
and AdvancedMC modules
A blade targeted at high-volume transaction

Interphase and user-plane traffic processing required for
AdvancedTCA iNAV 74K Freescale 8641D (4)
www.interphase.com next-generation wireless infrastructure and
IMS control planes
Dual Core Freescale

Kontron AdvancedTCA,
www.kontron.com MicroTCA
AM4100 PowerPC  An AdvancedMC module
MPC8641D, 1.5 GHz
Eridon Development A development framework comprising hardware,
UnifiedLogic
www.eridon.com Tool development tools, and software
Jungo Development A development tool used to incorporate complete
Embedded USB
www.jungo.com Tool USB software connectivity

Rugged
available
Macraigor An implementation that packages Eclipse 3.2.1,

Development Eclipse+GNU
www.macraigor.com several of the open-source GNU tools/utilities,
Tool Tools
and a program called OCDRemote
A high-speed in-circuit emulator where code is
MICETEK Development USB TAP For
loaded by JTAG/COP/BDM interface at speeds
www.micetek.com Tool PowerPC
up to 1.6 Mbps
An Integrated Development Environment (IDE)
MICETEK Development JediView for
that provides a simple, versatile graphical user
www.micetek.com Tool PowerPC
y
interface
MICETEK
nl
Development
Tools for PowerPC
PowerPC development tools, including in-circuit
emulator, evaluation board, and IDE, along with EV
O
www.micetek.com Tool board models such as MPC8313E, 8323E, 8347E,
8349E, and others
Embedded Planet
www.embeddedplanet.com
n
it EPIC EP440xS
AMCC PowerPC 440EPx,
667 MHz
A credit card sized SBC (3.5" x 2.2")
r
A feature-packed computer delivering high
P
Embedded Planet AMCC PowerPC 440GR,
EPIC EP440K levels of performance and reliability in a small,
www.embeddedplanet.com 667 MHz
power-efficient package
MPL
www.mpl.ch
ge
l PC/104 MIP470
MPC8347 PowerPC, 400
MHz  A controller board with 400 MHz PowerPC and FPU
n
i
MEN Micro MPC8548, 1.33 GHz or
PCI-104 EM9  An embedded system module
S
www.menmicro.com MPC8543, 800 MHz
r
GE Fanuc Embedded Systems An FPGA DSP board with high-speed inputs
PMC ICS-1580 IBM 400 MHz PowerPC
o
www.gefanucembedded.com in PMC format
F
A series of compute nodes providing FPGA
processing resources on a PMC form factor,
Micro Memory
www.micromemory.com
PMC MM-71xx Series Virtex-4 FPGAs  targeting applications such as synthetic aperture
and phased array radar, Software-Defined Radio,
and signal intelligence
PrPMC6001 MPC7448 PowerPC G4, A PMC designed for embedded applications
Communications Computing PMC
Processor PMC 1.4 GHz requiring low power and high performance
PrPMC2750 PowerPC 750 GX, 1.0 GHz A high-performance PowerPC processor
Communications Computing PMC
Processor PMC (2 optional) PMC module
Orion Technologies An extended temperature, conduction-cooled

www.otisolutions.com
PMC PMC7525 PowerPC IBM 750FX/GX  PMC7525 PowerPC PMC SBC
4DSP
PMC/XMC AD491 PowerPC RISC A dual-channel, 8-bit, 1 GHz PMC/XMC digitizer
www.4dsp.com
PrPMC8005E MPC7410 or MPC750 A high-performance Processor PMC that operates
Communications Computing PrPMC
Processor PMC PowerPC  in extended temperatures

PrPMC8150 A high-performance Processor PMC with
Communications Computing PrPMC PowerPC 750FX, 800 MHz
Processor PMC optional encryption
Orion Technologies IBM 750GX, 1 GHz or
PrPMC PMC7520 A PowerPC PrPMC single board computer
www.otisolutions.com IBM 750FX, 600/800 MHz
MICETEK A low-cost, high-performance system that
www.micetek.com
System MPC8313E-RDB PowerQUICC II Pro  includes a built-in security accelerator
GE Fanuc Embedded Systems PowerPC
VME 7410 PowerPC DSP (4) PCI software radio PowerPC DSP blade
www.gefanucembedded.com DSP Blade

Rugged
available
A DSP board with two PMC sites integrated with

GE Fanuc Embedded Systems GE Fanuc radio PMC modules to offer a complete
VME ICS-8550 G4 PowerPC (4)
www.gefanucembedded.com receive and/or transmit solution in only one
VMEbus slot
MPC7457 PowerPC, Motorola’s original SBC designed with the 2eSST
Communications Computing VME MVME6100
1.267 GHz VMEbus protocol
y
Communications Computing VME MVME5500 MPC7457, 1 GHz Motorola’s latest VME single board computer
l
n
Motorola’s second VMEbus SBC designed with
Communications Computing VME MVME3100 MPC8540, 800 MHz
O
the 2eSST VMEbus protocol
t
Hybrid computing platforms that integrate the
n
i
Freescale 8641D multicore General Purpose
CSPI
r
VXS 3000 SERIES Freescale 8641D Processor (GPP), Xilinx Virtex-5 FPGA, and
www.cspi.com
Myricom’s 10 GbE Myri-10G clustering technology
P
on a VXS platform
e
A digital signal processor supporting VITA 41
l
VMETRO
www.vmetro.com
VXS Phoenix VPF1 PowerPC 7447A (2)  backplane switch fabric communications via
g
VXS over P0
n
Data was extracted from OSP’s product database on July 31, 2007. Search keyword was “PowerPC” on products entered January 1, 2007 through June 30, 2007 within all OSP magazines.
i
L-3Targa_MilEmbedded_HalfPg_Aug07:Layout 1 theme.
Products were also selected according to relevance to the product guide’s 8/7/2007 11:36
Entries have been editedAM Page 1
for publication, and OpenSystems Publishing is not responsible for errors or
omissions. Vendors are encouraged to add their new products to our website at www.opensystems-publishing.com/vendors/submissions/np.
rS
Fo

n ly
t O
r i n
e P
g l
S i n
o r
Fintroduces affordable FPGA I/O. For ALL your projects.
Acromag
A
s an engineer, your projects are unique, Cost-effective custom I/O Call or visit our website today –
ever-changing, and budget-bound. That’s Choose from a variety of I/O configurations: for VME, CompactPCI, PMC,
why our new PMC modules give you an • Digital I/O: TTL, CMOS, RS422, or LVDS I/O and Industry Pack solutions.
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• Analog I/O: 16-bit 100MHz A/D, 900KHz D/A
But if you thought FPGA computing was only
for top-end applications, think again. Our PMCs Faster time to market
are ideal for protocol conversion, simulation, Why waste precious time building a board from
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Manufactured in Wixom, Michigan, USA All trademarks are the property of their respective companies

Editor’s Choice Products
Unless you’re in the NSA, read this …
NSA-encrypted red/black systems are without a doubt the most secure systems on the planet – they have to be. Trouble is, all the rest of the DoD’s
equipment might literally include computers and peripherals purchased off the GSA from Best Buy, Wal-Mart, Radio Shack, and other civilian COTS
suppliers. That’s the benefit of COTS, folks. But there’s still the problem of lost laptops, unencrypted files, malware, forgotten passwords and cookies,
and all the other crud that affects our personal computers every day. So Lavasoft, a recognizable name in the anti-spyware business, has created a trio of
digital protection tools that apply to DoD users just as well as consumers.
Sure, you can do some of these same functions with open source tools like Eraser or TrueCrypt, but Lavasoft’s are commercial-grade COTS packages
that are designed for utility and ease of use. The Digital Lock – File Encryptor product includes multiple encryption algorithms such as AES standard 256
bits, multilayered encryption, shredding after encryption, and an e-mail security channel. File Shredder’s drag-and-drop features work with Word, Excel,
PowerPoint, videos, and other multimedia files, and has some tricks to work with Windows Vista. And the Privacy Toolbox combines both products into
one. A 30-day trial is available on Lavasoft’s website.
Lavasoft • www.lavasoft.com
y
RSC# 34057
nl
Serial RapidIO AdvancedMC for radar, sonar, telecom
tO
The AdvancedMC card – used on AdvancedTCA and MicroTCA platforms – is turning into quite the mezzanine for
n
communications connectivity. Originally designed for telecommunications applications, AdvancedMCs are appealing
i
to the military primarily because of their COTS status and myriad networking options. If rugged MicroTCA gains
r
traction in defense, AdvancedMCs such as Mercury Computer’s Ensemble MPC-102 might be coming to a TOC or
P
AWACS near you.
e
Based on the Power Architecture dual-core Freescale 8641D, the MPC-102 offers Serial RapidIO or PCI Express
l
connections to the carrier card, along with four GbE connections (two to the panel and two to the AdvancedMC
g
connector), a SATA port, and dual RS-232 connections. With up to 10 Gbps raw I/O bandwidth on Serial RapidIO
and the on-the-fly processing afforded by the 1.3 GHz PowerPC and 2 GB DDR2 SDRAM combo, the module is ideal
n
i
for networking applications that process radar or sonar data.
S
Mercury Computer Systems • www.mc.com
r
RSC# 34056
Fo

Brightness beyond “nits”

How many times have you tried to use that fast Wi-Fi pipe out on your porch, patio, or deck – only to find that the sunlight washed out your
laptop’s display so badly that it was illegible? Me, too. Now imagine how this affects soldiers and Marines in the Middle East – whether they’re
dismounted, under sun shades, or in HWMMVs. That’s why General Dynamics Itronix invented the DynaVue all-light viewable touchscreen display.
A manufacturer of rugged laptops, notebooks, and Tablet PCs, Itronix deploys its portables into all kinds of battlefield conditions – including
bright sunlight.
Focusing on contrast ratio and polarization techniques, the patent-pending light filtering technology increases the display’s contrast ratio to
provide rich color saturation and improved fine detail visibility. With a single cold cathode fluorescent backlight lamp, the computer saves bat-
tery power because the display requires less energy to maintain sunlight readability. General Dynamics Itronix says DynaVue will debut on the
company’s next-gen computers.
General Dynamics Itronix • www.gd-itronix.com
y
l
RSC# 34053
On
t
32 instruments on
one PC
rn
i
P
Think of it as a data acquisition Swiss Army knife – one
of those ridiculously large ones that even has a fishing
e
l
pole built in, tucked next to the shortwave transceiver
g
in the handle. Well, you get the idea. The Version 6.5
n
MultiScope software from DSPCon runs on a PC and
i
provides display power for 32 test and lab instruments
S
on a single PC. “Feature rich” is an understatement for
r
this product. The package replaces oscilloscopes, spec-
o
trum analyzers, data loggers, recorders, pianos (kidding
about that last one), and several other instruments.
F
The GUI desktop works with DSPCon’s Piranha III and
DataFlex-1000 products for acquiring, analyzing,
and displaying data from up to 32 test channels.
MultiScope can display data in Time Series, FFT, Strip
Chart, Lissajous, Campbell, Spectrum, and myriad other
modes – with up to 32 scopes per user-defined page.
And, users can create multiple pages just like “sheets”
inside of Microsoft’s Excel environment. The convenience
of having one multichannel tool that does it all – on a
single PC – with the ability to display, analyze, process,
record, and playback is extremely compelling for design
and test engineers. Amazing.
DSPCon • www.dspcon.com
RSC# 33488

FPGAs for Mars

Picture this: Ground control, Major Tom, little green men. What image comes to mind? That’s right: Mars, space, the Final Frontier. A truly
hostile environment, no matter how glamorous Hollywood makes it out to be. Surviving in space means constant radiation bombardment,
temperature extremes, and imperative energy vigilance as batteries charge in sunlight, then go flat in the inky darkness.
Actel’s RTAX-SL FPGAs were designed with just this environment in mind. The new “L” variation of the company’s RTAX line includes the
RTAX250SL (30,000 ASIC gates), RTAX1000SL (125,000 ASIC gates), and RTAX2000SL (250,000 ASIC gates) and promises 50 percent
lower standby current “than the leading space FPGA at 125 °C.” (We’re assuming they mean a product from “A” or “X.”) The devices
use SEU - hardened registers, eliminate the need for TMR, and promise an SEU rate of less than 10E-10 errors/bit-day in worst-case
geosynchronous orbit. The devices are also all available in QML Class V per MIL-PRF-38535.
Actel Corporation • www.actel.com
y
l
RSC# 34051
On Itty bitty 15 A fuse
n
it
Pr
ge
l
Sn
i
or
F In electric shop during my childhood, I built my first
project power supply out of an old MIL-SPEC power
supply. I remember vividly the mombo fuses that thing
had because every time I was careless with the leads:
Pop! I fried one of them. Those suckers musta been
0.5" diameter and more than 1.0" long. My, how
times have changed. Today you can surface mount a
125 V/15 A subminiature fuse that’s about the size of
Lincoln’s head (see photo).
The 465 Series Littelfuse devices are RoHS compliant

and offer 20 A and 30 A ratings in 0.397" (10.10 mm) x
0.123" (3.12 mm). Even more impressive are their
interrupting ratings of 100 A at 125 Vac and 300 A at
65 Vac, respectively. Designed for overcurrent protec-
tion in space-constrained applications, they’re ideal for
vehicle-mounted military comms and telemetry equip-
ment that relies on “shore power” but must fit into
suitcase-size cubbyholes.
Littelfuse • www.littelfuse.com
RSC# 34052
Editor’s Choice Products are drawn from OSP’s product database and
press releases. Vendors may add their new products to our website at
www.opensystems-publishing.com/vendors/submissions/np/ and submit
press releases at www.opensystems-publishing.com/news/submit.
OSP reserves the right to publish products based on editors’ discretion
alone and does not guarantee publication of any product entries.

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Dual-Core Xeon security server

Besides courage and guts, the military relies on communications equipment – from extremely rugged to civilian COTS gear. The 1U
rack-mount PL-01039 from WIN Enterprises is a security server/switch with eight GbE ports. The 2.0 GHz Dual-Core Xeon LV/ULV processors
run two Ethernet modules, one powered by the Intel 82571EB (four ports) and the other by the Intel 82573L (four ports). There’s also
a 32-bit PCI connector, Mini PCI socket, a USB 2.0 port, and an RS-232 port.
But the heart of this system is the security element. The PL-01039 can run multiple security apps, including IDS/IPS, firewall, VPN
gateway, Unified Threat Management (UTM), anti-spam, anti-virus, and several other security profiles. Available with copper, fiber, or
mixed media, the unit also has its own onboard battery and can run three hours without external power.
WIN Enterprises • www.win-ent.com

RSC# 34054
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More mobile
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it graphics realism
Pr
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Quadro professional GPU architecture is ideal for
power-constrained military boards and systems that
create intense graphics workloads. Borrowing from
the company’s recent Quadro FX 5600 and FX 4600
workstation GPUs, three new mobile chips carry over
the Shader Model 4.0 and uniform feature set. All the
devices are aimed at engineers, scientists, artists, and
other users of large datasets, models, and high-res
images.
The unified architecture is capable of dynamically

allocating compute, geometry, shading, and pixel pro-
cessing power. Shader Model 4.0 adds next-gen vertex
and pixel programmability with ultra-realistic OpenGL
and DirectX 10 effects. The NVIDIA CUDA technology
aids in solving complex visualization problems, and the
PowerMizer 7.0 technology is the company’s seventh-
generation hardware power management feature set
that brings lower power consumption and longer bat-
tery life to portable systems. It all adds up to kick-butt
realistic images and displays in defense applications.
NVIDIA Corporation • www.nvidia.com

RSC# 34055

OpenSystems
Publishing™
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30233 Jefferson Avenue Page # Advertiser/Description Page # Advertiser/Description
St. Clair Shores, MI 48082 25 ACCES I/O Products, Inc. – I/O needs 63 GE Fanuc Embedded Systems – VPX
Tel: 586-415-6500 n Fax: 586-415-4882 55 Acromag, Inc. – Customize It 5 Intel – Fully functional ultra-mobile PC
45 ACT/Technico – 6U VME VITA 31.1 2 Jacyl Technology Inc. – XG-5000k
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47 ACT/Technico – PMC, CompactPCI, and 2.16 51 MPL AG – Pentium M or Power PC
phopper@opensystems-publishing.com
49 ACT/Technico – Rugged applications 50 Phoenix International – Data storage modules
Business Manager 38 Acumen Instruments – DataBridge SDR-CR 28 Radian – We can find a solution
Karen Layman 60 Advantech Corporation – PC/104 embedded 32 RTD Embedded Technologies, Inc. –
box computers Hi Rel PC/PC1-194 modules and systems
61 Aeroflex Test Solutions – RAD-HARD processors- 40 Schroff – Depend on Birtcher
Sales Group SpaceWire Routers 19 Seagate Technology – Engineered for extremes
y
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30 Agilent Technologies – COTS solutions 15 Seagate Technology – How far could you go?
Dennis Doyle
37 Alphi Technology Corporation – PMC-1553 17 Seagate Technology – The edge of endurance is a
n
Senior Account Manager
59 Ampro Computers, Inc. – Embedded solutions lot farther than you think
ddoyle@opensystems-publishing.com
O
35 Annapolis Micro Systems, Inc. – FPGA 54 Targa Systems Division – Dual-port GbE data
t
Tom Varcie 3 Ballard Technology – BusBox transfer unit
Senior Account Manager 22 Creative Electronic Systems – Mission computers 28 TEWS Technologies LLC – PMC
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tvarcie@opensystems-publishing.com 64 CWCEC: Data communications 21 Thales Computers – PowerMP
r
11 Data Device Corp. (DDC) – Data networking 21 Thales Computers – PowerMP
Doug Cordier
P
56 Diamond Systems Corporation – Single board 27 Tri-M Systems Inc. – 100 MHz PC/104 module
Account Manager
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dcordier@opensystems-publishing.com
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Andrea Stabile 57 ELMA Electronic – VPX portable tower 46 White Electronic Designs –
g
Advertising/Marketing Coordinator 61 Excalibur Systems, Inc. – ccVME MIL PRF 38534/38535
n
astabile@opensystems-publishing.com
Christine Long
E-marketing Manager
Si
r
clong@opensystems-publishing.com
Jerry Bleich
New England
Fo
Regional Sales Managers
Space system engineering
from development to flight
Aeroflex Colorado Springs
invites you to discuss your
space programs with us. We
can assist you in technology
jbleich@opensystems-publishing.com selection, proof of concept, and
16-port
SpaceWire flight solutions. New technology
Barbara Quinlan
Midwest/Southwest Router additions to the Aeroflex
bquinlan@opensystems-publishing.com RadHard portfolio include the
LEON 3FT µProcessor and a
Ron Taylor
16-port SpaceWire Router.
East Coast/Mid Atlantic
Plan your next generation
rtaylor@opensystems-publishing.com
system today with Aeroflex
Ernest Godsey QML Q&V RadHard compo-
Central and Mountain States nents. We can do it for you.
egodsey@opensystems-publishing.com
You’re not out there alone. 800-645-8862
www.aeroflex.com/ME707
International Sales
Dan Aronovic
Account Manager – Israel
daronovic@opensystems-publishing.com
Reprints and PDFs

Nan Lamade: 800-259-0470
mesreprints@opensystems-publishing.com 32-bit LEON 3FT
with Gaisler IP

Crosshairs Editorial
The “A’s” have it

By Chris A. Ciufo
Last month, a coincidence of media events and new product Although the previous sentence is a mouthful, what this means
releases aligned (or maybe “conspired”) on my desk in such a is important for several reasons. First is that users now have a
way that they all came from companies starting with the letter way to run legacy Ada code on top of VxWorks, marrying the
“A”: Altera, Aonix, AMD. I didn’t plan it this way, folks. But old with the new. Secondly, by using the ARINC-653 API,
I might as well take advantage of this woo-woo Twilight Zone VxWorks 653 creates partitioned environments above the kernel
y
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moment. Here’s what’s new, and why you should care. into which multiple distinct and segregated environments can run.
Altera steps up mil tempo
On
In the world of big FPGAs, there’s Altera and there’s Xilinx.
This partitioned model is the core of ARINC-653 safety-critical
systems. The idea is that a failure in one module, such as an Ada
t
Using public information, I estimate that about 25 percent of DO-178B application, would have no effect on the other parti-
n
Xilinx’s $1.8 billion revenue is due to the military market, while tions and hence the overall system’s integrity is maintained.
i
only about 10 percent of Altera’s $1.29 billion revenue comes Additionally, the Aonix ObjectAda RAVEN has an ACATS 2.5
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from defense. But Altera is looking to change all that in a big Ada 95 compiler and tools that help create or recompile Ada
P
way by focusing on SWaP, SDR, VPX, mil temp, and AQEC. code in a partition; it also relies on the APEX communications
e
API for easy communication with the VxWorks 653 executive
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In a recent interview with company bigwigs, I got the G2 on this API. According to Aonix, this Ada + VxWorks + ARINC-653
g
alphabet soup. Size, Weight, and Power (SWaP) are important combo is unique in the industry. Well, except for something
n
in many applications these days, but even more so in Software- from AdaCore that doesn’t have the APEX API. (Notice the
i
Defined Radios (SDRs) that are often either deployed as hand- preponderance of “A’s” again. Coincidence? I think not.)
S
helds, or rely on limited power sources in avionics bays or
AMD adds multicore “triple threat”
r
wheeled vehicles. The company’s new Programmable Power
Technology in Stratix III devices only activates essential tran- Just as we went to press, AMD one-upped Intel by introducing
o
sistors, leaving unused gates in low power standby. Altera says the triple-core desktop Phenom x86 processor. Expected to ship
F
this saves up to 90 percent of active power in SDR waveforms in Q1 2008, the device sports three cores on the same die – a feat
such as Soldier Radio Waveform (SRW). Also, the company not to be confused with multicore CPUs having multiple dies in
surprisingly has VITA’s new 3U VPX form factor on its charts as one package. Although it’s rumored that the triple-core Phenom
a key platform for military SWaP applications. might be a quad-core Phenom with one core “disabled,” this
doesn’t detract from AMD’s achievement. (In fact, the original
Altera also maintains a secure ITAR design facility, and was 8031 MCU was just a mask-programmed 8051 with the ROM
one of the very first participants in the DoD’s AQEC IC design disabled, and today’s flash memories contain mask-enabled
flow. Now sponsored by GEIA, AQEC (GEIA-STD-0002-1A) memory arrays.)
is a voluntary IC spec, and companies promise to provide
design data to aid mil contractors in making uprating and life- AMD’s Balanced Smart Cache speeds access to memory and
cycle decisions. Finally, and perhaps most importantly, the the shared L3 cache aids in multithreaded applications such as
company designs all of its devices for industrial temp [-40 °C to HD video, games, and as-yet-unannounced software applica-
+100 °C (Tj)], and some Stratix and HardCopy devices extend to tions. Bill Mitchell, corporate VP of the Windows Ecosystem at
the MIL-STD-883 range of -55 °C to +125 °C (Tj). Altera seems Microsoft, said “Microsoft is excited to see AMD creating new
very keen on growing military beyond that 10 percent in FY07 technologies.” Well, sure. The device sports HyperTransport 3.0
(ending December 2007). with up to 16 GBps I/O transfer bandwidth, and each core can
run at a separate frequency via Cool ‘n’ Quiet 2.0 technology.
Aonix offers Ada for safety critical SYSmark 2007 and 3DMark06 benchmarks are due out soon,
You’re as surprised as I am that Ada is still out there kicking as is the quad-core version of the Phenom. We’ll keep an eye on
around. Or, maybe you’re not surprised if you’re working on this multicore race between titans.
legacy defense systems. Ada’s strong typing and rigid syntax
make it ideal for military applications where code ambiguity –
things like priority inversions or oddly defined variables – can’t
be tolerated lest lives be lost.
During September’s Embedded Systems Conference, Aonix Chris A. Ciufo

announced a version of their ObjectAda RAVEN that works with Group Editorial Director
Wind River’s VxWorks ARINC 653 for PowerPC processors. cciufo@opensystems-publishing.com

GE Fanuc
Embedded Systems
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walk the talk.
Real world, deliverable VPX from GE Fanuc Embedded Systems.
While others were talking about their commitment subsystem that leads the market in performance,
to VPX, we were walking the talk. And as a result, flexibility and ruggedness. And because it is so small
we can now offer you an impressive selection of VPX and lightweight, it’s perfect for embedded training,
products. Not words, products. Like our Intel- and simulation and mission rehearsal.
PowerPC-based single board computers, graphics
processors, switches and full VPX systems. With more To us, VPX isn’t just cool technology. It’s technology
MAGIC1
in the pipeline. that solves problems for our customers. For more 3U VPX system with leading
information about VPX and our real world products, edge graphics performance
Take, for example, the MAGIC1 Rugged Display Com- give us a call or visit our site. No one knows more
puter. Because it’s VPX-based, it is able to connect a about how VPX can solve problems for you.
2.0 GHz Intel® Core™ Duo to an NVIDIA® G73 with 16-
lane PCI Express®. The result is an integrated graphics www.gefanucembedded.com/vpx
Now a part of GE Fanuc Embedded Systems
© 2007 GE Fanuc Embedded Systems, Inc. All rights reserved.

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T O U G H H A R D WA R E E A S Y S O F T WA R E .
Software shouldn’t be hard. That’s why we back our rugged boards and subsystems CHAMP-AV6 CHAMP-FX2
with all the tools you need to easily and rapidly design, integrate and support
your deployed electronics systems. You can depend on our board support packages,
built-in test routines, diagnostic utilities, extensive software libraries and broad
operating system support to reduce design costs and get your product to market
faster. That’s hard evidence that makes Curtiss-Wright the easy choice.
VPX6-185
The CHAMP-AV6, CHAMP-FX2 and VPX6-185

are three of our latest generation of VPX/VPX-REDI
boards and include a rich set of COTS Continuum
system and support software designed to ease
integration and reduce system development time.
w w w. c w c e m b e d d e d . c o m EMPOWERED SOFTWARE...

The Defense Electronic Product Source
Sept/Oct 2007
In This Issue
Day-to-night mode
All the products you need LCDs
for Aerospace and Defense
y T
he NVIS A and NVIS B are VGA and XGA
l
You’re holding in your hands resolution TFT LCDs backlit by LED rails
the second installment of
n
that can be switched back and forth
MIL/COTS DIGEST (MCD) now between day and night mode via the company’s
O
part of Military Embedded Systems standard PRISMA II industrial controller board. Compatible with Night Vision Imaging
t
magazine. My vision for MCD is Systems (NVIS) technology, NVIS A is for upper echelon applications, while NVIS B is for
applications with less stringent requirements. The units feature updated technology that
n
to dramatically expand our cover-
i
age of new COTS products for the eliminates the cumbersome and expensive filters – large glass overlays bonded to the out-
r
side of the display – previously used. NVIS LCDs can be used in military aircraft cockpits,
Aerospace and Defense (A&D)
tanks, trucks, ground mobile applications, and communications systems. The LCDs are
P
markets. Why’s that? Because we get 8.4" diagonal, scalable up to 15" diagonal, and fully RoHS compliant.
about 100 new product announce-
e
www.apollodisplays.com Apollo Display Technologies, LLC
l
ments per day! How else can we tell
g
you about all this great new stuff?
MCD gives you a quickie “thumbnail”
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view of some of my favorite ones – 3U VPX SBC and
S
in an easy-to-scan print format. carrier board
r T
Even in an era of way-cool Web
o
pages, old-fashioned paper is still he VPX3-125 is a 3U VPX SBC
handy for perusing new product
F
featuring a single or dual core
listings, and easier to read while P.A. Semi PWRficient PA6T-1682M
leaning back in a chair or on an air- processor at 1.5 GHz. Highly suited to
plane. In this eight-page supplement, harsh environment A&D applications,
the VPX3-125 provides 512 MB/1 GB
you’ll find 28 products, ranging from
DDR2 memory @ 400 MHz, 128 MB NOR flash, 1 GB NAND flash, and 512 KB NVRAM. I/O includes
boards and systems to blades, vision one XMC/PMC site, two 10/100/1000 Ethernet ports, RS-232 and RS-422 serial channels, and two
systems, cameras, rugged box-level x4 lane PCI Express egress ports off-board. Its optional 3U VPX I/O expansion companion car-
computers, LCDs, components, and rier board, the ExpressReach, provides an XMC/PMC site supporting x8 lane PCI Express port
… well, you get the idea. A wide (VITA 42.4) with differential pair I/O routing, along with two x4 PCI Express switch ports to simplify
variety of new products awaits you. expansion.
Go ahead and start thumbing www.cwcembedded.com Curtiss-Wright

through. Something’s bound to
catch your interest.
(By the way … one of the most One-million bit
intriguing products is the nonvolatile memory
“hygienic design” industrial PC
T
from noax Technologies. Think he HXNV0100 is a one-million bit nonvola-
you can just hose it off?) tile static memory component for strategic
space electronics applications. The memory
Chris Ciufo, Editor array and control electronics are both radiation
cciufo@opensystems-publishing.com hardened, providing high reliability for low-voltage
systems operating in radiation environments. The
magnetic RAM runs from a 3.3 V power supply and
PS: In 2008, MCD will increase to offers >1e15 read/write cycles. Fabricated with Honeywell’s Silicon-On-Insulator (SOI)
quarterly as Military Embedded Complementary Metal Oxide Semiconductor (CMOS) technology and combined with mag-
Systems increases to eight issues. netic thin films, the new memory component can either replace plated wire memory or be
So, look for even more products integrated into new systems designs.
in the future. www.honeywell.com Honeywell International

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www.milcotsdigest.com on the Sept/Oct 2007 • PAGE
MARKET
3U CompactPCI
Dual-channel PMC/XMC digitizer
codec board
T
he AD491 – an 8-bit, 1 GHz PMC/
XMC digitizer featuring two
Virtex-4 FPGAs – includes two
ADC channels that provide a 30 MHz
to 1,000 MHz (1 GHz) sampling range.
Useful for connecting to a remote
server or storage system, the AD491
provides 8-bit data resolution and
onboard clock generation in steps
of 1 MHz. Memory comprises 2x 32 M
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x 16 DDR2 SDRAM (128 MB), 4x 2 M
he MPEG4CPCI is a single 3U form factor x 32 QDR2 SRAM devices (32 MB),
n
CompactPCI MPEG4 codec board that and a 128 Mb flash device. Several interfaces – PCI; PCI-X 64-bit 133 MHz, 3.3 V; PCI-X/PCI 64/32-bit
encodes up to four concurrent full-size
O
66 MHz, 3.3 V; PCI 64/32-bit 33 MHz, 3.3 V; and four-lane PCI Express – are available. Includes 4x
real-time analog inputs at a full frame rate of 2.5 Gbps optical transceivers for SFPDP, Fibre Channel, GbE, and InfiniBand applications.
t
25/30 fps from PAL or NTSC video and audio
www.4dsp.com 4DSP
n
sources. The board decodes and plays back
i
video and audio recordings from storage to
r
display, and a preview feature allows incoming
P
video to be viewed on the host screen in paral-
lel with the recording process. The MPEG4CPCI
Conduction-cooled FPGA
PMC modules
e
features a 32-bit PCI architecture and sup-
l T
ports Windows NT/2000/XP, Linux, and QNX. he PMC-CX Series comprises
g
Text and graphics annotation can be super- user-configurable Virtex-II
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imposed on any channel, and audio/video FPGA PMC modules with con-
i
synchronization is provided on each channel. duction cooling and differential
S
The device operates from 0 °C to +60 °C, and digital I/O. Accordingly, I/O includes
an extended temperature version (-40 °C to 16 bidirectional CMOS I/O lines,
r
+85 °C) is available. 24 bidirectional RS-422/485 differen-
o
www.ampltd.com tial I/O lines, and rear I/O connection.
F
The series features customizable
Advanced Micro Peripherals FPGAs with 11,500 or 24,192 logic
cells (Xilinx Virtex-II XC2V1000 or
XC2V2000), and FPGA code loads
XScale touch from PCI bus or flash memory. PMC-CX modules feature 256 K x 36-bit dual ported SRAM memory,
panel computer along with support for dual DMA channel data transfer to the CPU and both 5 V and 3.3 V signaling.
The series operates at extended temperatures of -40 °C to +85 °C.
www.acromag.com Acromag
High-availability MicroTCA server
T
he U-3000 – a NEBS Level 3/
ETSI compliant, high-avail-
ability MicroTCA commu-
nications server – provides fully
T
he TPC-120H is an Intel XScale PXA 12.1" redundant power, cooling, and
SVGA TFT touch panel computer featur- front-accessible MCHs. The 3U
ing two 10/100BASE-T Ethernet ports. rack-mount MicroTCA system
The computer’s resolution is 800 x 600, and it accommodates two-post 19" to 24"
comes complete with a Windows CE operat- racks and features dual redundant,
ing system to support thin-client solutions. hot-swap 400 W AC or -48 Vdc
I/O includes two RS-232 and one RS-232/485 power supplies with power and
serial port, two USB 1.1 ports, and one VGA cooling for up to 80 W per slot. The
port. The fanless TPC-120H provides one server features a dual-star topol-
CompactFlash expansion slot and 64 MB ogy with a fully passive MTCA.0 R1.0 backplane for 10 Gbps throughput. The U-3000’s horizontal,
SDRAM in a super slim design. flexible design enables installation of double-wide and/or single-wide AdvancedMCs: 4 double-wide
and 2 single-wide AdvancedMCs or 10 single-wide AdvancedMCs.
www.eAutomationPro.com
www.alliancesystems.com Alliance Systems
Advantech eAutomation Group

PAGE • Sept/Oct 2007 on the www.milcotsdigest.com
MARKET
Quad-core Xeon
Multi-threat security appliances
appliance
T
he FortiGate-3810A and
FortiGate-3016B are multi-
threat security appliances
for large enterprise and MSSP
applications. The appliances
are highly scalable and deliver
up to 26 Gbps of firewall per-
T
formance. Ideally suited for
he FW-8890 is a 2U, two-way, quad-
network core and data center
core Xeon rack-mount appliance for
deployments, FortiGate-3810A
y
enterprise-grade network security and
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and the FortiGate-3016B com-
management applications. Its Intel core micro-
bine Fortinet’s existing FortiASIC-CP6 content processor with its new FortiASIC-NP2 network
n
architecture increases performance headroom
processor, which enables firewall throughput of up to 26 Gbps from a single device. Additionally,
for single- and multi-threaded applications.
O
hardware-accelerated GbE interfaces are available for all FortiGate-3000 Series platforms to
An onboard Cavium Nitrox CN1010 VPN Accel-
enable wire speed firewall and near wire speed VPN performance; this ensures that time-sensitive
t
erator increases total system throughput by
applications like VoIP or IPTV do not suffer from network latency or jitter. The FortiGate-3810A
processing high-level IPsec and IKE, IPv6,
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and FortiGate-3016B also accommodate optional AdvancedMC expansion, providing hardware-
i
SSL, and wireless LAN security protocol
r
accelerated 10-gigabit XFP interfaces, gigabit SFP interfaces, and hard drive storage options.
macro commands, reducing host I/O traffic
www.fortinet.com fortineT
P
and offloading the system processor. The
FW-8890 provides up to 12 enterprise-grade
e
Intel Gigabit NICs, and Intel Virtualization
l
technology enables migration of more envi-
g
ronments including 64-bit applications and DSP motion control kit
operating systems to virtual environments.
Sn
i T
www.lannerinc.com
LANNER ELECTRONICS
he MCK2812 is a DSP motion control kit that contains
three parts: MCK2812 DSP board, PM50 power module,
and IB-2812 interface board. The MCK2812 can be used
r
for a variety of applications, including digital motor control
o
(DC brush/brushless servo motor, stepping servo motor, AC
Software radio
F
servo motor), as a Variable Frequency Control (VFC) pack-
FPGA blade ing mechanism, as a digital control machine tool, and for
electrical control. The DSP board features a DSP controller
(TMS320F2812) operating at 150 MHz with a single DC power
supply of +5 V or +24 V, along with an RS-232 serial port
and opto-isolated CAN communication interface. Memory
includes 128 K word on-chip flash program memory, 18 K
word on-chip data/program RAM memory, and 128 K word
on-board data/program RAM memory.
www.ezembedded.com EZ-EMBEDDED
T
he Xilinx FPGA Blade is a PCI soft-
ware radio FPGA blade consisting of
GE Fanuc radio PMC modules and an
Intel-based processor blade
T
FPGA PMC module mounted on a PCI carrier
card. The circuit card assembly occupies he ATCA-7140 blade is an Intel-based
one PCI bus slot, and the Xilinx FPGA module processor blade featuring two Dual-Core
includes a Virtex-II FPGA with up to 8 mil- Intel Xeon (2.13 GHz) LV processors. The
lion gates. The module also includes 128 MB blade suits any 32- or 64-bit application requir-
(64-bit wide) SDRAM, six QDR SRAM banks, ing high-performance processing and pro-
and a PCI 2.2 compliant high-performance vides SMP support. The blade also supports
bus interface. The device provides direct the PICMG 3.0 GbE base interface and PICMG
data transfer to processor via P4 user I/O and 3.1, Option 1 and 2 fabric interfaces. The ATCA-
has a 64-bit, 66 MHz PCI host interface on the 7140 has an AdvancedMC site for I/O, copro-
PMC modules. The Xilinx FPGA Blade sup- cessing, or SAS hard disk drive flexibility, and
ports Windows, Linux, and Solaris. Baseband is designed for NEBS and ETSI compliance.
processing custom coding in the Xilinx FPGA The ATCA-7140, which also provides multiple
is also supported. software packages and an operating system,
is RoHS (6 of 6) compliant.
www.motorola.com/computing Motorola Inc.
GE Fanuc Embedded Systems

MARKET
Rugged USB
Xilinx DSP platform family
interface
T
he Spartan-3A DSP is a digital signal
processing platform family featuring
the Xilinx XtremeDSP slice, which can
be interconnected in many different ways on-
chip and provides an 18-bit x 18-bit multiplier,
18-bit pre-adder, 48-bit post-adder/accumula-
tor, and cascade capabilities for various DSP
applications. The Spartan-3A DSP provides
T
up to 2,200 Gbps memory bandwidth, and the he SiliconDrive USB CF is a USB
chip’s DSP48A slices can implement wide math
y
interface in the rugged and industry-
l
functions, DSP filters, and complex arithme- standard CF (Type 1) form factor. It pro-
tic, all at low power consumption. The device
n
vides enhanced protection from host system
provides up to 53,712 logic cells, 2,268 Kb block voltage and power anomalies, preventing
O
RAM, and 373 Kb distributed RAM. Xilinx development tools including System Generator for DSP and data and drive corruption. It also incorporates
AccelDSP synthesis have been updated for the Spartan-3A DSP.
t
a more precise useable-life monitoring system
www.xilinx.com XILINX to compensate for lower-endurance storage
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i
components. The SiliconDrive USB CF incor-
r
porates a robust storage management archi-
Ultra-compact video-over-Ethernet tecture to ensure long product life; therefore,
P
it is well-suited to space-constrained embed-
camera
e
ded applications such as SBCs, edge routers,
Tl
he Nuvation IP Camera is a wearable computers, and medical devices
g
production-ready camera that demand high-performance, high-reliability
for streaming real-time, full- storage solutions. The SiliconDrive USB CF
n
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color, compressed 720 x 480 (D1 reduces host system design complexity, board
resolution) video over Ethernet at space, and susceptibility to electrical noise
S
30 frames per second. Progres- by requiring that only 4 signals be routed on
r
sive image capture is -540 HTVL the host system motherboard versus the
equivalent, and the camera has 50 required for standard CF interfaces.
o
a wide dynamic range of 102 dB www.siliconsystems.com
F
typical/120 dB max. (Video encod-
ing options include H.264, MPEG-4/ SiliconSystems
H.263, and JPEG.) The embedded
Linux-enabled camera features a TI DaVinci DM6446 Dual-Core DSP with ARM926, along with Pixim’s
ultra Wide Dynamic Range (WDR) imaging technology. The Nuvation IP Camera comes in an ultra VXS switch
low-power, compact form factor measuring (L) 3.25" (79 mm), (H) 1.7" (43 mm), and (W) 1.8" (47 mm), fabric backplane
excluding mounting bracket and lens. Interfaces include USB 2.0, analog video (NTSC/PAL), and
Ethernet (RJ-45). The device is also RoHS compliant.
www.nuvation.com Nuvation
Multifunction, single-slot VME card
T
he 64CS4 is a GbE-capable,
multifunction, single-slot VME
T
card designed to eliminate he VITA 41 VXS is a switch fabric back-
the complexity of using multiple, plane for military and aerospace appli-
independent, single-function cards. cations, enabling users to integrate a
The 64CS4 – ideal for avionics, cost-effective, high-performance upgrade to
ground mobile, and C3I applica- the latest VITA standards. The 12-slot back-
tions – accommodates up to five plane provides 10 VME64x payload slots and
independent function modules that two fabric switch slots. Other features include
may be selected from the included interswitch links, SMT passive termination, and
library. The card’s GbE interface decoupling capacitors. A passive ABG option
transfers data to and from the board is also available. The VITA 41 VXS backplane
without a VME backplane bus, enabling the board to be used as a stand-alone remote sensor inter- comes in a dual star configuration and can also
face without a separate computer board. The 64CS4 operates at -40 °C to +85 °C and 0 °C to +70 °C, be customized with multiple configurations.
and conduction cooling is available. www.gavazzi-computing.com
www.naii.com North Atlantic Industries Carlo Gavazzi CS

PAGE • Sept/Oct 2007 on the www.milcotsdigest.com
MARKET
COTS power
Vertical PCB interconnects
management
T
he HPC-Z interconnects solve thick board
drilling and wire density problems. They also
meet the need for functional isolation with the
capability of isolating high-speed channels on one
subassembly and low-speed channels on another.
HPC-Z provides interconnections within the board,
and eliminates unnecessary Plated-Thru-Holes
(PTH) drilling. The interconnections provide signal
connections only where desired, with functional
T
isolation for single- or double-side surface-mount
y
he COTS Continuum Power Manage-
l
partitions. HPC-Z eliminates PTHs that are blocking
ment features address power dissipa-
other wiring channels, which increases wireability,
n
tion issues to benefit customers who
eliminates PTH stubs, and results in a thinner, faster
want to use new technologies in legacy
O
board. HPC-Z provides a “PTH-like” connection
systems: Power Management Software
at lamination with a pad-to-pad connection made
t
API – A standardized API across product
with conductive epoxy. Since there is vertical con-
lines ensures board configuration control
n
nection with a lamination in place of a PTH, aspect
i
and system power optimization; Power
r
ratios for drill and plate are limited to subassembly
Disconnect – Users power down a module
dimensions.
P
via an external hardware mechanism, sup-
porting the fail-over concept in systems with www.eitny.com Endicott Interconnect Technologies, Inc.
e
redundant chassis-level CPUs; CPU Low
l
Power Mode – The CPU operates at lower
g
power modes under software control, pro-
viding a single variant configuration to sup- Rugged, ultra-slim laptop
n
i
port both low- or high-performance mode;
T
Peripherals Component Low Power Mode – he M230 is a rugged laptop designed for field-
S
Reduces power dissipation for component based, harsh environment applications. The
r
functions not being used by a given applica- device packs high performance into an ultra-
o
tion, via software control; and Power Surge portable, slim design that meets MIL-STD 810F and
Prevention – Enables control of system mod- IP54 standards for durability. It includes a large
F
ule power-up sequencing. 14" XGA or 15" SXGA TFT LCD high-resolution dis-
www.cwcembedded.com play, an optional ATI M54 chip for additional graph-
ics processing power, and storage up to 120 GB. The
Curtiss-Wright M230 accommodates a wide range of plug-ins and
offers an Intel Core Duo L2400 1.66 GHz processor,
2 MB L2 cache, and 512 MB DDR2 (expandable to
High-power 4 GB). Options include a sunlight readable dis-
DC-DC converter play, touch screen, waterproof membrane keyboard,
TPM 1.2 and Kensington lock security features, and a smart card reader. It also accommodates an
optional GPS receiver.
www.getac.com GETAC Inc.
RISC-based, ready-to-run computer
T
he ThinkCore IA240-241 is a RISC-based,
T
he DC500 converter is a high-power industrial ready-to-run embedded Linux
DC-DC unit that converts inputs of 18 V computer featuring a MOXA ART 32-bit
to 32 V to outputs of 28 Vdc with 90 per- ARM9 industrial communication processor.
cent efficiency. Customized output voltages Memory comprises 64 MB onboard RAM and a
are also available, and single outputs of up to 16 MB flash disk. Also provided are four RS-232/
560 W are provided as standard. Input tran- 422/485 serial ports, four-channel digital input,
sients are 50 V, and input inrush current is lim- and four-channel digital output, along with dual
ited to 50 A. DC500 converters are unaffected 10/100M Ethernet for redundant networking.
by time, temperature, and radiation, and they ThinkCore IA240-241 also offers wireless LAN
provide output short-circuit protection with expansion (802.11b/802.11g), a robust fanless
autorecovery. design, and an IP30 protection mechanism. SD socket storage expansion is supported, and the unit
www.centuryele.com can be utilized via DIN-rail or wall-mount installation. ThinkCore IA240-241 operates at -40 °C to +75 °C.
Century Electronics www.moxaUSA.com Moxa Technologies

MARKET
Industrial-grade
“Hygienic design” industrial PC
box computer
T
he S19 is a 19" stand-alone indus-
trial PC in a V2A (304) stainless
steel enclosure. The enclosure
is completely sealed in a “hygienic
design” with no external fan. The
NEMA12- and NEMA4-compliant
computer features an Intel Celeron M
@ 1.0 GHz or an Intel Pentium M @
1.4 GHz. The S19’s TFT XGA (1,280 x
T
he Matrix 520 is an industrial-grade, 1,024) 300 cd/m2 display has a resistive
y
l
Linux-ready box computer. The unit analog touch screen with protective
includes an ATMEL AT91RM9200 foil. Memory ranges from 512 MB to
n
(ARM9-core) CPU and a Linux 2.6.x prebuilt 2 GB, and I/O includes COM 1 RS-232,
O
operating system. Memory comprises 32 MB COM 2 RS-232, LPT, and 4x USB 2.0.
SDRAM and 16 MB flash, and storage is pro- The unit measures 19.6" (W) x 17.1" (H) x 5.4" (D) (498 x 435 x 136 mm) and weighs just under 50 lbs.
t
vided via an internal SD memory card slot. The S19 operates at temperatures of 32 °F to +104 °F (0 °C to +40 °C).
n
i
I/O includes two host and one client USB www.noax.com noax Technologies AG
r
2.0 ports; two 10/100 Mbps Ethernet ports;
21 pins, TTL-level GPIO; and eight 921.6 Kbps
P
baud TTY (serial) ports. A GNU C/C++
tool chain is included, and power input is Rugged SSD card
e
l
9~40 Vdc, 300 mA @ 12 V.
g A
www.artila.com dvanced Media introduces its harsh envi-
ronment RiDATA Solid State Disk (SSD)
n
Artila Electronics
i
card, geared toward the aerospace and
aviation markets. The nonvolatile flash SSD card
S
features 16 GB and 32 GB capacities. RiDATA
Embedded
r
uses NAND flash memory technology and offers
system module
o
1.8" and 2.5" module-type flash SSD for an ATA/IDE
interface and 2.5" for a SATA interface. It also sup-
F
ports up to PIO Mode-4 and up to Multiword DMA
Mode-2. The device has a flash media interface of
8- or 16-bit access and supports up to eight flash-
media devices directly and 32 devices through external decoding logic. Its ECC corrects up to three
random 12-bit symbols per 512-byte sector. RiDATA operates at 0 °C to +70 °C for commercial opera-
tion and -40 °C to +85 °C for industrial operation.
www.ritekusa.com Advanced Media (RITEK USA)
T
he EM6 SBC is an Embedded System
Module (ESM) ideal for embedded Nano-structured thermoelectric cooler
industrial and communications applica-
N
tions where high computing power is neces- extreme’s thin film Em-
sary. The single board computer is powered by bedded Thermoelectric
an Intel CoreT Duo or single core Celeron M Cooler (eTEC) addresses
processor, along with the Intel 3100 chipset. thermal management needs of
The EM6’s Altera Cyclone FPGA provides flex- the electronics, photonics, bio-
ibility, and required system I/O can be tailored tech, and defense/aerospace
for specific applications using IP cores such as industries. Functioning as a min-
IDE, graphics, additional fieldbus and legacy iature, solid-state heat pump,
interfaces, and binary I/O. Memory includes eTEC is ideal for cooling hot spots
1 GB flash and DDR2 SDRAM with ECC for that result from localized areas of
shock and vibration resistance. Front I/O com- high heat flux on an IC. The nano-
prises two GbE controllers via PCI Express and structured devices are designed
two COM interfaces via RJ-45 connectors. The to add only 100 microns of height to a heat spreader, enabling unobtrusive integration close to the
EM6 can function as a stand-alone system, heat source. The eTEC has an ultra-fast, millisecond response time for rapid cooling and heating to
with an application-specific carrier card, or be maintain an application’s precise temperature. The device pumps a maximum heat flux of 150 W/cm2
connected to additional PCI-104 modules. with some designs delivering as much as 400 W/cm2.
www.menmicro.com www.nextreme.com Nextreme
MEN Micro

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P owe r P C : S TI LL TO P S F O R DE F E N S E

The COTS Technology Authority

EMBEDDED SYSTEMS Only

VOLUME 3 NUMBER 5 Duncan Young

FPGA vs. DSP? Pr

©2007 OpenSystems Publishing. Not for distribution.

©2007 OpenSystems Publishing. Not for distribution.

ARINC 429 Mil-Std-1553

Conduction cooled box coming soon! Powerful solutions

(425) 339-0281 www.ballardtech.com

20 New design methodologies offer easier path

61 Advertiser Index RoHS world K

By Doug Patterson, Aitech Defense Systems, Inc.

E-LETTER www.mil-embedded.com/eletter Special feature: PowerPC still tops for defense

Multilevel security in tightly coupled military WEB RESOURCES

All registered brands and trademarks within Military Embedded Systems

4 / September/October 2007 Military EMBEDDED SYSTEMS

©2007 OpenSystems Publishing. Not for distribution.

Embedded Computing Knowledge Webcasts

presented by Military and Aerospace Group

RapidIO: Developments Embedded and Test & Analysis Group

ISSN: Print 1557-3222

6 / September/October 2007 Military EMBEDDED SYSTEMS

©2007 OpenSystems Publishing. Not for distribution.

©2007 OpenSystems Publishing. Not for distribution.

Small form factor

8 / September/October 2007 Military EMBEDDED SYSTEMS

©2007 OpenSystems Publishing. Not for distribution.

©2007 OpenSystems Publishing. Not for distribution.

A (life)time to achieve Headache-eliminating

Corporation, whose The helicopter – assigned to the

Semiconductor sales: Moving up in the world

©2007 OpenSystems Publishing. Not for distribution.

DDC IS YOUR DATA NETWORKING SOLUTION

Toll Free: 1-800-DDC-5757 www.ddc-web.com

FPGA coprocessing architectures

Military electronic equipment

Application Processor Only FPGA Coprocessing Speed Up

(2) Black-Scholes (Financial Application (single

(3) Prewitt Edge Detection (compute-intensive 327M Clks

©2007 OpenSystems Publishing. Not for distribution.

One such process utilizes a hardware 357

IMPLICIT+EXPLICIT. It can be used 304

power consumption and greater sensor

Another processing challenge in sensor Figure 2

©2007 OpenSystems Publishing. Not for distribution.

Accordingly, the goal of multicore

©2007 OpenSystems Publishing. Not for distribution.

As computing architectures become opti- Altera Corporation

©2007 OpenSystems Publishing. Not for distribution.

FPGA/DSP hybrid architectures:

16 / September/October 2007 Military EMBEDDED SYSTEMS

©2007 OpenSystems Publishing. Not for distribution.

ATLANTiS Interconnect Fabric

Inter-Processor Standard Multiport

©2007 OpenSystems Publishing. Not for distribution.

Output Output Output Output Output Output Output Output

128 128 128 128 128 128 128 128

128 128 128 128 128 128 128 128

Input Input Input Input Input Input Input Input

18 / September/October 2007 Military EMBEDDED SYSTEMS

©2007 OpenSystems Publishing. Not for distribution.

©2007 OpenSystems Publishing. Not for distribution.

(2) Black-Scholes (Financial Application (single

(3) Prewitt Edge Detection (compute-intensive 327M Clks