EXPERIMENT 8

Aim: To design a full adder using structural modelling by using VHDL.

Write a suitable test bench to verify suitable function.

Code for Full adder :

Library ieee ;
Use ieee.std_logic_1164.ALL;
entity fastructuralbeh is
port (
A : IN std_logic;
B : IN std_logic;
Ci : IN std_logic;
S : OUT std_logic;
Co : OUT std_logic );
end fastructuralbeh;
architecture behaviour of fastructuralbeh is
component OR_BERLIN
port (
B0 : IN std_logic;
B1 : IN std_logic;
C0 : OUT std_logic );
end component ;
component halfticket
port (
A : IN std_logic;
B : IN std_logic;
S : OUT std_logic;
C : OUT std_logic );
end component ;
signal s1, s2, s3 : std_logic;
begin
half1 : halfticket port map (A=>A,B=>B,S=>S1,C=>S2);
half1 : halfticket port map (A=>S1,B=>C,S=>S,C=>S3);
or3 : OR_BERLIN port map(B0=>S2,B1=>S3,C0=>c0)
end Behavioral;
Output :
Test bench code for Full adder :
Library ieee ;
Use ieee.std_logic_1164.ALL;
entity fulladdr_test IS
END fulladdr_test ;
ARCHITECTURE behaviour OF fulladdr_test IS
COMPONENT claire
PORT (
A : IN std_logic;
B : IN std_logic;
Ci : IN std_logic;
S : OUT std_logic;
Co : OUT std_logic );
END COMPONENT ;

-- Inputs
signal A : std_logic : = ‘0’ ;
signal B : std_logic : = ‘0’ ;
signal Ci : std_logic : = ‘0’ ;
--Outputs
signal S : std_logic ;
signal Co : std_logic;
BEGIN
uut : claire PORT MAP (
A => A ,
B => B ,
Ci => Ci,
S => S,
Co => Co
);
--Stimulus process
stim_proc : process
begin
wait for 100 ns ;
A <= ’0’ ;
B <= ‘0’ ;
Ci <= ‘0’ ;
wait for 100 ns ;
A <= ’0’ ;
B <= ‘0’ ;
Ci <= ‘1’ ;
wait for 100 ns ;
A <= ’0’ ;
B <= ‘1’ ;
C <= ‘0’ ;

wait for 100 ns ;

A <= ’0’ ;
B <= ‘1’ ;
Ci <= ‘1’ ;
wait for 100 ns ;
A <= ’1’ ;
B <= ‘0’ ;
Ci <= ‘0’ ;
wait for 100 ns ;
A <= ’1’ ;
B <= ‘0’ ;
Ci <= ‘1’ ;
wait for 100 ns ;
A <= ’1’ ;
B <= ‘1’ ;
Ci <= ‘0’ ;
wait for 100 ns ;
A <= ’1’ ;
B <= ‘1’ ;
Ci <= ‘1’ ;
wait ;
end process ;
END ;
Output :
Aim:To design a 4x1 mux using structural modelling by using VHDL .
Write a suitable test bench to verify suitable function.

Code for 4x1 mux :

Library ieee ;
Use ieee.std_logic_1164.ALL;
entity muxfouronestructural is
port (
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : OUT std_logic;
O : OUT std_logic ;
S0 : in std_logic;
S1 : in std_logic; );
end muxfouronestructural;
architecture behaviour of muxfouronestructural is
component twoone2
port (
A : IN std_logic;
B : IN std_logic;
S : IN std_logic;
OU : OUT std_logic );
end component ;
signal l1 l2 : std_logic;
begin
comp1 : twoone2 port map (A=>A,B=>C,S=>S0,OU=>L1);
comp2 : twoone2 port map (A=>A,B=>D,S=>S0,OU=>L2);
comp1 : twoone2 port map (A=>L1,B=L2,S=>S1,OU=O);
end Behavioral;
Output:
Test bench code for 4x1 Mux :
Library ieee ;
Use ieee.std_logic_1164.ALL;
entity fouronetest IS
END fouronetest ;
ARCHITECTURE behaviour OF fouronetest IS
COMPONENT mux1
PORT (
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
OU : OUT std_logic );
END COMPONENT ;

-- Inputs
signal A : std_logic : = ‘0’ ;
signal B : std_logic : = ‘0’ ;
signal C : std_logic : = ‘0’ ;
signal D : std_logic : = ‘0’ ;
signal S0 : std_logic : = ‘0’ ;
signal S1 : std_logic : = ‘0’ ;
--Outputs
signal OU : std_logic;
BEGIN
uut : claire PORT MAP (
A => A ,
B => B ,
C => C,
D => D,
SO => SO,
S1 => S1,
OU => OU
);
--Stimulus process
stim_proc : process
begin
A <= ’0’ ;
B <= ‘0’ ;
C <= ‘1’ ;
D <=’1’;
S0 <=’0’;
S1 <= ‘0’;
wait for 100 ns ;
S0 <= ’0’ ;
S1 <= ‘0’ ;
wait for 100 ns ;
SO <= ’0’ ;
S1 <= ‘1’ ;
wait for 100 ns ;
SO <= ’0’ ;
S1 <= ‘1’ ;
wait for 100 ns ;
SO <= ’1’ ;
S1 <= ‘1’ ;
end process ;
END;
Output :
Aim: To design a ripple carry adder using structural modelling by using VHDL .
Write a suitable test bench to verify suitable function.
Code for Ripple carry adder :
Library ieee ;
Use ieee.std_logic_1164.ALL;
entityripplecarryadder is
port (
a: IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
e : IN std_logic;
f : IN std_logic;
g : IN std_logic;
h : IN std_logic;
sum1 : OUT std_logic;
sum2 : OUT std_logic;
sum3 : OUT std_logic;
sum4 : OUT std_logic;
coutf : OUT std_logic );
endripplecarryadder ;
architecture behaviour of ripplecarryadder is
componentfull_adder
port (
a : IN std_logic;
b : IN std_logic;
cin:INstd_logic;
sum:OUTstd_logic
cout : OUT std_logic );
end component ;
componenthalf_adder
port (
a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic;
Cout : OUT std_logic);
end component ;
signal s1, s2, s3 : std_logic;
begin
block1 :half_adder port map (a=>a,b=>b,sum=>sum1,cout=>s1);
block2 :full_adder port map(a=>c,b=>d,cin=>s1,sum=>sum2,cout=>s2);
block3 :full_adder port map(a=>e,b=>f,cin=>s2,sum=>sum3,cout=>s3);
block4:full_adderportmap(a=>g,b=>h,cin=>s3,sum=>sum4,cout=>coutf);
endBehavioral;
Output :
Test bench code for Rippe carry adder :
Library ieee ;
Use ieee.std_logic_1164.ALL;
entityripplecarry_test IS
END ripplecarry_test ;
ARCHITECTURE behaviour OF ripplecarry_test IS
COMPONENT ripplecarryadder
PORT (
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
e : IN std_logic;
f : IN std_logic;
g : IN std_logic;
h :IN std_logic;
sum1 : OUT std_logic;
sum2 : OUT std_logic;
sum3 : OUT std_logic;
sum4 : OUT std_logic;
Coutf : OUT std_logic );
END COMPONENT ;

-- Inputs
signal a : std_logic : = ‘0’ ;
signal b : std_logic : = ‘0’;
signal c : std_logic : = ‘0’ ;
signal d : std_logic : = ‘0’ ;
signal e : std_logic : = ‘0’ ;
signal f : std_logic : = ‘0’ ;
signal g : std_logic : = ‘0’ ;
signal h : std_logic : = ‘0’ ;

--Outputs
signal Sum1 : std_logic ;
signal Sum2 : std_logic ;
signal Sum3 : std_logic ;
signal Sum4 : std_logic ;
signalcoutf : std_logic ;
BEGIN
uut :ripplecarryadderPORT MAP (
a=>a,
b=>b,
c=>c,
d=>d,
e=>e,
f=>f,
g=>g,
h=>h,
sum1=>sum1,
sum2=>sum2,
sum3=>sum3,
sum4=>sum4,
coutf=>coutf ) ;
--Stimulus process
stim_proc : process
begin
wait for 100 ns ;
a<=0,
b<=0,
c<=0,
d<=1,
e<=1,
f<=0,
g<=1,
h<=0,
wait for 100 ns ;
a<=1,
b<=1,
c<=1,
d<=1,
e<=1,
f<=1,
g<=1,
h<=1,
wait ;
end process ;
END ;
Output :

Conclusion: