Master-slave D flip-flop

• When clock=1, the master tracks the values of the D

input signal and the slave does not change
– Thus Qm follows any changes in D and Qs remains constant
• When the clock signal changes to 0, the master
ECE380 Digital Logic stage stops following the changes in the D input
signal
• At the same time, the slave stage responds to the
value of Qm and changes states accordingly
Flip-Flops, Registers and
• Since Qm does not change when clock=0, the slave
Counters: stage undergoes at most one change of state during
Flip-Flops a clock cycle
• From an output point of view, the circuit changes Qs
(its output) at the negative edge of the clock signal

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-1 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-4

Flip-flops Master-slave D flip-flop

• The gated latch circuits presented are level
Clock
sensitive and can change states more than
once during the ‘active’ period of the clock D
signal
Qm
• Circuits (storage elements) that can change
their state no more than once during a clock Q = Qs
period are also useful
• Two types of circuits with such behavior D Q
– Master-slave flip-flip
clock Q
– Edge-triggered flip-flop

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-2 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-5

Master-slave D flip-flop Edge-triggered flip-flop

• Consists of 2 gated D latches • A circuit, similar in functionality to the master-slave
– The first, master, changes its state while clock=1 D flip-flop, can be constructed with 6 NAND gates
– The second, slave, changes its state while 1 P3
clock=0

Master Slave P1
2
Q Qs 5 Q
m D Q
D D Q D Q Q
Clock
P2 clock Q
Clk Q Clk Q 6 Q
Clock Q 3
Positive-edge-triggered
D type flip-flop

38 transistors D 4 P4 24 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-3 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-6

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 Edge-triggered flip-flop T flip-flop
• The previous circuit responds on the positive • Another flip-flop type, the T flip-flop, can be
derived from the basic D flip-flop presented
edge of the clock signal
• Feedback connections make the input signal D equal
• A negative-edge triggered D flip-flop can be to the value of Q or Q’ under control of a signal
constructed by replacing the NAND with NOR labeled T
gates

D Q D Q
D Q Q
clock Q clock Q T
Q Q
Positive-edge-triggered Negative-edge-triggered
D type flip-flop D type flip-flop Clock

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-7 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-10

Comparing D storage elements T flip-flop

D
• The name T derives from the behavior of the
D Q Qa
circuit, which ‘toggles’ its state when T=1
clock – This feature makes the T flip-flop a useful element
clk Q
clock when constructing counter circuits
D Q Qb D
T Q(t+1) Clock
Qa
Q 0 Q(t) T
Q 1 Q’(t)
b Q
D Q Qc
Q
c
T Q
Q
clock Q
Positive edge triggered
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-8 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-11

Clear and preset inputs JK flip-flop

• It may be desirable to specifically set (Q=1) • The JK flip-flop can also be derived from
or clear (Q=0) a flip-flop the basic D flip-flop such that
• Practical flip-flops often have preset and D=JQ’+K’Q
clear inputs • The JK flip-flop combines aspects of the SR
– Generally, these inputs are asynchronous (they and the T flip-flop
do not depend on the clock signal) – It behaves as the SR flip-flop (where J=S and
Preset’ K=R) for all values except J=K=1
D Q As long as Preset’=0, Q=1 – For J=K=1, it toggles like the T flip-flop

clock Q As long as Clear’=0, Q=0

Clear’

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-9 Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-12

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 JK flip-flop

J
D Q Q
K Q Q

Clock

J K Q(t+1)
0 0 Q(t)
J Q
0 1 0 clock
1 0 1 K Q
1 1 Q’(t) Positive edge triggered
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-13

JK flip-flop timing diagram

Complete the following timing diagram
1
Clk
0
1
K
0
1
J
0
1
Q
0
1
Q
0
Time
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-14

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