Rca Cmos Databook

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RCA CMOS Integrated Circuits
Table of Contents
This DATABOOK contains complete technical in- General Guide to CMOS Integrated Circuits •
formation on RCA standard commercial CMOS
integrated circuits. It covers the full line of RCA
standard A- and B-series digital logic circuits, and General Operating and Application . .
special-function circuits (telecommunications and .Conslderatlons . . . .
special interface and display·driver circuits).
The DATABOOK is divided into eight major sections.
The first section includes a complete index of types, CMOS High-Voltage 8-Series Integrated . .
classification and selection charts, functional dia-
grams, and photographs of available package op-
Circuits-Technical Data . . : .
tions. This section is followed by a discussion of
general considerations that should be taken into
account in the operation and application of CMOS CMOS A-Series Integrated Circuits-
integrated circuits. Technical Data
Three separate data sections provide definitive
ratings and characteristics for (1) high-voltage B-
series types, (2) A-series types, (3) special-function
types.
Data pages for individual devices are included as
CMOS Telecommunications, Display-Oriver, ~
and Interface Circuits-Technical Data -=-
nearly as possible in alphanumerical sequence of
type numbers. Because some devices are grouped
together to show similarity of function or data, CMOS High-Reliability Integrated Circults _ _
individual type numbers may be out of sequence. If
--
you don't find the type number you're looking for
where you expect it to be, check the Index to
Devices.
Dimensional Outlines
Next, a high-reliability CMOS IC's section describes
the extensive line of RCA high-reliability integrated
circuits that are processed and screened in accord-
ance with military, RCA, or special custom speci-
fications to meet the needs of modern military,
aerospace, and critical industrial and scientific
Application Notes III
applications.
The DATABOOK also includes Dimensional Out- RCA Sales Offices, Authorized Distributors, r..
lines, Application Notes, and RCA Sales Offices, and Manufacturers' Representatives . : .
Manufacturers' Representatives, and Authorized
Distributors.
nCI" Solid I
, . . State
Somerville, NJ '. Brussels • Paris • London
Hamburg. Sao Paulo. Hong Kong
Information furnished by RCA is believed to be accurate and
reliable. However, no responsibility is assumed by RCA for its use;
nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication
or otherwise under any patent or patent rights of RCA.
The device data shown for some types are indicated as preliminary
or objective. Preliminary data are intended for guidance purposes
in evaluating devices for equipment design. Such data are shown
for types currently being designed for inclusion in our standard
line of commercially available products. Objective data are
intended for engineering evaluation of types in the initial stages of
design. The type designations and data are subject to change,
unless otherwise arrilnged. No obligations are assumed for notice
of change or future manufacture of these devices. For current
information on the status of preliminary or objective programs,
please contact your local RCA sales office.
Copyright 1983 by RCA Corporation

(All rights reserved under Pan-American Copyright Convention)
Trademark(s) ® Registered
Marca(s) Registrada(s)
Printed in USA 8-83
2
General Guide to CMOS
Integrated Circuits
Page
Index to Devices ................................................. 4
Index to Application Notes. .. .. .. . . .. .. .. .. .. . . . . . . .. .. . . . . . . .. ... 5
Product Classification Chart . . . .. .. .. . . . . .. .. . . .. . . .. . . . . .. .. . . ... 6
Function Selection Chart ..................................•...... 7
Package and Ordering Information ............................... 14
Functional Diagrams ..................................... ; •......15
Industry-to-RCA Type Cross-Reference Guide ..•................. 31
3
Index to Devices
This index does not include package
designation suffix letters for individual
type numbers; the various packages avail-
able are shown in the data section.
Data Data Data Data

Bulletin Bulletin Bulletin Bulletin
Type No. Page FileNo. Type No. Page File No. Type No. Page FileNo. Type No. Page File No.
CA3300 620 1316 CD4023UB 86 947 CD4050B 202 926 CD4527B 333 1006
CA3308 631 1352 CD4024A 525 930 CD4051B 206 902 CD4532B 338 876
CA3308A 631 1352 CD4024B 122 1063 CD4052B 206 902 CD4536B 342 1186
CD4000A 478 944 CD4025A 478 944 CD4053B 206 902 CD4538B 350 1245
CD4000B 58 985 CD4025B 58 985 CD4054B 213 634 CD4541B 356 1378
CD4000UB 62 945 CD4025UB 62 945 CD4055B 213 634 CD4543B 360 1327
CD4001A 478 944 CD4026A 528 918 CD4056B 213 634 CD4555B 366 858
CD4001B 58 985 CD4026B 126 1118 CD4057A 593 635 CD4556B 366 858
CD4001UB 62 945 CD4027A 532 941 CD4059A 601 898 CD4585B 371 1146
CD4002A 478 944 CD4027B 132 942 CD4060A 609 813 CD4724B 375 1111
CD4002B 58 985 CD4028A 535 937 CD4060B 218 1120 CD22100 636 1076
CD4002UB 62 945 CD4028B 136 1016 CD4062A 612 816 CD22101 641 1039
CD4006A 481 920 CD4029A 538 931 CD4063B 222 805 CD22102 641 1039
CD4006B 66 1033 CD4029B 140 1028 CD4066A 616 769 CD221 03 649 1310
CD4007A 484 921 CD4030A 541 932 CD4066B 226 1114 CD22104 656 1259
CD4007UB 70 977 CD4030B 146 1055 CD4067B 231 909 CD22104A 656 1259
CD4008A 487 950 CD4031A 543 569 CD4068B 237 809 CD22105 661 1258
CD4008B 74 951 CD4031B 149 1073 CD4069UB 240 804 CD22105A 661 1258
CD4009A 489 939 CD4032A 546 915 CD4070B 243 910 CD22301 666 1368
CD4009UB 78 940 CD4032B 154 1081 CD4071B 246 807 CD22401 670 1388
CD4010A 489 939 CD4033A 528 918 CD4072B 246 807 CD22413 676 1279
CD4010B 78 940 CD4033B 126 1118 CD4073B 250 806 CD22414 676 1279
CD4011A 492 946 CD4034A 549 575 CD4075B 246 807 CD22859 683 1257
CD4011B 82 986 CD4034B 158 1062 CD4076B 254 903 CD40100B 379 980
CD4011UB 86 947 CD4035A 553 568 CD4077B 243 910 CD40101B 384 1000
CD4012A 492 946 CD4035B 164 1101 CD4078B 258 810 CD40102B 387 984
CD4012B 82 986 CD4037A 556 576 CD4081B 250 806 CD40103B 387 984
CD4012UB 86 947 CD4038A 546 915 CD4082B 250 806 CD40104B 394 1220
CD4013A 495 935 CD4038B 154 1081 CD4085B 261 811 CD40105B 401 1044
CD4013B 90 936 CD4040A 558 624 CD4086B 265 812 CD40106B 406 1017
CD4014A 498 922 CD4040B 122 1063 CD4089B 269 1003 CD40107B 410 1015
CD4014B 94 1043 CD4041A 561 572 CD4093B 274 836 CD40106B 413 1011
CD4015A 500 943 CD4041UB 169 934 CD4094B 278 869 CD40109B 418 1018
CD4015B 99 1024 CD4042A 565 589 CD4095B 282 879 CD40110B 422 1125
CD4016A 503 952 CD4042B 172 954 CD4096B 282 879 CD40115 687 1075
CD4016B 103 953 CD4043A 568 590 CD4097B 231 909 CD40116 689 1234
CD4017A 507 927 CD4043B 176 956 CD4098B 286 979 CD40117B 431 1333
CD4017B 108 1113 CD4044A 568 590 CD4099B 291 948 CD40147B 435 1117
CD4018A 511 929 CD4044B 176 956 CD4502B 295 1002 CD40160B 438 1047
CD4018B 113 1034 CD4045A 571 614 CD4503B 298 1224 CD40161B 438 1047
CD4019A 514 923 CD4045B 180 1119 CD4508B 301 1009 CD40162B 438 1047
CD4019B 118 1045 CD4046A 574 637 CD4510B 305 899 CD40163B 438 1047
CD4020A 516 928 CD4046B 184 1099 CD4511B 311 901 CD40174B 445 1031
CD4020B 122 1063 CD4047A 579 623 CD4512B 316 1032 CD40175B 449 1326
CD4021A 519 933 CD4047B 190 1123 CD4514B 319 814 CD40181B 455 989
CD4021B 94 1043 CD4048A 585 636 CD4515B 319 814 CD40182B 460 1008
CD4022A 522 919 CD4048B 197 1124 CD4516B 305 899 CD40192B 464 993
CD4022B 108 1113 CD4049A 590 599 CD4517B 323 1148 CD40193B 464 993
CD4023A 492 946 CD4049UB 202 926 CD4518B 328 808 CD40194B 394 1220
CD4023B 82 986 CD4050A 590 599 CD4520B 328 808 CD40208B 469 1007
CD40257B 474 982
4
Index to Application Notes
Number Title Page

ICAN-6080 •..... "Digital-to-Analog Conversion Using the RCA-CD4007A COS/MOS IC" (Abstract) ..............• 786
ICAN-6086 ...... "Timekeeping Advances Through COS/MOS Technology" ....•....•............................ 708
ICAN-6101 ...... "The RCA COS/MOS Phase-Locked Loop-A Versatile Building Block for Micro-Power Digital and
Analog Applications" ........................................................................ . 714
ICAN-6166 ...... "COS/MOS MSI Counter and Register Design and Applications" (Abstract) ..................... . 786
ICAN-6176 ...•.. "Noise Immunity of COS/MOS Integrated-Circuit Logic Gates" (Abstract) .........•.........•...• 786
ICAN-6210 ...... "A Typical Data-Gathering and Processing System Using CD4000A-Serles COS/MOS Paris"
(Abstract) ............................................................•..•...•................
ICAN-6230 ...... "Using the CD4047A In COS/MOS Timing Applications" ...................................... ..
ICAN-6289 ...... "A COS/MOS PCM Telemetry and Remote Data Acquisition Design" (Abstract) ................. .
786
718
786
I
ICAN-6315 ...... "COS/MOS Interfacing Simplified" ............••••.....•...................................... 725
ICAN-6346 ...... "Applications of the RCA-CD4093B COS/MOS Schmitt Trigger" •.....•..•.................•..... 728
ICAN-6362 ...... "Using the CD4520B to Design Dividers with Symmetrical Outputs" (Abstract) •.•....•........... 786
ICAN-6374 .•.... "The COS/MOS CD4059A Programmable Dlvlde-by-N Counter In FM and Cltlzens-Band-
Transceiver Tuners" (Abstract) ............................................................... . 786
ICAN-6466 ...... "Astable and Monostable Oscillators Using RCA COS/MOS Digital Integrated Circuits" .......... . 731
ICAN-6498 ..•... "Design of Fixed and Programmable Counters Using the RCA-CD4018A COS/MOS Presellable
Dlvlde-by-N Counter" (Abstract) ............................................................. . 786
ICAN-6525 ...... "Guide to Beller Handling and Operation of CMOS Integrated Circuits" ......................... . 737
ICAN-6532 ...... "Fundamentals of Testing COS/MOS Integrated Circuits" ...................................... . 740
ICAN-6552 ...... "A Basic Selection Guide to Digital Counters" ................................................ .. 749
ICAN-6558 ...... "Understanding Buffered and Unbuffered CMOS Characteristics" ...........................•... 752
ICAN-6563 ...... "Radiation Resistance of the COS/MOS CD4000A and CD4000B Series" ..•...................... 757
ICAN-6564 ...... "Application of CD40107BE COS/MOS Dual NAND Buffer" .........................•........... 759
ICAN-6572 ...... "COS/MOS Electrostatic-Discharge Protection Networks" ..................................... . 762
ICAN-6576 ...... "Power-Supply Considerations for COS/MOS Devices" ........................................ . 764
iCAN-6587 ...... "Noise Immunity of COS/MOS B-Serles Integrated Circuits" ................................... . 767
ICAN-6595 ...... "Interfacing Analog and Digital Displays with CMOS Integrated Circuits" ....................... . 775
ICAN-6600 ...... "Arithmetic Arrays Using Standard COS/MOS Building Blocks" (Abstract) ...................... . 786
ICAN-6601 ...... "Transmission and Multiplexing of Analog or Digital Signals Utilizing the CD4016A Quad Bilateral
Switch" (Abstract) .................................................... : ...................... . 786
ICAN-6602 ...... "Interfacing COS/MOS with Other Logic Families" (Abstract) ...............................•... 786
ICAN-6716 ...... "Low-Power Digital Frequency Synthesizers Utilizing COS/MOS IC's" (Abstract) ................ . 786
ICAN-6733 ...... "Ballery-Powered Digital-Display Clock/Timer and Metering Applications Utilizing the
. RCA-CD4026A and CD4033A Decade Counteril-7-Segment Output types" (Abstract) ......•.... 786
ICAN-6739 ...... "COS/MOS Rate Multipliers-Versatile Circuits for Synthesizing Digital Functions" (Abstract) .... . 786
ICAN-6883 ...... "Simplified Design of Astable RC OSCillators Using the CD4060B or two CMOS Inverlers" ........ . 781
ICAN-6948 ...... "Parallel Clocking of Sequential CMOS Devices" ........•.•.•.................................. 782
ICAN-7037 ...... "Logarithmic Units of Measure In Telecommunications" ....................................... . 783
5
Product Classification Chart
GATES MULTIVIBRATORS
Single-Level Multi-Level Flip-Flops/Latches
Buffers & Multi- Decoders/ Schmitt
NOR/NAND OR/AND Inverters function/AOI Encoders Trigger
CD4000B CD4012B CD4071B CD4007UB CD4019B CD40288 CD4093B CD4013B CD4096B
CD4000UB CD4012UB CD4072B CD4007A CD4019A CD4028A CD40106B CD4013A CD4099B""
CD4000A CD4012A CD4073B CD4009UB CD4030B .: CD4514B CD4027B CD4508B
CD4001B CD4023B CD4075B CD4009A CD4030A • CD4515B CD4027A CD4724B""
CD4001UB CD4023UB CD4081B CD4010B CD4037A CD4532B CD4042B CD40174B
CD4001A CD4023A CD40B2B CD4010A CD404BB CD4555B" CD4042A CD4017SB
CD4002B CD4025B CD4041UB CD404BA CD4556B" CD4043B Astable/
CD4002UB CD4025UB CD4041A CD4070B. CD40147B CD4043A. Mono-
CD4002A CD4025A CD4049UB CD4077B. CD4044B stable
CD4011B CD406BB CD4049A CD40B5B CD4044A CD4047B
CD4011UB CD407BB CD4050B CD40B6B CD4076B"" CD4047A
CD4011A CD40107B CD4050A CD4095B
CD4069ltB
.... See Mono-
CD4502B .See "See
Demultiplexers Storage stable
CD4503B Comparators
CD40107B ,Registers CD409BB
CD453BB
MUL TIPLEXERS/ PHASE- QUAD INTER-

REGISTERS COUNTERS
DEMULTIPLEXERS LOCKED BILATERAL FACE
LOOP SWITCHES CIRCUITS
FIFO Binary Analog/Digital
Shift Storage Buffer Ripple Synchronous Data Selectors
CD4006B CD4076Bt CD40105B CD4020B CD4017B CD4016B 6. CD4046B CD4016B+ CD4009UB

CD4006A CD4099B CD4020A CD4017A CD4016A 6. CD4046A CD4016A+ CD4009A
CD4014B CD4724B CD4024B CD401BB CD4019B CD4066B+ CD4010B
CD4014A CD40108Be CD4024A CD4018A CD4019A CD4066A+ CD4010A
CD4015B CD40174B CD4040B CD4022B CD4051B CD4049UB
CD4015A CD40175B CD4040A CD4022A CD4052B CD4049A
CD4021B CD4020BB. CD4060B CD4029B CD4053B CD4050B
CD4021A CD4060A CD4029A CD4066B 6. CD4050A
CD4031B CD4059A CD4066A 6. ' CD4054B
CD4031A' CD4510B CD4067B CD40107B
CD4034B· TIMERS CD4516B CD4097B CD40109B
CD4034A CD4518B CD4512B CD4011SV
CD4035B CD4520B CD4555Be CD40116V
CD4045B
CD4035A CD40102B CD4556B$ CD40117B V
tSee CD4045A
CD4062A CD40103B CD40257B
CD4094B
Flip/Flops CD4536B
CD4541B CD40160B I AID Converter!
CD4517B CD40161B CA3300 v
CD40100B .See CD40162B 6.See eSee +See CA3308v
CD40104B Multlport CD40163B Quad Decoders/ Multiplexers
CD40194B Register CD40192B Bilateral Encoders
CD40193B Switch
ARITHMETIC CIRCUITS DISPLAY DRIVERS TELECOMMUNICATION

CIRCUITS
Parity For For
Adders/ ALU/Rate Generator/ Multiport LCD· LEDee Crosspoint Tone
Comparators Multipliers Checker Register With Counter Drive Drive Switches Generator
CD4008B CD4057A CD40101B CD40108B" CD4026B CD4054B CD4511B CD22100 V CD22859 V
CD4008A CD4089B CD40208B" CD4026A CD4055B CD22101 V
CD4030B CD4527B CD4034.· CD4033B CD4056B CD22102 V Timer/Driver
CD4030A CD40181B CD40:MA· CD4033A CD4543B
PCM Line CD22401 v
CD4032B CD40182B CD40110B CD221 04 V Repeater
CD4032A CD22.104AV PCM Data
CD403BB CD22105 V CD22301 v Filters
CD4038A CD22105AV
HDB3 CD22413V
CD4063B
Transcoder CD22414 v
CD4070B+ + See ·See "Liquid •• Llghl
CD4077B+ Multllunc- Storage Cryslal Emitting CD22103 v
CD4585B tlon/AOI Register Display Diode
V Indicates types designed for special applications. Ratings and characteristics data for these types differ in some aspects from
the standardized data for A- and B-series types. Refer to data pages on these types for specific differences.
6
Function Selection Chart
Function
I Type No.
I
No. of
Pins Function I Type No.
I
No. of
Pins
Gates Gates (cont'd)

NOR/NAND Multlfunctlon/AOt (cont'd)
Dual 4-input NOR CD4002B 14 Quad AND/OR Setect CD4019B 16
CD4002UB 14 CD4019A 16
Dual 2-wide, 2-input AND/OR
Dual 4-input NAND
CD4002A
CD4012B
CD4012UB
CD4012A
14
14
14
14
invert (AOI)
Expandable 4-wide, 2-input
AND/OR invert (AOI)
CD4085B
CD4086B
14
14
I
Triple 3-input NOR CD4025B 14 Multifunctional expandable 8-input
CD4025UB 14 (3-state output) CD4048B 16
CD4025A 14 CD4048A 16
Triple 3-input NAND CD4023B 14 Decoders/Encoders
CD4023UB 14 BCD-to-decimal decoder CD4028B 16
CD4023A 14 CD4028A 16
Quad 2-input NOR CD4001B 14 8-input priority encoder CD4532B 16
CD4001UB 14 10-line to 4-line
CD4001A 14 BCD priority encoder CD40147B 16
Quad-2 input NAND CD4011B 14 4-bit latch / 4-to-16 line decoder
CQ4011UB 14 (outputs high) CD4514B 24
CD4011A 14 4-bit latch /4-to-16 line decoder
8-input NOR/OR CD4078B 14 (outputs low) CD4515B 24
8-input NAND/AND CD4068B 14 Dual l-of-4 decoder/demultiplexer
Dual 3-input NOR plus inverter CD4000B 14 (outputs high) CD4555B 16
CD4000UB 14 Dual l-of-4 decoder/demultiplexer
CD4000A 14 (outputs low) CD4556B 16
Dual 2-input .NAND buffer/driver CD49107B 8,14 Schmitt Trigger
OR/AND Quad 2-input NAND CD4093B 14
Dual 4-input OR CD4072B 14 Hex CD40106B 14
Dual 4-input AND CD4082B 14 Interface
Triple 3-input OR CD4075B 14
Triple 3-input AND CD4073B 14 Quad low-to-high voltage CD40109B 16
Quad 2-input OR CD4071B 14 Hex high-to-Iow voltage (inverting) CD4009UB 16
Quad 2-input AND CD4081B 14 CD4009A 16
CD4049UB 16
Buffers and Inverters CD4049A 16
Dual complementary pair plus Hex high-to-Iow voltage (non- CD4010B 16
inverter CD4007UB 14 inverting) CD4010A 16
CD4007A 14 CD4050B 16
Hex inverter CD4069UB 14 CD4050A 16
Hex inverter/buffer (3-state) CD4502B 16 Dual 2-input NAND buffer/driver CD40107B 8,14
Hex buffer (3-state non-inverting) CD4503B 16 8-bit bidirectional CMOS-to-TTL
Hex buffer/converter (inverting) CD4009UB 16 level converter CD40115 V 22
CD4009A 16 8-bit bidirectional CMOS-to-TTL
Hex buffer / converter (inverting) CD4049UB 16 level converter CD40116 V 22
CD4049A 16
Programmable dual
Hex buffer / converter (non-inverting) CD4010B 16
4-bit terminator CD40117B V 14
CD4010A 16
Hex buffer/converter (non-inverting) CD4050B 16 AID Converters
CD4050A 16 Video-speed 6-bit
Quad true/complement buffer CD4041UB 14 flash A/D converter CA3300 18
CD4041A 14 Video-speed 8-bit
Dual 2-input NAND buffer/driver CD40107B 8,14 flash AID converter CA3308 24
Multifunction/AOI
Triple AND-OR bi-phase pairs CD4037A 14
Multlvibrators
Quad exclusive-OR CD4030B 14 Monostable/astable CD4047B 14
CD4030A 14 CD4047A 14
Quad exclusive-OR CD4070B 14 Dual monostable CD4098B 16
Quad exclusive-NOR CD4077B 14 Dual precision monostable CD4538B 16
V Indicates types designed for special applications, Ratings and characteristics data for these types differ in some aspects from
the standardized data for A- and B-series types, Refer to data pages on these types for specific differences.
7
I No. of
I No. of
Function
Multivibrators (cont'd)
I Type No. Pins
Counters
Function Type No. Pins
Flip-Flops Binary Ripple

Dual "0" with set/reset capability CD4013B 14 7-stage CD4024B 14
CD4013A 14 CD4024A 14
Dual "J-K" with set/reset capability CD4027B 16 12-stage CD4040B 16
CD4027A 16 CD4040A 16
Gated "J-K" (non-inverting) CD4095B 14 14-stage CD4020B 16
Gated "J-K" (inverting and non- CD4020A 16
inverting) CD4096B 14
Hex "0" CD40174B 16 14-stage counter/divider and
4-bit "0" with 3-state outputs CD4076B 14 oscillator CD4060B 16
Quad "0" CD40175B 16 CD4060A 16
Timers
Latches 21-stage CD4045B 14
Quad clocked "0" CD4042B 16 CD4045A 14
CD4042A 16 Programmable CD4536B 16
Quad NOR R/S (3-state outputs) CD4043B 16 CD4541B 14
CD4043A 16 Synchronous
Quad NAND R/S (3-state outputs) CD4044B 16 Decade counter/divider plus 10
CD4044A 16 decoded decimal outputs CD4017B 16
Dual 4-bit CD4508B 24 CD4017A 16
8-bit addressable CD4099B 16 Divide-by-8 counter/divider with
Registers CD4724B 16 8 decimal outpu:s CD4022B 16
CD4022A 16
Shift Registers-Static Presettable divide-by-"N" counter,
Dual 4-stage with serial input/ fixed or programmable CD4018B 16
parallel output CD4015B 16 CD4018A 16
CD4015A 16 Programmable-divide-by-"N"
18-stage CD400SB 14 counter CD4059A 24
CD4006A 14 Presettable up/down counter,
64-stage CD4031B 16 binary or BCD-decade CD4029B 16
CD4031A 16 CD4029A 16
Dual 64-bit CD4517B 16 Presettable 4-bit BCD up/down
8-stage with synchronous parallel counter CD451DB 16
or serial input/serial output CD4014B 16 Presettable 4-bit binary up/down
CD4014A 16 counter CD4516B 16
8-stage with asynchronous parallel Presettable 2-decade BCD down
input or synchronous serial counter CD40102B 16
input/ serial output CD4021B 16 Presettable 8-bit binary down
4-stage parallel-in / parallel-out with Presettable 4-bit BCD up/down
J-K input and true/complement counter CD40192B 16
output CD4035B 16 Presettable 4-bit binary up/down
4-bit universal bidirectional Dual BCD up counter CD4518B 16
with 3-state outputs CD40104B 16 Dual binary up counter CD4520B 16
4-bit universal bidirectional Decade counter/asynchronous clear CD40160B 16
with asynchronous master reset CD40194B 16 Binary counter/asynchronous clear CD40161B 16
8-stage bidi'ectional parallel or Decade counter/synchronous clear CD40162B 16
serial input/parallel output CD4034B 24 Binary counter/synchronous clear CD40163B 16
CD4034A 24
32-bit left/right CD40100B 16 Display Drivers
8-stage shift-and-store bus CD4094B 16 With Counter
Shift Registers-Dynamic Decade counter/divider with 7-
200-stage CD4062A 12 segment display outputs and
Storage Registers display enable CD4026B 16
8-bit addressable latch CD4099B 16 CD4026A 16
CD4724B 16 Decade counter / divider with 7-
4-bit "D"-type with 3-state outputs CD4076B 16 segment display outputs and
4 X 4 Multiport CD40108B 24 ripple blanking CD4033B 16
4 X 4 Multiport CD40208B 24 CD4033A 16
FIFO Buffer Registers Up/Down Counter-Latch-
4-bit X 16 word CD40105B 16 Decoder-Driver CD40110B 16
8
Function I Type No. I No. of

Pins Function
I Type No.
I
No. of
Pins
Arithmetic Circuits (Cont'd)

Display Drivers (cont'd)
Adders/Comparators
•
For Liquid-Crystal-Display Drive
Quad exclusive-OR gate CD4030B 14
4-segment display driver CD4054B 16 CD4030A 14
BCD-to-7 -segment decoder Idriver Quad exclusive-OR gate CD4070B 14
with "display-frequency" output CD4055B 16 Quad exclusive-NOR gate CD4077B 14
BCD -to-7 -segment decoder Idriver
with strobed-latch function CD4056B 16 ALUIRate Multipliers
CD4543B 16 4-bit arithmetic logic unit CD40181B 24
4-digit decoder Idriver with CD4057A 28
hexidocimal display CD22104V 40 BCD rate multiplier CD4527B 16
4-digit decoder I driver with Binary rate multiplier CD4089B 16
decimal display CD22104A V 40 Look-ahead-carry block CD40182B 16
4-digit decoder I driver with Parity Generator/Checker
hexidecimal display CD22105 V 40 9-bit CD40101B 14
4-digit decoder I driver with
decimal display CD22105A V 40 Multiport Register
4 X 4 CD40108B 24
For Llght-Emitting-Diode Drive 4 X 4 CD40208B 24
BCD-to-7 -segment latch decoder I 8X1 CD4034B 24
driver CD4511B 16 8 Xl CD4034A 24
Multiplexers/Demultiplexers Quad Bilateral Switches
Analog For transmission or multiplexing of CD4016B 14
Triple 2-channel CD4053B 16 analog or digital signals CD4016A 14
Differential 4-channel CD4052B 16 CD4066B 14
Single 8-channel CD4051B 16 CD4066A 14
Differential 8-channel CD4097B 24
Single 16-channel CD4067B 24 Telecommunication Circuits
Quad bilateral switch CD4016B 14 Crosspoint Switches
CD4016A 14 4 X 4 crosspoint switch with
Quad bilateral switch CD4066B 14 control memory CD22100 V 16
CD4066A 14 4 X 4 X 2 crosspoint switch with
Digital (Data Selectors) CD22101 V 24
control memory
Quad AND lOR select CD4019B 16 4 X 4 X 2 crosspoint switch with
CD4019A 16 control memory CD221 02 V 24
Dual 1-of-4 decoder Idemultiplexer
(outputs high) CD4555B 16 HDB3 Transcoder
Dual 1-01-4 decoder/demultiplexer HDB3 transcoder for
(outputs low) CD4556B 16 2.048/8.448 Mb/s transmission
Quad 2-line-to-l-line CD40257B 16 applications CD22103 v 16
8-channel CD4512B 16
PCM Line Repeater
Phase-Locked Loop PCM line repeater CD22301 v 18
Micropower CD4046B 16
CD4046A 16
Timer/Driver
Arithmetic Circuits 16-channel precision
Adders/Comparators timer/driver CD22401 v 40
4-bit full adder with parallel carry
out CD4008B 16 PCM Data Filters
CD4008A 16 Pulse code modulation
Triple serial adder, positive logic CD4032B 16 sampled-data filters CD22413v 16
CD4032A 16 CD22414 v 16
Tone Generator
Triple serial adder, negative logic CD4038B 16
Dual-tone multifrequency
CD4038A 16
tone generator CD22859 V 16
4-bit magnitude comparator CD4063B 16
CD4585B 16
V
Indicates types designed for special applications. Ratings and characteristics data for these types differ in some aspects from
the standardized data for A- and B-series types. Refer to data pages on these types for specific differences.
9
CMOS LSI Products
In addition to the logic and special-function integrated In addition to the memories designed to interface directly
circuits listed in the preceding pages, RCA offers an all- with CDP 1800-series microprocessors, RCA also offers a
CMOS line of microprocessor, memory and peripheral line of general-purpose memories.
integrated circuits. For descriptive information on RCA microprocessor and
The RCA CDPI800 series offers the most complete line memory circuits, refer to the RCA "CMOS-LSI" DAT A-
of CMOS microprocessor and associated memory and BOOK, SSD-260A.
peripheral devices in the industry. In addition to For the designers of microprocessor-based equipment
microprocessors and microcomputers, this product line and in support of the CDPl800-series microprocessors
includ.es a hardware multiply/ divide unit (MDU), a and associated memory and peripheral circuits, RCA
programmable 1/ 0, video and keyboard interface circuits, provides a strong and extensive line of systems, system
latches and decoders, a universal asynchronous receiver- support components, system support software, system
transmitter (UART), buffers, separators, and a broad modules (including Microboard milliwatt computer
complement of directly interfaceable random-access systems), and other development aids.
memories (RAM's) and read-only memories (ROM's).
The RCA Microsystems DAT ABO OK SSD-270 provides
RCA also offers the CDP6800 family, a new series of detailed information on RCA Microprocessor-based
pin-for-pin replacements for the MCI46805 Series of development systems and Microboard computer modules.
CMOS microprocessors and peripherals primarily in-
tended for single-chip system applications.
CMOS LSI Products

Part No. Description No. of Pins Part No. Description No. of Pins
Microprocessors ROMs
CDPI802A 8-Bit 40 CDM5332 Mask-programmable ROM
CDPI802B 8-Bit 40 512 x 8 24
CDPI805C 8-Bit with RAM 40 CDM5333 Mask-programmable ROM
CDPI805AC 8-Bit with RAM 40 512 x 8 24
CDPI806C 8-Bit with Counter-Timer 40 CDM53128 Mask-programmable ROM
CDPI806AC 8-Bit with Counter-Timer 40 16K x8 28
CDP6805E2 8-Bit with RAM/I-O/Counter- CDM53256 Mask-programmable ROM
Timer 40 32K x 8 28
Microcomputers CDPI831 Mask-programmable ROM
CDPI804A 8-Bit with RAM/ROM/Counter- 512 x 8 24
Timer 40 CDPI832 Mask-programmable ROM
CDP6805F2 8-Bit with RAM/ROM/I-O/ 512 8x 24
Counter-Timer 28 CDPI833 Mask-programmable ROM
CDP6805G2 8-Bit with RAM/ROM/I-O/ IKx8 24
Counter-Timer 40 CDPI833B Mask-programmable ROM
RAMs IK x 8 24
CDPI821 IKx I 16 CDPI834 Mask-programmable ROM
CDPI822 256 x 4 22 lK x 8 24
CDP1835 Mask~programmable ROM
CDPI823 128 x 8 24
CDPI824 32 x 8 18 2K x 8 24
CDP1826 64 x 8 22 CDPI837 Mask-programmable ROM
CDM6116 2K x 8 24 4K x 8 24
CDM6117 2Kx 8 24 CDP65516 Mask-programmable ROM
CDM6118 2K x 8 24 2K x 8 18
Input/Output Circuits
MWS5101 256 x 4 22 CDP1851 Programmable I/O (Pia) 40
MWS510IA 256 x 4 22 CDPI852 Byte I/O - 8-Bit I/O Port 24
MWS5114 IK x4 18 CDPI853 Decoder - I of 8 16
CD4036A 4x8 24 CDPI855 Multiply/Divide Unit (MDU) 28
CD4039A 4x8 24 CDP1856 Buffer - 4-Bit 16
CD4061A 256 x I 16 CDP1857 Buffer - 4-Bit 16
CD40061A 256 x I 16 CDP1858 Latch/Decoder - 4-Bit 16
CD40114B 16 x 4 16 CDP1859 Latch/Decoder - 4-Bit 16
10
CMOS LSI Products (Cont'd)
Part No. Description No. of Pins Part No. Description No. of PIns
CDPI861 Video Display Controller (VDC) 24 CDPI874 High-Speed Input Port - 8-Bit 22
CDPI862 Color Generator Circuit 24 CDPI875 High-Speed Output Port 22
CDPI863 Programmable Frequenl=Y CDPI876 Video Interface System (VIS) 40
Generator 16 CDPI877 Programmable Interrupt
CDPI864 PAL Video Display Controller Controller 28
(VDq 40 CDPI878 Dual Counter-Timer 28
•
CDPI866 Latch/ Decoder - 4-Bit 18 CDPI879 Real Time Clock 24
CDPI867 Latch/ Decoder - 4-Bit 18 CDPI881 Latch/ Decoder - 4-Bit 20
CDPI868 Latch/ Decoder - 4-Bit 18 CDPI882 Latch/ Decoder - 4-Bit 18
CDPI869 Video Interface System (VIS) 40 CDP6818 Real Time Clock with RAM 24
CDPl870 Video Interface System (VIS) 40 CDP6823 Parallel Interface 40
CDPl87lA Keyboard Encoder, ASCII/ Hex 40 UARTs
CDPI872 High-Speed Input Port - 8-Bit 22 CDPl854A UART 40
CDPl873 High-Speed Decoder - I of 8 16 CDP6402 Industry Standard UART 40
11
The QMOS Product Line
RCA also offers the QMOS series of high-speed CMOS • Direct LSTTL Input Logic Level Compatibility
logic integrated circuits which include an extensive line of as well as CMOS Input Compatibility-
products that are pin compatible with many existing CD74/54HCT Family
bipolar 54(74LSTTL and CMOS 4000 series of digital (Can replace LSTTL or be mixed with LSTTL IC's.)
logic types. The new QMOS IC's provide high-speed VIL = 0.8 V max., VIH = 2 V min.
CMOS replacements for the most popular LSTTL devices • 2 to 6 V Operation - CD74/54HC Family
in existing designs and also offer low-power all-CMOS • 4.5 to 5.5 V - CD74/54HCT Family
designs for new digital systems. Key family features of the • Gate Propagation Delay of 8 ns typ., CL=15 pF
RCA QMOS types include: • Balanced High-to-Low and Low-to-High
Propagation Delays
• High Noise Immunity for Optimum • Significant Power Reduction Compared to LSTTL
AII-CMOS-System Compatibility - Bipolar Logic IC's
CD74/54HC Family • Alternate Sourced
NIL = 20% of Supply, NIH = 30% of Supply
For descriptive information on the RCA QMOS series,
refer to the RCA DATABOOK "QMOS High-Speed
CMOS Logic", SSD-290.
QMOS Products
CMOS Logic TTL Logic

Plastic Pkg. CERDIP Plastic Pkg. CERDIP Pins Description
CD74HCOOE CD54HCOOF CD74HCTOOE CD54HCTOOF 14 Quad 2-1 nput NAND Gate
CD74HC02E CD54HC02F CD74HCT02E CD54HCT02F 14 Quad 2-lnput NOR Gate
CD74HC04E. CD54HC04F CD74HCT04E CD54HCT04F 14 Hex Inverter/Buffer
CD74HCOBE CD54HCOBF CD74HCTOBE \ CD54HCTOBF 14 Quad 2-lnput AND Gate
CD74HC10E CD54HC10F CD74HCT10E i CD54HCT10F 14 Triple 3-lnput NAND Gate
CD74HCllE CD54HCllF CD74HCT11E i\ CD54HCTllF 14 Triple 3-lnput AND Gate
CD74HC14E CD54HC14F CD74HCT14E \ CD54HCT14F 14 Hex Schmitt Trigger Inverter
CD74HC20E CD54HC20F CD74HCT20E CD54HCT20F 14 Dual4-lnput NAND Gate
CD74HC27E CD54HC27F CD74HCT27E CD54HCT27F 14 Triple 3-lnput NOR Gate
CD74HC30E CD54HC30F CD74HCT30E CD54HCT30F 14 B-Input NAND Gate
CD74HC32E CD54HC32F CD74HCT32E CD54HCT32F 14 Quad 2-lnput OR Gate
CD74HC42E CD54HC42F CD74HCT42E CD54HCT42F 14 BCD-to-Decimal Decoder
CD74HC73E CD54HC73F CD74HCTI3E CD54HCTI3F 14 Dual J-K Flip-Flop w/CLEAR
CD74HC74E CD54HC74F CD74HCTI4E CD54HCT74F 14 Dual D Flip-Flop w/PRESET and CLEAR
CD74HC75E CD54HC75F CD74HCTI5E CD54HCT75F 16 4-Bit Bistable Latch
CD74HC85E CD54HC85F CD74HCT85E CD54HCT85F 16 4-Bit Magnitude Comparator
CD74HC86E CD54HC86F CD74HCT86E CD54HCT86F 14 Quad 2-lnput Excl. OR Gate
ggi:~gi~~~~
CD74HC107E CD54HC107F CD54HCT107F 14 Dual J-K Flip-Flop w/CLEAR
CD74HC109E CD54HC109F I CD54HCT109F 14 Dual J-K Flip-Flop w/PRESET and CLEAR
CD74HC112E CD54HC112F CD74HCT112Ei CD54HCT112F 16 Dual J-K Flip-Flop w/PRESET and CLEAR
CD74HC123E CD54HC123F CD74HCT123E, CD54HCT123F 16 Dual Retriggerable Monostable Multivibrator
CD74HC132E CD54HC132F CD74HCT1326 CD54HCT132F 14 Quad 2-lnput NAND Schmitt Trigger
CD74HC138E CD54HC138F CD74HCTI38E;' CD54HCT138F 16 3-to-8 Line Decoder
CD74HC139E CD54HC139F CD74HCT139E CD54HCT139F 16 Dual 1-01-4 Line Decoder
CD74HC147E CD54HC147F CD74HCT147E CD54HCT147F 16 10-to-4 Line-Priority Encoder
CD74HC151E CD54HC151F CD74HCT151E CD54HCT151F 16 8-Channel Digital Multiplexer
CD74HC153E CD54HC153F CD74HCT153E CD54HCT153F 16 Dual 4-lnput Multiplexer
CD74HCI54E CD54HC154F CD74HCT154E CD54HCT154F 24 4-to-16-Line Decoder
CD74HC157E CD54HC157F CD74HCT157E CD54HCT157F 16 Quad 2-lnput Multiplexer
CD74HC158E CD54HC158F CD74HCT158E CD54HCT158F 16 Quad 2-lnput Multiplexer. Inverting
CD74HC160E CD54HC160F CD74HCTI60E CD54HCT160F 16 BCD Decade Counter. Asynchronous Reset
CD74HC161E CD54HC161F CD74HCT161E CD54HCT161F 16 4-Bit Binary Counter, Asynchronous Reset
CD74HC162E CD54HC162F CD74HCT162E CD54HCT162F 16 BCD Decade Counter, Synchronous Reset
CD74HCI63E CD54HC163F CD74HCT163E CD54HCT163F 16 4-Bit Binary Counter, Synchronous Reset
CD74HC164E CD54HC164F CD74HCT164E CD54HCT164F 14 8-Bit Serial-to-Parallel Shift Register
CD74HC165E CD54HC165F CD74HCT165E CD54HCT165F 16 8-Bit Parallel-to-Serial Shift Register
CD74HC166E CD54HC166F CD74HCT166E CD54HCT166F 16 8-Bit Serial/Parallel In, Serial Out Shift Register
CD74HC173E CD54HC173F CD74HCT173E CD54HCT173F 16 Quad D Flip-Flop, 3-State
CD74HC174E CD54HC174F CD74HCT174E CD54HCT174F 16 Hex 0 Flip-Flop w/CLEAR
CD74HC175E CD54HC175F CD74HCT175E CD54HCT175F 16 Quad D Flip-Flop w/CLEAR
CD74HC190E CD54HC190F CD74HCT190E CD54HCT190F 16 Async. Presettable BCD/Decade Up/Down Counter
CD74HC191E CD54HC191F CD74HCT191 E CD54HCT191 F 16 Presettable Sync. 4-Bit Binary Up/Down Counter
CD74HC192E CD54HC192F CD74HCT192E CD54HCT192F 16 Synchronous Decade Up/Down Counter
CD74HC193E CD54HC193F CD74HCT193E CD54HCT193F 16 Synchronous Binary Up/Down Counter
CD74HC194E CD54HC194F CD74HCT194E CD54HCT194F 16 4-Bit Bidirectional Universal Shift Register
12
The QMOS Product Line (Cont'd)
CMOS Logic TTL Logic

Plastic Pkg. CERDIP Plastic Pkg. CERDIP Pins Description
r'CD74HCI95E CD54HC195F CD74HCT195E CD54HCT195F 16 4-Bit Parallel Shilt Register
CD74HC221E CD54HC221F CD74HCT221 E CD54HCT221 F 16 Dual Monostable Multivibrator
CD74HC23BE CD54HC23BF CD74HCT23BE CD54HCT23BF 16 l-ol-B Decoder
CD74HC240E CD54HC240F CD74HCT240E CD54HCT240F 20 Octal Bulfer Line Driver, 3-State, Inverting
CD74HC241E CD54HC241F CD74HCT241 E CD54HCT241 F 20 Octal Buffer Line Driver, 3-State
CD74HC242E CD54HC242F CD74HCT242E CD54HCT242F 14 Quad-Bus Transceiver, 3-State, Inverting
CD74HC243E CD54HC243F CD74HCT243E CD54HCT243F 14 Quad-Bus Transceiver, 3-State
CD74HC244E CD54HC244F CD74HCT244E CD54HCT244F, 20 Octal-Buffer Line Driver, 3-State
CD74HC245E CD54HC245F CD74HCT245E CD54HCT245F 20 Octal-Bus Transceiver, 3-State
CD74HC251E CD54HC251F CD74HCT251 E CD54HCT251 F 16 8-Channel Multiplexer, 3-State
CD74HC253E CD54HC253F CD74HCT253E CD54HCT253F 16 Dual 4-lnput Multiplexer, 3-Stale
CD74HC257E CD54HC257F CD74HCT257E CD54HCT257F 16 Quad 2-lnput Multiplexer, 3-State
CD74HC259E CD54HC259F CD74HCT259E CD54HCT259F 16 8-Bit Addressable Latch
CD74HC266E CD54HC266F CD74HCT266E CD54HCT266F 14 Quad 2-lnput Exci. NOR
CD74HC273E CD54HC273F CD74HCT273E CD54HCT273F 20 Octal 0 Flip-Flop w/CLEAR
CD74HC280E CD54HC280F CD74HCT280E CD54HCT280F 14 8-Bit Odd/Even Parity Generator/(;hecker
CD74HC297E CD54HC297F CD74HCT297E CD54HCT297F 16 Digital Phase-Locked Loop Filter
CD74HC299E CD54HC299F CD74HCT299E CD54HCT299F 20 B-Bit Universal Shift Register
CD74HC354E CD54HC354F CD74HCT354E CD54HCT354F 20 B-Input Multiplexer, Latched-Data, 3-State
CD74HC356E CD54HC356F CD74HCT356E CD54HCT356F 20 B-Input Multiplexer, Clocked-latched-Dala, 3-State
CD74HC365E CD54HC365F CD74HCT365E CD54HCT365F 16 Hex 3-State Buffer
CD74HC366E CD54HC366F CD74HCT366E CD54HCT366F 16 Hex 3-State Buffer, Inverting
CD74HC367E CD54HC367F CD74HCT367E CD54HCT367F 16 Hex 3-State Buffer
CD74HC368E CD54HC36BF CD74HCT368E CD54HCT36BF 16 Hex 3-State Buffer, Inverting
CD74HC373E CD54HC373F CD74HCT373E CD54HCT373F 20 Octal Transparent Latch 3-State
CD74HC374E CD54HC374F CD74HCT374E CD54HCT374F 20 Octal 0 Flip-Flop, 3-State
CD74HC377E CD54HC377F CD74HCT377E CD54HCT377F 20 Octal 0-Type Flip-Flop with Data Enable
CD74HC3B4E CD54HC384F CD74HCT384E CD54HCT384F 16 8-Bit Serial Multiplier
CD74HC390E CD54HC390F CD74HCT390E CD54HCT390F 16 Dual Decade Counter
CD74HC393E CD54HC393F CD74HCT393E CD54HCT393F 16 Dual 4-Bit Binary Counter
CD74HC423E CD54HC423F CD74HCT423E CD54HCT423F 16 Dual Retriggerable Monostable Multivibrator
CD74HC533E CD54HC533F CD74HCT533E CD54HCT533F 20 Octal Transparent Latch, 3-State, Inverting
CD74HC534E CD54HC534F CD74HCT534E CD54HCT534F 20 Octal 0 Flip-Flop, 3-State, Inverting
CD74HC540E CD54HC540F CD74HCT540E CD54HCT540F 20 Octal Buffer Line Driver, 3-State, Inverting
CD74HC541E CD54HC541F CD74HCT541E CD54HCT541 F 20 Octal Buffer Line Driver, 3-State
CD74HC563E CD54HC563F CD74HCT563E CD54HCT563F 20 Octal Transparent latch, 3-State, Inverting
CD74HC564E CD54HC564F CD74HCT564E CD54HCT564F 20 Octal 0 Flip-Flop, 3-State, Inverting
CD74HC573E CD54HC573F CD74HCT573E CD54HCT573F 20 Octal Transparent Latch, 3-State
CD74HC574E CD54HC574F CD74HCT574E CD54HCT574F 20 Octal 0 Flip-Flop, 3-State
CD74HC640E CD54HC640F CD74HCT640E CD54HCT640F 20 Octal Bus Transceiver, 3-State, Inverting
CD74HC643E CD54HC643F CD74HCT643E CD54HCT643F 20 Octal Bus Transceiver, 3-State
CD74HC646E CD54HC646F CD74HCT646E CD54HCT646F 20 Octal Bus Transceiver, 3-State
CD74HC648E CD54HC64BF CD74HCT64BE CD54HCT64BF 20 Octal Bus Transceiver, 3-State, Inverting
CD74HC670E CD54HC670F CD74HCT670E CD54HCT670F 16 4 x 4 Register File, 3-State
CD74HC6BBE CD54HC6BBF CD74HCT6BBE CD54HCT6BBF 20 8-Bit Equality Comparator
CD74HC4002E CD54HC4002F CD74HCT4002E CD54HCT4002F 14 Dual 4-lnput NOR Gate
CD74HC4015E CD54HC4015F CD74HCT4015E CD54HCT4015F 16 Dual 4-Stage Serial In/Parallel Out Shift Register
CD74HC4016E CD54HC4016F CD74HCT4016E CD54HCT4016F 14 Quad Bilateral Switch
CD74HC4017E CD54HC4017F CD74HCT4017E CD54HCT4017F 16 Decade Counter/Divider
CD74HC4020E CD54HC4020F CD74HCT4020E CD54HCT4020F 16 14-Bit Binary Counter
CD74HC4024E CD54HC4024F CD74HCT4024E CD54HCT4024F 14 7-Stage Binary Counter
CD74HC4040E CD54HC4040F CD74HCT4040E CD54HCT4040F 16 12-Bit Binary Counter
CD74HC4046E CD54HC4046F CD74HCT4046E CD54HCT4046F 16 Phase-Locked Loop
CD74HC4049E CD54HC4049F - - 16 Hex Buffer, Inverting
CD74HC4050E CD54HC4050F - - 16 Hex Buffer
CD74HC4051 E CD54HC4051 F CD74HCT4051 E CD54HCT4051F 16 B-Channel Analog MUX/DEMUX
CD74HC4052E CD54HC4052F CD74HCT4052E CD54HCT4052F 16 Dual 4-Channel Analog MUX/DEMUX
CD74HC4053E CD54HC4053F CD74HCT4053E CD54HCT4053F 16 Triple 2-Channel Analog MUX/DEMUX
CD74HC4060E CD54HC4060F CD74HCT4060E CD54HCT4060F 16 14-Stage Binary Counter w/Oscillalor
CD74HC4066E CD54HC4066F CD74HCT4066E CD54HCT4066F 14 Quad Bilateral Switch
CD74HC4067E CD54HC4067F CD74HCT4067E CD54HCT4067F 24 16-Channel Analog Multiplexer/Demultiplexer
CD74HC4075E CD54HC4075F CD74HCT4075E CD54HCT4075F 14 Triple 3-lnput OR Gate
CD74HC4094E CD54HC4094F CD74HCT4094E CD54HCT4094F 16 8-Stage Shift-and-Store Bus Register
CD74HC4511E CD54HC4511 F CD74HCT4511E CD54HCT4511 F 16 BCD-to-7-Segment Latch/Decoder/Driver
CD74HC4514E CD54HC4514F CD74HCT4514E CD54HCT4514F 24 '4-to-I6-Line Decoder wlLatch
CD74HC451BE CD54HC451BF CD74HCT4518E CD54HCT4518F 16 Dual BCD Up Counter
CD74HC4520E CD54HC4520F CD74HCT4520E CD54HCT4520F 16 Dual Binary Up Counter
CD74HC453BE CD54HC453BF CD74HCT453BE CD54HCT453BF 14 Dual Retriggerable Precision Monostable Multivibrator
CD74HC40102E CD54HC40102F CD74HCT40102E CD54HCT40102F 16 Dual Decade BCD Down Counter
CD74HC4Ql03E CD54HC40103F CD74HCT40103E CD54HCT40103F 16 8-Bit Binary Down Counter
CD74HC40104E CD54HC40104F CD74HCT40104E CD54HCT40104F 16 4-Bit Bidirectional Universal Shift Regisler, 3-State
CD74HC40105E CD54HC40105F CD74HCT40105E CD54HCT40105F 16 FI FO Shift Register
Note: Add package suffix code to part number on all orders.

E=Dual-in-Line Plastic Package-Temp. Range=-40' C to +85' C.
F=Dual-ln-Line Frit-Seal Ceramic Package (CERDIP)-Temp. Range=-55'C to +125'C.
13
CMOS IC Packages
D Suffix E Suffix
Ceramic Dual-In-Line Packages Plastic Dual-In-Line Packages
Welded-8eaI14,16,24, 18, 22, 24, 40-Lead

4 MiniDIP
8,14,16,18,22,24, and 40-lead Versions

and 28-lead Versions Side-Brazed Versions
F'Suffix K Suffix T Suffix

Frit-Seal Ceramic Dual-In-Line Packages Ceramic Flat Packages 12-Lead TO-S Style Package
14,16, and 24-lead Versions 14,16, and 24-lead Versions CD4024A and CD4062A only
Ordering Information
H Suffix
Most RCA CMOS integrated circuits are available in the
CMOS Chip
following package styles and are identified by the Suffix
Letters indicated below: dual-in-line ceramic, dual-in-line
frit-seal ceramic, dual-in-line plastic, ceramic flat package,
and in chip form. Some types are only available in one or two
package styles. The available package styles for any specific
type are given in the technical data for this type.
When order CMOS devices, it is important that the appropri-
ate suffix letter be affixed to the type number of the device
required. For example, a CD40168 in a dual-in-line ceramic
package will be identified as the CD40168D.
Suffix
Package Letters
Dual-In-Line Welded-Seal or D
Side-Brazed Ceramic
Dual-In-Line Frit-Seal Ceramic F
Dual-In-Line Plastic E
Ceramic Flat Package K
TO-5 Style T
Chip H
14
Functional Diagrams
14 voo
NC K=OtE+F VOO
2
•. J=A+B+C+O
NC 2 13
A K
A H
•
4 B H
B G
5 C G
M
H L 0 F
7
VSS
E
7 K=E+F+G+H 8
92CS-24757 VS5 NC
92CS-24762
Dual 3-lnput NOR Gate 92CS-24758
Plus Inverter Quad 2-lnput NOR Gate Dual 4-lnpul NOR Gale 18-Stage Static Shift
Register
CD4000A (Page 478) CD4001A (Page 478) CD4002A (Page 47/j)
CD4000B (Page ~8) CD4001B (Page 58) CD4002B (Page 58) CD4006A (Page 481)
CD4000UB (Page 62) CD4001UB (Page 62) CD4002UB (Page 62) CD4006B (Page 66)
Co A
~ G'P; A~G'A
14 2 II
8
~ H'B B~H'B
J~ ~
~-~
83
*2
53
e
~ I·e C ---v-- I'C
~ J. ii
*3
{l{l{t
A3 0
*4
~ K'E
B2
{j {j N A2 *5
F ~
1 1}
7
??
4 9
B, *6
*7
5, ~ L'F ---v-- L·F
AI Vee-'- VCC-
' -
VSS·7 VSS _8_ V 00 ~ 16 VSs-8- VOO"'6
92C5- 25035 *9
C,
VOO"'4 NC "3 NC "3
(CARRY IN) 9255- 4140R2
97CS- 25Q77J:f2
Dual Complementary Pair 4-Bit Full Adder with Hex Buffer/Converter Hex Buffer/Converter
Plus Inverter Parallel Carry Out Inverting Type Non-Inverting Type
CD4007A (Page 484) CD4008A (Page 487) CD4009A (Page 489) CD4010A (Page 489)
CD4007UB (Page 70) CD4008B (Page 74) CD4009UB (Page 78) CD4010B (Page 78)
Voo PAR. IN. Voo

J=A-B·C-O
14 VOO I
A-",+--,
• 2345678
2 13 SETI 6
B H A K
0, 5
12
B H eLOCKI 3 ~:t-..!
CONT.
RESET I 4
K-+--, M C G SER. II
SET28 IN·
10
C L 0 F 02 9 CLOCK!Q.
CLOCK2 II
9
O-'T--' F NC E
RESET2!.0
7 K=E'F'G'H 8 8
VSS NC 92CS-250~7
VSS 7 L----1F--E VSS
'-------::9"'2::-CS::--~l!4 763 .92CR-24759 8-Stage Synchronous Shift
Quad 2-lnput NAND Gate Dual 4-lnput NAND Gate Dual "0" Flip-Flop with Register with Parallel or
CD4011 A (Page 492) CD4012A (Page 492) Set/Reset Capability Serial Input/Serial Output
CD4011 B (Page 82) CD4012B (Page 8~ CD4013A (Page 495) CD4014A (Page 498)
CD4011 UB (Page 'S6) CD4012UB (Page 86) CD4013B (Page 90) CD4014B (Page 84)
15
Functional Diagrams
YDD IN/OUT 14 +VOO Voo
16 IN~t'1S YOO
~
16 SIG A "0"
7 5 CONT "I" "111 "3" "5"
DATA A QIA OUT/IN 2
A
14 "2"
9 4 CLOCK
CLOCK A Q2A
RESET A
6
4
STAGE. 3
Q3A
OUT/IN 3
SIG B
CONT
°
CLOCK 13
INHIBIT
RESET
IS 10 "4"
"3"
mm lO
10 4 "sit CLOCK 14
Q4A IN/OUT IN/OUT
:;:
15 13 SIG ° "6" 0
DATAB
12
QIB CONT
B
5 10 OUTfiN
"7"
"e"
~ OATA
CLOCKB Q2B
4 II RESET 15
STAGE "9"
14 CONT 6 9
RESETB
"
2
Q3B C
OUTfiN
SIG C
12
CARR""
Q4B OUT
7
YSS IN/OUT 8
8 92C$-25074 YSS
92C5-21627 92CS-25072R2
92C5-25048 Vss
Yss
Dual 4-Stage Static Shift Register Decade Counter/Divider w;th Presettable Divide-by-"N"
Quad Bilateral Switch
with Serial Input/Parallel Output 10 Decoded Decimal Outputs Counter Fi xed or Programmable
CD4015B (Page 99) CD4016B (Page 103) CD4017B (Page 108) CD4018B (Page 113)
voo PAR. IN.

I
16
2345678
9
QI 2
....en
13 0•
7 Q4
5 Q5
4
......
J
J ~:::-2-
CLOCK
CLOCK
INHIBIT
13
14 "0"
"I"
,.:
Q6 o CONT. 15 3 "2" ::>
RESET
1203
6 Q7
13 Q8 ...
o
0: SER. "
IN·
7 "3"
0
0
'"a0
......
-UJ
12 Q9 II "4"
:0.'iA4·Ko'+iB4Kb' II 02 14 QIO J u
CLOCK!Q 4
I 15
QII
CD "5" '"0
I 1°01 I
012
~
5 "6"
2 013
VOO=16 10 "7"
II 8
8 014 92C5-25047
VSS RESET YSS V5S= 8 12
8-Stage Static Shift Register CARRY
92C5-25036
92CS·25053R2 Asynchronous Parallel or 92CS_2S073.~2---..JOUT
Vss Synchronous Serial Input/ Divide-by.s Counter/Divider with
Quad AND/OR Select Gate Serial Output 8 Decoded Decimal Outputs
14-Stage Binary Ripple Counter
CD4019A (Page 514) CD4020A (Page 516) (Page 522)
CD4019B (Page 118) CD4020B (Page 122) (Page 108)
Voo
14
A-+-----, 14 !lDD 16
-,-,"_ _-,~IO=- a ~
13
B --'=t-----, G 12 Q,
12 b ~
'"....J
D H
INPUT
PULSES
II Q2 ..
....
"
~
0
o
~
.
J
d 0
9 Q3 0
0
8
~
E r 2
RESET 6 Q4 '"0:
......
w
7 •
F L 5 Q5 J
CD 5 CARRVOUT
40l> "- _4-
K-'+-=== DISPLAY
ENABLE
OUT
3 07
14
YSS '-----+--C NC=8,10,13 '----t"'--C
UNGATEO "e"
SEGMENT
7
92CS-24761 Vss 92:C5- 2'078 FU
92CS-25051A3 vss 92CS- 24760
Triple 3-lnput NAND Gate Triple 3-lnput NOR Gate Decade Counter/Divider with 7-
7-Stage Ripple-Carry
Segment Display Outputs and
CD4023A (Page 492) Binary Counter/Divider CD4025A (Page 478) Display Enable
CD4023B (page !l21 CD4024A (Page 525) CD4025B (Page 58) CD4026A (Page 528)
CD4023UB (Page 86) CD4024B (Page 122) CD4025UB (Page 62) CD40268 (Page 126)
16
Functional ·Diagrams
PRESET
ENABLE
VDD BUFFERED B-o:,...,........... I ' VDD
16 16 OUTPUTS 13 H
.UFFERED A-'="-..r"t<--'
~
~4 )g~~~~ED
~:~ ~
12 G
o
~
, ,. ~IUci:~~S
2
I
BINARYI K 4
DECADE 9
" M
C 5 10
4 ~ BUFFERED
,
6 7
DECIMAL
DECODED UP/OOWN 10 I'~
o 6 9
7 4 OUTPuTS
9 II OF 101 VSS .......-'"'""1...I.-=-E
• CLOCK I~ 2 0,
9 •
CARRY JoA@B L' E@F
OUT KoC@D MoG@H
V5S
92CS-191~, 8
92CS 17410RI
92CS-171B7RI 92CS -11190R3 VSS
Dual J-K Master-Slave
Presettable Up/Down Counter,
Flip-Flop with Set-Reset
BCD-to-Decimal Decoder Binarv or BCD-Decade Quad Exclusive-OR Gate
Capability
DATA I
IN BI
AI-"'_...r---' ,.
vDO
10
SI
AE
A/8
MOOE INvERT I CLOCK
t'? AIS
CONT
RECIRC
'2
~
• PIS
DATA 2
IN CLOCK ", 0
Q
CL
INHIBIT
CLOCK SUM 2
,. • "'
Q
IN
RESET
,. ·~ on
"':::;z ::!Z
LAMP
TEST •
CARRY :::;
VDD 0 16
DELAYED
CLOCK
OUT RIPPLE
5 OUT
RIPPLE
.
:!
0
~
:§
"LK "LK
VSS 08 IISS =8 'N DUT
NC' 3,4,11,12,13,14 92CS·17663
'J2CS 2':JO~'J Voo =16 V5S 92CS-29108
Decade Counter/Divider 8·Stage Static Bidirectional
54-Stage Static Shift Triple Serial Adder with 7·Segment Display Paraliel/Serial Input/Output
Register Positive Logic Outputs and Ripple Blanking Bus Register
Voo -14
VDD
AI-"'_...r---.,
BI 16
INVERT I ,
,.
SER.{J 4, • 10 012
IN K INPUT 15 011
PULSES on
cu< 6 010 I-
12
09 ~
PIS 7 I-
13 08 0>
0
TIC 2 12-STAGE
• RIPPLE
07 0
RESET
~ COUNTER 06 "'
0:
~
"00:;16
Vss '8
13
5 r--- -------~ 02
O~
0'
03
.
"-
0>
~
0,/0, Oi020'/03 0./0., C2 --1 AND/OR PAIR III 02
L---rr-------.F E2
TIC' OUT
'J2CS·'9966RI
6 r - - - L------""1..! 03
RESET " 01
C3 -tL _ _ _AND/OR
_ _ _PAIR
_ _ _ J19
- E3
4-Stage Parallel In/Parallel
Out Shift Register with 92CS-29066RI
92tS·''''llil 92CS-17663 VSS
J-K Serial Inputs and Truel Triple Serial Adder 12-Stage Ripple-Carry Binary
Complement Outputs Triple AND/OR Bi-Ph..e Negative Logic Counter/Divider
Pair
CD4035A (Page 553) CD4038A (Page 546) CD4040A (Page 558)
CD4035B (Page 164) CD4037A (Page 556) CD4038B (Page 154) CD4040B (Page 122)
17
Functional Diagrams
140-----1-
CLOCK
D 13~1I M SLr--....."1
M'D
VSS '? 12
POLARITY
VDD"4 N.O N Ne
60---+-"1
92CS-20034RI ENABLE B
VDD~ 92C5-20191 ENABLE
Vss 92CS-20222
Quad True/Complement Vss
vsso-!- Quad 3-State NOR R/S Quad 3-Stota NAND R/S
Buffer Quad Clocked "0" Latch latch Latch
CD4042A (Page 565) CD4043A (Page 568) CD4044A (Page 568)
CD4041A (Page 561)
(Page 169) CD4042B (Page 172) CD4043B (Page 176) CD4044B (Page 176)
CD4041UB
VOO:3 4,5,6,9,10,11,12,13=
VSS=14 NO CONNECTION
92C5- 29107
21-Stage Counter
CD4045A (Page 571) CD4046A (Page 574)

CD4045B (Page 180) CD4046B (Page 184)
.
BINARY CONTROL INPUTS
'FUNCTION CONTROL'
A
~ G'A
~
--------.. 3-STATE 8 H.B
Ka Kb Kc Kd CONTROL
C
~ I.e
~r
!; 8
~ c
13
12 D
~ J·e
0 II
EXPAND 15 J
OUTPUT
E
~ K'E
~r ~
6
F L';;
... F 5
EX T[RNAL
~ G 4 Vce - , -
RESET H 3 Vss _8_
L ________ _
92C5-22249
VSS'8 NC'13
92CS-27506
Low-Power Monostable/Astable Voo"6 Ne'I6
Multi-Function Expendable Hex Buffer/Converter
Mult;vibrator
8-lnput Gate Inverting Type
CD4047A (Page 579) (Page 585) CD4049A (Page 590)
CD4048A
CD4047B (Page 190) (Page 197) CD4049UB (Page 202)
CD4048B
18
Functional Diagrams
A
~ G-A
{~ ~! "x"
~
13
B H-B "x" COMMON
CHANNELS 2 15 OUT/IN
IN/OUT 3 II
C
~ I-C
"Y"
CHANNELS
{~2 ~
2 "Y"
.:3_ _4~_ _~3
• 0
E
~
~
J-D
K-E
IN/OUT
CONTROL {
-
:
VoO'16
Vs 5' 8
COMMON
OUT/IN
I
ll~N~H_ _ _ _~ VEE-7
F ~ -v-- L-F 92CS - 26373
VCC _ 1 -
V5S _8_ 92CS - 26372
NC -13
NC'16
Hex Buffer/Converter Single a·Channel Analog Differential 4·Channel Analog
Non·lnverting Type Multiplexer/Demultiplexer Multiplexer/Demultiplexer
CD4050A (Page 590) C040518 (Page 206) CD40528 (Page 206)
CD4050B (Page 202)
ax 12
IN/OUT { ay 13
b. 2
IN/OUT { I
c. 5
IN/OUT { cy 3
·A----~~~~~~
!:~'------'
VOD -16
CONTROL { VSS '8
INH VEE' 7
92CS - 22708RI
ALL INPUTS PROTECTED BY

COS/Mas PROTECTION NETWORK 92CS-20090R2
Triple 2·Channel 4·Segment Liquid·Crystal

Multiplexer/Demultiplexer Display Driver
C040538 (Page 206) C040548 (Page 213)
~8
VSS =vEE ~Voo
0 16
I" --+-- -I
20 5
.",
ffi [
21
...
I-
BCD
INPUTS 22
%
'".J I- 7-
Za: 23 SEGMENT
'"> 0"''''
1-20 7-5EG·
OUTPUTS
'".J o",u
<00
u",,,,
OUT• STROBE I
DISPLAY -
'" I 0
... FREQ. IN
92CS- 20092RI ALL INPUTS PROTECTED BY 92CS-Z009IR2

COS/MOS PROTECTION NETWORK
'--~--~-""-(I
BCD-to-7·Segment Decoder/Driver BCD-to-7 -Segment Decoder/Driver

with "Display-Frequency" Output with Strobed-Latch Function
Liquid-Crystal Display Driver Liquid-Crystal Display Driver
C040558 (Page 213) C040568 (Page 213)
19
Functional Diagrams
,~'"''
SEI..ECT
{:.
,
.6
OllERfLOW
va
"
OVERFLOW' LEFT
.
NEG
S~:TI} ma "
OUTPUT
ROT.{f[-2
(Ro21 4-Bit Arithmetic Logic Unit
'" LINE
C04057 A (page 593)
14-Stage Ripple-Carry
Binary Counter/Divider
Programmable Divide-by-"N" and Oscillator
Counter C04060A (Page 609)
C04059A (Page 601) C04060B (Page 218)
IN/OUT
SIG A
AO II~ CONT
WORO"~o { :~ 13 A
o ~--,------,
A3 15
C
RC Q CONT
REC~-'-'__r-~'-~
CASCAOING
>B 4
A'B 3
5 A>B
6 'B SIG B
0
O~>---i--I--t--.
INPUTS A<B 2
I ~t-----+--lOUT/IN
7 A<B
IN/OUT IN/OUT
92CS-24664
WORO"B"{~~ :~ B2
SIG 0
OUT/IN
N/OUT
,
,
t
t I
B3
VOO'I6
L-_ _-J
VSS'B
15 Of----"'------'c)-- J
92CS-24~16RI
OUT/IN VOO'24
92CS- 24924RI
VSS'12
SIG C
IN/OUT
200-Stage Dynamic Quad Bilateral Switch 16-Channel

Shift Register 4-Bit Magnitude Comparator Multiplexer/Demultiplexer
C04066A (Page 616)
C04062A (Page 612) C04063B (Page 222) C04066B (Page 226) C04067B (Page 231)
20
Functional Diagrams
VO~
A A~G'A AI
3 J
B "2
B~H'B C 5
B 3 J
•
4 K A
C~I'C 0 6
0
E B 4 K
O~J.5 F 9
10 L
G
E~K'E G 12
11M 10 L
H 13 9
VDO -14
VSS :t 7 6,0> NO CONNECTION F~L'F H
12
VOO'14 J.A(±)B M 'G~H II M
K'C(±)O L • E +F 13
VSS=7 92CS-23731R2 G
92CS· 23874R3
VSS '7
VOO.ll4 92CS- 24~66R2
VSS
92es- 27685
a-Input NAND/AND Gate Hex Inverter Quad Exclusive"OR Gate Quad 2-lnput OR Gate
CD406BB (Page 237) CD4069UB (Page 240) CD4070B (Page 243) CD4071 B (Page 246)
Yoo Vee
14
A
A 9
B 2 9 J
B B -"-+---1
C 8
A
3
o 0
4 6 4 6
E K
5
o
G II I
I
H 10 H 12 10 L
12
H L
G 13
7 G 13
Vss
7
92C5-27686
Vss Vss
92C5-27571 92CS-27587
Dual 4-lnput OR Gate Triple 3-lnput AND Gate Triple 3-lnput OR Gate
CD4072B (Page 246) CD4073B (Page 250) CD4075B (page 246)
AI
OUTPUT 3 J
B 2
OISABLE A
M N C 5
I 2
6
4 K B
0 C
B
E
9
F
G 12 F
II M
H 13 G
J 'A(±)B M'G(±)H VOO'14

K .c(±)o [ 'E(±)F
VSS ·7
15 VSS'8
RESET VOO'16 92CS - 2449 7R2 92CS - 23877R4
92CS-24885RI
4-Bit D-Type Register Quad Exclusive-NOR Gate a-Input NOR/OR Gate

CD4076B (Page 254) CD4077B (Page 243) CD407BB (Page 258)
21
Functional Diagrams
INHIBI:II~IO
BI 2 3 EI
0 CI 12
01 13
INHIBI:!~~
B
A
F 10 B2 6 4 E2
13
II K C2 8
G
02 9
H
E 'INHIBIT+AB+CO
LOGIC I • HIGH
9lCS- V!lBl
LOGIC O!LOW
92CS - 27570
92CS-23890R2
Dual 2-Wide, 2-lnput
AND-DR-INVERT (AD!)
Quad 2-lnput AND Gate Dual4-lnput AND Gate Gate
CD4081B (Page 250) C04082B (Page 250) C04085B (Page 261)
INHIBIT/EXP .::IO~_ _ _ _ _ _---,

J-r::i
A I A
B 2
B H
K M
C L
lOGIC I II HIGH
lOGIC OalOW
F
VOO'14
VOO'II
VSS·7
vss·e E
ENA8LE/EXP,~I~I-------~
92CS-2!m04AI
NC·4
J .INH + ENABLE +AB+CO+EF+GH 92C5- 2 38 70RI

92CS-23880
Expandable 4-Wide, 2-lnput Quad 2-lnput NAND
AND-OR-INVERT (AO!) Binary Rate Multiplier Schmitt Trigger
Gate
CD4086B (Page 265) C04089B (Page 269) C04093B (Page 274)
SET------------, SET - - - - - - - ,
13 13
5 S
Q B Q Q 8 Q
-:7-"---.,CL -;7------1CL
K Q 6 Q K2 K Q 6 Q
R
K3~-u.. __" R
2
RESET ___________-'2 VOO' 14 RESET - - - - - - - ' VOO-14
VSS ·7 VSS -7
PARALLEL OUTPUTS QI- Q8 NC " NC -I
92CS - 244Z7RI
92CS - 24430RI
(TERMINALS 4,5,6,7,14,13,12,11,
RESPECTIVELY)
92CS - 24564RI Gated J-K Master-Slave Gated J-K Master-Slave
8-Stage Shift-and-Store Flip-Flop, Non-Inverting Flip-Flop, Inverting and
Bus Register Inputs Non-Inverting Inputs
C04094B (Page 278) C04095B (Page 282) C04096B (Page 282)
22
Functional Diagrams
VOO
2 RXCxtil
~
4 6
, r: I 1"',
•
+TR 01
t,
5
I -TR MONOI
IN/OUT{{':~~.,
I iii
RESET WRITE DISABLE
a I~ 00
+TR 10 Q2
DATA
L II ~~
A 12 all
-TR :rC 13 04
902 H
140S
15 06
Y
IN/OUT
I
I
""-
-..........
I tOUT/IN
VOO'I6
RXCX (2)
E
S I 07
9ZCS-24425RI
7 I .;>""'"o----J VSS"8
Voo '24 RX2 VOO
Vss=12 92C$ -24980R2 92CS- 24253
Di!ferential 8-Channel Dual Monostable
Multiplexer/Demultiplexer Multivibrator 8-Bit Addressable Latch
C04097B (Page 231) C040988 (Page 286) C04099B (Page 291)
THREE-STATE
OUTPUT ~::::::::::::~----l
OUTPUT 4 DISABLE DISABLEt
OISABLE A DOA
12 OOA
INHI81T 2 3 01
3 01 01 DIA QIA
01 4- BIT 3-STATE
D2A Q?A
4 5 02 LATCH OUTPUTS
6 02 D2 D3A Q3A
p2
2 STROBE
03 6 703
03 D3 RESET
04
10
9
04
04 10 9 04 gl~-r:a~1+----------------,
DOB L__I ~~QOB
II
13 05 DIB QIB
05 D5 12 1105
D2B 4-BIT 3-STATE Q2B
14 LATCH OUTPUT,S
D6 15 06 D3B Q3B
06 14 13 06
STROBE.-.'-_ __
VOO'I6
DIS\BLE 15 RESET L -_ _ _ _ _ _ _ ___
VSS -8
16-VDO a-vSS 92CS-3Z392RI 9ZCS·27494R'
92CS-22921RI
Strobed Hex Inverter/Buffer Hex Buffer Dual 4-Bit Latch

CD4502B (Page 295) 3-State Non-Inverting C04508B (Page 301)
C045038 (Page 298)
BCD 7-SEGMENT
PRESET INPUTS LT OUTPUTS
ENABLE
I I
l
3-STAT[ DISABLE
4 6 INHIBIT - - - - ,
13
PI 01
• 10
r
12 12 b OO_1
P2 02 0 01-2
13 14 0
P3 03 L E R II c 02-3
3 2 A C CHANNEL. D3-4
P4 04 I 10 d INPUTS 04-5
T 0 14 SELECT
2 V D5-6 OUTPUT
VOO -16
c C 0
E 9. 01-7
H E 07-9
15 R 15,
CLOCK R A-II
VSS= 8
UP/DOWN
0 6 14 Q ggrritL { C-13
8-12 VOO-II
vas· •
CARRY IN CARRY OUT
1... CD4!S128
92CS - 25083R2
RESET ¥SS"a
VDO'16
BCD Presettable Up/Down BCD-to-7-Segment

Counter Latch Decoder Driver 8-Channel Data Selector
C04510B (Page 305) C045118 (Page 311) C045128 (Page 316)
23
Functional Diagrams
VOO'24
I~ 50 PRE5ET
V55' 12 ENABLE
10 51
8 52 6
PI QI DMA(OU
7 53
12 WRITE
6 54 P2 Q~
14 ENABLE
2 5 55 13
DATA I P3 Q3
4 56 3 2
3 P4 Q4
DATA 2 4 TO 16 18 S7 WE- 0-- QI6---Q32---Q48---Q64
21 DECODER 17 58
DATA 3 VOO cl6 WE= 1----OI7---033---049--HiZ
20 S9 15
OATA4 22 CLOCK I OF 2 SHIFT REG.ISTER5. TERM. NaI.
STROBE
I 19 ~:? UP/DOWN
10
VSS= 8
IN PARENTHESES ARE FOR 2 ND NALF.
14
13
SI2 5 VOO'16 vSS"e
16
SI3 CARiiYiN CARRY OUT
514
15 92CS-30371
SI5 RESET 92CS·24824
INHIBIT -,2::3't=====::::'.._~
92CS - 24597
4-Bit Latch/4-to-16 Binary Presettable Up/Down

Line Decoder Counter Dual 64-Bit Shift Register
Output "High" on Select Output "Low" on Select
CLOCK A 3 QIA
I +1%16 4 Q2A
5 Q3A STROBE
Cl.OCK
6 Q4A to CASCADE
RESET A INHIBIT
•• RATE
OUTPUTS
7--------' (CARRY) IN II +10
II QIB S~TNTf 4 c
0
.OUT~
U 5 OUT
'2 Q2B CLEAR I N
+1%16 T
13 Q3B E
R
14 Q4B
INHIBIT {CARRY} OUT
RESET B VOO" 1&
t;t2CS-24913RI
15 - - - - - - - - ' VSS'8 vDD- 16
92CS-26360fU
9lCS-Z4506RI VSSR8
Dual Up Counter
CD4518B (P~ge 328)
BCD
CD45?OB (Page 328) BCD Rate Multiplier 8-Bit Priority Encoder
Binary
C04527B (Page 333) (Page 338)
CD4532B
12
eXI A
13
Voo
RTC
eTC
+TR 0, RS Q
-TR AR
RESET 7 OJ MR
10
MODE
o~
+TR 10 A. SELECT
-TR Voo' PIN 14
RESET 9 iii VSS • PIN 7
92C9-35066
'-il-<......V\f\r-.VOO
ex.
VOo'16 vSS"e 92CS-50573 92CS-242!53
Programmable Timer Dual Precision Monostable Programmable Timer

CD4536B (Page 342)
Multivibrator
CD4536B (Page 350) CD4541B (Page 356)
24
Functional Diagrams
IobD
16
4
A A QO
5 QI
LATCH BDC DISPLAY B 6
B TO DRIVER Q2
7-SEGMENT E 7
Q3
C DECODER
7 SEGMENT 12
OUTPUTS A 14 QO
"
•
D 13 QI
B 10 Q2
15
9 Q3
LD 92CS -2291BRI
BL
92CS-34515
Ph Dual Binary-to-1-of-4
Decoder/Demultiplexer
BCD-to-7-Segment Latch/Decoder/Driver Output "High" on Select
(Page 360) CD4555B (Page 366)

CD45438
14
WORD"A"{:~ '~
4 Qo WRITE DISABLE QO
A 2 13 & 5 QI
5 DATA
B
3 Cii A2 2 6
6 Q2 L Q2
A3 15 7 Q3
E 7 AD I DE A
is! A>B 4 13 A>8 T
AI2 & 9 Q4
C
12 IRl CASCADING { A' B 3 A"8 COD 10
A 14 INPUTS A<B 5 12 A<8 42 3 H Q5
ER E
B
13 " OJ S
"Q6
WORD"8"{:~ '~
10 02 15
15 RESET 12 Q7
E 9 03
:~ 14 VDD"'6
VSS"& 92CS-30372
L--_--'
92CS-.22919RI VDD" 16 VSS·&
92CS-3037!5
Dual Binary-to-1-of-4
Decoder/Demultiplexer
Output "Low" on Select 4-Bit Magnitude Comparator a-Bit Addressable Latch
CD4556B (Page 366) CD4585B (Page 371) CD4724B (Page 375)
STROBE
DATA
IN [82f~I02.
r---~-----,p---...,...--o15 21 YI
VI 'Kb Ka'
SIGNALS
OUT (IN)
v, " 16 Y3
23
17 Y4
D
I
10 jB e
E
0
" Ie 2
D
E
16
•
S
4 VI'
r-t--.-I---...+...,...-I-+:-!5V2'
SIGNALS
OUT (IN)
9 Y3'
X2
I
"
12
" B Y4'
4-by-4 Crosspoint Switch 4-by-4-by-2 Crosspoi nt Switch

with Control Memory with Control. Memory
CD22100 . (Page 636) CD22101 (Page 641)
CD22162 (Page 641)
25
F~nctional Diagrams
2 15
CTX +HDB3 OUT
NRZ IN
I J TRANSMITTER I 14
HDB3 OUT DATA }
Ol SEGMENT
OUTPUTS
INPUTS
H D 83/Aii'i
3 T 10
CKR
II
1 1
02 SEGMENT
+HDB3 IN
13 :1 RECEIVER I 4
NRZ OUT
DIGIT
SELECT
} OUTPUTS
-HDB3 IN
I INPUTS
~.! . . ,
12
LTE
03 SEGMENT
} OUTPUTS
OSCILLATOR
5 9 INPUT 36
CRX ERR
6 :1 US 1 7
A:tS
04 SEGMENT
DETECT } OUTPUTS
VOO-16 BACKPLANE
INPUT IOUTPUT
VSS·8 92 CS - 36527
92CS-33rOI
HDB3 Transcoder
4-DIglt Decoder Driver
CD22103 (Page 649) CD22104 (Page 656) CD22104A (Page 656)
Hexadecimal Display Decimal Display
I Voo 35 VSS
40 Vee
39 14
38 } 01 SEGMENT
27 37 OUTPUTS
DATA 28 4
INPUTS 29 3
30 2
12
DIGIT
SELECT {
CODE
31
32
II
10
9
8
7
_
} 02 SEGMENT
OUTPUTS
AL80
OUTPUTS lJ 2r+-------i
~~~ECT{
33
34 6
19
18
17
16 }03 SEGMENT
15 OUTPUTS
f-------+-{13
OSCILLATOR
14
36 13
INPUT 26 PHASE
25 SHIFT
2.
23 }04 SEGMENT
22 OUTPUTS
21
20 f------+-<112
5 BACKPLANE
INPUT fOUTPUT
PREAMP { 5
INPUT
9ZCS-33100
GLSE
4-DIglt Decoder Driver
CD22105 (Page 661)

PREAMP{
OUTPUT
7
)-f-'~----~-j
[M
I\
Hexadecimal Display
CD22105A (Page 661)

PCM Line Repeater
Decimal Display
CD22301 (Page 666)
26
Functional Diagrams
3e
EP5 37
Q'
EP4 Q2
{~~~
36
m _Q3 4 AO }
OPAMP
El'2 Q4 A°r.\'P 5 BO OUTPUTS
INPUTS B- 7 C022413
rn Q5
Bt C022414
016 Q6
017 Q7
FILTER lTXI 13 12 LPOI} FILTER
I
S'R'"CLR Q8
INPUTS RXI 15 TXO OUTPUTS
SR elK Q9 14 RXO
QIO TlMI lceI"
Sf INPt/¥ MSI 10
TMR eLK QII
INH QI2
QI3 's'FtYH-!VLS 9
TGI INPUT -,-----'
TBI QI4 Voo "6 VSs'B VAG' I
QI5 92CS-33227
QI6
QI7
817
of> TEST
TOI
T02
OTO 16-Channel Precision Pulse Code Modulation
BOI Timer/Driver Sampled - Data Filters
TEl
CD22413 (Page 676)
92CS- 36526 CD22401 (Page 670)
CD22414 (Page 676)
INHIBIT
CI 8-{)o---,
LEFT/RIGHT 01 I
VOUT CONTROL
02 o
SHifT 13 SHIFT
RIGHT RIGHT 03 3 E
IN OUT
II 12
CLOCK 044 C
RI VOO 3
CLOCK SHin 0510 o
R2 --0 INHIBIT LEFT
4
OUT
06 " o
SHIFT 2
R3
IN~6 0712
VOO"6
R4 NC'I,5,7, 9 vss,a 0813
RX 10,14,15
10 RECIRCULATE 095
CONTROL 92CS- 27567 92CS-21391
OSC I MUTE
TX
CONTROL
OSC 2 2 32-Stage Static
LefVRight Shift 9-Blt Parity Generator/Checker
Register
VSS
Dual-Tone Multlfrequency Tone Generator 92CM-33099
CD22859 (Page 683) CD40100B (Page 379) CD40101B (Page 384)
OUTPUT 3-STATE
ENABLE
15 13
DO
3 QO DO QO
4 14 5 12
01 QI 01 QI
13 6
02
12
Q2
Q3
02
7
"
10
Q2
SHIFTD3 03 Q3
CD40102B (Page 387)
IN LEFT
2-Decade BCD SHIFT 3 14 DATA-OUT
SHIFT IN READY
IN RIGHT 2 15
DATA-IN
a-STAGE SHIFT OUT
READY
~OWN MODE {SO
CD40103B (Page 387) "SELECT SI 10 VOO"'6 9
COUNTER VSS"B Voo" 16
CO/ZO ,4 MASTER
8-Bit Binary II 92CS-24a162R2 RESET
VSS' B
CLOCK
92CS-27282
92CS-2BSIIRI
4-Bit Universal Bidirectional FIFO Register
Shift Register 4-Blts Wide by 16-Blls Long
a-Stage Presettable 3-State Outputs
Synchronous Down Counter CD40104B (Page 394) CD40105B (Page 401)
27
Functional Diagrams
A~G"ii ,lSI
WRITE
ENABLE 3-STATE A
C"A'8
B~H"i II'I~ i'.. 1f---"9 DO 19

·~ 00}
2141~ DATA { 01 QI WORD A
~2:~
C~I"t:"
VSS INPUTS QZ OUTPUT
Q'
a
O~J"1i
WAITE
5191 WRITE I
71111~ 19~'o:E
2.
E~K"1
i'.. READ IA
61'OI~ READ OA
"
13
2'
OO}
01
Q?
WOAD B
OUTPUT
VSS
F~L"F
10
92cs-29434RZ
READ 18
READ OB 0'
VOO" '4 NOTE: "
VOD~ 24
VSS.7 92CS-28682 NUMBERS IN PARENTHESES FOR CD40107BF, CLOCK 3-STATE 8
OTHERS FOR C0401078E Vss ~ 12
92CS 2.S'<}Al
Hex Schmitt Trigger Dual 2-lnpul NAND 4-by-4 Multiporl Register

Buffer/Driver
C0401068 (Page 406) C0401078 (Page 410) C0401088 (Page 413)
CLOCK UP
CLOC)!; DOWN I "l':':':=='-'-'-="-'
RESET-+--------"
TOGGLE_+-_ _ _ _ _ _~
Vcc Voo ENABLE
LATCH ENABLE -1-------+1
ENABLE
2,7,9,15
--Vee
NC "2 92C5-292oo
VOO'I6 - - -Vss
vss ~ 8
92C5- 26669RI
Vec" Vss Decade Up-Down Counter/
Decoder/Latch/Driver
Quad Low-Io-High
Vollage Level Shifter
C0401098 (Page 418) C0401108 (Page 422)
CONTROL
/ STROBE' DATA \
• A
I. T
4 PULL -uP OR E
2. R
PULL - DOWN
RESI STQRS
,. ,
M
N
4 LATCHES
OR 4. •
T
o
16 R
4 PULL-UP OR 5
26 T
PULl- DOWN
RESISTORS
o
Voo" 1
VOO"
OR
'6 6
U
VCC'22 4 LATCHES
46 5
VCC- 22 92CS-32569RI E
92C5- 30246 Vss,",12 5
Vss" II
STROBE DATA
6 6
8-BII Universal Bidirectional 8-Bil Universal Bidirectional 92CS-35283
CMOS/TTL Level Converter CMOS/TTL Level Converter

Programmable Dual 4-811
C040115 (Page 687) C040116 (Page 689) Terminator
C0401178 (Page 431)
28
Functional Diagrams
7 14 Ol----''---~
PE 01
10
TE
13
lliAR 02 02 4
9
LOAD
0" 12
CLOCK 03
u l
03 6
I
82' PI
,,0 4 II
P2 04
5
P3 04 II
6 15 CARRY
P4
OUT
05 13
92CS - 2e62BRI 06 14
10-Line-to-4-Line CLOCK --=9'-1--+-l
BCD Priority Encoder Synchronous 4-Bit Counter ~--'~~ ______J
CD40162B (Page 438) CD40160B (Page 438)
VSs·8
CD40147B (Page 435) Decade with Synchronous Decade with Asynchronous 92(S-29231
VOO" 16
Clear Clear
CD40163B (Page 438) CD40161 B (Page 438) Hex "0" Type Flip-Flop
Binary with Synchronous Binary with Asynchronous CD40174B (Page 445)
Clear Clear
4
01- 01
~
Ql ,o
02
5 7
6
02 WORO AI
2
23 , 1!L}FI OUTPUT
A A2: 21 F2 FUNCTION
Q2
Al 15
12 10 SO ,
"
03 03 14 A_a COMPARE
Q3 em
WORD{ 81 22
B 8L 20 16n+4RIPPLE
15 CARRY
04 04 B318 0",
14
Q4 CARRY'"
MODE
COIliTROL
~ 8
CARRY IN " G} LOOK
I~ P AHEAD
MODE M
CLOCK 9 1100';>4 CARRY
CONTROL OUTPUTS
I Vss"S IISS"2
CLEAR VOO'24
VOO"'6 VSS"Z
92CS-3450B
Quad "D"-Type Flip-Flop 4-Bit Arithmetic Logic Unit
CD40175B (Page 449) Active-Low Data Active-High Data

CD40181B (Page 455)
r
_ Gi
_
G2
G3
12
en -+X
J I 15
J2
J3 'O
1
01
02
DO
01
r---1~-'15
00
01
r
"
0' 13
II 02 02
J4 9 7 O.
4 en +'f 03 12
03
9 CLOCK uP 5 13 BORROW
_ Pi en + Z 12 CARRY
SHIFT
CLOCK DOWN IN LEFT
P - SHIFT
P2 IN RIGHT 2
RESET " 1100= 16
P3 P "ss· B
10
MODE {SO 1100 ~ 16
CARRY IN Cn 13 92CS- 27561RI SELECT 5, 10
G
VSS "B
VOO,'6 Presettable Up/Down Counter
VSS=8 92CS-24826Rr (Dual Clock with Reset) CLOCK
CD40192B (Page 464) 4-Bit Universal Bidirectional Shift

Look-Ahead Carry Generator
BCD Register with Asynchronous Master Reset
CD40182B (Page 460) CD40193B (Page 464)
CD40194B (Page 394)
Binary
29
Functional Diagrams
OUTPUT
WRITE DISABLE
ENABLE ENABLE A
DATA 15
.
r
INPUTS
~}
20
I.
01 5 01 WORD A VDO
18
02
03
17 7
02
03
OUTPUT
d
WRITE 0
~4
WRITE I • 9
"~}
I. Vss
REAO I A
READ OA
13 23 01
2 02
WORD B
OUTPUT ,
. '2
02
B2
READ 18
READ 08
"
10
I 03
3 ADDITIONAL IDENTICAL CIRCUITS
I. 21 92CS-Z854,RI
10
B, 0'
9
Veo· 24 CLOCK ENABLE B A.
YSS = 12 14
B. D.
13 12
4·bV·4 Multiport Register . Quad 2·Line·to·1·Line
CD40208B (Page 469) Data Selector/Muhiplexer '32CM-2B1"4IRI
CD40257B (Page 474)
VDD
@ VDD-@~~~m
OVERFLOW
MSB MSB
6-BIT B-BIT
PARALLEL PARALLEL
OUTPUT OUTPUT
LSB
LSB
sCEi
5 CE2
ANALOG DIGITAL
GROUND t GROUND
ZENER VSS CLOCK PHASE REF-
.2CS-3Ga81 4i> @) @) ®
DIODE AGND CLOCK PHASE -REF VSS
.2CS·,GBB2
8-BII FI••h AID Converter 8-BII FI..h AID Converter
CA3300 (Page 620) CA3308 (Page 831)

CA330BA (Page 631)
30
Cross-Reference Guide
•
This guide provides a quick reference to a wide variety of industry CMOS logic
integrated circuits that can be replaced by RCA types.
The RCA types listed as replacements are electrically and mechanically equivalent to
the corresponding industry types and can be used as direct replacements in most
applications. The recommendations are based on the electrical and mechanical data
published by various solid-state device manufacturers.
Before substituting any replacement type in a particular application, the user should
review the operating conditions of the particular application with the specifications of
the type he is planning to use as the substitute type.
RCA RCA RCA

Industry Replacement Industry Replacement Industry Replacement
Type Type Type Type Type Type
CD4000CN CD4000AE CD4010MJ CD4010AF CD4017BMD CD4017BD

CD4000MD CD4000AD CD4011BCJ CD4011 BF CD4017BMJ CD4017BF
CD4000MJ CD4000AF CD4011BCN CD4011BE CD4018BCN CD4018BE
CD4OO1BCJ CD4OO1BF CD4011BMD CD4011BD CD4018BMD CD4018BD
CD4OO1BCN CD4OO1BE CD4011BMJ CD4011 BF CD4018BMJ CD4018BF
CD4OO1BMD CD4OO1BD CD4012BMD CD4012BD CD4019BCJ CD4018BF
CD4OO1BMJ CD4OO1BF CD4012CN CD4012AE CD4019BCJ CD4019BE
CD4OO2BCJ CD4OO2BE CD4012MD CD4012AD CD4019BMD CD4019BD
CD4OO2BCN CD4OO2BE CD4012MJ CD4012AF CD4019BMJ CD4019BF
CD4OO2BMD CD4OO2BD CD4013BCJ CD4013BF CD4020BCJ CD4020BF
CD4OO2BMJ CD4OO2BF CD4013BCN CD4013BE CD4020BCN CD4020BE
CD4OO2CN CD4OO2AE CD4013BMD CD4013BD CD4020BMD CD4020BD
CD4OO2MD CD4OO2AD CD4013BMJ CD4013BF CD4020BMJ CD4020BF
CD4OO2MJ CD4OO2AF CD4014BCJ CD4014BF CD4021BCJ CD4021BF
CD4OO6BCJ CD4OO6BF CD4014BMD CD4014BD CD4021BCN CD4021BE
CD4OO6BCN CD4OO6BE CD4014BMJ CD4014BF CD4021BMD CD4021BD,
CD4OO6BMD CD4OO6BD CD4014CN CD4014AE CD4021BMJ CD4021BF
CD4OO6BMJ CD4OO6BF CD4014MD CD4014AD CD4021CN CD4021AE
CD4OO6CN CD4OO6AE CD4014MJ CD4014AF CD4021MD CD4021AD
CD4OO6MD CD4OO6AD CD4015BCJ CD4015BF CD4021MJ CD4021AF
CD4OO6MJ CD4OO6AF CD4015BCN CD4015BE CD4022BCJ CD4022BF
CD4OO7CN CD4OO7AE CD4015BMD CD4015BD CD4022BCN CD4022BE
CD4OO7MD CD4OO7AD CD4015BMJ CD4015BF CD4022BMD CD4022BD
CD4OO7MJ CD4OO7AF CD4015CN CD4015AE CD4022BMJ CD4022BF
CD4OO7UBMD CD400lUBD CD4015MD CD4015AD CD4023BCJ CD4023BF
CD4OO7UBCN CD4OO7UBE CD4015MJ CD4015AF CD4023BCN CD4023BE
CD4OO8BCJ CD4OO8BF CD4016BCJ CD4016BF CD4023BMD CD4023BD
CD4OO8BCN CD4OO8BE CD4016BCN CD4016BE CD4023BMJ CD4023BF
CD4OO8BMD CD4OO8BD CD4016BMD CD4016BD CD4023CN CD4023AE
CD4OO8BMJ CD4OO8BF CD4016BMJ CD4016BF CD4023MD CD4023AD
CD4OO9CN CD4OO9AE CD4016CN CD4016AE CD4023MJ CD4023AF
CD4OO9MD CD4OO9AD CD4016MD CD4016AD CD4024BCJ CD4024BF
CD4OO9MJ CD4OO9AF CD4016MJ CD4016AF CD4024BCN CD4024BE
CD4010CN CD4010AE CD4017BCJ CD4017BF CD4024BMD CD4024BD
CD4010MD CD4010AD CD4017BCN CD4017BE CD4024BMJ CD4024BF
31
RCA RCA RCA
CD4025BCJ CD4025BF CD4046BCN CD4046BE CD4073BCJ CD4073BF

CD4025BCN CD4025BE CD4046BMD CD4046BD CD4073BCN CD4073BE
CD4025BMD CD4025BD CD4046BMJ CD4046BF CD4073BMD CD4073BD
CD4025BMJ CD4025BF CD4047BCN CD4047BE CD4073BMJ CD4073BF
CD4025CN CD4025AE CD4047BMD CD4047BD CD4075BCJ CD4075BF
CD4025MD CD4025AD CD4047BMJ CD4047BF CD4075BCN CD4075BE
CD4025MJ CD4025AF CD4048BCJ CD4048BF CD4075BMD CD4075BD
CD4027BCJ CD4027BF CD4048BCN CD4048BE CD4075BMJ CD4075BF
CD4027BCN CD4027BE CD4048BMD CD4048BD CD4076BCJ CD4076BF
CD4027BMD CD4027BD CD4048BMJ CD4048BF CD4076BCN CD4076BE
CD4027BMJ CD4027BF CD4049BMD CD4049UBD CD4076BMD CD4076BD
CD4027DM CD4027BD CD4049BPC CD4049UBE CD4076BMJ CD4076BF
CD4028BCJ CD4028BF CD4049CN CD4049AE CD4081BCJ CD4081BF
CD4028BCN CD4028BE CD4049MD CD4049AD CD4081BCN CD4081BE
CD4028BMD CD4028BD CD4049MJ CD4049AF CD4081BMD CD4081BD
CD4028BMJ CD4028BF CD4050BCJ CD4050BF CD4081BMJ CD4081BF
CD4029BCJ CD4029BF CD4050BCN CD4050BE CD4089BCJ CD4089BE
CD4029BCN CD4029BE CD4050BMD CD4050BD CD4089BMD CD4089BD
CD4029BMD CD4029BD CD4050BMJ CD4050BF CD4089BMJ CD4089BF
CD4029BMJ CD4029BF CD4051BCJ CD4051BF CD4093BCJ CD4093BF
CD4030BMD CD4030BD CD4051BMD CD4051BD CD4093BCN CD4093BE
CD4030MD CD4030AD CD4051BMJ CD4051BF CD4093BMD CD4093BD
CD4030MJ CD4039AF CD4052BCJ CD4052BF CD4093BMJ CD4093BF
CD4031BCN CD4031BE CD4052BCN CD4052BE CD4099BCJ CD4099BF
CD4031BDM CD4031BD CD4052BMD CD4052BD CD4099BCN CD4099BE
CD4031BMD CD4031BD CD4052BMJ CD4052BF CD4099BMD CD4099BD
CD4031BMJ CD4031BF CD4053BCJ CD4053BF CD4099BMJ CD4099BF
CD4034BCN CD4034BE CD4053BCN CD4053BE CD4503BCJ CD4503BF
CD4034BMD CD4034BD CD4053BMD CD4053BD CD4503BCN CD4503BE
CD4034BMJ CD4034BF CD4053BMJ CD4053BF CD4503BMJ CD4503BF
CD4035BCN CD4035BE CD4060BCJ CD4060BF CD4503BMD CD4503BD
CD4035BMD CD4035BD CD4060BCN CD4060BE CD4510BCJ CD4510BF
CD4035BMJ CD4035BF CD4060BMD CD4060BD CD4510BCN CD4510BE
CD4040BCJ CD4040BF CD4060BMJ CD4060BF CD4510BMD CD4510BD
CD4040BCN CD4040BE CD4066BCJ CD4066BF CD4510BMJ CD4510BF
CD4040BMD CD4040BD CD4066BCN CD4066BE CD4511BCJ CD4511BF
CD4040BMJ CD4040BF CD4066BMD CD4066BD CD4511BCN CD4511BE
CD4041BMD CD4041UBD CD4066BMJ CD4066BF CD4511BMD CD4511BD
CD4041CJ CD4041 UBF CD4066BPC CD4066BE CD4512BCJ CD4512BF
CD4041CN CD4041AE CD4069CN CD4069AE CD4512BCN CD4512BE
CD4041MD CD4041AD CD4069MD CD4069AD CD4512BMD CD4512BD
CD4041MJ CD4041AF CD4069MJ CD4069AF CD4512BMJ CD4512BF
CD4042BCJ CD4042BF CD4069UBMD CD4069UBD CD4514BCJ CD4514BF
CD4042BCN CD4042BE CD4070BCJ CD4070BF CD4514BCN CD4514BE
CD4042BMD CD4042BD CD4070BCN CD4070BE CD4514BMD CD4514BD
CD4042BMJ CD4042BF CD4070BMD CD4070BD CD4514BMJ CD4514BF
CD4043BMD CD4043BD CD4070BMJ CD4070BF CD4515BCJ CD4515BF
CD4043CN CD4043AE CD4070CN CD4070AE CD4515BCN CD4515BE
CD4043MD CD4043AD CD4070MD CD4070AD CD4515BMD CD4515BD
CD4043MJ CD4043AF CD4070MJ CD4070AF CD4515BMJ CD4515BF
CD4044BMD CD4044BD CD4071BCJ CD4071BF CD4516BCJ CD4516BF
CD4044CN CD4044AE CD4071BCN CD4071BE CD4516BCN CD4516BE
CD4044MD CD4044AD CD4071BMD CD4071BD CD4516BMD CD4516BD
CD4044MJ CD4044AF CD4071BMJ CD4071BF CD4516BMJ CD4516BF
CD4045BMD CD4045BD CD4072BMD CD4072BD CD4518BCJ CD4518BF
32
RCA RCA RCA
CD4518BCN CD4518BE CD40175BCN CD40175BE F4021BDM CD4021BF

CD4518BMD CD4518BD CD40192BCJ CD40192BF F4021BPC CD4021BE
CD4518BMJ CD4518BF CD40192BCN CD40192BE F4022BDC CD4022BF
CD4520BCJ CD4520BF CD40192BMD CD40192BD F4022BDM CD4022BF
CD4520BCN CD4520BE CD40192BMJ CD40192BF F4022BPC CD4022BE
CD4520BMD CD4520BD CD40193BCJ CD40193BF F4023BDC CD4023BF
CD4520BMJ CD4520BF CD40193BCN CD40193BE F4023BDM CD4023BF
CD4527BCJ CD4527BF CD40193BMD CD40193BD F4023BPC CD4023BE
CD4527BCN CD4527BE CD40193BMJ CD40193BF F4024BDC CD4024BF
CD4527BMD CD4527BD F4001BDC CD4001BF F4024BDM CD4024BF
CD4528BCJ CD4528BF F4001BDM CD4001BF F4024BPC CD4024BE
CD4528BCN CD4528BE F4001BPC CD4001BE F4025BDC CD4025BF
CD4528BMJ CD4528BF F4002BDM CD4002BF F4025BPC CD4025BE
CD4538BCJ CD4538BF F4002BPC CD4002BE F4027BDC CD4027BF
CD4538BCN CD4538BE F4006BDC CD4006BF F4027BDM CD4027BF
CD4538BCN CD4538BE F4006BDM CD4006BF F4027BPC CD4027BE
CD4538BMD CD4538BD F4006BPC CD4006BE F4028BDC CD4028BF
CD4538BMJ CD4538BF F4007UBDC CD4007UBF F4028BDM CD4028BF
CD4543BCJ CD4543BF F4007UBDM CD4007UBF F4028BPC CD4028BE
CD4543BCN CD4543BE F4007UBPC CD4007UBE F4029BDC CD4029BF
CD4724BCN CD4724BE F4011BDC CD4011 BF F4030BDM CD4030BF
CD4724BMD CD4724BD F4011 BDM CD4011 BF F4030BPC CD4030BE
CD4724BMJ CD4724BF F4011BPC CD4011 BE F4031BDC CD4031BF
CD40106BCJ CD40106BF F4012BDC CD4012BF F4031BDM CD4031BF
CD40106BMJ CD40106BF F4013BDC CD4013BF F4034BDM CD4034BF
CD40161BCJ CD40161BF F4014BPC CD4014BE: F4040BDC CD4040BF
CD40161BCN CD40161BE F4015BDC CD4015BF F4040BDM CD4040BF
CD40161B'MD CD40161BD F4015BDM CD4015BF F4040BPC CD4040BE
CD40161BMJ CD40161BF F4015BPC CD4015BE F4041BDC CD4041BF
CD40162BCN CD40162BE F4016BDM CD4016BF F4041 BPC CD4041 BE
33
RCA RCA RCA
F4046BPC CD4046BE F4081BDC CD4081BF F4556BDM CD4556BF

F4047BDC CD4047BF F4081BDM CD4081BF F4556BPC CD4556BE
F4047BDM CD4047BF F4081BPC CD4081BE F4581BDC CD40181BF
F4049BDC CD4049UBF F4082BDM CD4082BF F4581BPC CD40181 BE
F4049BDM CD4049UBF F4082BPC CD4082BE F4582BDC CD40182BF
F4049BPC CD4049UBF F4085BDC CD4085BF F4582BDM CD40182BF
F4052BCD CD4052BF F4093BDM CD4093BF F40160BPC CD40160BE
F4053BDC CD4053BF F4510BDM CD4510BF F40161BPC CD40161 BE
F4066BDC CD4066BF F4511BDM CD4511 BF F40162BPC CD40162BE
F4066BDM CD4066BF F4511 BPC CD4511BE F40163BDC CD40163BF
F4069UBDC CD4069UBF F4515BDM CD4515BF F40175BPC CD40175BE
F4069UBDM CD4069UBF F4515BPC CD4515BE F40192BDC CD40192BF
F4069UBPC CD4069UBE F4516BDC CD4516BF F40192BDM CD40192BF
F4071BDM CD4071BF F4518BPC CD4518BE HCF4000BD CD4000BD
F4071BPC CD4071BE F4520BDC CD4520BF HCF4000BE CD4000BE
F4072BDC CD4072BF F4520BDM CD4520BF HCF4000BF CD4000BF
F4072BDM CD4072BF F4520BPC CD4520BE HCF4001BD CD4001 BD
F4073BDM CD4073BF F4527BPC CD4527BE HCF4001BE CD4001BE
F4073BPC CD4073BE F4532BDC CD4532BF HCF4002BD CD4002BD
F4075BDM CD4075BF F4532BPC CD4532BE HCF4002BE CD4002BE
F4075BPC CD4075BE F4538BDC CD4538BF HCF4006BD CD4006BD
F4076BDM CD4076BF F4538BPC CD4538BE HCF4007UBD CD4007UBD
F4076BPC CD4076BE F4543BDC CD4543BF HCF4007UBE CD4007UBE
F4077BDC CD4077BF F4543BDM CD4543BF HCF4007UBF CD4007UBF
34
RCA RCA RCA
HCF4011BF CD4011BF HCF4030BD CD4030BD HCF4052BE CD4052BE

HCF4012BD CD4012BD HCF4030BE CD4030BE HCF4052BF CD4052BF
HCF4012BE CD4012BE HCF4030BF CD4030BF HCF4053BD CD4053BD
•
HCF4018BF CD4018BF HCF4041UBD CD4041UBD HCF4066BE CD4066BE
HCF4019BD CD4019BD HCF4041UBE CD4041 UBE HCF4066BF CD4066BF
HCF4019BE CD4019BE HCF4041UBF CD4041UBF HCF4067BD CD4067BD
HCF4021BE CD4021BE HCF4043BF CD4043BF HCF4069UBD CD4069UBD
HCF4021BF CD4021BF HCF4044BD CD4044BD HCF4069UBE CD4069UBE
HCF4022BD CD4022BD HCF4044BE CD4044BE HCF4069UBF CD4069UBF
HCF4023BE CD4023BE HCF4045BF CD4045BF HCF4071BD CD4071 BD
HCF4026BF CD4026BF HCF4049UBD CD4049UBD HCF4075BE CD4075BE
HCF4027BD CD4027BD HCF4049UBE CD4049UBE HCF4075BF CD4075BF
HCF4027BE CD4027BE HCF4049UBF CD4049UBF HCF4076BD CD4076BD
35
RCA RCA RCA
HCF4078BF CD4078BF HCF4515BD CD4515BD HEF4015B CD4015BE

HCF4081BD CD4081 BD HCF4515BE CD4515BE HEF4016B CD4016BE
HCF4081BE CD4081BE HCF4515BF CD4515BF HEF4017B CD4017BE
HCF4081 BF CD4081BF HCF4516BD CD4516BD HEF4018B CD4018BE
HCF4082BD CD4082BD HCF4516BE CD4516BE HEF4019B CD4019BE
HCF4082BF CD4082BF HCF4518BD CD4518BD HEF4021 B CD4021BE
HCF4095BF CD4095BF HD14503B CD4503BE HEF4049B CD4049UBE
, HCF4096BD CD4096BD HD14541B CD4541 BE HEF4050B CD4050BE
HCF4096BE CD4096BE HD174C04 CD4096BD HEF4051B CD4051BE
HCF4096BF CD4096BF HD174C14 CD40106BD HEF4052B CD4052BE
HCF4097BD CD4097BD HD174C86 CD4030BD HEF4053B CD4053BE
HCF4097BE CD4097BE HD174C86 CD4070BD HEF4059B CD4059BE
HCF4097BF CD4097BF HD374C04 CD4069BE HEF4060B CD4060BE
HCF4098BD CD4098BD HD374C14 CD40106BE HEF4066B CD4066BE
HCF4098BE CD4098BE HD374C160 CD40160BE HEF4067B CD4067BE
HCF4099BD CD4099BD HD374C162 CD40162BE HEF4069UB CD4069UBE
HCF4099BF CD4099BF HD374C164 CD4015BE HEF4071 B CD4071BE
HCF4508BF CD4508BF HEF4000B CD4000BE HEF4078B CD4078BE
HCF4510BD CD4510BD HEF4000BD CD4000BE HEF4081B CD4081BE
HCF4510BE CD4510BE HEF4001 B CD4001BE HEF4082B CD4082BE
HCF4510BF CD4510BF HEF4001UB CD4001UBE HEF4085B CD4085BE
HCF4511BD CD4511BD HEF4002B CD4002BE HEF4086B CD4086BE
HCF4511BE CD4511BE HEF4006B CD4006BE HEF4093B CD4093BE
HCF4511BF CD4511BF HEF4007UB CD4007UBE HEF4094B CD4094BE
HCF4512BD CD4512BD HEF4008B CD4008BE HEF4502B CD4502BE
HCF4512BE CD4512BE HEF4011B CD4011 BE HEF4508B CD4508BE
HCF4512BF CD4512BF HEF4011UB CD4011 UBE HEF4510B CD4510BE
HCF4514BD CD4514BD HEF4012B CD4012BE HEF4511B CD4511 BE
HCF4514BE CD4514BE HEF4013B CD4013BE HEF4512B CD4512BE
HCF4514BF CD4514BF HEF4014B CD4014BE HEF4514B CD4514BE
36
RCA RCA RCA
HEF4515B CD4515BE MC14010BCP CD4010BE MC14025UBAL CD4025UBF

HEF4516B CD4516BE MC14011BAL CD4011 BF MC14025UBCL CD4025UBF
•
HEF4517B CD4517BE MC14011BCL CD4011 BF MC14025UBCP CD4025UBE
HEF4518B CD4518BE MC14011BCP CD4011 BE MC14027BAL CD4027BF
HEF4520B CD4520BE MC14011 UBAL CD4011UBF MC14027BCL CD4027BF
HEF4527B CD4527BE MC14011UBCL CD4011UBF MC14027BCP CD4027BE
HEF4532B CD4532BE MC14011 UBCP CD4011UBE MC14028BAL CD4028BF
HEF4538B CD4538BE MC14012BAL CD4012BF MC14028BCL CD4028BF
HEF4541B CD4541BE MC14012BCL CD4012BF MC14028BCP CD4028BE
HEF4543B CD4543BE MC14012BCP CD4012BE MC14029BAL CD4029BF
HEF4555B CD4555BE MC14012UBAL CD4012UBF MC14029BCL CD4029BF
HEF4556B CD4556BE MC14012UBCL CD4012UBF MC14029BCP CD4029BE
HEF4585B CD4585BE MC14012UBCP CD4012UBE MC14032BAL CD4032BF
HEF40161B CD40161 BE MC14013BCP CD4013BE MC14034BAL CD4034BF
MC14000BAL CD4000BF MC14016BCL CD4016BF MC14038BCP CD4038BE
MC14000BCL CD4000BF MC14016BCP CD4016BE MC14040BAL CD4040BF
MC14000BCP CD4000BE MC14017BAL CD4017BF MC14040BCL CD4040BF
MC14000UBAL CD4000UBF MC14017BCL CD4017BF MC14040BCP CD4040BE
MC14000UBCL CD4000UBF MC14017BCP CD4017BE MC14042BAL CD4042BF
MC14000UBCP CD4000UBE MC14018BAL CD4018BF MC14042BCL CD4042BF
MC14001 BAL CD4001BF MC14018BCL CD4018BF MC14042BCP CD4042BE
MC14001 UBAL CD4001UBF MC14019BCL CD4019BF MC14043BCP CD4043BE
MC14001UBCL CD4001UBF MC14019BCP CD4019BE MC14044BAL CD4044BF
MC14001 UBCP CD4001UBE MC14020BAL CD4020BF MC14044BCL CD4044BF
MC14002BAL CD4002BF MC14020BCL CD4020BF MC14044BCP CD4044BE
MC14002UBAL CD4002UBF MC14021BCL CD4021BF MC14046BCP CD4046BE
MC14002UBCL CD4002UBF MC14021BCP CD4021 BE MC14049UBAL CD4049UBF
MC14002UBCP CD4002UBE MC14022BAL CD4022BF MC14049UBCL CD4049UBF
MC14006BAL CD4006BF MC14022BCL CD4022BF MC14049UBCP CD4049UBE
MC14007BCL CD4007UBF MC14023BCL CD4023BF MC14050BCP CD4050BE
MC14007UBAL CD4007UBF MC14023BCP CD4023BE MC14051BAL CD4051BF
MC14007UBCL CD4007UBF MC14023UBAL CD4023UBF MC14051BCL CD4051BF
MC14007UBCP CD4007UBE MC14023UBCL CD4023UBF MC14051BCP CD4051BE
MC14008BAL CD4008BF MC14023UBCP CD4023UBE MC14052BAL CD4052BF
MC14008BCL CD4008BF MC14024BAL CD4024BF MC14052BCL CD4052BF
MC14008BCP CD4008BE MC14024BCL CD4024BF MC14052BCP CD4052BE
MC14009UBCL CD4009UBF MC14025BAL CD4025BF MC14053BCP CD4053BE
MC14009UBCP CD4009UBE MC14025BCL CD4025UBF MC14053BCP CD4053BE
MC14010BAL CD4010BF MC14025BCP CD4025BE MC14060BAL CD4060BF
37
RCA RCA RCA
MC14060BCL CD4060BF MC14161BCP CD40161BE MC14517BCL CD4517BF

MC14060BCP CD4060BE MC14162BAL CD40162BF MC14517BCP CD4517BE
MC14066BAL CD4066BF MC14162BCL CD40162BF MC14518BAL CD4518BF
MC14069UBCL CD4069UBF MC14175BAL CD40175BF MC14527BCL CD4527BF
MC14069UBCP CD4069UBE MC14175BCL CD40175BF MC14527BCP CD4527BE
MC14070BCL CD4070BF MC14181BAL CD40181 BF MC14532BCL CD4532BF
MC14073BCL CD4073BF MC14413L CD22413F MC14541BCL CD4541BF
MC14073BCP CD4073BE MC14413P CD22413E MC14541BCP CD4541BE
MC14075BAL CD4075BF MC14414L CD22414F MC14543BAL CD4543BF
MC14075BCL CD4075BF MC14414P CD22414E MC14543BCL CD4543BF
MC14075BCP CD4075BE MC14502BAl CD4502BD MC14543BCP CD4543BE
MC14076BAl CD4076BF MC14502BCL CD4502BF MC14555BAL CD4555BF
MC14076BCl CD4076BF MC14502BCP CD4502BE MC14555BCl CD4555BF
MC14077BAl CD4077BF MC14503BCl CD4503BF MC14556BAL CD4556BF
MC14077BCl CD4077BF MC14504BAl CD40109BF MC14556BCl CD4556BF
MC14077BCP CD4077BE MC14504BCl CD4504BF MC14556BCP CD4556BE
MC14078BAl CD4078BF MC14504BCP CD40109BE MC14581BAl CD40181BF
MC14078BCl CD4078BF MC14508BAL CD4508BF MC14581BCl CD40181BF
MC14081BCl CD4081BF MC14510BAl CD4510BF MC14582BCl CD40182BF
MC14082BCl CD4082BF MC14511BAl CD4511 BF MC14584BCL CD40106BF
MC14093BCl CD4093BF MC14511BMJ CD4511 BF MC14585BCL CD4585BF
MC14094BAL CD4094BF MC14512BCl CD4512BF MC15000UBAL CD4000UBF
MC14094BCl CD4094BF MC14512BCP CD4512BE MC15162BCP CD40162BE
MC14094BCP CD4094BE MC14514BAl CD4514BF MC15403BCP CD4503BE
MC14099BAL CD4099BF MC14514BCL CD4514BF MC3419 CD22419
MC14099BCl CD4099BF MC14514BCP CD4514BE MM54C04D CD4069BF
MC14099BCP CD4099BE MC14515BAl CD4515BF MM54C160D CD40160BF
MC14160BAl CD40160BF MC14515BCP CD4515BE MM54C161D CD40161BF
MC14160BCl CD40160BF MC14516BAl CD4516BF MM54C162D CD40162BF
MC14160BCP CD40160BE MC14516BCl CD4516BF MM54C163D CD40163BF
MC14161BAl CD40161BF MC14516BCP CD4516BE MM54C173D CD4076BF
MC14161BCl CD40161BF MC14517BAl CD4517BF MM54C174D CD40174BF
38
RCA RCA RCA
MM74C04N CD4068BE SCL4014BC CD4014BF SCL4030BD CD4030BD

MM74C160N CD40160BE SCL4014BD CD4014BD SCL4030BE CD4030BE
MM74C161N CD40161 BE SCL4014BE CD4014BE SCL4033ABC CD4033BF
MM74C162N CD40162BE SCL4015BC CD4015BF SCL4033ABD CD4033BD
MM74C163N
MM74C164N
MM74C165N
CD40163BE
CD4015BE
CD4021BE
SCL4015BD
SCL4015BE
SCL4016BC
CD4015BD
CD4016BE
CD4016BF
SCL4034ABC
SCL4034ABD
SCL4034ABE
CD4034BF
CD4034BD
CD4034BE
I
MM74C173N CD4076BE SCL4016BD CD4016BD SCL4034BC CD4034BF
MM74C174N CD40174BE SCL4016BE CD4016BE SCL4035BC CD4035BF
MSM4036 CD4036A SCL4017BC CD4017BF SCL4035BD CD4035BD
MSM4039 CD4039A SCL4017BD CD4017BD SCL4035BE CD4034BE
MSM4061 CD4061 SCL4017BE CD4017BE SCL4040ABC CD4040BF
MSM4061A CD4061A SCL4018BC CD4018BF SCL4040ABD CD4040BD
S2859P CD22859E SCL4018BD CD4018BD SCL4040ABE CD4040BE
SCL4000BC CD4000BF SCL4018BE CD4018BE SCL4040BC CD4040BF
SCL4000BD CD4000BD SCL4019BC CD4019BF SCL4040BD CD4040BD
SCL4001BC CD4001BF SCL4019BD CD4019BD SCL4040BE CD4040BE
SCL4001BD CD4001BD SCL4019BE CD4019BE SCL4041UBC CD4041UBF
SCL4001BE CD4001BE SCL4020ABC CD4020BF SCL4041UBD CD4041UBD
SCL4001UBC CD4001UBF SCL4020ABD CD4020BD SCL4041UBE CD4041UBE
SCL4001UBD CD4001UBD SCL4020ABE CD4020BE SCL4042BC CD4042BF
SCL4001UBE CD4001UBE SCL4020BC CD4020BF SCL4042BD CD4042BD
SCL4002BD CD4002BD SCL4020BE CD4020BE SCL4043ABC CD4043BF
SCL4002BE CD4002BE SCL4021BC CD4021BF SCL4043ABD CD4043BD
SCL4006ABC CD4006BF SCL4021BD CD4021 BD SCL4043ABE CD4043BE
SCL4006ABD CD4006BD SCL4021BE CD4021BE SCL4043BC CD4043BF
SCL4006ABE CD4006BE SCL4022ABC CD4022BF SCL4043BD CD4043BD
SCL4006BC CD4006BF SCL4022ABD CD4022BD SCL4043BE CD4043BE
SCL4006BD CD4006BD SCL4022ABE CD4022BE SCL4044ABC CD4044BF
SCL4006BE CD4006BE SCL4022BC CD4022BF SCL4044ABD CD4044BD
SCL4007UBC CD4007UBF SCL4022BD CD4022BD SCL4044ABE CD4044BE
SCL4007UBD CD4007UBD SCL4022BE CD4022BE SCL4044BC CD4044BF
SCL4008BD CD4008BD SCL4023BE CD4023BE SCL4046BC CD4046BF
SCL4008BE CD4008BE SCL4024BC CD4024BF SCL4046BD CD4046BD
SCL4009UBC CD4009UBF SCL4024BD CD4024BD SCL4046BE CD4046BE
SCL4010BD CD4010BD SCL4025BE CD4025BE SCL4049UBC CD4049UBF
SCL4010BE CD4010BE SCL4026ABC CD4026BF SCL4049UBD CD4049UBD
SCL4011BC CD4011BF SCL4026ABD CD4026BD SCL4049UBE CD4049UBE
SCL4011BD CD4011BD SCL4026ABE CD4026BE SCL4050BC CD4050BF
SCL4011UBD CD4011UBD SCL4027BE CD4027BE SCL4051BC CD4051 BF
SCL4013BE CD4013BE SCL4030BC CD4030BF SCL4053BD CD4053D
39
RCA RCA RCA
SCL4053BE CD4053BE SCL4094BC CD4094BF SCL4527BD CD4527BF

SCL4060ABC CD4060BF SCL4094BD CD4094BD SCL4527BE CD4527BE
SCL4060ABD CD4060BD SCL4094BE CD4094BE SCL4528BC CD4528BF
SCL4060ABE CD4060BE SCL4099BC CD4099BF SCL4528BD CD4528BD
SCL4060BC CD4060BF SCL4099BD CD4099BD SCL4528BE CD4528BF
SCL4075BD CD4075BD SCL4510BE CD4510BE TC4001 BP CD4001BE
SCL4075BE CD4075BE SCL4511BC CD4511 BF TC4001 UBP CD4001UBE
SCL4076BC CD4076BF SCL4511BD CD4511BD TC4002BP CD4002BE
SCL4076BD CD4076BD SCL4511BE CD4511BE TC4006BP CD4006BE
SCL4076BE CD4076BE SCL4512BC CD4512BF TC4007UBP CD4007UBE
SCL4077BD CD4077BD SCL4512BE CD4512BE TC4009UBP CD4009UBE
SCL4077BE CD4077BE SCL4514BC CD4514BF TC4010BP CD4010BE
SCL4078BD CD4078BD SCL4514BE CD4514BE TC4011UBP CD4011UBE
SCL4081BD CD4081 BD SCL4515BE CD4515BE TC4014BP CD4014BE
SCL4093BE CD4093BE SCL4527BC CD4527BD TC4028BP CD4028BE
40
RCA RCA RCA
TC4029BP CD4029BE TC4520BP CD4520BE TP4044AN CD4044AE

TC4030BP CD4030BE TC4527BP CD4527BE TP4044BN CD4044BE
TC4034BP
TC4035BP
TC4036B
CD4034BE
CD4035BE
CD4036A
TC4543BP
TC4544BP
TC4556BP
CD4543BE
CD4555BE
CD4556BE
TP4049UBN
TP4050AN
TP4050BN
CD4049UBE
CD4050AE
CD4050BE
I
TC4039B CD4039A TP4000AN CD4000AE TP4051BN CD4051BE
TC4040BP CD4040BE TP4001AN CD4001AE TP4052AN CD4052AE
TC4042BP CD4042BE TP4001AN CD4002AE TP4052BN CD4052BE
TC4043BP CD4043BE TP4001BN CD4001BE TP4053AN CD4053AE
TC4047BP CD4047BE TP400lUBN CD4007UBE TP4066AN CD4066AE
TC4049BP CD4049UBE TP4008BN CD4008BE TP4068AN CD4068AE
TC4050BP CD4050BE TP4009AN CD4009AE TP4069UBN CD4069UBE
TC4051BP CD4051 BE TP4009UBN CD4009UBE TP4070BN CD4070BE
TC4053BP CD4053BE TP4010BN CD4010BE TP4072BN CD4072BE
TC4061 CD4061A TP4013AN CD4013AE TP4082BN CD4081BE
TC4069BP CD4069UBE TP4015BN CD4015BE TP4520AN CD4520AE
TC4071BP CD4071BE TP4016AN CD4016AE IlPD4001C CD4001AE
TC4072BP CD4072BE TP4016UBN CD4016BE IlPD4002C CD4002AE
TC4073BP CD4073BE TP4017AN CD4017AE IlPD4011 C CD4011AE
TC4076BP CD4076BE TP4018BN CD4018BE IlPD4013C CD4013AE
TC4082BP CD4082BE TP4020AN CD4020AE IlPD4017C CD4017BE
TC4086BP CD4086BE TP4022AN CD4022AE IlPD4021 C CD4023AE
TC40175BP CD40175BE TP4028BN CD4028BE IlPD4034C CD4034BE
-TC4511BP CD4511BE TP4040AN CD4040AE IlPD4044C CD4044BE
TC4516BP CD4516BE TP4043AN CD4043AN IlPD4052C CD4052BE
41
RCA RCA RCA
pPD4063C CD4063BE pPD4094C CD4094BE pPD4555C CD4555BE

pPD4066C CD4066AE IlPD4099C CD4099BE IlPD4556C CD4556BE
IlPD4069C CD4069UBE IlPD4508C CD4508BE
IlPD4071C CD4071BE IlPD4510C CD4510BE
pPD4075C CD4075BE IlPD4516C CD4516BE
IlPD4081 C CD4081BE IlPD4518C CD4518BE
42
General Operating and
Application Considerations
Page
General Operating and Handling Considerations .................. 44
A-Series CMOS Integrated Circuits ............................... 48
High-Voltage B-Serles CMOS Integrated Circuits .................. 48
43
General Operating and Application Considerations
This section is intended as a guide to cir- crystal oscillators, a minimum supply CD MCtlAGES E le·e RATINGI
@PACfCAGES D,F," {l2:5·C RATINGI
cuit and equipment designers in the voltage of 4 volts is recommended.
operation and application of MOS inte-
Power DIssipatIon and DeratIng
grated circuits. It covers general operat-
ing and handling considerations with re- The power dissipation of a CMOS inte-
spect to the following critical factors: grated circuit is the sum of a dc (quies-
cent) component and an ac (dynamic)
• Operating supply-voltage range 100
component. The dc component is the
• Power dissipation and derating
sum of the net integrated-circuit reverse ...
• System noise considerations ..MBIENT T[MP[RATtJRE 1l,,1-·C
diode-junction current and the surface
• Power-source rules
leakage current times the supply volt-
• Gate-oxide protection networks Fig. 1-Standard CMOS thermal derating
age. In standard A- or B-series logic de-
• Input signals and ratings chart.
vices, the dc dissipation typically ranges,
• Chip assembly and storage
depending upon device complexity,
• Device mounting
from 100 to 400 nanowalts for a supply
• Testing
voltage of 10 volts. Worst-case dc dissi- System NoIse ConsIderatIons
More specific information is then given pation is the product of the maximum In general, CMOS devices are much less
on significant features, special design quiescent current (given in the data sensitive to noise on power and ground
and application requirements, and sheet on each device) and the dc supply lines than bipolar logic families (such as
standard ratings and electrical character- voltage Voo. TTL or DTL). However, this sensitivity
istics for CMOS A- and B-series logic
Dynamic power dissipation has 3 com- varies as a function of the power-supply
circuits, and on CMOS special-function
ponents: voltage, and more importantly as a
circuits (telecommunications and special
function of synchronism between noise
interface and display driver circuits). a) The dissipation that results from cur-
rent that charges and discharges the spikes and inputtransitions. Good power
external load capacitance of the out- distribution in digital systems requires
put buffers. The dissipation of each that the power bus have a low dynamic
output buffer is equal to CV 2 f, where impedance; for this purpose, discrete
GENERAL OPERATING AND decoupling capacitors should be dis-
HANDLING CONSIDERATIONS C is the load capacitance, V is the
supply voltage, and F is the switching tributed across the power bus. A more
frequency of that output. detailed discussion of CMOS noise
b) The dissipation that results from cur- immunity is provided by ICAN-6587,
The following paragraphs discuss some
rent that charges and discharges the "Noise Immunity of B-series CMOS Inte-
key operating and handling considera-
internal node capacitances. grated Circuits," in the Application Notes
tions that must be taken into account to
c) The dissipation caused by the cur- Section.
achieve maximum advantage of the
CMOS technology. Additional informa- rent spikes through the PMOS and
tion on the operation and handling of NMOS transistors in series at the in- Power-Source Rules
CMOS integrated circuits is given in stant of switching. This component Fig. 2 shows the basic CMOS inverter and
ICAN-6525, "Guide to Belter Handling amounts to approximately 10 per its gate-oxide protection network plus
and Operation of CMOS Integrated Cir- cent of the total dissipation, shown inherent diodes. The safe operating
cuits," included in the Application Notes graphically in the data sheets of most procedures listed below can be under-
Section of this DA TABOOK. RCA CMOS circuits. stood by reference to th is inverter.
All CMOS devices are rated at 200 mW
per package at the maximum operating
OperatIng Supply-Voltage Range ambient temperature rating (TA ) for the
01
Because logic systems occasionally ex- package type (85° C for plastic packages
perience transient conditions on the and 125°C for ceramic packages). Power
power-supply line which, when added to ratings for temperatures below the max-
the nominal power-bus voltage, could imum operating temperature are shown
exceed the safe limits of circuits con- in the standard CMOS thermal derating
nected to the power bus, the recom- chart in Fig. 1. This chart assumes that (a) 01 J112~V
02-50V
mended operating supply-voltage ranges the device is mounted and soldered (or R2«RI
* THESE DIODES ARE INHERENTLY PART OF THE
are 3 to 12 volts for A-series devices and placed in a socket) on a PC board; (b) MANUFACTURING PROCESS.
3 to 18 volts for B-series devices. The there is natural convection cooling, with
recommended maximum power-supply the PC board mounted horizontally; and Fig. 2-Basic CMOS inverter with B-series
limit is substantially below the minimum (c) the pressure is standard (14.7 psia). In types protection network.
primary breakdown limit for the devices addition to the over-all package dissipa-
to allow for limited power-supply tran- tion, device dissipation per output tran- 1. When separate power supplies are
sient and regulation limits. For circuits sistor is limited to 100 mW maximum over used for the CMOS device and for
that operate in a linear mode over a por- the full package operating-temperature the device inputs, the device power
tion of the voltage range, such as RC or range. supply should always be turned on
44
before the independent input signal should be limited to ±100pA to mini-

sources, and the input signals should mize cross talk between input signals
be turned off before the power supply on adjacent terminals, and also to
is turned off (Vss::5 V, ::5 Vee as a maxi- minimize any reduction in noise im-
mum limit). This rule will prevent over- munity.
dissipation and possible damage to The absolute-maximum input-cur-
the 02 input-protection diode when • THESE DIODES ARE INHERENTLY PART Of THE rent rating of ±10 mA, shown in the
the device power supply is grounded. MANUFACTURING PROCESS
published data, protects the device
When the device power supply is an against the possible occurence of an
open circuit, violation of this rule can (a) For standard A-series CMOS product. induced Vee - Vss latch condition, or
result in undesired circuit operation damage to the input protection di-
although device damage should not odes. Latch-Up conditions are ex- •
result; ac inputs can be rectified by di- plained in ICAN-6525.
ode 02 to act as a power supply.
2. ALL CMOS inputs should be termi-
2. The power-supply operating voltage nated. An exception can be made in
should be kept safely below the abso- the case of unbuffered NOR and
lute maximum supply rating, as indi- NAND gates (A-series and US types)
cated previously. where terminating one of the series
*THESE DIODES ARE INHERENTLY PART OF THE
3. The power-supply polarity for MANUFACTURING PROCESS inputs to the proper polarity will not
CMOS circuits should not be reve, :.icrl permit current flow caused by a float-
The positive (Voe) terminal should (b) For improved B-series CMOS prod- ing input. Thus, tying low one of the
never be more than 0.5 volt negative uct. inputs of an unbuffered NAND gate,
with respect to the negative (V ss) ter- or tying high one of the inputs of an
minal (Voe - Vss>-0.5 V). Reversal of unbuffered NOR gate will satisfy this
polarities will forward-bias and short requirement.
the structural and protection diode When CMOS inputs are wired to edge
between Vee and Vss. card connectors with CMOS drive
4. Vooshould be equal to or greater than coming from another PC board, a
Vcc for CMOS buffers which have shunt resistor in the range of 100
two power supplies (except for the kohms should be connected to Voo or
C040109B, and in particular, for CO- Vss, as applicable, in case the inputs
4009 and C04010 CMOS-to- TTL become unterminated with the power
"down"-conversion devices). (c) ForCD4049UB, CD4050B, andCD40109B supplyon.
CMOS types.
5. Power-source current capability 3. When CMOS circuits are driven by
should be limited to as Iowa value as TTL logic, a "pull-up" resistor should
reasonable to assure good logic oper- be connected from the CMOS input to
ation. 5 volts (further information is given in
6. Large values of resistors in series with ICAN-6602).
Voe or Vss should be avoided; tran- IN/OUT CUTIIN
sient turn-on of input protection di-
odes can result from drops across Output Rules
such resistors during switching. 1. The power diSSipation in a CMOS
DIODE BREAKDOWN
01 =:I25V
package should not exceed the rated
D2=50V
value for the ambient temperature
* THESE DIODES ARE INHERENTLY PART OF THE specified. The actual dissipation
MANUFACTURING PROCESS.
Gate-Oxide Protection Network should be calculated when (a) short-
92CS-27967RI
A problem occasionally encountered in ing outputs directly to Voo or Vss, (b)
handling and testing low-power semi- (d) For CMOS transmission gates. driving low-impedance loads, or (c)
directly driving the base of p-n-p or
conductor devices, including MOS and
n-p-n bi-polar transistor.
small-geometry bipolar devices, has Fig. 3-Gate-oxide protection networks used in
been damage to gate oxide and/or p-n RCA CMOS integrated circuits. 2. Output short circuits often result from
junctions. Fig. 3 shows the gate-oxide testing errors or improper board as-
protection circuits used to protect CMOS sembly. Shorts on buffer outputs or
devices from static electricity damage. Input Signals and Ratings across power supplies greater than 5
ICAN-6572 gives further information on 1. Input signals should be maintained volts can damage CMOS devices.
protection circuits. Although these cir- within the power-supply voltage 3. CMOS, like active pull-up TTL, cannot
cuits are included in all CMOS devices, range, Vss ::5 V,::5 Voo. If the input sig- be connected in the "wire-OR" con-
the handling precautions in ICAN-6572 nal exceeds the recommended input- figuration because an "on" PMOS and
and ICAN-6525 should be observed. signal-swing range, the input current an "on" NMOS transistor could be
45
directly shorted across the power- Noise margin is the difference between data between certain synchronously
supply rails. (Exception: CD40107B) the noise-immunity voltage (VIL or VI H) clocked sequential circuits, as shown in
and the output voltage Vo. Noise-margin Fig. 6. This problem can be avoided if the
4. Paralleling inputs and outputs of voltage is the meximum voltage that can maximum clock rise time (t.Cl) for cas-
gates is recommended only when the be impressed upon an input voltage VIN cading any two CMOS sequential de-
gates are within the same IC package. (where VIN is the VOL or VOH voltage of the vices is limited in accordance with the
preceding stage) at any (or all) logic I/O following equations:
5. Output loads should return to a volt-
terminals without upsetting the logic or
age within the supply-voltage range causing any output to exceed the output A Series Types
(Voo to Vss). voltage (Va) conditions specified for VIL
6. large capacitive loads (greater than and VIH ratings. Fig. 5 illustrates the . _ 0.8 Voo (v)
Mexlmum t.Cl - 1.25 (v) X tp(ns)
5000 pF) on CMOS buffers or high- noise-margin concept in a simple sys-
current drivers act like short circuits tem. Minimum noise margins for buf-
and may over-dissipate output transis- B Series Types
fered B-series CMOS devices are 1, 2,
tors. and 2.5 volts, respectively, for supply vol- _ 0.8Voo (v)
7. Output transistors may be over-dissi- tages of 5,10, and 15 volts. Meximumt.Cl - 1.15 (v) X tp(ns)
pated by operating buffers as linear
amplifiers or using these types as where t p = tPHL or tPLH (whichever is
one-shot or astable multivibrators. smaller) for the unit A in Fig. 6 as speci-
fied on the device data sheet at the speci-
Noise Immunity and Noise Margin fied value of Voo and loading conditions.
The complementary structure of the in- Schmitt trigger circuits such as the CD-
verter, common to all CMOS logic de- 40938 are an ideal solution to applica-
vices, results in a near-ideal input-output Fig. 5 - Noise margin example iH!ing invert- tions requiring wave-shaping.
transfer characteristic, with switching ers.
point midway (45% to 55%) between the 0 CASCADING WITH SLOW CLOCK
and 1 output logic levels. The result is Of the two noise-limitation specifica- CAN CAUSE ERROR
cJ~ ~
high dc noise immunity. tions (noise immunity and noise mar-
gin), RCA considers noise immunity to
Fig. 4 shows a typical transfer curve that be more practical for CMOS devices
because CMOS outputs are normally
~
VDO
may be used to define the dc noise O.7VOD
within 50 millivolts of supply rails. Ct. .3VOD I
immunity of CMOS integrated circuits. I I
The noise-immunity voltage (VIL orV IH ) is Noise immunity increases as the input 01 ~ ~ PC!I~!.
SWITCHING ...
the noise voltage at anyone input that pulse width becomes less than the prop- ~DO
does not propagate through the system. agation delay of the circuit. This condi-
Dz----...J....' ------PRQPER
Minimum noise immunity for buffered B- tion is often described as ac noise immu- \
SWITCHING POINT-
,-._ _0_.'_V::::DD:...ERROR
series CMOS devices is 30, 30, and 27 per nity. (Further information on noise im-
cent, respectively for supply voltages munity is given in ICAN-6587). 92CS-33024
VDD of 5, 10, 15 volts and 20 per cent Fig. 6-Error effect that results from a slow
of Voo for all unbuffered gates. The VIL clock In cascaded circuits.
Clock Rlse- and Fail-Time Requirements
and VIH specifications define the maxi-
mum permissible additive noise voltage Most CMOS clocked devices have maxi-
at an input terminal when input signals mum rise- and fall-time ratings (normally Three-State Logic
are within 50 millivolts of the supply rails. 5 to 15 microseconds). With longer rise or
fall times, a device may not function Three-state logic can be easily imple-
properly because of data ripple-through, mented by use of a transmission gate in
VILITYP) ---i false triggering problems, etc. Some B- the outpu~ circuit; this technique pro-
10 I
series CMOS counters have Schmitt- vides a solution to the wire-OR problem
VOIH1GHl 9 ----l-- in many cases.
I
trigger shaping circuits built into the
VNMl· VIL(MAX.)-VO(LOWl
I clock circuit, removing the restriction for
I VNMH "VO(HIGH)-VIH(MIN') Chip Assembly and Storage
I input rise or fall times. long rise and fall
VOUT 5 i times on CMOS buffer-type inputs cause RCA CMOS integrated circuits are pro-
I
I increased power dissipation which may vided in a chip form (H suffix) to allow
i
I
I
r-- V1H(TYPI ~
I exceed device capability for operating customer design of special and complex
circuits to suit individual needs. CMOS
VOILOW ) I ----t--- -t- : power-supply voltages greater than 5
volts. chips are electrically identical to and offer
012345678910
the features of their counterparts sealed
Parallel Clocking in ceramic and plastiC packages. The fol-
Process variations leading to differences lowing paragraphs describe mounting
Fig. 4- Typical transfer curve for a inverting in input threshold voltage among ran- .considerations, packaging, shipping and
gate at VDD = 10 V. dom device samples can cause loss of storage criteria, handling criteria, visual
"
46
inspection criteria, testing criteria, and protection of these devices from tested by circuit probe in the wafer stage
bonding pad layout and dimensions for other harmful environments which and are 100-percent tested again after
each chip. could conceivably affect, their they have been packaged. DC tests of
performance and/or reliability. RCA devices are performed at 5, 10, 15,
Mounting Considerations. All CMOS Handling Criteria. The user should find and 20 volts; functionality is checked at
chips are non-gold backed and require 2.8, 17, and 20 volts depending on family
the following suggested precautions
the use of epoxy mounting. DuPont (i.e., A or B series). Sample testing is
helpful in handling CMOS chips.
No's. 6838 or 5504A conductive silver used to assure adherence to quality re-
paste or equivalent is recommended. In Because of the extremely small size and
quirements and ac specifications.
any case the manufacturer's recommend- fragile nature of chips, the equipment
designer should exercise care in Static tests, high-speed functional and
ations for storage and use should be handling these devices. dc parametric tests, are performed at
followed. If DuPont No., 6838 or 5504A
For additional handling considerations wafer and package stages by means of a
paste is used, the bond should be cured
for CMOS devices, refer to ICAN-6525, Teradyne J283 test set. A Teradyne
at temperatures between 185·C and
"Guide to Better Handling and Operation S157CM test set and a Macrodata MD154
200·C for 75 minutes.
of CMOS integrated Circuits." test set are used in dynamic testing. Dy-
In CMOS circuits MOS-transistor p- namic tests are performed with 15and 50
channel substrates (n-type bulk materi- 1. Grounding picofarad loads. Testing at 15 picofarads
al) are connected to Voe, therefore, when is accomplished primarily by laboratory
chips are mounted and a conductive a. Bonders, pellet pick-up tools, table
"bench-test" techniques; automatic test-
paste Is used care must be taken to keep tops, trim and form tools, sealing
ing at 15 picofarads is difficult because
the active substrate Isolated from ground equipment, and other equipment
of the high input capacitance (approxi-
used in chip handling should be
or other circuli elements. mately 20 to 35 picofarads) of most auto-
properly grounded.
Packing, Shipping, and Storage Criteria. matic ac test sets.
b. The operator should be properly
Solid-state chips, being small in size and grounded. Users should follow the sequence below
unencapsulated, are physically fragile when testing CMOS devices:
and small in physical size, and therefore, 2. In-Process Handling 1. I nsert the device into the test socket.
require special handling considerations a. Assemblies or subassemblies of 2. Apply Vee.
as follows:
chips should be transported and 3. Apply the input Signal.
1. Chips must be stored under proper stored in conductive carriers. 4. Perform the test.
conditions to insure that they are not b. All external leads ofthe assemblies 5. On completion of test, remove the in-
subjected to a moist and/or contami- or subassemblies should be short- put signal.
nated atmosphere that could alter ed together. 6. Turn off the power supply (Vee).
their electrical, physical, or mechani- 7. Remove the device frorTl the test socket
cal characteristics. After the shipping 3. Bonding Sequence and insert it into a conductive carrier.
container is opened, the chip must be a. Connect Vee first to external con- CMOS devices under test must not be
stored under the following condi- nections, for example, terminal 14 exposed to electrostatic discharge or
tions: of the CD4001AH. forward biasing of the intrinsic protec-
A. Storage temperature, 40·C max. b. Remaining functions may be con- tive diodes shown in Fig. 3.
B. Relative humidity, 50% max. nected to their external connec-
Detailed information on the techniques
C. Clean, dust-free environment. tions in any sequence.
employed in the testing of RCA CMOS
2. The user must exercise proper care 4. Testing integrated circuits are described in ICAN-
when handling chips to prevent even 6532 included in the Application Notes
a. Transport all assemblies of chips Section of this DATABOOK.
the slightest physical damage to the
in conductive carriers.
chip.
b. In testing chip assemblies or sub-
3. During mounting and lead bonding of assemblies, the operator should be Device Mounting
chips the user must use proper as- properly grounded.
Integrated circuits are normally supplied
sembly techniques to obtain proper with lead-tin plated leads to facilitate
electrical, thermal, and mechanical Visual Inspection Criteria. All standard
commercial CMOS chips undergo a soldering into circuit boards. In those
performance. relatively few applications requiring
visual inspection which is patterned after
4. After the chip has been mounted and MIL-STD-883, Method 2010, Condition Ei welding of the device leads, rather than
bonded, any necessary procedure with modifications reflecting CMOS soldering, the devices may be obtained
must be followed by the userto insure requirements. with nickel-plated Kovar leads. * Itshould
that these non-hermetic chips are not be recognized that this type of plating
subjected to a moist and contaminat- Testing Criteria. CMOS chips are dc elec-
will not provide complete protection
ed atmosphere which might cause the trically tested 100% in accordance with
against lead corrosion in the presence of
development of electrical conductive the same standards prescribed for RCA
high humidity and mechanical stress.
paths across the relatively small insu- devices in standard packages.
lating surfaces. In addition, proper Device Testing *MIL-M-38510, paragraph 3,5,6,1 (a), lead
consideration must be given to the RCA CMOS circuits are 100-percent material
47
In any method of mounting integrated Table I shows the maximum ratings and major features of this series are as fol-
circuits which involves bending or form- the recommended operating supply-volt- lows:
ing of the device leads, it is extremely im- age range for RCA A-series CMOS inte- • High-voltage (20-V) ratings
portant that the lead be supported and grated circuits. • 100% tested for quiescent current at
clamped between the bend and the 20 V
package seal, and that bending be done Static Electrical Characteristics
• 5-V, 10-V, and 15-V parametric rat-
with care to avoid damage to lead plat- Table II shows the standard dc electrical ings
ing. In no case should the radius of the characteristics for A-series types. The • Standardized, symmetrical output
bend be less than the diameter of the data sheet for each of these types con- characteristics
lead. It is also extremely important that tains the family characteristics shown in • Maximum input current of 1 /JA at 18
the ends of bent leads be straight to as- Table I plus additional dc characteristics V over full-package-temperature
sure proper insertion through the holes that are type-dependent. range; 100 nA at 18 V and 25°C
in the printed-circuit board. • Noise margin (full package-temper-
ature range) =
A-5ERIES CMOS Dynamic Electrical Characteristics
INTEGRATED CIRCUITS 1VatVoo = 5V
A-series dynamic electrical characteris-
2VatVoo = 10 V
RCA CD4000A-series types have a maxi- tics are specified for individual types un-
2.5VatVoo = 15 V
mum dc supply-voltage rating of -0.5 to der the following conditions: Voo = 5 V
and 10 V; T A= 25° C (temperature coeffi- • Meets all requirements of JEDEC
15 volts, and a recommended operating
cient is typically 0.3%/oC); CL = 15 pF; t, Tentative Standard No. 13B, "Stand-
supply-voltage range of 3 to 12 volts. The
and tf of inputs = 20 ns. ard Specifications for Description of
major features of this series are as fol-
'B' Series CMOS Devices
lows:
• Quiescent current specified to 15
volts HIGH-VOLTAGE 8-SERIES
CMOS INTEGRATED JEDEC Minimum Standard
• 5-volt and 1Q-volt parametric ratings
• Maximum input leakage of 1 /JA at 15 CIRCUITS Under the sponsorship of the Joint Elec-
volts over the full package operat- RCA-CD4000B-series types have a max- tron Devices Engineering Council
ing-temperature range imum dc supply-voltage rating of -0.5 to (JEDEC) of the Electronic IndustriesAs-
• 1-volt noise margin (full package 20 volts, and a recommended operating sociation (EIA), minimum industrial
temperature range) supply-voltage range of 3 to 18 volts. The standards have been established for the
Table I - Maximum Ratings and Recommended Operating Conditions for A-Series CMOS
Integrated Circuits
MAXIMUM RATINGS, Absolute-Maximum Values:

DC SUPPL V-VOLTAGE RANGE, (VDD)
(Voltages referenced to VSS Terminal) .......................................... -0.5 to +15 V
INPUT VOLTAGE RANGE. ALL INPUTS ..................................... -0.5 to VDD +0.5 V
POWER DISSIPATION PER PACKAGE (PD):
For T A = -40 to +60° C (PACKAGE TYPE E) .......................................... 500 mW
For T A = +60 to +85° C (PACKAGE TYPE E) ......................... Derate Linearly to 200 mW
For T A = -55 to +100° C (PACKAGE TYPES D. F. K. H) ................................. 500 mW
For T A = +100 to +125°C (PACKAGE TYPES D. F. K. H) .............. Derate Linearly to 100 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR:
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ............... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES D. F. K. H .............................•......••.......•.•.. -55 to +125°C
PACKAGE TYPE E ........................................................... -40 to +85° C
STORAGE TEMPERATURE RANGE (TSTG) ..................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.......•......•.••.. +265°C
RECOMMENDED OPERATING CONDITIONS

For maximum reliability, nominal operating conditions should be selected so that opera-
atlon Is always within the following ranges:
LIMITS
CHARACTERISTIC UNITS
Min. Max.
Supply-Voltage Range (For TA = Full Package-
Temperature Range) 3 12 V
48
Table II - A-Series Static Electrical Characteristics (Full Package Temperature Range)
CONDITIONS LIMITS
SYMBOL PARAMETER VIN Vo (volts) Voo
VOLTS MIN. MAX. VOLTS MIN. TYP. MAX. UNITS
VOL Output Low 5 - - 5 - 0 0.05 V
Voltage 10 - - 10 - 0 0.05 V
VOH Output High 0 - - 5 4.95 5 - V
Voltage 0 - - 10 9.95 10 - V
VNL Noise Voltage - 3.6 - 5 1.5 2.25 - V
- -
(SSI Types) (Input Low)
VNH Noise Voltage
(SSI Types) (Input High)
-
-
7.2
-
-
-
1.4
2.8
10
5
10
3
3
1.5
4.5
2.25
4.5
-
-
V
V
V
I
VNL Noise Voltage - 4.2 - 5 1.5 2.25 - V
(MSI Types) (Input Low) - 9.0 - 10 3 4.5 - V
VNH Noise Voltage - - 0.8 5 1.5 2.25 - V
(MSI Types) (Input High) - - 1.0 10 3 4.5 - V
VNML Noise Margin - 4.5 - 5 1 - - V
(Input Low) - 9.0 - 10 1 - - V
VNMH Noise Margin - - 0.5 5 1 - - V
(Input High) - - 1.0 10 1 - - V
IILI hH Input Leakage - - - 15 - ± 10-' ±1 pA
Low
IL Quiescent Device - - - 5, 10, 15 See Data Sheets pA
Leakage
IONI IDP Output Source and - - - 5,10 See Data Sheets
mA
Sink current
Note: Logic Level Inversion Assumed in Table II.

maximum ratings, static and ac electri- The JEDEC minimum standard also in- cuits meet or exceed the most stringent
cal characteristics of 8-series CMOS includes in the 8-series CMOS types that requirements of the JEDEC 8-series
tegrated circuits. The JEDEC standard have analog inputs or outputs and, in ad- specifications. Table V shows the stand-
(JEDEC Tentative Standard No. 138) dition, have maximum ratings and logi- ardized maximum ratings and recom-
defines 8-series CMOS integrated cir- cal input and output parameters that mended operating supply-voltage range
cuits as a uniform family of both buffered conform to 8-series specifications for RCA 8-series CMOS integrated cir-
and unbuffered types that have an abso- wherever applicable. These CMOS de- cuits. The standardized static electrical
lute dc supply-voltage rating of at least vices are also designated by the suffix characteristics for these devices are
18 volts. u8". shown in Table VI. As with the JEDEC
Buffered CMOS devices are types in All 8-series CMOS devices can directly specifications, the RCA standardized
which the output "on" impedance is in- replace their A-series counterparts in characteristics classifies the 8-series
dependent of any and all valid input logic most applications. The U8 types are devices into three leakage (quiescent-
conditions, both preceding and present. high-voltage versions of corresponding device-current) categories. Table VII lists
All such CMOS product are designated A-series (unbuffered) types. the RCA types in each category and indi-
by the suffix "8" following the basic type cates types that, although they are still
Table III lists the JEDEC minimum
number. 8-series types, differ in one or more static
standards established for the maximum
charactistics.
Unbuffered CMOS devices are types ratings and recommended operating
that meet all 8-series specifications ex- conditions for 8-series CMOS integrat- Tables V and VI show that, in a number of
cept that the logical outputs are not buf- ed circuits. ·important respects, RCA has established
fered and the noise-immunity voltages, new performance standards for 8-series
Table IV shows the J EDEC standards for CMOS logic circuits.
VIL and VIH, are specified as 20 and 80 per the static electrical characteristics of
cent, respectively, of Voe for operation CMOS 8-series integrated circuits. 1. Tight limits for all packages
from 5 or 10 volts, and 17 and 83 per cent, RCA devices use the same set of lim-
respectively, of Vee for operation from 15 Standardized RCA Ratings its for all package styles. The JEDEC
volts. All such CMOS product are desig- and Static Characteristics standard establishes two sets of limits
nated by the suffix "U8". RCA 8-series CMOS integrated cir- for most dc (static) parameters; a
49
Table III - JEDEC Minimum Standards for Maximum Ratings
and Recommended Operating Conditions for 8-serles CMOS
Integrated Circuits"
Absolute Maximum Ratings (Voltages referenced to Vss):

DC Supply Voltage Vee -0.5 to +18 Vdc
Input Voltage V,N -0.5 to Vee +0.5 Vdc
DC Input Current liN ±10 mAdc
(anyone input)
Storage-Temperature Range Ts -65 to +150 ·C
Recommended Operating Conditions:
DC Supply Voltage Vee +3 to +15 Vdc
Operating-Temperature Range, TA
Military-Range Devices -55 to +125 ·C
Commercial-Range Devices -40 to +85 ·C
'Reprinted from JEDEC Tentative Standard No. 13-8, "Standard

Specifications for Description of 8-Series CMOS Devices."
Table IV - JEDEC Standard for Static Characteristics of B-Series CMOS Integrated Circuits....
LIMITS
TEMP. Voo TLOW" +25'C THIGH"
PARAMETER RANGE (Vdc) CONDITIONS Min Max Min TVD Max Min Max Units
Quiescent 5 0.25 0.25 7.5
100 Device Current Mil 10 Y,N = VSS or VOO 0.5 0.5 15
15 1.0 1.0 30
GATES uAdc
5 All valid input 1.0 1.0 7.5
Comm 10 combinations 2.0 2.0 15
15 4.0 4.0 .:30
5 1.0 1.0 30
Mil 10 Y,N = VSS or VOO 2.0 2.0 60
15 4.0 4.0 120
BUFFERS. uAdc
FLIP.FLOPS Comm 5 All valid input 4 4 30
10 combinations 8 8 60
15 16 16 120
5 5 5 150
Mil 10 Y,N = VSS or VOO 10 10 300
15 20 20 600
MSI uAdc
5 All valid input 20 20 150
Comm 10 combinations 40 40 300
15 80 80 600
VOL Low-Level 5 0.05 0.05 0.05

Output Voltage All 10 Y,N = VSS or VOO 0.05 0.05 0.05 Vdc
15 1101<luA 0.05 0.05 0.05
VOH High·Level 5 4.95 4.95 4.95

Output Voltage All 10 Y,N = VSS or VOO 9.95 9.95 9.95 Vdc
15 1'01<luA 14.95 14.95 14.95
V,L Input Low 5 Va = 0.5V or 4.5V 1.5 1.5 1.5

Voltage All 10 Va = 1.0V or 9.0V 3.0 3.0 3.0 Vdc
15 VO= 1.5Vor 13.5V 4.0 4.0 4.0
S Types
1'01
<luA
5 Va = 0.5V or 4.~V 1.0 1.0 1.0
US Types All 10 Va = 1.0V or 9.0V 2.0 2.0 2.0 Vdc
15 Va = 1.5Vor 13.5V 2.5 2.5 2.5
l'OI<luA
V,H Input High 5 Va = 0.5V or 4.5V 3.5 3.5 3.5
Voltage All 10 Va = 1.0V or 9.0V 7.0 7.0 7.0 Vdc
15 VO=I.5Vor 13.5V 11.0 11.0 11.0
B Types 1'01 <luA
5 Va = 0.5V or 4.5V 4.0 4.0 4.0

US Types All 10 Va = 1.0V or 9.0V B.O B.O B.O Vdc
15 Va = 1.5V or 13.5V 12.5 12.5 12.~
j1OI<1uA
50
Table IV - JEDEC Standard for Static Characteristics of B-serles CMOS Integrated Circuits (cont'd)
TEMP. Voo TLOW

. LIMITS
+25 0 C THIGH
.
PARAMETER RANGE (Vdc) CONDITIONS Min Max Min Typ Max Min Max Units
5 I/o = 0.4V
VIN =00r5V 0.64 0.51 0.36
10 Va = 0.5V,
Mil VIN=00rl0V 1.6 1.3 0.9
15 Va = 1.5V,
Output Low VIN= Oor 15V 4.2 3.4 2.4
10L mAde
ISink) Current
I
5 Va = 0.4V,
VIN = 0 or 5V 0.52 0.44 0.36
10 Va = 0.5V,
Comm VIN = Oor 10V 1.3 1.1 0.9
15 Va = 1.5V,
VIN=00r15V 3.6 3.0 2.4
5 VO= 4.6V,
VIN = Oor 5V -0.25 -0.2 -0.14
10 Va = 9.5V,
Mil VIN = 0 or 10V -0.62 -0.5 -0.35
15 Va = 13.5V,
Output High VIN=00r15V -1.8 -1.5 -1.1
10H (Source) mAdc
Current 5 Vo = 4.6V
Y,N = 0 or 5V -0.2 -0.16 -0.12
10 Vo = 9.5V,
Comm Y,N = 0 or 10V -0.5 -0.4 -0.3
15 Vo = 13.5V,
Y,N = 0 or 15V -1.4 -1.2 -1.0
liN Input Mil 15 Y'N = 0 or 15V ±0.1 ±0.1 ±1.0 uAdc

Current
Comm 15 Y,N = 0 or 15V ±0.3 ±0.3 ±1.0 uAdc
3-State Mil 15 Y,N = 0 or 15V ±0.4 ±0.4 ±12 uAdc

IOUTmax Output
Leakage
Current Comm 15 Y'N = 0 or 15V ±1.6 ±1.6 ±12 uAdc
C,N Input
Capacitance All - Any Input 7.5 pF
per Unit Load
'T LOW = -55 0 C for Military Temp. Range device, -40 0 C for Commercial Temp. Range device
'THIGH = +125 0 C for Military Temp. Range device, +85 0 C for Commercial Temp. Range device
.. Reprinted from JEDEC Tentative Standard No. 13-8, "JEDEC Standard Specification for Description of 8-series CMOS Devices."
tight set for products having a full op- 2. Improved voltage rating ommended maximum operating-volt-
erating temperature range of -55°C All RCA B-series devices are tested to age of 18 volts. This higher limit per-
to + 125· C (normally used for ceram- voltages that insu re safe operation at mits 18-volt system supply operation,
Ic packages), and a relaxed set for the absolute maximum dc supply and also permits wider power-source
products having a limited tempera- voltage rating of 20 volts. This higher tolerances and transients for supplies
ture range of -40·C to +85·C (nor- rating permits greater derating for re- normally set up to 18 volts.
mally used for plastiC packages). Be- liable 15-voltoperation, permits great-
cause RCA supplies only one premi- er 15-volt supply tolerance and peak 4. Lower leakage current
um grade of B-series p~oduct in all transients, and permits system use to The JEDEC standard establishes
package styles (i.e., fall-out chips are 18-volts with confidence. three sets of limits for quiescent de-
not used), all B-series CMOS devices vice current (100) intended to match
are specified to the tight set of limits 3. Wider operating range chip complexity to device leakage
only. All RCA B-series devices have a rec- current as realistically as possible.
51
Table V - RCA Standardized Maximum Ratl~gs and Recommended Operating Conditions for
B-Serles CMOS Integrated Circuits
Maximum Ratings, Absolute-Maximum Values
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltages referenced to Vss Terminal) ................................................. -n.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ............................................ -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ..................................................... ±10 rnA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60° C (PACKAGE TYPE E) ............................................... 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) .............. Derate Linearly at 12mW/oC to 200 mW
For TA = -55 to +1 00° C (PACKAGE TYPES D, F, K) ...................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPES 0, F, K) ...... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................... 100 mW
PACKAGE TYPES D, F, K, H........................................................ -55 to +125° C
PACKAGE TYPE E .................................................................. -40 to +85° C
STORAGE-TEMPERATURE RANGE (Tot.) ............................................. -65 to +150° C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ...................... +265° C
Recommended Operating Conditions:

For maximum reliability, nominal operating conditions should be
selected so that operation is always within the following ranges:
LIMITS
MIN. MAX.
Supply-Voltage Range (For
TA = Full Package Temp- 3 18 V
erature Range)
For all three levels of chip complexity, of limits established in the JEDEC maximum limit of 1 pA at the upper
all RCA B-series devices (regardless standard. The balanced output pro- limit of the package-temperature
of package) conform to the tighter set vides uniform rise and fall time perfor- range. Actually, the 100 nA rating is a
of limits established in the standard. mance, improved system noise ener- practical specification limited by the
In addition, a maximum rating is spec- gy (dynamic) immunity, optimum de- inability of commercial test equip-
ified at 20V, as well as at 5V, 10V, and vice speed for both output switching ment to measure lower currents. Lab-
15V. As a result: low-to-high (tPlH) and output switch- oratory tests show that input leakage
(a) In current-limited applications, ing high-to-Iow (tPHl), and in general currents of RCA B-series CMOS de-
CMOS users can depend on one the identical high and low dc and ac vices are significantly lower than this
tight leakage limit independent of characteristics normally associated limit, typically ranging from 10 to 100
package style selected. with a good complementary output pA.
(b) Customer use of CMOS product up drive circuit. MOS system design, 7. Buffered and unbuffered gates
through 18 volts is protected by a simulation, and performance are sig- The new industry standard establish-
published tight leakage current spec- nificantly enhanced by equal high es a suffix "UB" for CMOS products
ification at 20 volts (as well as by an and low dc and ac performance rat- that meet all B-series specifications
input leakage specification at 18 ings and one tight specification limit except that the logical outputs of the
volts). for all package styles. devices are not buffered and the Vil
5. Symmetrical output 6. Improved Input current (leakage) and VIH specifications are relaxed.
Most RCA B-series devices have bal- ratings The suffix "B" defines only buffered-
anced complementary output drive All RCA B-series devices (regardless output devices in which the output
(i.e., the output high current 10H rating of package) have a maximum input "on" impedance is independent of
is the same as the output low current leakage current (liN) rating of 100 nA any and all valid input logic condi-
10l rating) specified to the tighter set specified at voltages up to 18 V, and a tions, both preceding and present.
52
Table VI - RCA B-series CMOS Standardized Electrical Characteristics
LIMITS AT INDICATED TEMPERATURES (oC)

CONDITIONS Values at -55, +25, +125 Apply to 0, F, K, H Packages
CHARACTER- Values at -40, +25, +85 Apply to E Package UNITS
ISTIC
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent Device - 0,5 5 0.25 0.25 7.5 7.5 - 0.01 0.25
Current, - 0,10 10 0.5 0.5 15 15 - 0.01 0.5
IDD Max.
I
- 0,15 15 1 1 30 30 - 0.01 1
Gates,
Inverters· - 0,20 20 5 5 150 150 - 0.02 5
Buffers, Flip-Flops, 0,5 5 1 1 30 30 - 0.02 1
Latches, Multi· 0,10 10 2 2 60 60 - 0.02 2
Level Gates 0,15 15 4 4 120 120 - 0.02 4 JlA
(MSI·l Types).
0,20 20 20 20 600 600 - 0.04 20
Complex Logic 0,5 5 5 5 150 150 - 0.04 5
(MSI·2 Types). 0,10 10 10 10 300 300 - 0.04 10
0,15 15 20 20 600 600 - 0.04 20
0,20 20 100 100 3000 3000 - O.OB 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low·Level, - 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High-Level .- 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 - 15 4 - - 4
B Types
UB Types 0.5,4.5 - 5 1 - - 1
1,9 - 10 2 - - 2
1.5,13.5 - 15 2.5 ~ - 2.5
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1 9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
B Types
UB Types 0.5,4.5 - 5 4 4 - -
1 9 - 10 8 8 - -
1.5,13.5 - 15 12.5 12.5 - -
I nput Current - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-b ±0.1 JlA
liN Max.
3-State Output
Leakage Cu rrent 0, 18 0,18 18 ±0.4 ±0.4 ±12 ±12 - ±10-4 ±0.4 JlA
lOUT Max.
·Classifications of RCA CMOS B-Series Types are shown in Table VII.
53
Table VII-Classification of RCA B-series CMOS Integrated Circuits According to Circuit Complexity
Buffers/flip-Flop/
Gates/ latches/Multi-Level
Inverters Gates (MSI-1) Complex Logic (MSI-2)
C04000B C04023UB C04009UB- C040708 C040068 C040518- C045278
C04000U8 C04025B C040108_ C040n8 C04OO88 C040528- C04532B
C040018 C04025U8 C040138 C040858 C040148 C04053B- C045368
C04001U8 C040488 C040198 C040868 C040158 C040548- C04538B
C04OO28 C040668- C040278 C040938 C040178 C040558- C045418
C04OO2U8 C040688 C040308 C040958 C040188 C04056B- C045438
C04007U8 C04069U8 C04041UB- C040968 C040208 C04060B C045558
C040118 C040718 C040428 C040988 C040218 C04063B C04556B
C04011U8 C040728 C040438 C045028- C04022B C04067B- C045858
C040128 C040738 C040448 C045038 C040248 C040768 C04724B
C04012U8 C040758 C040478 C040106B C040268 C04089B C0401008
C040168- C040788 C04049U8- C0401078_ C040288 C040948 C040101B
C040238 C040818 C040508_ C0401098- C040298 C04097B- C040102B
C04082B C040174B C040318 C04099B C0401038
C0401178 C0401758 C040328 C04508B C040104B
C0402578 C040338 C04510B C040105B
C040348 C04511B- C040108B
C040358 C04512B C0401108-
C04038B C04514B C040147B
C040408 C04515B C040160B
C04045B- C04516B C040161B
-Indicates types for which. because of special design requirements. one C040468- C04517B C040162B
or more static characteristics differ from the standardized data. Refer to C04518B C040163B
RCA data pages on these types for specific differences.
C04520B C040181B
C040182B
C040192B
C040193B
C040194B
C040208B
RCA will supply both buffered ("B") provements in processing technolo- B-Serles Oynamlc Electrical
and unbuffered ("UB") versions ofthe gy and plastic and ceramic packaging Characteristics
popular NOR and NAND gates to techniques. Product quality is real- B-series dynamic electrical characteris-
make available to designers the ad- time controlled using accelerated- tics are specified for individual types un-
vantages of both. The chart below temperature group quality screening der the following conditions: VDD = 5V;
briefly compares the features of the in which measured dc parameters are 10V. and 15V; TA = 25° C; CL = 50 pF; RL
two versions (a more detailed cover- criticized against tight B-series limits. = 200 kQ; tr and t, = 20 ns. Table VIII lists
age of the special features of B- and Figs. 7 through 10showthestandardized dynamic characteristics specified for
UB-series CMOS gates is provided by n- and p-channel drain characteristics RCA B-series CMOS integrated circuits.
ICAN-6558 in the Application-Notes for B-series CMOS devices. and Figs. 11 Fig. 13 shows the variation of B-series
section): through 14 shows the normalized varia- dynamic parameters with temperature.
8. Reliability tion of output source and sink currents Fig. 14 shows the variation of output
RCA B-series CMOS integrated with respect to temperature and voltage transition time with supply voltage. Fig.
circuits incorporate the latest imin these devices. 15 shows the variation of the standard-
ized output transition time with load
Buffered Unbuffered capacitance.
Version Version Maximum propagation delay or transi-
Characteristic ("B") ("UB") tion times for values of CL other than the
specified 50 picofarads can· be deter-
Propagation Delay (Speed) Moderate Fast mined by use of the multiplication factor
Noise Immunity/Margin Excellent Good (usually 2) between the typical and max-
Output Impedance and imum values given in the dynamic char-
Output Transition Time Constant Variable acteristics chart included in the techni-
AC Gain High Medium cal data for each device applied to the
Output Oscillation for typical curves. and also shown in the
Slow Inputs Yes No device technical data.
Input Capacitance Low High
54
DRAIN-lO-SOURCE VOLTAGE (V05I-V
I
II
I"
GATE-TO-SOURCE VOLTAGE IVGs)-IOY
Ii lOY
•
DRAIN·T~-SOURCE VOLTAGE (YOSI-Y
!5 10 15
DRAIN-TO-SOURCE VOLTAGE (Vosl-Y
Fig. 7 - Typical output low (sink) current Fig. 8-Minimum output low (sink) current Fig. 9 - Typical output high (source) current
characteristics. characteristics. characteristics.
DRAIN-TO-SOURCE VOLTAGE (VOSI-Y
-100. -so 50 100 5 10 U5

AMBIENT TEMPERATURE (TAI-·C SUPPLY VOLTAGE I Vool-VOLTS
92CS-33021
Fig. 10 - Minimum output high (source) cur- Fig. 11-Variation of normalized output low Fig. 12-Variation of normalized output low
(sink) current 10L and output high (source) (sink) current 10L and output high (source)
rent characteristics.
current 10H with temperature. current 10H with supply voltage.
AMBIENT TEMPERATURE (")~ 25"C
E5
~~
~il
o"as
g~'
~f
!l 0
-100 -7, -!SO -25 0 25 50 75 100 125 46810121416
AMBIENT TEMPERATURE ITA)-OC SUPPLY VOLTAGE IVool-YOL.TS
92CS-33022 9ZCS-330Z3
OF
Fig. 13-Variation of low-to-high (ITLH) and Fig. 14-Variation of low-to-high (ITLH) and Fig. 15- Variation of transition time (tTHl '
high to low (ITHL) transition time, and low-to- high-to-/ow (ITHL) transition time with (tTLH) with load capacitance.
high (tPLH) and high-to-/ow(tPHc) propagation supply voltage.
delay time with temperature.
"DO
-'-
B-Serles DynamIc (Ae) SwItchIng
Parameters
Table VIII defines the major CMOS ac
characteristics, with reference to the Outputs should be switching from 10% Voo to
waveforms shown in Fig. 16 through 19. 90% Voo in accordance with device truth table.
Test conditions of Voo, low capacitance
(CL), and input conditions are given for Fig. 16- Transition times and propagation Fig. 17 - Clock-pulse rise and fall times and
individual types in the published data. delay times, combination logic. pulse width.
55
Table VIII - Dynamic Electrical Characteristics - Definitions
Characteristic Symbol Limits Notes

Max. Min.
Propagation Delay:
Outputs going high to low tPHL X
Outputs going low to high tPLH X
Output Transition Time:
Outputs going high to low bHL X
Outputs going low to high bLH X
Pulse Width-Set, Reset, Preset
Enable, Disable, Strobe, Clock tWL or tWH X 1
Clock Input Frequency fCL X 1,2
Clock Input Rise and Fall Time trCL, tlCL X
Set-Up Time tsu X 1
Hold Time tH X 1
Removal Time - Set, Reset, Preset-Enable tREM X 1
Three State Disable Delay Times:
High level to high impedance tPHZ X
High impedance to low level tPZL X
Low level to high impedance tpLZ X
High impedance to high level tPZH X
NOTE: (1) By placing a defining min. or max. in front of definition, the limits can change from min.
to max., or vice versa.
(2) Clock input waveform should have a 50% duty cycle and be such as to cause the outputs
to be switching from 10% VDD to 90% V DD in accordance with the device truth table.
CMOS Special Products

RCA supplies a variety of special CMOS
products that have operating supply-
voltage ranges and other characteristics
that differ from the standardized data
specified for A- and B-series CMOS inte-
grated circuits.
These special applications types include
flash AID converters for use in low-
power consumption, high-speed digit-
ization applications; crosspoint switches
for use in telephone and PBX systems, in
studio audio switching applications, and
as multisystem bus interconnects; tone
generators for use in dual-tone telephone
f dialing systems; interface circuits for
aT ....
INPUTS 1 OUTPUT RL"'"Q fVoo rot' IPLl ond IpZl
level-shifting applications to interface
Vss for 'PHZ and IpZH C9-20069R4
CL CMOS logic levels with different logic
OUTPUT "'of
DISABLE types; and display drivers non-multi-
C9-29514RI
plexed, 4-digit, 7-segment LCD types
Fig: 19-5etup times, hold times, removal containing all the circuitry necessary for
time, and propagation delay times driving conventional LCD displays
Fig. 18 - Three-state propagation delay wave for positive-edge triggered sequen- without the need for external com-
shapes and test circuit. tiallogie circuits. ponents.
56
CMOS High-Voltage
B-Series Integrated Circuits
Technical Data
57
CD4000B, CD4001 B, CD4002B, CD4025B Types
CMOS NOR Gates Features:

• Propagation delay time = 60 ns (typ.) at
High·Voltage Types (2()'Volt Rating) CL = 50 pF, VDD = 10 V
NC
• Buffered inputs and outputs
Dual 3 Input
• Standardized symmetrical output characteristics NC
plus Inverter - CD4000B
• 100% tested for maximum quiescent current at 20 V
Ouad 2 Input - CD4001 B
• 5·V, 1()'V, and 15·V parametric ratings
Dual 4 Input - CD4002B
Triple 3 Input - CD4025B • Maximum input current of 1 /1A at 18 V
over full package·temperature range;
100 nA at 18 V and 25 0 C v,s
• Noise margin (over full package temperature
RCA·CD4000B, CD4001B, CD4002B, and range):
CD4025B NOR. gates provide the system 1 VatVDD= 5 V
designer with direct implementation of the 2 V at VDO = 10 V
NOR function and supplement the existing 2.5 Vat VDD = 15 V CD40008
family of CMOS gates. All inputs and outputs FUNCTIONAL DIAGRAM
are buffered. • Meets all requirements of JEDEC Tentative
The CD4000B, CD4001 B, CD4002B, and Standard No.13A, "Standard Specifications
C04025B types are supplied in 14-lead for Description of "B" Series CMOS Devices"
hermetic dual-in-line ceramic packages (D
and F suffixes). 14-lead dual-in-line plastic
packages (E suffix), 14-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
STATIC ELECTRICAL CHARACTERISTICS

92C5-24162
LIMITS AT INDICATED TEMPERATURES (OC) C040018
CONDITIONS Values at -55, +25, +125 ApplytoD,F,K,H Packages FUNCTIONAL DIAGRAM
CHARACTER· Values at -40, +25. +85 Apply to E Package
ISTIC UNITS
Vo +25
VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Current, - 0,10 10 0.5 0.5 15 15 - 0.01 0.5
100 Max. IJA
- 0,15 15 1 1 30 30 - 0.01 I
- 0,20 20 5 5 150 150 - 0.02 5
Output Low 0.4 0.5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0.10 10 1.6 1.5 1.1 0.9 1.3 2.6 ,.
IOL Min.
1.5 0.15 15 4.2 4 2.8 2.4 34 6.8 -
Output High 4.6 0.5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
Vss
(Source) 2.5 0.5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 "'
Current,
9.5 0.10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
92CS-241!j8
IOH Min. C040028
13.5 0.15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - FUNCTIONAL DIAGRAM
Output Voltage: - 0.5 5 0.05 - 0 0.05
Low·Level. - 10 0.05 - 0 0.05
0.10
VOL Max.
- 0.15 15 0.05 - 0 0.05
V I.V,,
Output Voltage: - 0.5 5 4.95 4.95 5 ..
High·Level. - 0.10 10 9.95 9.95 10 -

VOH Min. - .-
0,15 15 14.95 14.95 15
Input Low 0.5.415 - 5 1.5 - - 1.5
Voltage, 10 3 - - 3
',,9 -
VIL Max.
1.5)13.5 - 15 4 - - 4
V
Input High 0.5 - 5 3.5 3.5 - -
Voltage, I - 10 7 7 - -
VIH Min. - 15 11 11 - -
1.5
Input Current CD40258
liN Max.
0,18 18 ~0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 /l-A
FUNCTIONAL DIAGRAM
58
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges:
LIMITS
MIN. MAX,
Supply-Voltage Range (For T A; Full Package
3 18 V
Temperature Rangel
MAXI MUM R A TI NGS, Absolute-Max imum Values:

DC SUPPLY-VOL TAGE RANGE, IV DDI
(Voltages referenced to VSS Terminal) -0.5 to +20 V INPUT VOLTAGE (VI) - V
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to VDD +0.5 V

DC INPUT CURRENT, ANY ONE INPUT ±lO rnA
POWER DISSIPATION PER PACKAGE IPDI: Fig. 1 - Typical voltage transfer characteristics.
For TA = -40 to +60 0 C (PACKAGE TYPE EI .. ... . 500 mW
For TA = +60 to +85 0 C IPACKAGE TYPE EI . . . Derate Linearly at 12 mW/oC to 200 mW
For T A ; -55 to +100·C (PACKAGE TYPES D, F, K) .. .. . 500 mW
For TA = +100 to +125 0 C (PACKAGE TYPES D, F, K) Derate Linearly at 12 mW/oC to 200 mW
OEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA - FULL PACKAGE·TEMPERATURE RANGE IAII Package Tvpesl
OPERATING·TEMPERATURE RANGE ITAI:
PACKAGE TYPES D, F, K, H .
100mW
-55 to +125 0 C
II
PACKAGE TYPE E . -40 to +85 0C
STORAGE TEMPERATURE RANGE ITstgl -65 to +150°C
LEAD TEMPERATURE IDURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case far lOs max.
DYNAMIC ELECTRICAL CHARACTERISTICS

10
AtTA =2!JC;lnpurr"t,=20ns,CL =50pF,R L =200kn 10
Z .. 68
102
Z .. 68
lol
Z .. 68
10"
INPUT FREQUENCY I1II- kHz
ALL TYPES
TEST CONDITIONS
LIMITS Fig.2 - Typical power dissipation vs. frequency.
V DD
TYP. MAX.
VOLTS
Propagation Delay Time, 5 125 250
tpHL, tpLH 10 60 120 ns
15 45 90
5 100 200
Transition Time, 10 50 100 ns
trHL, tTLH 15 40 80
Input Capacitance, CIN Any Input 5 7.5 pF
,
CRAIN~TO~SOURCE VOLTAGE (VDSI-V
Fig.3 - Typical output low (sink) current

characteristics.
a
• tI.t~
3011 6(0)
4(131
DO
LOGIC DIAGRAM 1
*PROTECTED
All. INPUTS ARE
BY
INVERTER AND I Of 2 GATES
7 (NUMBERS IN PARENTHESES ARE
DRAIN-lO-SOURCE VOLTAGE (Vcsl-V
COS/MOS PROTECTION VSS TERMINAL NUMBERS FOR SECOND GATE)

NETWORK Fig.5- Minimum output/ow (sink)
Vss Fig.4 - Schematic and logic diagrams for CD4000B. cu "en t characteristics.
59
ORAIN- TO-SOURCE VOLTAGE (Vosl-V
1(8,6'13}~
J'
(10.4,11)
2(9,5,12)
LOGIC DIAGRAM
~~.
ADD
J 1.
(9;0:' q~
*ALL INPUTS ARE PROTECTED BY
COS/MOO PROTECTION NETWORK
I OF' 4 GATES
(NUMBERS IN PARENTHESES
92CS-21901
ARE TERMINAL NUMBERS
FOR OTHER GATES) Fig.9 - Tvpical output high (sourcel
curren t ~haracteristics.
;:ig.6 - Schematic and logic diagrams for C04001B.
ORAIN-TO-SOURCE VOLTAGE (VOS1-V
2(121~
3 {Ill
1(13)
4(101
5(9)
LOGIC DIAGRAM
Fig. 10 - Minimum output high (source}

current characteristics.
iEAL.L INPUTS ARE PROTECTED BY

COSIMOS PROTECTION NETWORK
10F 2 GATES (NUMBERS IN

PARENTHESES ARE TERMINAL
"UMBERS FOR SECOND GATE)
Fig.7 - Schematic and logic diagrams for CD4002B.
'(I'III~
4(2,12) 6
(9.101 LOAD CAPACITANCE ICLI-pF
5(8,131
LOGIC DIAGRAM Fig. It - Typical transition time vs. load

capacitance.
12.12) fiDD
.*
IB,131
* BY
Y .
ALL INPUTS ARE PROTECTED
COSIMOS PROTECTION
10F 3GATES (NUMBERS IN NETWORK
PARENTHESES ARE TERMINAL
NUMBERS FOR OTHER GATES)
LOAD CAPACITANCE {ct.1 - pF
Fig.S - Schematic and logic diagrams for CD4025B.

Fig. 12 - Typical propagation delay rime
vs. load capacitance.
60
VOO
INPUTOVOO
OUTPUTS o
Voo 1NPUOS
VOO NOTE' Vss
V,"
~
Vss
~::~~:i,~~~~~S
TO BOTH Voo AND Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
VI: - - t
VOD OR Vss' NOTE:
Vss Vss TEST ANY COMBINATION
OF INPUTS
Fig. 13 - Input leakage current Fig. 14 - Input-voltage Fig. 15 - Quiescent-device

test circuit. test circuit. current teSt circuit.
TERMINAL ASSIGNMENTS (TOP VIEW)
I. I. voo I. I. VDO J&~ I. I. VDD

I. I. VDO
NC{
" 2
" A 2
" K'E+F+GfH "
•
12
A 12 J=m 12 12
B
10 Ka5+ffi
K~m
C 10
M'G+'H
laE+F "
10
"
10 L=G+H+I
K~5+Ti-F 9 J=A+B+C
H=A+8+C 9 L-G 9 F NC 9 VSS C
Vss Vss Vss NC
92CS-24445RI 92CS-24446RI 92CS-2446BRI

He=NO CONNECTION Ne.NO CONNECTION HC=NOCONNECTION N C. NO CONNECTION
CD4000B CD4001B CD4002B CD4025B

CHIP PHOTOGRAPHS
Dimensions and Pad Layouts
o 10 20 30 40 50 60 68
52-60
1.320-1.524)
CD4001B
CD4000B
57-65
1.448-1.6511
92CS-35060
CD4002B CD4025B
61
CD4000UB, CD4001 UB, CD4002UB, CD4025UB Types
CMOS NOR Gates Features:

High-Voltage Types (20-Volt Rating) CL = 50 pF, VDD = 10 V He
Dual 3 Input • Standardized symmetrical output characteristics
NC
plus Inverter-CD4000UB • 100% tested for maximum quiescent current
Quad 2 Input-CD4001UB at 20V
Dual 41nput-CD4002UB • Meets all requirements of JEDEC Tentative
Triple 3 Input-CD4025UB Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices"
• Maximum input current of 1 /lA at 18 V
RCA-CD4000UB, CD4001UB, CD4002UB, over full package-temperature range;
and CD4025UB NOR gates provide the 100 nA at 18 V and 25°C 92CS·24757
system designer with direct implementation • 5-V, 10-V, and 15-V parametric ratings CD40DDUB
of the NOR function and supplement the FUNCTIONAL DIAGRAM
existing family of CMOS gates.
The CD4000UB, CD4001UB, CD4002UB,
and CD4025UB types are supplied in 14-lead
and F suffixes), 14-lead dual-in-line plastic
suffix).
STATIC ELECTRICAL CHARACTERISTICS CD40D1UB

FUNCTIONAL DIAGRAM
LIMITS AT INDICATED TEMPERATURES (DC)
CONDITIONS Values at-55, +25, +125 Apply 10 D, F, K, H Packages
CHARACTER- Value. at -40, +25, +85 Apply to E Package
ISTIC UNITS
+25
Vo
(V)
VIN VDD
(V) (V) -55 -40 +85 +125 Min. Typ. Max. ,. VDD
Quiescent Device - .0,5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 " --
J:A+B+C+D
13
Current. - 0,10 10 0.5 0.5 15 15 - 0.01 0.5
100 Max. J1A
- 0,15 15 1 1 30 30 - 0.01 1
- 0,20 20 5 5 150 150 - 0.02 5
Output low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
Nt
IOlMin. 015 15 4.2 4 2.8 2.4 3.4 6.8 -
1.5
K"'~
0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
Output High 4.6
(Source) 2.5 0.5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - 92C5·24758
Current, CD4002UB
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - FUNCTIONAL DIAGRAM
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
low-level,
Val Max.
- 0,10 10 0.05 - 0 0.05
- 0,15 . 15 0.05 - 0 0.05
Output Voltage: - 0,5 5 4.95 4.95 5
V ,. VDD
High-level,
VOH Min.
- 0,10 10 9.95 9.95 10
"
- 0,15 15 14.95 14.95 15 -
Input low 0.5,4.5 - 5 1 - - 1
Voltage,
Vil Max.
1,9 - 10 2 - - 2
1.5,13.5 - 15 2.5 - 2.5
V
Input High 0.5 - 5 4 4 - -
Voltage, 1 - 10 8 8 - -
VIH Min. 1.5 - 15 12.5 12.5 - -
Input Current
liN Max. - 0.18 18 to. 1 to.l tl tl - tl0- 5 to.l J1A CD4025UB
FUNCTIONAL DIAGRAM
62
.M8IENT TEMP !'ATURE I~A'.n·c
selected so that operation is always within the following ranges: i&:r.' 8- >-0"
LIMITS ~
! ..
MIN. MAX. ~ 'ov
Supply·Voltage Range IFor

T A = Full Package Temp· 3 18 V
erature Rangel ~ ~
MAXIMUM RATINGS, Absolute·Maximum Values: INPUT VOLTAGE fVr l - V ucs-z. . ,u.
DC SUPPLY·VOL TAGE RANGE, IV DD )

Fig. 1 - Minimum and maximum voltage
(Voltages referenced to VSS Terminal) -0.5 to +20 V transfer characteristics.
DC INPUT CURRENT, ANY ONE INPUT ±lOmA
POWER DISSIPATION PER PACKAGE (PO):
For T A = -40 to +60 0 C (PACKAGE TYPE E) . . . . . . , .. 500mW [{"UP~LY VOLTAGE
I
For TA = +60 to +85 0 C (PACKAGE TYPE E) . . Derate Linearly at 12 mW/oC to 200 mW ~VDDI.15V
For TA = -55 to +100 0 C (PACKAGE TYPES D,F,K) . . . . . . . . .. 500mW

For TA = +100 to +125 0 C (PACKAGE TYPES 0, F, Kl. Derate Linearly at 12 mW/oC to 200 mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types) 100mW
OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES 0, F, K, H . -55 to +125 0 C
PACKAGE TYPE E . -40 to +85 0 C
STORAGE TEMPERATURE RANGE ITstg ) -65 to +150°C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
INPUT VOLTAGE !Vtl-V
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =25°C, Input t r • tt = 20 ns. Fig. 2 - Typical voltage transfer characteristics
and C L = 50 pF. RL =200 K.\1 as a function of temperature.
ALL TYPES
TEST CONDITIONS
LIMITS
V DD
Volts TYP. MAX.
tpHL' tpLH 10 30 60 ns
15 25 50
5 100 200
Transition Time, 1(} 50 100 ns
t THL , tTLH 15 40 80
Input Capacitance, CIN Any Input 10 15 pF

Fig. 3 - Typical current & voltage transfer
characteristics.
,.
'00
,*
n DD
,*
.*
455
'" AU. INPUTS ARE
PROTECTED BY ,
COS/MOS PROTECTION ORAIN-TO-SOURCE VO~"AGE (Vos)-I/
NETWORK
Fig. 5 - Typical output low (sink) current
Fig. 4 - Schematic diagram for type CD4000UB. characteristics.
63
0-' IURC'
*ALL INPUTS ARE

PROTECTED BY
COS/MOS PROTECTION
NETWORK
ORA"'-TO"SO",,'CE VOLTAGE 'os,-v
Fig. 9 - Minimum output low (sink)

Vss
,
DRAIN-lO-SOURCE VOLTAGE {Vosl-V
Fig. 6 - Schem~tic diagram for type CD4001UB.
9*
.*
3*
'0*
11*
2*
Fig. 10 - Typical output high (soufce)

&
DRAIN-TO-SOURCE VOLTAGE (\Iosl-V
-15 -10 -5
AIiIBIENT TEMPERATURE (TAJo25"C
Vss 92CM-I505IRZ
00 *'U.'NPUTSARE '
PROTECTED BY .,
COSI MOS PROTECTI~
NETWORK
vSS
-IOV •
·0
Fig. 7 - Schematic diagram for type CD4002UB.
. !:,
<-15V
r-------------------~--------------------~_oVOO
,.
,* ,* 11* Fig. 11 - Minimum output high (source)
PROTECTED BY
COS/NOS PROTECTION
NETWORK
g V
55
7
'---->----<'--------<'---__'___~_________'----.....----~_<OvS5
*a.L1. INPUTS ARE

OO
Fig. 8 - Schematic diagram for type CD4025UB. Fig. 12 - Typical transition time VS. load
capacitance.
64
TERMINAL ASSIGNMENTS
Ne:
I.
,
2 "
"
12
VOD
II
H;A+BtC
,
10 K'O+E+F
L'G
Vss • G
92CS- 2444~ AI
N( ,,"0 (0,,"N[(110N
CD4000UB
LOAD CAPACITANCE !CLI-pF

I. I. VOD
Fig. 13 - Typical propagation delay time J;ffi ,

2
"
12
vs. load capacitance. K=C+O II M'G+H
C
,
10 L,E+"""F
92CS-35054
;~=~~TD~SES~~!~~~~R~.!~~~~i~ :CpOUIESCENT L
•
105
~ CD4001UB
4
CD4001UB
?10
.~ 103
~ 102
SUPPLY VOLTS{IJ oJ'15
J;A+STCTO I. I. VDD
A 2
"
12
K'E+F+G+H
II
'0
LOADCAPACITANCElCLJ'15pf
NC 9
CL'50pf- -
V5S • NC
,,2 ,0'
NC'NO CONNECTION 65-73
INPUT FREQUENCY!lII-Hr (1.652-1.854)
CD4002UB
Fig. 14 - Typical power dissipation vs. frequency.
VDD
I.
2 "
"
12
VDO
G
II
INPUTS 1"0 L;~I
o 9 J=A.e.c
Vss C
92C5-27148
N(' NO CONN[( TION 92CS-24468 RI
CD4002UB
CD4025UB
CHIP PHOTOGRAPHS
Fig. 15 - Quiescent·device·current test circuit.
INPUTQVOO
OUTPU. TS
V,H
"-0-...
V~L
~
r
NOTE
vss TEST ANY COMBINATION
OF INPUTS
92CS-27441RI
Fig. 16 - Input· voltage test circuit.
CD4025UB
DD
Voo INPuV
( J s NOTE The photographs and dimensions of each CMOS chip
represent a chip when it is part of the waler. When the
~ ~i~~~:;I~~~~~S 92C$·27146 wafer is separated into individual chips, the angle of
Vss TO BOTH Voo AND VSS cleavage may vary with respect to the chip lace for
CONNECT ALL UNUSEO CD4000UB dilferent chips. The actual dimensions of the isolated
INPUTS TO EITHER
chip. therefore, may differ slightly from the nominal
Voo OR VSS· Dimensions in parentheses are in millimeters and are dimensions shown. The user should consider a tolerance
VSS o;J2C5-21402 derived from the basic inch dimensions as indicated. of -3 mils to +18 mils applicable to the nominal
Fig. 17 -Input leakage current test circuit. Grid graduations are in mils (10- 3 inchJ. dimensions shown,
65
CD4006B Types
CMOS 18-Stage Features:

- Fully static operation
Static Shift Register - Shifting rates up to 12 MHz @ 10 V (typ.)
High-Voltage Types (20-Volt Rating) - Permanent register storage with clock line high or low -
no information recirculation required
The RCA-CD4006B types are composed of - 100% tested for quiescent current at 20 V
4 separate shift register sections: two sec- - Standardized, symmetrical output characteristics
tions of four stages and two sections of five - 5-V, 10-V, and 15-V parametric ratings
stages with an output tap at the fourth - Maximum input current of 1 p.A at 18 V
stage. Each section has an independent over full package-temperature range; 100
single·rail data path. nA at 18 V and 25°C
• Noise margin (full package·temperature
A common clock signal is used for all stages.
range) = 1 Vat VOD = 5 V
Data are shifted to the next stage on nega· 2 V at VDD = 10 V
tive-going transitions of the clock. Through 2.5VatVDD=15V FUNCTIONAL DIAGRAM
appropriate connections of inputs and out-
puts, multiple register sections of 4, 5, 8, - Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
and 9 stages or single register sections of 10,
for Description of '8' Series CMOS Devices"
12, 13, 14, 16, 17 and 18 stages can be TRUTH TABLE FOR SHI FT REGISTER STAGE
implemented using one CD4006B package. 0 CL'" 0+1
longer sh ift register sections can be assem·
bled by using more than one CD4006B.
Applications: 0 \... 0
- Serial shift registers - Frequency division 1 \... 1
To facilitate cascading stages when clock
rise and fall times are slow, an optional out·
- Time delay circuits X ..r NC
put (D1+4') that is delayed one·half clock- TRUTH TABLE FOR OUTPUT FROMTERM.2
cycle, is provided (see Truth Table for Out· CL 0,+4 CL'" 0,+4'
put from Term. 2).
0 ...r 0
The CD40068 types are supplied in 14-lead 1 ...r 1
hermetic dual-in-line ceramic packages (D x '-x NC
and F suffixes), 14-lead dual-in-line plastic = DON'T CARE
1 = HIGH
packages (E suffix), 14-lead ceramic flat ~U.rth OR 0 = LOW '" = LEVEL CHANGE
packages (K suffix), and in chip form (H CL .th STAGE NC = NO CHANGE
suffix). 92CS-17887RI
Fig. 1 - Logic diagram and truth table (one register stage).
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted. For maximum

reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
TERMINAL ASSIGNMENT CHARACTERISTIC liMITS UNITS

VOD
(V) Min. Max,
0,
01+ 4'
CLOCK
I.
• "
13
VDD
°1+ 4
Supply-Voltage Range (For T A = Full Package
Temperature Range) - 3 18 V
°2+ 5
D. " 5 180 -
03 "
10
°2+4
03+4 Clock Pulse Width, tw 10 80 - ns
S °4+ 5
D.
Vss 7 °4+ 4 15 50 -
TOP VIEW 5 100 -
92CS-28973
Data Setup Time, ts 10 50 - ns
15 40 -
5 60 -
ADD Data Hold Time, tH 10 40 - ns
15 30 -
Y ss
Clock Rise or Fall Time: If'tf
5,10,
15
5
-
-
15
2.5
p.S
ALL INPUTS (TERWNALS 1,3,4,5.61

PROTECTED BY COS/MOS PROTECTION Clock Input Frequency, fCl 10 - 5 MHz
NETWORK
15 - 7
66
CD4006B Types
MAXIMUM RATINGS, Absolute·Maximum Values: AMBIENT TEMPERATURE (TAI-25"C;tnt Hl+H H-t
DC SUPPLY·VOL TAGE RANGE, (V DD ) il iJ:itllill:t:J:
(Voltages referenced to VSS Terminal! I
. -0.5 to +20 V -J
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to V DD +0.5 V ~ 30 GATE-lO-SOURCE VOLTAGE (VGS,.15 V
DC INPUT CURRENT, ANY ONE INPUT ±10mA
POWER DISSIPATION PoER PACKAGE (PO): i 25
For T A = -40 to +60 C (PACKAGE TYPE E) . . . . . . . .. 500 mW
~
For T A = +60 to +85°~ (PACKAGE TYPE E). . .
20
Derate Linearly at 12 mW/oC to 200 mW
For T A = -55 to +100 C (PACKAGE TYPES 0, F, K). . . . . . . . .. 500mW § 15 IOV
For TA = +100 to +125°C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mW/oC to 200 mW •

9
DEVICE DISSIPATION PER OUTPUT TRANSISTOR ~ 10
FOR T A = FULL PACKAGE·TEMPERATURE RANGE (All Package Types) 100mW 5 5 5V
OPERATING·TEMPERATURE RANGE (T A):
PACKAGE TYPES 0, F, K, H . -55 to +125°C 5 10 15
PACKAGE TYPE E -40 to +85°C DRAIN-lO-SOURCE VOLTAGE IVosl-V
STORAGE TEMPERATURE RANGE (T stg ) . . -65 to +150 oC
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. characteristics.
•
AMBIENT TEMPfRATURE ITA'"25"C
~
LIMITS AT INDICATED TEMPERATURES (OC) E

I
CONDITIONS Value. at -55, +25, +125 Apply to 0, F, K, H ,Packages ~1!5
CHARACTER· Value. at -40, +25, +85 Apply to E Package ~ GATE-TO-SOURCE VOLTAGE (VGS,*15V
ISTIC UNITS ~t2.5
+25
Va VIN VDO
(V) (V) (V) -55 -40 +85 +125 Min. Typ, Max. a 10
Quiescent Device - 0,5 5 5 5 150 150 - 0.04 5 10V
Current, - 0,10 10 10 10 300 300 - 0.04 10

100 Max. /lA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - 5 10 15
DRAIN-TO-SOURCE VOLTAGE (Vosl-V
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOlMin. -
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 Fig. 3 - Minimum output low (sink) current
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA characteristics.
Output High
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - DRAIN-TO-SOURCE VOLTAGE (Vosl-V
Current,
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - -15 -10 -5
IOH Min. AMBIENT TEMPERATURE (TAI*25·C
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
GATE-TO-SOURCE VOLTAGE (VGSI~-5V
Output Voltage: - 0,5. 5 0.05 - 0 0.05 • ~f

low·level, -IO~
VOL Max.
- 0,10 10 0.05 - 0 0.05
- 0,15 15 0.05 - 0 0.05
V -15 ~
Output Voltage: - 0,5 5 4.95 4.95 5 - -IOV
-20~
High·level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input low 0.5,4.5 - 5 1.5 - - 1.5 -15V
Voltage, 1,9 - 10 3 - - 3
Vil Max.
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - - Fig. 4 - Typical output high (sourcel current
characteristics.
VIH Min. 1.5,13.5 - 15 11 11 - -
ORAJN-TO-SOURCE VOLTAGE (Vosl-V
I nput Current
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 /lA -15
AMBIENT TEMPERATURE nAI.~·C
-10 ·5
GATE-TO-SOURCE VOLTAGE (VGS}.-5 V
-IOV
-15 V
Fig. 5 - Minimum output high (source) current

characteristics.
67
CD4006B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =2fPC; Input t" tf = 20 ns,
CL =50pF, RL =200KfI.
TEST CONDITIONS TYPICAL

VDD(V) VALUES
5 200
Propagation Delay Time,
10 100 ns
tpHL, tplH 15 80
5 100
Transition Time,
10 50 ns
tTHl, tTlH 15 40
5 50
Minimum Data Setup Time,
10 25 ns LOAD CAPACtTANCE.ICL)-pF 92C$-24322
ts Fig. 7 - Typical transition time as a function of

15 20 load capacitance.
5 100
Minimum Clock Pulse Width,
10 45 ns
tw 15 30
5 5
Maximum Clock Input Frequency,
10 12 MHz
fCl 15 16
f·
5 15
Maximum Clock Input Rise or Fall
10 15 lIS ~200
Time trCl, tfCl*
15 15 0 150
i3 10V
~
Input Capacitance, CI N Any Input 5 pF ;; 100 ,.V
~
* If more than one unit is cascaded trel should be made less than or equal to the sum of the transition :t 50
ti me and th~ fi xed propagation delay of the output of the driving stage for the estimated capacitive load.
20 40 60 80 100
L.OAD CAPACITANCE {Cll-pF
92CS-29829
Fig. 8 - Typical propagation delay time as a

function of load capacitance.
•
CLOCK ·
-.
-~
AMBIENT TEMPEonE ITA I- 2'·C
, r-- -----j11 - ,4,

~~
~
,;~;,~
I
~104
c •
_f-I,-~/' ~~=t=T ;
--++
!'o • I-
~O"~'"
n. TO 14 MORE STAGES z
Q 2 t-- If ,L
02~Q ~--2-S~G-;;---- 0
~I038
::l • F= -;:,.'
,} v
f=
"""~
c • Vf-j
_ CL-SOpF
- __ CL~15pF
CL CL Oz" :!i '
cL ~IO~
·,
tl
03~Q -~--------1J 2 STAGES

10
... , ... , ... , ... ...
2
I
I 2
CL CL Q 1-------1 10 10 2 10 3 104
CL.OCK INPUT FREQUENCY (fCL1--kHz
CL TI 92CS-29827
O'~Q -+ -2-;;G~----
Fig. 9 - Typical dyanamic power dissipation
as a function of clock frequency.
CL CL Q
CL CL.
I-------~------I
101"fi"'H .~ .n
O II
I CL I
I a I 92CM·29830A 1
I I
l~~'~E~L:'~O~:C~ ____~ _~_ J
Fig. 6 - Logic diagram with detail of latch.
68
CD4006B Types
Voo
INPUTO··"~
INPUTS
o
Vss
NOTE:
VSS ~~SJNAp't~~OMBINATION
<:I2CS- 21401RI 92CS-27441RI
'DATA
tCl
-"""'2" 92CS-29828 VSS
Fig. 10 - Dynamic power dissipation test Fig. 11 - Quiescent device Fig. 12 - Input voltage test circuit.
circuit. current test circuit
Veo
~ _
o ~
Vss
INPUCS
voo
NOTE:
MEASURE INPUTS
SEQUENTIALLY,
TO BOTH Veo ANO VSS
CONNECT ALL UNUSED
20
I
40 70
•
INPUTS 10 EITHER
50
VSS VCO OR VSS
40
66-74
(\.677-1.879)
Fig. 13 - Input current test circuit.
109-117
(2.769-2.97
92CM-29744
The photographs and dimenSions of each CMOS chip

Dimensions in parentheses are in millimeters and represent a chip when it is part of the wafer, When the
are derived from the basic inch dimensions as in- wafsr Is separated into individua' chips, the angle of
dicated. Grid graduations are in mils (1(J3 inch). cleallage may v8ry with respect to the chip face for
different chips. The actual dimensions of the isolated
chip, therefore, may differ slightly from the nominal
dimensions shown. The user should consider a tolerance
of -3 mils to +16 mils applicable to the nominal
dimensions shown.
Dimensions and pad layout for CD40068H.
69
CD4007UB Types
CMOS Features:
• Standardized symmetrical output characteristics
Dual Complementary • Medium Speed Operation - tpH L. tpLH = 30 ns (typ.)
Pair Plus Inverter at 10 V
• 100% tested for quiescent current at 20 V
High-Voltage Types (20-Volt Rating)
• Meets all requirements of JEDEC Tentative
The RCA·CD4007UB types are comprised of
three n·channel and three p·channel enhance· • Maxi mum input current of 1 fJA at 18 V VSS=7
92CS-25035
ment·type MOS transistors. The transistor over full package-temperature range; VOD"'14
elements are accessible through the package 100 nA at 18 Vand 25°C

Terminal No.14 - VDO
terminals to provide a convenient means for Terminal No.7 - VSS
constructing the various typical circuits as
shown in Fig. 2. FUNCTIONAL DIAGRAM
More complex functions are possible using
multiple packages. Numbers shown in paren· RECOMMENDED OPERATING CONDITIONS
theses indicate terminals that are connected
For maximum reliability. nominal operating conditions should be selected so that
together to form the various configurations
listed.
The CD4007UB types are supplied in 14-lead LIMITS
hermetic dual-in-line ceramic packages (D CHARACTERISTIC UNITS
and F suffixes), 14-lead dual-in-line plastic MIN. MAX.
Supply·Voltage Range
suffix). (For T A = Full Package

LIMITS AT INDICATED TEMPERATURES (OC)
Applications: Valu •• at--65, +25, +125 ApplytoD. ·F. K, H Package.
CONDITIONS
• Extremely high·input impedance amplifiers CHARACTER· Value. at --40, +25, +85 Apply to E Package
ISTIC UNITS
+25
• Shapers Vo VIN VDD
(VI (VI (VI -55 --40 +85 +125 Min. Typ. Max.
• Inverters
• Threshold detector Quiescent Device - 0,5 5 0.25 0.25 7.5 7.5 - 0.01 0.25
Current, - 0,10 10 0.5 0.5 15 15 - 0.01 0.5
• Linear amplifiers 100 Max. p.A
- 0,15 15 1 1 30 30 - 0.01 1
• Crystal oscillators
- 0,20 20 5 5 150 150 - 0.02 5
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOLMin. 0,15 15 4.2 4 2.B 2.4 34 6.B
1.5
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
Output High
TERMINAL DIAGRAM
(Source) 2.5 0,5 5 -2 -loB -1.3 -1.15 -1.6 -3.2 -
Current.
Q21PlSOURCE
Q2(PIDRAIN
,.
Top View
2
,.
I>
VDD,QlaQ2aQ3IP)
:.r~~1'f{Q!(P)DRAIN
IOH Min.
Output Voltage:
9.5
13.5
-
0,10
0,15
0,5
10
15
5
-1.6
-4.2
-1.5
-4
-1.1
-2.B
-0.9
-2.4
-1.3
-3.4
-
-2.6
-6.B
0
-
0.05
Q2GATES
Q2(NI SOURCE
• '2 Q3 (NI DRAlN,Q3(P) SOURCE
03 (P) DRAIN Lew·Level,
0.05
Q2 (Nl DRAIN '0 'Q3GATES
- 0,10 10 0.05 - 0 0.05
QIGATES
VOL Max.
~(~I=,:CE 0,15 15 .0.05 - 0 0.05
Vas,Qla 02 a 03 IN} V
SUBSTRATES QUN)
.....ct Output Voltage: - 0,5 5 4.95 4.95 5 -
':tel.24"'" High·Level, -
- 0,10 10 9.95 9.95 10
VOH Min. -
- 0.15 15 14.95 14.95 15
Input Low 4.5 - 5 .1 - - 1
Voltage. 9 - 10 2 - - 2
VIL Max.
13.5 - 15 2.5 - 2.5
V
Input High 0.5 - 5 4 4 - -
Voltage, 1 - 10 8 8 - -
VIH Min. 1.5 - 15 12.5 12.5 - -
Input Current ±10- 5
liN Max.
O,lB lB ±0.1 ±0.1 ±1 ±1 - ±0.1 jJA
70
CD4007UB Types
MAXIMUM RATI NGS, Absolute-Maximum Values:

DC SUPPLY-VOLTAGE RANGE, IV Dol a) Triple Inverters
(Voltages referenced to VSS Terminal) -0.5 to +20 V
DC INPUT CURRENT, ANY ONE INPUT ±10 rnA
POWER DISSIPATION PER,PACKAGE !POl:
For TA = -40 to +60 o C IPACKAGE TYPE EI . . . . . . . . .. 500 mW (14,2,11); (8,13);
For TA = +60 to +85 0 C !PACKAGE TYPE EI . . Derate Linearly at 12 mW/oC to 200 mW (1,5); (7,4,9)
For T A = -55 to +100 0 C PACKAGE TYPES D, F, K) . . 500 mW
For TA = +100 to +125 0 CIPACKAGE TYPES D, F, K) . Derate Linearly at 12 mW;oC to 200 mW
FOR TA" FULL PACKAGE·TEMPERATURE RANGE IAII Package Typesl 100mW
OPERATING-TEMPERATURE RANGE ITAI:
b) 3 -Input NOR Gate ;~'""'12
PACKAGE TYPES D, F, K, H -55 to +12SoC IO~
STORAGE TEMPERATURE RANGE ITstgl -65 to + 150°C 92C5-15349
(13,2); (1,11);
LEAD TEMPERATURE lOURING SOLDERINGI:
At distance 1/16 ± 1/32 inch ~ 1.59 ± 0.79 mm) from case for lOs max. (12,5,8); (7,4,9)
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input t" tf = 20 ns,

CL = 50 pF, RL = 200 Krl
ALL TYPES c) 3-lnput NAND Gate ~~'"'12

IO~
I
CONDITIONS
LIMITS
VDD (1,12,13); (2,14,11);
Volts Typ. Max. (4,8); (5,9)
Propagation Delay Time: 5 55 110
tPHL, 10 30 60 ns
tPLH 15 25 50 d) Tree (Relay) Logic
5 100 200
lTHL. 10 50 100 ns
Transition Time
lTLH 15 40 80
Input Capacitance CIN Any Input 10 15 pF
B I
OUT
12
A 3
c•
# ALL P-UNIT SUBSTRATES

ARE CONNECTED TO VOD
ALL N-LfoIIT SUBSTRATES
ARE CONNECTED TO VSS VSS
Voo
(4'9'8)~'
a'
*C051P.405 INPUT (13,12,5); A c
PROTECTION NETWORK
(14,2); (1,11) B
OUT
.
Voo
A B OUHVDOl=C .. AB
01 - N+TO P WELL ~ MtVssl=CA+CB
cos I MOS OUTPUT PROTECTION
NETWORK BETWEEN TERMINAL
0' OUTPUT
02 = p+ro SUBSTRATE
RI- 1-5 Kn
R2- 15-30n
NOS. 1,2,4,5,6,9,11,12,13 TERMINAL :Jvss
AND THE CORRESPONDING
DRAINS ANDIOR SOURCES
01 --- or
Vss Fig. 2 - Sample COS/MOS logic circuit arrangements

Fig. 1 - Detailed schematic diagram of CD4007UB showing input, output, and parasitic diodes. using type CD4001UB.
71
CD4007UB Types
el High Sink-Current Driver
(6,3,101; (8_5, 121;
(OPTIONAL VDO PULL-UP) (11,141; 7.4,91
92C$-15330
'Iss INPUT \lOLTAGE (VI:1-V
92CS-11786
Fig. 3 - Typical voltage-transfer characteristics
fl High Source-Current Driver (6,3,101; (13,1,121; for NAND gate.
(14,2,111; (7,91
I----<---~@
I--
'1
{OPTIONAL VSSPULL-DOWN}
92CS-I0327 A-SINGLE INPUT ONLY}

Vss e - TWO lNPUTS ONLY
C - THREE INPUTS
II OTHER INPUTS
SWITCHED TO GROUND
gl High Sink - and Source-Current Driver hI Dual Bi-Directional Transmission Gating
Voo 12.!5 IS.

INPUT VOLTAGE tVtl-V

for NOR gate.
92CS-15347
(1,5,121; (2,91;
(11.41; (8,13,101;
(6,3,101; (14,2,111;
(7,4,9); 13,8,1,5,12) V55 92CS-15328
(6,31
Fig. 2 - Sample COS/MOS logic circuit arrangements using type CD4007UB (Cont'd).
DRAIN-TO-SOURCE VOLtAGE t -v
Fig. 5 - Typical output low (sink)
>
" -0
f'2.5
~"
'0
~::'i.
":'
'0
'"
7~: ~
"
~ 5
~ ~ID-- 0
TERM. 3 81 6 TO GIIID
25 '0 25
INPUT VOLTAGE {VI J -v 92C$- 28836RI

7.5 12.5
INPUT VOLTAGE !V:tl-V
15
,
DRAIN-TO-SOURCE VOLTAGE
Fig. 6 - Minimum and maximum voltage-transfer Fig. 7 - Typical current and vOltage-transfer Fig. 8 - Minimum output low (sink)
characteristics for inverter. characteristics for inverter. current characteristics.
72
CD4007UB Types
DRAIN-TO~SDURCE VOLTAGE IlIosl-V
,
'NPUTO-
Voo OUTPUTS
Fig. 9 - Typica' output high (source) V'H
current characteristics. Fig. 13 - Typical transition time vs. load '--
V~L
~
J
•
capacitance.
DRAIN~TO~SOURCE VOLTAGE IVDSI-V
NOTE:
TEST ANY ONE INPUT
Vss WITH OTHER INPUTS AT
Veo OR Vss'
Fig. 16 - Input voltage test circuit.
VDO
VOD
INPUTS
o
Vss
Fig. 10 - Minimum output high (source)

current characteristics. Fig. 14 - Typical dissipation vs. frequency
Vss
characteristics.
Fig. 17 - Quiescent device current test circuit.
i
~o
,ov
= 10
ffj",
tIt-we
12S-C
INPUT VOLTAGE rv[)-v " 50-58
]<~J
as a function of temperature.
54-62
92CS-2B635
DIMENSIONS AND PAD LAYOUT FOR CD4007UBH

The photographs and dimensions 01 each CMOS chip
represent a Chip when It is part of the wal". When the
wafer is separated into individual chips. the angle of
Dimension, in pafBnth"" .re in millimeterl and are cleallage may vary with respect to the chip face for
derivad 110m the baIIc inch dimen,ion, III indicated.
different chips. The actual dimensions of the Isolated
LOAD CAPACITANCE fCLI-pF 92C5-244,4,., Gn'd ".duation, ar, in mil, (U,-3 InchJ. chip, therefore, may differ slightly from the nomInal
Fig. 12 - Typical propagation delay time VI.
of -3 mils to + 16 mils applicable to the nominal
load capacitance. dimensions shown.
73
CD4008B Types
CMOS 4-Bit Full Adder

With Parallel Carry Out
High-Voltage Types (20-Volt Rating) Features:
A'
B3
I.
,.
I. VDD
B'
A3 I. Co
• 4 sum outputs plus parallel look-ahead carry-output B. 13 S.
A. S3
• High-speed operation - sum in-to-sum out, 160 ns typ; BI "
The RCA-CD400BB types consist of four
full adder stages with fast look ahead carry carry in-ta-carry out, 50 ns typ, at VDD = 10 V, AI "
10
S'
Sl
VSS CI
provision from stage to stage. Circuitry is CL =50pF TOP VIEW
included to provide a fast "parallel-carry-out" • Standardized, symmetrical output characteristics 92CS·244'O
but to permit high-speed operation in arith- • 100% tested for quiescent current at 20 V
metic sections using several CD400BB's. • Maximum input current of 1 p.A at 18 V CD4008B
CD400BB inputs include the four sets of bits over full package-temperature range; 100 TERMINAL ASSIGNMENT
to be added, Al to A4 and Bl to B4, in nA at 18 V and 250 C
addition to the "Carry In" bit from a pre- • Noise margin (over full package tempera-
vious section. CD400BB outputs include the ture range): 1 Vat VDD = 5 V
four sum bits, 51 to 54. In addition to the 2 V at VDD = 10 V
high speed "parallel·carry-out" which may be 2.5 Vat VDD = 15 V
utilized at a succeeding CD400BB section.
• 5-V, la-V, and 15-V parametric ratings
The CD4008B types are supplied in 16-lead • Meets all requirements of JEDEC Tentative
hermetic dual-in-line ceramic packages (D Standard No_ 13A, "Standard Specifications
and F suffixes), 16-lead dual-in-line plastic for Description of 'B' Series CMOS Devices"
packages (E suffix), 16-lead ceramic flat Applications:
packages (K suffix). and in chip form (H
suffix). • Binary additionlarithmetic units 82 *4
AZ
8, *6
*"
"S'~oo
SI __
AI *' T
*.
c,cr.....___..J
(CARRY IN)
STATIC ELECTRICAL CHARACTERISTICS VD D " 16

Vss '"8
vSS
LIMITS AT INDICATED TEMPERATURES (OC) *PROTECTED
All INPUTS ARE
BY
CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H Packages
CoSIMOS PROTECTION
CHARACTER- Values at -40, +25; +85 Apply to E Package NETWORK
ISTIC UNITS
Vo VIN VDD +25 92C5-27643
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max. Fig. 7 - CD40088 logic diagram.
Quiescent Device - 0,5 5 5 5 150 150 - 0.04 5

Current, - 0,10 10 10 10 300 300 - 0.04 10
100 Max. IJA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - TRUTH TABLE
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min.
1.5 0,15 15 4.2 4 2.B 2.4 34 6.8 - Ai Bi Ci Co SUM
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA a 0 0 0 0
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - 1 0 0 a 1
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - 0 1 0 0 1
IOH Min. 1 1 0 1 0
13.5 0,15 15 -4.2 -4 -2.B -2.4 -3.4 -6.B -
Output Voltage: - 0,5 5 0.05 - a 0.05 0 0 1 a 1
Low-Level, 1 0 1 1 0
VOL Max.
- 0,10 10 0.05 - a 0.05 0 1 1 1 0
- 0,15 15 0.05 - 0 0.05
V 1 1 1 1 1
Output Voltage: - 0,5 5 4.95 4.95 5 -
High-Level, - 0,10 10 9.95 9.95 10
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage,
VIL Max.
1,9 - 10 3 - - 3
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
Input Current fl0- 5
liN Max.
- O,lB 18 fO.l fO.l fl ±1 - fO.l IJA
74
CD4008B Types
RECOMMENDED OPERATING CONDITIONS at TA = 2fiDC, Except as Noted.

selected so that operation is always within the fol/owing ranges:
LIMITS
MIN. MAX.
Supply-Voltage Range (For
T A = Full Package Temp- 3 18 V
erature Range)
LOAD CAPACITANCE (CL.l- pF
MAXIMUM RATINGS,Absolute-Maximum Values:

Fig.3 - Typical sum-in to sum-out propagation delay
DC SUPPLY-VOLTAGE RANGE, (V DD )
time vs. load capacitance.
•
For TA = -40 to +60 C (PACKAGE TYPE E)
o . • . . . . • •. 500mW
For T A = +60 to +850 C (PACKAGE TYPE E) . . . Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +1000 C (PACKAGE TYPES 0, F, K) . . • . . _ . . _. 500mW
For T A = +100 to +125 0 C (PACKAGE TYPES D.-F', K). Derate Linearly at 12 mW/oC to 200 mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) 100mW
OPERATING-TEMPERATURE RANGE ITA):
PACKAGE TYPES 0, F, K, H • -55 to +125 0 C
PACKAGE TYPE E '. -40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstg ) -65 to +1500 C
At distance 1/16 ± 1/32 inch (1.59 ±O.79 mm) from case for lOs max.
L.OAD CAPACITANCE ICL.)- pF
Fig.4 - Typical carry-in to carry-out propagation

delay time vs. load capacitance.
21S0) + 90 + ISS
2ICI-Co)+ ISi-Co)+ ICI-So)-34S
A9-,2{ SO 90 15S
89-12 }S9-12 SO+ 90+ 155 ICI-Co)+ ISI-Co)+ICI-So)
LOAD CAPACITANCE (CL.l- pF

92C$-28306
Fig.5 - Typical carry-in to sum-out propagation delay

ISI-Co)HCi-So)- 90+ ISS time vs. load capacitance.
}S5-S 90 +ISS
lSI-So)
}SI-4 160
VSS ALL SUMS SETTLED AFTER 34S n.
S2CS-SIOM
Fig.2 - Tvpical propagation delay for a 16-bit adder (10 V operation)_

20 40 60 eo 100 120 140
LOAO CAPACITANCE ICL)- pF
Fig.6 - Typical sum-in to carry-out propagation delay

time vs. load capacitance.
75
CD4008B Types
DYNAMIC ELECTRICAL CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (Vosl-V
At TA = 25'C; Input tr, t,= 20ns, CL = 50pF, RL = 200kn
LIMITS
VDD
CHARACTERISTIC ALL TYPES UNITS
IV)
TYP. MAX.
tPHL, tPLH 10 160 320 ns
Sum In to Sum Out 15 115 230
5 370 740
Carry In to Sum Out 10 155 310 ns
15 115 230
5 200 400 Fig. 7 - Typical output high (source)
Sum I n to Carry Out 10 90 180 ns current characteristics.
15 65 130
5 100 200 ORAIN-TO-SOURCE VOLTAGE (VosJ-V
Carry I n to Carry Out 10 50 100 ns -15

AMBIENT TEMPERATURE ITA)" 25'C
-10
15 40 80 GATf-TO-SOURCE VOLTAGEIVGS"-5V
Transition Time: 5 100 200
lTHL, tTLH 10 50 100 ns
-,
15 40 80
I nput Capacitance, CI N - 5 7.5 pF -10'1
-15V
Fig.S - Minimum output high (source)

AMBIENT TEMPERATURE (TAI-Z5-C
1
I
~ 15
GATE TO-SOURCE VOLTAGE (VGS1-15V~.
ffi12.5
~
a 10
10V
LOAD CAPACITANCE 1Cl)'15p'

CL-50pF
I 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VosJ-V DRAIN-TO-SOURCE VOL.TAGE (VOSI-V
10' 103 '0'
INPUT FREQUENCY It.l-~HI
Fig.9 - Typical output low (sink) Fig. to - Minimum output low (sink)
Fig. 11 - Typical dissipation characteristics.
current characteristics. current characteristics.
INPUTS
o
Vss
DD
Voo 1 N P UV
O S NOTE
~ ~:~~~:;I~~~~~S
Vss TO BOTH Voo ANO VSS'
Vss
INPUTS 10
CONNECT ALL UNUSED
EITHER
Voo OR VSS'
Vss
Fig. 12 - Quiescent-device-current test circuit. Fig. 13 - Input-voltage test circuit. Fig. 14 - Input current test circuit.
76
CD4008B Types
79-87
~]'""
'U.I'U"_.UIO'.'8:0~"_91
1-+-----(2.108-2.311) -----...J
I
92CS-21745
II
Dimensions in parentheses are in milli- The photographs and dimensions of each CMOS chip
meters and are derived from the basic represent B chip when it is part of the wafer, When the
inch dimensions as indicated. Grid wafer is separated into individual chips, the angle of
graduations are in mils (10- 3 inch). cleavage may vary with respect to the chip face lor
chip, thefefore, may differ slightly (rom the nominal
dimensions shown. The user should considers tolerance
of -3 mils to +16 mils applicable 10 the nominal
dimensions shown.
Dimensions and Pad Layout for CD4008BH
77
CD4009UB, CD4010B Types
CMOS Hex Features:
Buffers/Converters • 100% tested for quiesce"t current at 20 V

• Maximum input current of 1 J.l.A at 18 V over full
High-Voltage Types (20-Volt Rating) package-temperature range; 100 nA at 18 V'and 25°C
• 5-V, 10-V, and 15-V parametric ratings ~,~
u---y--v
Inverting Type: CD4009UB c I-e
Non-Inverting Type: CD4010B

Applications: .
o
~, ,O~
u---y--v
""-- _
J. 0
• CMOS 10 DTLlTTL hex converter NCQE

The RCA-C04009UB and C04010B Hex • CMOS currenl "sink" or "source" o--L ...i'.~-
Buffer/Converters may be used as CMOS to driver
Vee
vsso-!
E u---y--v K'E
TTL or DTL logic-level converters or CMOS • CMOS high-la-low logic-level vooo-J!

.
high-sink-current drivers.
The C04049UB and CD4050B are preferred
converter F
~ "- L'F
92SS-4140R2
• Multiplexer - 1 10 6 or 6 to 1 CD400QUB
hex buffer replacements for the C04009UB
FUNCTIONAL DIAGRAM
and CD4010B, respectively, in all applica-
tions except multiplexers. For applications
not requiring high sink current or voltage
conversion, the CD4069UB Hex Inverter is Vee I. I. Voo "ce
G·. I. .. VOD
recommended.
G"A
A
•
0 " L-' • 0
I•
,L·'
H-B' " Ne " Ne
The C04009UB and C04010B types are
supplied in 16-lead hermetic dual-in-line •
13
K=E
H·B
B
13
K·.
" •J-O " •
I ~c " I·e "
ceramic packages (0 and F suffixes), 16- e 1O e 1O J·D ~.~
Vss Vss C~I.C
lead dual-in-line plastic packages (E suffix), 9 0
16-lead ceramic flat packages (K suffix), TDPVI£W TOP VIEW
92CS_2""!llRI 92CS_Z'l452Rl ~'O~'
and in chip form (H suffix). Ne- NO CONNECTION Ne- NO CONNECTION O~J.o
CD4009UB CD4010B
DC SUPPLY-VOLTAGE RANGE, (VDD, VCC)
-0.5 to +20 V CD4010B
(Voltages referenced to VSS Terminal) FUNCTIONAL DIAGRAM
INPUT VOLTAGE RANGE, ALL INPUTS. -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT • ±10mA
POWER DISSIPATION PER PACKAGE (PO): .... SIENT TEMPERATURE 11",-25-C MAX.
For TA ~ -40 to +60o C (PACKAGE TYPE E) . • • • • • • •• 500mW
For TA = +60 to +85 0 C (PACKAGE TYPE E) • • . Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100 C (PACKAGE TYPES 0, F. K) .
o , • • • . . • • • 500mW C>-t>-8
For TA = +100 to +125 0 C IPACKAGE TYPES D. F, K) • Derate Linearly at 12 mW/oC to 200 ritW
~~61T10N: VCC '5
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) loomW
PACKAGE TYPES 0, F, K, H -55 to +12SoC
PACKAGE TYPE E • -40 to +8SoC
STORAGE T6MPERATURE RANGE (Tstg ) -65 to+150oC
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s rna •.
Ii 8 10
INPUT VOl.TS IV,I
Fig. 3 - Minimum and maximum voltage transfer

ch.racteristics-CD4009UB.
ADO
*A~IN::tss
CONfiGURATION:
CONFIGURATION HEX COS/MOS TO Oll OR Tn
HEX COStMOS TO OTL OR TTL CONVERTER (HON·INVERTING)
CONVERTER (INVERTING) WIRING SCHEDULE:
WIRING SCHEDULE:
CONNECT Vee TO OTL OR PROTECTED BY
CONNECT Vee TO OTL OR
TTL SUPPLY. TTL SUPPLY COS/MOS PROTECTION
CONNECT YDD TO COS/MOS CO~ECT VDO TO COS/MOS NETWORK
SUPPLY SUPPLY.
'55 92SS-4159RI 92SS-4141"2
Fig. 1 - Schematic diagram of CD4009UB- Fig. 2 - Schematic diagram of CD4010B-

1 of 6 identical stages. 1 6f 6 identical stages.
78
operation is always within the fol/owing ranges:
LIMITS
CHARACTER ISTIC UNITS
MIN. MAX.
Supply·Voltage Range (For T A - Full
Package Temperature Range). V[;)D 3 18 V
VCC' 3 VDD
Input Voltage Range (VI) VCC' VDD V
·The CD4009UB and CD401 DB have high-ta-Iow level voltage conversion capability but not ',?w-to-
high level, therefore it is recommended that VOO;;' VI ;;. Vee. Fig. 4 - Typical voltage trilnsfer characteristics
as function of temp.-CD4009UB.
CHARAC·
TERISTIC
CONDITIONS
Vo VIN VDD -55 -40

(V) (V) (V)
Limits At Indicated Temperatures (OC)
Values at -55,+25,+125 Apply to D,F,K,H Pkgs.
Values at -40,+25.+85 Apply to E Package
+85 +125
Min.
+25
Typ. Max.
UNITS •
- -
.
Quiescent 0,5 5 1 1 30 30 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
}1A , ,
Current, I DD - 0,15 15 4 4 120 120 - 0.02 4 INPUT VOLTS lVI'
Max. - 0,20 20 20 20 600 600 - 0.04 20

Fig. 5 - Minimum and maximum voltage transfer
Output Low 0.4 0,5 4.5 3.2 3.1 2.1 1.B 2.6 3.4 characteristics IV DD~5)-CD4010B.
(Sink) 0.4 0.5 5 3.75 3.6 2.4 2.1 3 4 -
Current 0.5 0,10 10 10 9.6 6.4 5.6 8 10 -
IOL Min. 1.5 0,15 15 30 40 19 16 24 36 - mA
Output High 4.6 0,5 5 -0.25 --0.23 --0.18 -0.15 -0.2 -0.4 -
(Source) 2.5 0,5 5 -1 -0.9 -0.65 -0.58 -0.8 -1.6 -
Current 9.5 0,10 10 -0.55 -0.5 -0.38 -0.33 -0.45 -0.9 -
IOH Min. 13.5 0,15 15 1.65 -1.6 -1.25 -1.1 -1.5 -3 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low·Level, - 0,10 10 0.05 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High-Level, - 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 15 -
INPUTYOLTS('II
Input Low
Voltage:
4.5 - 5 1 - - 1 Fig. 6 -Minimum and maximum voltage transfer
9 - 10 2 - - 2 characteristics IV DD~10)-CD4010B.
VIL Max.
CD4009UB
13.5 - 15 2.5 - - 2.5
Input Low
Voltage:
0.5 - 5 1.5 - - 1.5
1 - 10 3 - - 3 /
VIL Max.
CD4010B
1.5 - 15 4 - - 4
V
Input High
Voltage:
0.5 - 5 4 4 - -
1 - 10 8 8 - -
VIH Min.
1.5 - 15 12.5 12.5 - -
CD4009UB
Input High
4.5 - 5 3.5 3.5 - -
Voltage:
9 - 10 7 7 - -
VIH Min.
13.5 - 15 11 , 11 - -
CD4010B
Input Current, ±10-5 ±0.1
- 0,18 18 ±0.11 ±0.1 ±1 ±1 - }1A Fig. 7 - Minimum and maximum voltage transfer
liN Max.
characteristics IVDD~15)-CD4010B.
79
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=25°C; Input t" tr=20 lIS,
CL=50pF, RL=200Kn
LIMITS·
CONDITIONS
ALLPKGS
VDD VI VCC
CHARACTERISTIC UNIT
IV) IV) IV) TYP. MAX.
Propagation Delay Time:

Low·to·High, tPLH 5 5 5 70 140
10 10 10 40 80
CD4009UB 10 10 5 35 70 ns
15 15 15 30 60
Fig. 8 - Typical voltage transfer characteristics
15 15 5 30 60
as a function of temperature-CD40 108.
5 5 5 100 200
10 10 10 50 100
CD40108 10 .10 5 50 100 ns

15 15 15 35 70
15 15 5 35 70
High·to·Low, tpHL 5 5 5 30 60
10 10 10 20 40
CD4009UB 10 10 5 15 30 ns
15 15 15 15 30
15 15 5 10 20
5 5 5 65 130
10 10 10 35 70 DRAIN-lO-SOURCE VOLTS IVosl
CD40108 10 10 5 30 70 ns Fig. 9 - Typical output low (sink)

15 15 15 25 50
15 15 5 20 40
Transition Time:
Low·to·High, tTLH 5 5 5 150 350
10 10 10 75 150 ns
15 15 15 55 110
High-to-Low, tTHL 5 5 5 35 70
10 10 10 20 40 ns
15 15 15 15 30
Input Captlcitance, CIN
CD4009UB - - - 15 22.5
pF
CD40108 - - - 5 7.5 10 20
ORAIN-TO-SOURCE VOLTS IVas'

DRAIN-lO-SOURCE VOLTAGE I Vos)-V
92CS·276S2RI
92CS·Z7651RI
Fig. 11 - Typical output high (source) Fig. 12 - Minimum output high (source) Fig. 13 - Typical/ow-ro-high propagation delay
current characteristics. curren t characteristics. time VS. load capacitance (CD4009UB).
80
AMBIENT TEMPERATURE (TA)'2~'C
5~ 30
~
~ 20
.
~ 10
10 20 30 40 50 60 70 SO 90 100
40 60 eo
LOAD CAPACITANCE (CL l-pF
100 120
a m w ~ ~ w ro ~ 00 ~
lOAO CAPACITANCE (Cl J-pF 92C5-2765<1 LOAD CAPACITANCE (CLI-pF
Fig. 14 - Typical high-to-Iow propagation delay Fig. 15 - Typical low-to-high propagation delay Fig. 16 - Typical high-to-Iow propagation
time vs. load capacitance (CD4009UB). time V5. load capacitance (CD4010B). delay time vs. load capacitance (CD4010B).
I
AMBIENT TEMPERATURE (TA)·25·C
I
~60
~ 50
r:
z
~ 40
z
g30
~ 20
~
~ 10
" a w ~ ~ ~ w ro 00 W ~
10 102 2 <I 6 8 ,0:' 2 104
LOAD .:ttPACITANCE (CL1-pF
INPUT FREQUENCY (f.l kHz
Fig. 17 - Typical low-to-high transition time Fig. 18 - Typical high-to-Iow transition time Fig. 19 - Typical dissipation characteristics.
V5. load capacitance. vs. load capacitance.
VDD
INPUTS 'NPUTOVOO
OUTPUTS
o V'H
Vss
'--
V~L
~
J
NOTE:
TEST ANY ONE INPUT,
VSS WITH OTHER INPUTS AT
Vao OR Vss·
100
VSS
Fig. 20 - Quiescent device current Fig. 21 - Noise immunity test
test circuit. circuit.
70-78
VDD
'NPUOs
VOO. 1.981) 92CS-276S0
~
Vss
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated. Photograph of chip for CD4009UB.
NOTE Grid Graduations Are In Mils (10- 3 Inch)
MEASURE INPUTS Vss Oimensions and pad layout for
SEQUENTIALLY, The photographs and dimensions of each CMOS chip CD40 1OB are identical.
TO BOTH Voo AND Vss represent a chip when it ;s part 01 the wafer. When the
CONNECT ALL UNUSED wafer ;s separated into individual chips, the angle of
INPlJTS TO EITHER
cleavage may vary with respect to the chip lace for
VOOORVSS·
different chips. The actusl dimensions of the isolated
Fig. 22 - Input current test dimensions shown. The usar should considera tolerance
circuit. of -3 mils to +16 mils applicable to the nominal
dimensions shown.
81
CD4011B, CD4012B, CD4023B Types
CMOS NAND GATES

Quad 2 Input -CD4011B CL=50pF,VOD=10V
Dual 4 Input - CD4012B • Buffered inputs and outputs
Triple 3 Input - CD4023B • Standardized symmetrical output characteristics
• Maximum input current of 1 p.A at 18 V
over full package temperature range;
RCA-C04011B, C04012B, and C04023B 100 nA at 18 V and 25 0 C
NAND gates provide the system designer
with direct implementation of the NAND • 100% tested for quiescent current at 20 V
function and supplement the existing family • 5-V, lo-V, and 15-V parametric ratings
of CMOS gates. All inputs and outputs are • Noise margin (over full package temperature
buffered. range:
The C04011 B, C04012B, and C04023B 1 VatVOO=5 V
92CS-24763
types are supplied in 14-lead hermetic dual- 2 V at VDD = 10 V
in-line ceramic packages (0 and F suffixes), C040118
2_5 Vat VDD = 15 V FUNCTIONAL DIAGRAM
14-lead dual-in-line plastic packages (E suf-
fix), 14-lead ceramic flat packages (K sufflxl, • Meets all requirements of JEDEC·Tentative
and in chip form (H suffix). Standard No.13A, "Standard Specifications
for Description of "B" Series CMOS Devices"

OC SUPPLY-VOLTAGE RANGE, IVpol J=:;::s.c:o
IVoltages referenced to VSS Termlna" . -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS -0_5 to V OD +0.5 V
POWER DISSIPATION PiR PACKAGE IP D):
For T A = -40 to +60. C IPACKAGE TYPE EI . . . . . . . .. SOOmW
For T A = +60 to +85 C IPACKAGE TYPE EI Derate Linearly at 12 mW/·C to 200 mW
For T A = -55 to +l00'C (PACKAGE TYPES 0, F, K) ... _ . . . .. 500mW
For T A = +100 to +125°C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mWfC to 200 mW
FOR T A = FULL PACKAGE-TEMPERATURE RANGE IAII Package Typesl 100mW Ne
OPERATING-TEMPERATURE RANGE ITA): Vss 1 K:'E'F'G'H NC
PACKAGE TYPES 0, F, K, H _ -55 to +125·C
PACKAGE TYPE E -40 to +85·C CD40128 92CS-24759
STORAGE TEMPERATURE RANGE ITS!) _ _ -65 to +150·C FUNCTIONAL DIAGRAM
LEAD TEMPERATURE lOURING SOLD~RING):
At distance 1/16 ± 1/32 inch 11.59 ±0_79 mm) from case for 10 s ma._ . +265·C

operation is a/ways within the following ranges:
LIMITS 14 ~OD
MIN_ MAX. 13
Supply-Voltage Range (For T A = Full Package

3 18 V
Temperature Range)
vss
•
• •
I.
2
I.
IS
vOD J~liC6 I.
2
I.
IS
voo
K·!mi
1.~4
2 13
_Y OD
G
CD40238
FUNCTIONAL DIAGRAM
'J2CS- 24761
J-Aii
K-C5
12 G
M.;jjI • 12 3
4
12 - H
,: ,....... I
e "
10 ",U'
11
10 '5 10' - L.'Clfj
0
vss
Ne
vss • Ne
- J"o!'e
-e
TOP VIEW TOP VIEW
TOP VIEW 92CS_Z4404 ru
92CS-24403
NC-NO CONNECTION
CD4011B CD4012B CD4023B
82
CD4011 B, CD4012B, CD4023B TypeS

CONDITIONS Values at -55, +25, +125 Apply toO, F, K, H Packages
CHARACTER· Valuer at -40, +25, +85 Apply to E Package
UNITS
ISTIC +25
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Current, - 0,10 10 0.5 0.5 15 15 - 0.01 0.5
100 Max. pA
- 0,15 15 1 1 30 30 - 0.01 1
- 0,20 20 5 5 150 150 - 0.02 5
I
Output LoVi 0.4 a,s 5 0.64 0.61 0.42 0.36 0.51 1 ..
INPUT VOLTAGE (VI' - V
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. Fig. 1 - Typical voltage transfer characteristics.
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
•
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current',
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - a,s 5 0.05 - a 0.05
Lew·Level, a
VOL Max.
- 0,10 10 0.05 - 0.05
- 0,15 15 0.05 - a 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 4,5 - 5 1.5 - - 1.5
10
Z 468
10 2
2 "68
103
2 4 68
10 4
Voltage, 9 - 10 3 - - 3 INPUT FREQUENCY ( f I l - kHz
VIL Max.
13.5 - 15 4 - - 4 Fig.2 - Typical power dissipation characteristics.
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
liN Max.
0,18 18 ±0.1 ±0.1 ±1 ±1 - ±0.1 pA
ORAIN-TO-SOURCE VOLTAGE !VOs)-V
Fig.3 - Typical output low (sink) current

characteristics.
CRAIN-lO-SOURCE VOLTAGE (Vosl-V ORAIN-TO-SOURCE VOLTAGE (Vosl-V

AMBIENT TEMPERATURE ITA)-2D-C
.•
I
I I I
~I!s
~12l5 GATE-TO-SOURCE VOLTAGE (YGS)-I!SV
Ie
B 10
10V
5V
5 10 15
DftAIN-TO-SOURCE VOLTAGE (Vosl-Y
92CS·24319111
Fig.4 - Minimum output low (sink) current Fig.5 - Typical output high (source) current Fig. 6 - Minimum output high (source) current
83
,.
VDD
VDD I.
"
•
1(131
3*(1)
LOGIC DIAGRAM
4*(10)
ROD 1(.,6,,,,~3
5*191
~31*
g
Y . ..J . . . ALL INPUTS ARE P:::ECTED
UD,4.11) BY COS/MOS PROTECTION
219.5.12) NETWORK
LOGIC DIAGRAM
* BY COSIMOS PROTECTION
ALL INPUTS ARE PROTECTED I OF 4 GATES (NUMBERS
IN PARENTHESES ARE
NETWORK TERMINAL NUNBERS
FOR OTHER GATES)
Fig. 7 - Schematic and logic diagrams for CD40118. Fig.S - Schematic and logic diagrams for CD4012B.
3I1'1l1~
412,12) 6(9,10)
5(8.131
LOGIC DIAGRAM
ROO
Y .
* BYALLCOS/MOS
INPUTS ARE PROTECTED
PROTECTION
NETWORK
Fig. TO - Typical propagation delay time per gate
I OF 3 GATES (NUMBERS IN
PARENTHESES ARE TERMINAL 7 as a function of load capacitance.
NUMIERS FOR OTHER GATES) vos
Fig. 9 - Schematic and logic diagrams for CD4023B.

At TA = 2!tC; Input tr, t,= 20ns, C L = 50pF, RL = 200Hl
ALL TYPES
TEST CONDITIONS
LIMITS
VDD
TYP. MAX.
VOLTS
Propagation Delay Ti me, 5 125 250
tpHL. tPLH 10 60 120- ns
15 45 90
5 100 200
tTHL, tTLH 15 40 80
Fig. 11 - Typical transition time as a function of
Input Capacitance, Ci N Any Input 5 7.5 pF
load capacitance.
84
o
INPUTS
Voo INPu(J'
'DO NOTE'
'55
~
Vss
... ~:~~;I~~~~~S
TO BOTH Voo ANO Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS'
'55
9ZCS-2:744IRI
Fig. 13 - Input-voltage test circuit. Fig. 14 - Input-current test circuit.
Fig. 12 - Ouiescent-device-current test circuit.
CHIP PHOTOGRAPHS
30 69
'1
OJ
51-65
11.448-1.6511
92CS-35052
J 92CS-28883
CD4011BH CD4012BH
Dimensions in parentheses are in millimeters and

are derived from the basic inch dimensions as in-
dicated. Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of 88eh CMOS chip

represent a chip when it is parI of the waf.,. When the
wafer is sepafated into Individual chips, the angle of
clsavage may vary with respect to the chip 'ace for
different Chips. The actual dimensions of the isolated
chip, therefore, may differ slightly from the nomine'
dimensions shown.
CD4023BH
85
CD4011 UB, CD4012UB, CD4023UB Types
CMOS NAND Gates

• Propagation delay time = 30 ns (typ). at
Quad 2 Input - CD4011 UB CL = 50 pF, VDD = 10 V
Dual 4 Input - CD4012UB • Standardized symmetrical output
Triple 3 Input - CD4023UB characteristics
• 100% tested for quiescent current at
The RCA-CD4011UB, CD4012UB, and 20V
CD4023UB NAND gates provide the system • Maximum input current of 1 j.lA at 18 V
designer with direct implementation of the over full package temperature range;
NAND function and supplement the existing 100 nA at 18 V and 25 0 C
family of CMOS gates. • 5-V, 10-V, and 15-V parametric ratings
CD4011UB
The CD4011 UB, CD4012UB, and CD4023UB • Meets all requirements of JEDEC Tentative FUNCTIONAL DIAGRAM
types are supplied in 14-lead hermetic dual- Standard No. 13A. "Standard Specifications
in-line ceramic packages (D and F suffixes),
14-lead dual-in-line plastic packages (E suf-
fix), 14-lead ceramic flat packages (K suffix),
and in chip form (H suffix).
Ne
Ne
~t>-------~--~--1--'
92C$-24759
CD4012UB
~
:'o-----------~----~
FUNCTIONAL DIAGRAM
,'O-------------------____J i--'-1
'0
~
.'t>--~--_+--_I_--_+_'
O----------_I_--_+_'
''''--r+--O''
goo, --
'--.......1----'
Vss
• Au.. INPUTSAR'
PROTECTED 8Y
c;,~,.'~~~ PROTECTION
"
12
,:" ~DD
V55
g
,,'t>-----------'"--_t_'
Fig. 2 - Schematic diagram for type CD401 7UB.
12t>---------------.J>-~_4
*ALL INPUTS ARE

OO Vss , V55
g
PROTECTED By
COS/MOS PROTECTION __ 92C5-24761
NETWORK
CD4023UB
OD
*ALL INPUTS ARE FUNCTIONAL DIAGRAM
PROTECTED BY
Vss COS/Mas PROTECTION
NETWORK --
Fig. 7 - Schematic diagram for type CD4072UB.

. Vss RECOMMENDED OPERATING
CONDITIONS
For maximum reliability, nominal operating
conditions should be selected so that opera-
tion is always within the following ranges.
,* CHARACTERISTIC MIN. MAX. UNITS
Supply Voltage
Range (For T A= 3 18 V
Fig. 3 - Schematic diagram for type CD4023UB. Full Package Tem-
perature Range)
86
CD4011UB, CD4012UB, CD4023UB Types
MAXIMUM RATI NGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DO)
For TA = -40 to +600 C (PACKAGE TYPE E) . . . . . . . .. 500mW
For TA = +60 to +850 C (PACKAGE TYPE E) . . . Derate linearly at 12 mW/oC to 200 mW
For TA = -55 to + 100°C (PACKAGE TYPES D,F,K) . . . . . . . . .. 500mW
For TA = +100 to +125 0 C (PACKAGE TYPES 0, F, K). Derate Linearly at 12 mW/oC to 200 mW
DEVICE DIl'SIPATION PER OUTPUT TRANSISTOR
PACKAGE TYPES 0, F, K, H . -·55 to +125 0 C
PACKAGE TYPE E . --40 to +85 0 C INPUT VOLTAGE lVII-V
STORAGE TEMPERATURE RANGE (T"g) -65 to +1500 C
LO:AD TEMPERATURE (DURING SOLDERING): Fig. 4 - Minimum and maximum voltage
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max. transfer characteristics.
CONDITIONS
LIMITS AT INDICATE') TEMPERATURES (DC)
Values at -55 +25, +125 Apply to D, F, K, H Packages-
, tttit±:tt±ttt:tt±:tJ
if::
'l'
t-
•
CHARACTER-
ISTIC
Vo VIN VDD
Values at -40, +25, +85 Apply to E Package
+25
UNITS m !;
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max. 10 15
.NPUT VOL.TAGE lVII-V
Current, - 0,10 10 0.5 0.5 15 15 - 0.01 0.5
fJA
100 Max. as a function of temperature.
- 0,15 15 1 1 30 30 0.01 1
- 0,20 20 5 5 150 150 0.02 5
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOLMin.
1.5 0,15 15 4.2 4 2.B 2.4 3.4 6.B -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
Output High
(Source) 2.5 0,5 5 -2 -1.B -1.3 -1.15 -1.6 -3.2 -
Current,
IOH Min.
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
13.5 0,15 15 -4.2 -4 -2.B -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05 a-I INPUT
b-2INPUTS
Lew·Level, e-3 INPUTS
VOL Max.
- 0,10 10 0.05 - 0 0.05 2.5 d-4 INPUTS
- 0,15 15 0.05 - 0 0.05

V ,
OTHER
Output Voltage: - 0,5 5 4.95 4.95 5 INPUT VOLTS IVI)

H igh·Level, - 0,10 10 9.95 9.95 10 Fig. 6 - Typical multiple input switching transfer
VOH Min.
- 0,15 15 14.95 14.95 15 characteristics for CD4012UB.
Input Low 4.5 - 5 1 - 1

Voltage, 9 - 10 2 - - 2
VIL Max.
13.5 - 15 2.5 - 2.5
V UPPLY VOLTS I I* I
Input High 0.5,4.5 - 5 4 4 -
12.5
Voltage, 1,9 - 10 8 8 - - >
0
VIH Min. 1.5,13.5 - 15 12.5 12.5

~
'0
10
Input Current 7.' "

liN Max.
O,lB lB ±O.l ±0.1 ±1 ±1 - ±10-5 ±0.1 fJA ~
il
2.5 10
2.5 7.' 10 12.5

INPUT VOLTS lVI'
92CS-11n2
Fig. 7 - Typical current and voltage transfer
characteristics.
87
CD4011 UB, CD4012UB, CD4023UB Types
At TA =2!tC, Inputtr, t,= 20ns, and CL =50pF, RL =200HI.
ALL TY~ES
TEST CONDITIONS
LIMITS
V DD
TYP. MAX
VOLTS
5 60 120
10 30 60 ns
tpHL' tpLH 15 25 50
5 100 200 DRAIN-TO-SOURCE VOLTAGE CVoSI-V
Transition Time,
10 50 100 ns Fig.8 - Typical output low (sink) current
tTHL' tTLH 40 characteristics.
15 80
Input Capacitance, CIN Any Input 10 15 pF
DRAIN-lO-SOURCE VOLTAGE (Vos)-V DRAIN-lO-SOURCE VOLTAGE (VDsl-V

I
DRAIN-1ro-'iOU"CE IJOLTAGE {Vosl-V

'ZCS-l4UIRl
Fig. 9 - Minimum output low (sink) current Fig. 10 - Typical output high (source) current Fig. 11 - Minimum output high (source) current
characteristics. characteristics. characteristics. .
105 :~:=Te::s~~~~~R;.I~~~~i~ ;POU1ESCENT C

~
I 10"
l'
~ 103 suPf'LY VOLTS(V 10'
10
LOAD CAPACITANCE tCLI·I~pf'
CL ·i~~F---
102
LOAO CAPACITANCE ICI..I- pF ~PUT FREQLiENCY\f,I-Hr
Fig. 12 - Typical propagation delay time vs. load Fig. 13 - Typical transition time VS. load Fig. 14 - Typical power dissipation vs.
capacitance. capacitance. frequency characteristics.
INPUTS
o
Vss DD
Voo INPu(Js
V NOTE'
~ ;~~i:i,!~~~~S
Vss TO BOTH VDe AND VSS'
CONNECT ALL UNUSED
INPUTS TO EITHER
Vee OR VSS'
VSS
92CS-2744IRI
Fig. 15 - Quiescent device current test circuit. Fig. 16 - Input voltage test circuit. Fig. 17 - Input current test circuit.
88
CD4011UB, CD4012UB, CD4023UB Types
A
B
J~Ai3
I. I~
13
12
Voo J'mo
A
I.
2
I.
13
12
Voo
K=ErG"H
I.
2 "13
12
Voo
G
K=CO MoGR II
C 10 LoU 10 F 10 L'G"Hi
0 F NC K=OEF J'ABC
Vss E Vss Ne Vss C
92C5_24453 nCS·Z4454RJ 92CS-24465

NC-NO CONNECTION
TOP VIEW TOP VIEW TOP VIEW
CD4011UB CD4012UB CD4023UB
CHIP PHOTOGRAPHS
•
61-69
~--]""
92C5-35051 '32CS-27143
CD4011UBH CD4023UBH
1.
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inchJ.
1I.575-1.778l The photographs and dimensions of each CMOS chip

represent a chip when It is part of the wafer, When the
J
wafer Is separated into individual chips, the angle of
cleavage may vary with respect to the chip face for
chip. therefore, may differ slightly Irom the nominal
01 -3 mils to +16 mils applicable to the nominsl
dimensions shown.
4~~0254l I
r - - - -.. 60-~~27l----1
CD4012UBH
89
CD40138 Types
Features:
C.MOS Dual • Set-Reset capability
'D'-Type Flip-Flop • Static flip-flop operation - retains state
indefinitely with clock level either
High-Voltage Types (20-Volt Rating) "high" or "low"
• Medium-speed operation - 16 MHz (typ.)
clock toggle rate at 10V
The RCA-CD4013S consists of two identical, • Standardized symmetrical output
independent data-type flip-flops. Each flip- characteristics
flop has independent data, set, reset, and • 100% tested for quiescent current at 20 V
clock inputs and Q and Q outputs. These de-
vices can be used for shift register applica- • Maximum input current of 1 J.l.A at 18 V
tions, and, by connecting Q output to the over full package temperature range;
data input, for counter and toggle applica- 100 nA at 18 V and 25 0 C CD40138
tions. The logic level present at the D input • Noise margin (over full package FUNCTIONAL DIAGRAM
is transferred to the Q output during the temperature range): 1 Vat VDD=5 V
positive-going transition of the clock pulse. 2 V at VDD=10 V
Setting or resetting is independent of the 2.5 V at VDD=15 V
clock and is accomplished by a high level on • 5-V, 10-V, and 15-V parametric ratings
the set or reset line, respectively.
The CD4013B types are supplied in 14-lead Standard No. 13A, "Standard Specifications
hermetic dual-in-line ceramic packages (D for Description of'S' Series CMOS Devices"
packages (E suffix). 14-lead ceramic flat Applications:
packages (K suffix), and in chip form (H • Registers, counters, control circuits
suffix).
DRAIN-TO-SOURCE VOLTAGE IV051-V
Fig_ 1 - Typical output low (sink)

RECOMMENDED OPERATING CONDITIONS current characteristics.
At TA = 25" C. Except as Noted. For maximum reliability, nominal operating condi-
tions should be selected so that operation is always within the following ranges:
V DD LIMITS
CHARACTERISTIC (V) UNITS
MIN. MAX.
Supply-Voltage Range
(For T A = Full Package - 3 18 V
Temperature Range)
5 40 -
Data Setup Time Is 10 20 - ns
15 15 -
5 140 - DRAIN-TO-SOURCE VOLTAGE (\IosI-V
92t5-2",,1t1
Fig_ 2 - Minimum output/ow (sink)
Clock Pulse Width tw 10 60 - ns current characteristics.
15 40 -
5 3.5 DRAIN- TO-SOURCE VOLTAGE Ivos,l-v
Clock Input Frequency fCl 10 dc 8 MHz

! 15 12
5 - 70
Clock Rise or Fall Time
10 - 6 /.Is
trCl: tfCl
15 - 2
5 180 -
Set or Reset Pulse Width
tw
10 80 - ns
15 50 -
*If more than one unit is cascaded in a parallel clocked op,:,ration. treL should be made less than or equal to
the sum of the fixed propagation delay time at 15 pF and the transition time of the output driving stage for Fig. 3 - Typical output high'l(~~~~~J
the estimated capacitive load. current characteristics.
90
CD4013B Types
DRAI.N-TO-SOURCE VOLTAGE eVosi-V

Values at -55,+25,+125 Apply to D,F,K,H Pkgs.
CHAAAC·
CONDITIONS Values at -40,+25,ta5 Apply to E Pkgs. UNITS
TERISTIC
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
Current - 0,15 15 4 4 120 120 - 0.02 4 Il A
100 Max. - 0,20 20 20 20 600 600 - 0.04 20
Output l.ow
(Sink) 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - Fig. 4 - Minimum output high (source)
Current, 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - current characteristics.
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 - rnA
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 -
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current,
IOH Min.
9.5
13.5
0,10
0,15
10
15
-1.6
-4.2
-1.5 -1.1 -0.9 -1.3
-4 -2.8 -2.4 -3.4
-2.6
-6.8
-
- II
Output Volt·
age: - 0,5 5 0.05 - 0 0.05
Low· Level , - 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output Volt·
age: - 0,5 5 4.95 4.95 5 -
High· Level, - 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 15 - LOAD CAPACITANCECC\. l-pF
Input Low 0.5,4.5 - 5 1.5 - - 1.5 Fig. 5- Typical propagation delay time vs. load
Voltage, 1,9 - 10 3 - - 3 capacitance (CLOCK or SET to O,CLOCK
VIL Max. 1.5,13.5 - 15 4 - - 4
V
or RESET to OJ.
Input High 0.5,4.5 - 5 3.5 3.5 - -

Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
Input
Current, - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 Il A
liN Max.
LOAD CAPACITANCE ICLJ-pF

/0'0
../'1'0 0 I 0
............. x' 0 • a Q 0
"
CHANGE Fig. 6 - Typical propagation delay time VI, load
x x , capacitance (SET to Q or RESET to O.
x x ,
LOGIC O. LOW IAMBIENT TEMPERATURE (TAJ a 25-C
LOGIC '~HIGH
I r ll,05"1
•• LEVEL CHANGE
CL o50pF
X' DON'T CARE
N!N).FFIIFF2 TERMINAL
ASSIGNMENTS
~.(.'IO-----j ~--+-""""-----' 1(13)
SET
~
DD
ZI12l
*PROTECTED
All. INPUTS ARE
BY
14o-VOD
COS/MOS PROTECTION VSS
7o-VSS NETWORK
10 20
Fig. 7 - Logie diagram and truth table for CD40138 . SUPPLY VOLTAGE (VDO!-V \l2(5-26392R2
(one of two identical flip·flopsJ. Fig. 8 - Typical maximum clock frequency vs.
supply voltage.
91
CD4013B Types
DC SUPPLY-VOLTAGE RANGE, (V DO)
(Voltages referenced to VSS Terminal! --0_5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS --0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ±10mA
For TA = -40 to +60 C (PACKAGE TYPE EI
0 • . __ . . . 500mW
For T A = +60 to +85 0 C (PACKAGE TYPE E) _ _ _ Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100 oC (PACKAGE TYPES D. F. K) . _ . . . . . . .. 500mW
0
For TA = +100 to +125 C (PACKAGE TYPES D. F. K). Derate Linearly at 12 mW/oC to 200 mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
PACKAGE TYPES D. F. K. H . _ . _ . .
PACKAGE TYPE E • . _ . _ . . . .
100mW
-55 to +125 0 C
-40 to +85 0 C
I
. 2462488"2 468
STORAGE TEMPERATURE RANGE (Tstg ) -65 to +150 0 C 102 10 3
92CS-35Z71
At distance 1116 ± 1132 inch (1.59 ± 0.79 mm) from case for 10 s max. Fig_ 9 - Typical power dissipation
vs_ frequency_
At TA = 2~C; Input t r • tf= 20ns. CL = 50pF, RL = 200HJ
TEST CIRCUITS
TEST ,I
CONDITIONS LIMITS
r---
CHARACTERISTIC V DD
(VI MIN_ TYP_ MAX.
UNITS
.
Vss
INPUTS
Propagation Delav Time: 5 - 150 300

Clock to a or Q Outputs
10 - 65 130 ns
tpHl' tplH
15 - 45 90
5 - 150 300
Set to a or Reset to a tplH 10 - 65 130 ns
15 - 45 90 Fig. 10 - Quiescent device current.
5 - 200 400
-
Set to a or Reset to a tpHl 10 - 85 170 ns
15 - 60 120
5 - 100 200
Transition Time tTHl• tTlH 10 - 50 100 ns INPUTaVDDOUTPUTS
15 - 40 80 V,--- .....!A
Maximum Clock Input Frequencv
5 3.5 7 - V~L l
Frequency # fCl
10 8 16 - MHz NOTE:
T£ST ANY ONE INPUT,
15 12 24 - Vss WITH OTHER INPUTS AT
Voo ORVss·
5 - 70 140
Minimum Clock Pulse Width W 10 - 30 60 ns Fig. 11 - Input voltage.
15 - 20 40
5 - 90 180
Minimum Set or Reset Pulse
10 - 40 80 ns
V~NPU(Js
Voo :~:~U.. IN,PUT'
Width W
15 - 25 50
5 - 20 40
Minimum Data Setup Time ts 10 - 10 20 ns o ~ SlOU[N"ALL't.
Vss TO 10TH Voo AND 'iss
CClNHECT ALL UNUSED
15 - 7 15 INPUrS TO [ITH[R
5 - - 70 Vos
Voa CRVSS
Clock Input Rise or Fall Time

t rCl• tfCl
10 - - 6 /.1.5
15 - - 2 Fig. 12 - Input current.
Input Capacitance CIN Anv Input - 5 7.5 pF
#1 nput t" tf = 5 n•.
92
CD4013B Types
VDD
01
Oi
I.
, "Il
12
vDO
0'
CLOCKI 0'
RESET I eLOct< 2
01 10 RESET 2
SETI 9 0'
Vss SEl2
TOP VIEW
92CS-244:i:iAI
TERMINAL ASSIGNMENT
92CS-36060
Fig. 13-Dynamic power dissipation test
•
circuit.
DIMENSIONS AND PAD LAYOUT FOR CD4013BH
55-63
1.397-1.600
92CS-35050
~I
The photographs and dimensions of elch CMOS chip
Dimensions in parentheses are in millimeters and are Tepresent 8 chip when it is part of the wa'e,. When the
wa'., Is separated into individual chips, the angle of
derived from the basic inch dimensions as indicated. C/88l/sge may vary with ,.spect to the chip face for
Grid graduations are in mils (10- 3 inch). diffs,sn' chips. The actual dimensions of the isolated
chip. theTefor". may differ slightly from the nomina'
dimensions shown. The usef ahould consider 8 tolerance
of -3 mils to + 16 mils applicable to the nomina'
dimensions shown.
93
CD4014B, CD4021 B Types
Features:
CMOS a-Stage • Medium-speed operation. _ . 12 MHz (typ_) clock
PAR.IN
I
Voo
rate at VOO-VSS =10 V

Static Shift Registers • Fully static operation
High-Voltage Types (20-Volt Rating) • 8 master·slave flip-flops plus output ~:....!
CD4014B:. buffering and control gating CONT
Synchronous Parallel or • 100% tested for quiescent current at 20 V ,.

SER. II
Serial Input/Serial Output • Maximum input current of 1 p.A at 18 V CLOCIC!!
CD4021B: over full package-temperature range; , 0,

100 nA at 18 V and 25 0 C
Asynchronous Parallel Input or
• Noise margin (full package-temperature
Synchronous Serial Input/Serial Output range) = 1 Vat VOO =5 V ,
'55
2 V at VOD = 10 V
The RCA-CD4014B and CD4021 B series 2.5 Vat VOO = 15 V
types are 8-stage parallel- or serial-input/ser- CD4014B, CD4021B
• Standardized, symmetrical output characteristics
ial output registers having common CLOCK FUNCTIONAL DIAGRAM
• 5-V, 10-V, and 15-V parametric ratings
and PARAllEL/SERIAL CONTROL inputs,
a single SERIAL data input, and individual • Meets all requirements of JEOEC Tentative
parallel "JAM" inputs to each register stage_ Standard No. 13A, "Standard Specifications
Each register stage is a D-type, master-slave for Oescription of 'B' Series CMOS Oevices" Applications:
flip-flop_ In addition to an output from stage • Parallel input/serial output
8, "a" outputs are also available from stages data queueing
6 and 7_ Parallel as well as serial entry is • Parallel to serial data conversion
made into the register synchronously with the
positive clock line transition in the CD4014B. • General-purpose register
In the CD4021 B serial entry is synchronous
with the clock but parallel entry is asyn- RECOMMENDED OPERATING CONDITIONS AT TA = 25 0 C, Unless Otherwise Specified
chronous. In both types, entry is controlled For maximum reliability, nominal operating conditions should be selected so that operation
by the PARAllEL/SERIAL CONTROL in- is always within the following ranges.
put_ When the PARAllEL/SERIAL CON-
TROL input is low, data is serially shifted LIMITS
into the 8-stage register synchronously with CHARACTERISTIC VDO UNITS
the positive transition of the clock line_ When (V) Min. Max_
the PARAllEL/SERIAL CONTROL input
is high, data is jammed into the 8-stage Supply-Voltage Range (T A = Full
register via the parallel input lines and syn- Package-Temperature Range)
- 3 18 V
chronous with the positive transition of the
clock line_ In the CD4021 B, the CLOCK 5 180 -
input of the internal stage is "forced" when Clock Pulse Width, tw 10 80 - ns
asynchronous parallel entry is made. Register 15 50 -
expansion using multiple packages is per- 5 - 3
mitted.
The CD4014B and CD4021 B series types are
Clock Frequency, fCl 10 - 6 MHz
supplied in 16-lead hermetic dual-in-line
15 - 8.5
ceramic packages (D and F suffixes), 16- Clock Rise and Fall Time,
5 - 15.
lead dual-in-line plastic packages (E suffix),
trCl, tfCl
10 - 15 p.s
16-lead ceramic flat packages (K suffix), and 15 - 15
in chip form (H suffix).
Set-up Time, ts:
5 120 -
Serial Input
10 80 - ns
(ref. to Cl)
15 60 -
Parallel Inputs 5 80 -
CD4014B 10 50 - ns
PI-S I. Voo (ref. to CLl 15 40 -
os
OB
•
3
"
IS
I.
PI-7
PI-6
Parallel Inputs 5 50 -
PI-4 13 PI-S CD4021B 10 30 - ns
PI-3
PI-2
I. 07
SERIAL IN
(ref. to PIS) 15 20 -
PI-I "
10 CLOCK
Parallel/Serial Control 5 180 -
Vss PARALLEL/SERIAL
CONTROL CD4014B 10 80 - ns
TOP VIEW 92CS_244~6
(ref. to Cl) 15 60 -
TERMINAL DIAGRAM Parallel/Serial Pulse Width,
S 160 -
CD4014B, CD4021B 10 80 - ns
tw (CD4021 B)
15 50 -
Parallel/Serial Removal Time,
5 280 -
tREM (CD4021 B)
10 140 - ns
15 100 -
94
TRUTH TABLE - CD4014B

ER. PAR SER I·' PI.n
a,
Cl liNTER· 0,
'N CONTROL
HAll
./ x , 0 0 0 0
./ x , , 0 , 0
L x , 0 , 0 ,
3
.0 L x , , , , ,
./ 0 0 x x 0 Qn"
./ , 0 x x , an"
........ x x x X a, a, NC
x ~ DON'T CARE CASE

Ne ~ NO CHANGE I
~
VD
Cl
* Alol. INPUTS ARE PROTECTED 92CM~2I6nRI
BY COS/MOS PROTECTION
_____ NETWORK.
Vss
Fig. 1 - Logic diagram for CD4014B.
TRUTH TABLE - CD4021B
ParallelJ
Serial Serial a'
Cl Input Contlol PI·n IInternall a,
x x , PI·'
0 0 0
x x , , 0 0
0
1
X X 1 1 0 , 0
x x , , , , 1
F1 . .0 .r
.r ,
L-
0
x
0
0
0
x
x
x
X
X
x
0
0,
, on,1
On,1
a, NC
rJ- x - DON T CARE CASE
o t1-i~-+'N-PU~T"'S-A-R-E-P-R-OT-E-CT-E-D- -'
Yss
NETWORK.
Cl
92CM-28674RI
Fig. 2 - Logic diagram for CD4021 B.
95
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltages referenced 10 VSS Terminal) ................................................ -0.510 +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -0.5 to VDD +0.5 V
. DC INPUT CURRENT, ANY ONE INPUT .................................................... ±10 mA
ForTA: -4010 +60"C (PACKAGE TYPE E) ................................................. 500mW
ForTA: +60 to +85"C (PACKAGE TYPE E) ................... Derale Linearly at 12 mWrCto 200 mW
For T A: -5510 +100"C (PACKAGE TYPES D, F, K) .......................................... 500 mW
ForTA: +100 to +125"C (PACKAGE TYPES D, F, K) ...... ".' Derate Linearly at 12 mW/"C to 200 mW
For TA: FULL PACKAGE-TEMPERATURE RANGE (All Package Types) •.....•.•..•.......•.. 100 mW
PACKAGE TYPES D, F, K, H ........................................................ -55 to +125"C DRAIN-lO-SOURCE VOLTAGE NoSI-V
PACKAGETYPEE .................................................................. -4010 +85"C
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -6510 +150"C Fig. 3 - Typical output low (sink) current
LEAD TEMPERATURE (DURING SOLDERING): characteristics.
At distance 1116t1/32 inch (1.59tO.79 mm) from case for 10 s max....•..................•.... +265"C

liMITS AT INDICATED TEMPERATURES (oCI 'U
N
CHARAC· CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H, Packages I
TERISTIC Values at -40, +25, +85 Apply to E Package T
+25 S
Vo V,N VDD
(VI (VI (VI -55 -40 +85 +125 Min. Typ. Max.
DRAIN-lO-SOURCE VOLTAGE (Vos}-V
- 0,5 5 5 5 150 150 - 0.04 5

Fig. 4 - Minimum output low (sink) current
Quiescent
Device - 0,10 10 10 10 300 300 - 0.04 10
IlA characteristics.
CUrrent, - 0,15 15 20 20 600 600 - 0.04 20 DRAIN-lO-SOURCE VOLTAGE I'JDS)-Y
'00 Max. I
- 0,20 20 100 100 3000 3000 - 0.08 100
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Output low
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOl Min. 0,15 15 4.2 4 2.8 6.8 -
1.5 2.4 3.4
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mil
Output High
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -·2.4 -3.4 -6.8 -
- 0,5 5 0.05 - 0 0.05
Output Voltage:
low·level, - 0,10 10 0.05 - 0 0.05
VOL Max. Fig. 5 - Typical output high (source) current
- 0,15 15 0.05 - 0 0.05 V characteristics.
Output - 0,5 5 4.95 4.95 5 - DRAIN-TO-SOURCE VOLTAGE {VDS)-\I

Voltage: - 9.95 10 - -15 -10 -5
0,10 10 9.95 AMBIENT TEMPERATURE {TA'*25·C
High· Level,
VOH Min. - 0,15 15 14.95 14.95 15 - GATE-lO-SOURCE VOLTAGE (VGS" -5 Y
0.5,4.5 - 5 1.5 - - 1.5 ·s

Input Low
Voltage 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 - 15 4 - - 4 V
-lOY
·0
Input High
0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - - --u~ V
·IS
VIH Min.
1.5,13.5 - 15 11 11 - -
Input Current ±10- 5 ±0.1 Il A
liN Max.
- 0,18 18 to. 1 ±0.1 ±1 ±1 -
characteristics.
96
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=25 0 C, Input t r ,tf=20 ns,

Cl=50 pF, Rl =200 KU
TEST
CONDITIONS LIMITS
CHARACTERISTIC V DD UNITS
(VI Min. Typ. Max.

5 - 160 320
10 - 80 160 ns
tplH, tpHl
15 - 60 120
5 - 100 200
Transition Time,
10 - 50 100 ns
tTHl' tTlH 15 - 40 80
LOAD CAPACITANCE (CLI-pF
Maximum Clock Input

5 3 6 - Fig. 7 - Typical transition time as a function of
92CS-MSZZ
Frequency, fCl
10 6 12 - MHz load capacitance.
15 8.5 17 -
Minimum Clock Pulse
5 - 90 180
Width, tw
10 - 40 80 ns
15 - 25 50
Clock Rise and Fall Time,

5 - - 15
trCl, tfCl *
10 - - 15 /lS
15 - - 15
Minimum Set·up Time, ts: 5 - 60 120
Serial Input 10 - 40 80 ns
(ref. to Cll 15 - 30 60
Parallel Inputs 5 - 40 80
CD4014B 10 - 25 50 ns
(ref. to Cll 15 - 20 40 -,F
9ttS-291!189
Parallel Inputs 5 - 25 50 Fig. B - Typical propagation delay time as a
CD4021 B 10 - 15 30 ns function of load capacitance.
(ref. to P/SI 15 - 10 20
.
10: AMBIENT TEMPERATURE (TAI-25-C
Parallel/Serial Control 5 - 90 180 4
I II I V
CD4014B 10 - 40 80 ns ' o/>~f. ~
(ref. to Cl) 15 - 30 60 ~IO: ~ /l1,~
~-{>"~"'~~~
!!: 4
Minimum Hold Time. tH: 5 - - 0 ~ r·r- j)~
Serial In. Parallel In.
Parallel/Serial Control
10
15
-
-
-
-
0
0
ns ~ 1038
~ 4
;;
., 2
rt..¢
~Ov
Minimum PIS Pulse Width,

tWH
(CD4021B)
5
10
15
-
-
-
80
40
25
160
80
50
ns
~
~
~ .,
10',
4
':--CL-15pF
CL -eOpF
IIII I
Minimum PIS Removal Time,
tREM
5
10
-
-
140
70
280
140 ns
10
, 468
~
, 468
~
2 4 68
~
CLOCK INPUT FREQUENCY (fell-kHz
, ... ,~
• 6B
~
CD4021 B (ref. to Cll 15 - 50 100 92CS-2ga71

Fig. 9 - Typical dynamic power dissipation
Average Input Capacitance, CI Any Input - 5 7.5 pF as a function of clock input frequency.
* If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition
time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
SER. DATA n)------~

11/4 feLl 92.CS-2987\
Fig. 10 - Dynamic power dissipation test circuit.
97
o
Vss
INPUTS
V~.PUO'
o ~
'. :::::.._ SEQUENTIALLY,
Vss TO 80TH voo AND Yss-
CONNECT ALL UNusm
INPUTS TO EITHER
VDO CRYSS '
V$S
92CS-21441RI
Vss
Fig. 11 - Ouiescent device Fig. 12 - Input voltage test circuit. Fig. 13 - Input current test circuit.
current test circuit.
80-88
(2.032-2.2351
Dimensions and pad
91 -99 =---------;;>-1 (CD4021 BH is identical)

I layout for CD4014BH
k---------,"'"~,~ 2.514)
92CM- 29870
The photographs and dimensions of each CMOS chip
represent a chip when it ;s part of the wafer. When the
wafer ;s separated Into individual chips, the angle of Dimensions in partmtheses are in millimeters and are
cleavage may vary with respect to the chip lace for derived from the basic inch dimensions as indicated.
different chips. The actual dimensions of the isolated Grid graduationure in mils (10- 3 inch).
dimensions shown.
98
CD4015B Types
CMOS Dual 4-Stage VDD

,.
Static Shift Register Features:
OATA A O'A
With Serial Input/Parallel Output CLOCKA

• °2A
• Medium speed operation _ .... _ .. ____ _ RESETA
STAGE
0..
12 MHz (typ.) clock rate at VDD - VSS = 10 V ID
°4A
The RCA-CD401SB consists oftwo identical, • Fully static operation

independent, 4-stage serial-input/parallel- • 8 master-slave flip-flops plus input and output buffering
OATAS
15
·12
" 0,.
output registers_ Each register has indepen- • 100% tested for quiescent current at 20 V
CLOCKa
RESETS
•
STAGE
°2 •
0,.
dent CLOCK and RESET inputs as well as • S-V, 10-V, and lS-V parametric ratings
°.8
a single serial DATA input. "Q" outputs are • Standardized, symmetrical output charac1eristics
8 nc~· ~~U41\
available from each of the four stages on • Maximum input current of 1 J.l.A at 18 V Vss
both registers. All register stages are D-type, over full package-temperature range; CD4015B
master-slave flip-flops. The logic level pre- 100 nA at 18 V and 25°C FUNCTIONAL DIAGRAM
sent at the DATA input is transferred into • Noise margin (full package-temperature
the first register stage and shifted over one range) =
stage at each positive-going clock transition. 1 Vat VDD = S V
Resetting of all stages is accomplished by a
high level on the reset line. Register expan-
sion to 8 stages using one CD401SB package,
2 V at VDD = 10 V
2_SVatVDD= 15V TERMINAL DIAGRAM II
or to more than 8 stages using additional Standard No. 13A, "Standard Specifications CLOCK B I. I. VOO
D' B 15 OATA B
CD401SB's is possible. for Description of 'B' Series CMOS Devices" D'A I. RESET B
D2 A 13 DI B
The CD4015B-series types are supplied in Applications: DI A 12 D2B
RE.SET A
IS-lead hermetic dual-in-line ceramic pack- • Serial-input/parallel-output data queueing DATA A "
10
D'B
D'A
ages (0 and F suffixes), IS-lead dual-in-line VSS 9 CLOCK A
• Serial to parallel data conversion
plastic package (E suffix), IS-lead ceramic
• General-purpose register 92CS·24457
flat package (K suffix), and in chip form (H
suffix).
J1 Qn-1
f-:'-:-"'f-:X+"'-I_Q?'Lf-'Q"'"-'itNO CHANGe,
* ALL INPUTS PROTECTED BY COS/MaS INPUT
PROTECTION NETWORK 92CM-293B3R2
x • DON'T CARE CASE
Fig. t - Logic diagram It register).
99
CD4015B Types
DC SUPPLY·VOLTAGE RANGE. (V DOl
(Voltages refertnced to V SS Terminall . -0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS -0.5 to V DO +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ±IOmA
POWER DISSIPATION PoER PACKAGE (POl:
For T A = -40 to +60. C (PACKAGE TYPE EI . . . . . . . ',; SOOmW
For T A = +60 to +85 ~ (PACKAGE TYPE EI Derate Linearly at 12 mWI C to 200 mW
For T A = -55 to +100·C (PACKAGE TYPES D. F. K) . . . . . . . .. 500mW
For T A = +100 to +12S·C (PACKAGE TYPES D. F. K) Derate Linearly at 12 mWi"C to 200 mW
FOR T A = FULL PACKAGE·TEMPERATURE RANGE {All Package Typesl 100mW
OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES D. F. K. H -55 to +125·C DRAIN-lO-SOURCE VOLTAGE IVoSl-V
PACKAGE TYPE E -40 to +85·C
STORAGE TEMPERATURE RANGE {Tst I . . -65 to +150·C Fig. 2 - Typical output low (sink) current
LEAD TEMPERATURE (DURING SOLD~RINGI: characteristics.
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mml from case for lOs ma •.
RECOMMENDED OPERATING CONDITIONS at TA = 250 C, Except as Noted. For maximum

reliability. nominal operating conditions should be selected so that operation is always within the
following ranges:
CHARACTERISTIC liMITS UNITS

VDD
(V) Min. Max.
Supply-Voltage Range (For T A = Full Package-
Temperature Rangel 3 18 V
5 180 -
DRA'N-,rO"'OU"CE VOLTAGE
Clock Pulse Width. twCl 10 80 - ns
15 50 - Fig. 3 - Minimum output low (sink) current
characteristics.
5 -
Clock Rise and Fall Time, trCl, tfCl 10 - 15 liS DRAIN-TO-SOURCE VOLTAGE IVosl-V
15 -
5 3
Clock Input Frequency. fCl 10 DC 6 MHz
15 8.5
5 70 -
Data Setup Time. tsu 10 40 -
15 30 - ns
5 200 -
Reset Pulse Width, tw R 10 80 -
15 60 -
Fig. 4 - Typical output high (source) current

characteristics.
ORAIN~TO-SOURCE VOLTAGE IVosl-V
250 AMBIENT TEMPERATURE ITAI-25-C
f
~
-200
-~
.
~
~,
50
I o 20 60 00 100
LOAD CAPACITANCE (CL)- pF LOAD CAPACITANCE ICLI-pF 92CS·2967!1
92CS-MU2
Fig. 7 - Typical propagation delay time as a func·
characteristics. Fig. 6 - Typical transition time as a function of tion of load capacitance.
load capacitance.
100
CD4015B Types
CONDITIONS Values at -55, +25, +125 Apply to D,K,F ,H Packages
CHARACTER· Values at -40, +25, +85 Apply to E Package
ISTIC UNITS
vb VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Ouiescent Device - 0,5 5 5 5 150 150 - 0.04 5
Current, - 0,10 10 10 10 300 300 - 0.04 10
IDD Max. J.IA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOLMin. 34 -
1.5 0,15 15 4.2 4 2.8 2.4 6.8
Output High 4.6 0.5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 .- rnA
(Source) 2.5 0.5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current,
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
Output Voltage:
Low·Level.
VOL Max.
13.5
-
-
0,15
0,5
0,10
15
5
10
-4.2 -4 -2.B
0.05
0.05
-2.4 -3.4
-
-
-6.B
0
0
-
0.05
0.05
II
- 0.15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level. - 0,10 10 9.95 9.95 10 -
VOH Min. -
- 0,15 15 14.95 14.95 15
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage,
VIL Max.
1.9 - 10 3 - - 3
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1.9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
Input Current
liN Max.
- O,1B 18 to. 1 to.1 t1 ±1 - t10- 5 to.1 J.IA
DimenSIons in parentheses are in millimeters and

85 dicated. Gnd graduations are in mils (10- 3 inchJ.
2.1591

represent a chip when it is par' of the wafer. When the
wafer is separated into individual chips, the angle of
differsnt chips. The actual dimensions of the isolated
chip, therefors, may differ slightly from the nominal
dimensions shown. The USBr should considers tolerance
dimensions shown.
92CM-2961S
Photograph of Chip Lavout for CD40158.
101
CD4015B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input t" tf=20ns, CL =50pF,
RL =200kn
CHARACTERISTIC TEST CONDITIONS

VDD(V)
LIMITS
Min. Typ. Max.
UNITS ~
.!.a
.
,~ AMBIENT TEMPERATURE {TA )-25·C
2
t"f, -20ns
RL -200 kn
I III I ,t;>~ W
!:. 10'"
CLOCKED OPERATION f5 t
t; • r- j tl"'';
5 - 160 320 ~ ~"
..
2
#
Propagation Delay Time; TpHL, TpLH 10 - 80 160 ffito! ~
15 - 60 120 ~
~ ".
~
.~
5 - 100 200 :~ 2
r'l
Transition Time; tTHL' tTLH 10 - 50 100 ns 6 : (L -so pF
L:
_CL-ISpF
-
Minimum Clock Pulse Width, tWCl rIO
15
5 -
-
40 80
90 180
40 80
~
2 •• B
10
2 ." 10 2
INPUT CLOCK FREQUENCY "CLI-kHt
2 B
10 3
2
I IIII ., I
." 104
.
92CS~29676
15 - 25 50 Fig. 8 - Typical power dissipation as a function

of frequency.
5 - - 15
Clock Rise & Fall Time; trCL., tfCL * 10 - - 15 /As
15 - - 15
5 - 35 70
Minimum Data Setup Time, tsu 10 - 20 40 ns
15 - 15 30
5 3 6 -
Maximum Clock Input Frequency, fCl 10 6 12 - MHz
15 8.5 17 - ,
2
Input Capacitance, CI N Any Input - 5 7.5 pF

CL
C •
4
5
RESET OPERATION DATA( f~n I •
7
8
5 - 200 400
Propagation Delay Time, TpHl, 10 - 100 200
15 - 80 160 ns
5 - 100 200
Minimum Reset Pulse Width tWR 10 - 40 80 Fig. 9 - Power dissipation test circuit.
15 - 30 60
* If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition
time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
INPUTS
... ="::'
V~NP(JU'
o
Vss
v,.
'NPUTOVCOOUTPUTS
V~ . ~
Vss TO BOTH VOO AND Vss
NOTE: CONNECT ALL UNUSED
v,s TEST ANY COMBINATION INPUH TO EITHER
OF INPUTS VOOCIIVSS'
Vss Vss
Fig. 10 - Quiescent device current test

circuit. Fig. 11 - Input voltage test circuit. Fig. '2 - Input current test circuit.
102
CD4016B Types
CMOS Quad Terminal Assignment

IN/OUT I
Bilateral Switch SIG A

IN
OUT
I.
• "
"
VDD
CONTROL A
SIG A
OUT liN Z
$IG 8 IN CONTROL 0
For Transmission or Multiplexing "
of Analog or Digital Signals CONTROL B

OUT
"
10
IN
OUT SIG 0 OUTIIN 3
CONTROL C
Vss
• OUT
IN
SIG C
SIG B

TOP VIEW
9ZCS-ZH58
The RCA-CD4016B Series types are quad VDD

bilateral switches intended for the trans-
mission or multiplexing of analog or digital
signals. Each of the four independent bi· CONTROL
lateral switches has a single control signal VC,o<.....'VV~......-I
input which simultaneously biases both the

p and n device in a given switch on or off. Functional Diagram
The CD4016 "B" Series types are supplied in

14-lead hermetic dual-in-line ceramic pack-
ages (D and F suffixes). 14-lead dual-in-line
plastic packages (E suffix). 14-lead ceramic
flat packages (K suffix). and in chip form (H
suffix). Schematic diagram - 1 of 4 identical sections.
II
Features: operation is always within the following range:
_ 20-V digital or ± 10-V peak·to-peak switching
LIMITS
• 280-Q typical on-state resistance for 15-V operation CHARACTERISTIC UNITS
_ Switch on-state resistance matched to within 10 Q Min. Max.
typo over 15· V signal·input range Supply Voltage Range (For T A = Full Package
_ High onloff output-voltage ratio: 3 18 V
Temperature Range)
65 dB typ. @fis=10kHz,RL = 10 kQ
_ High degree of linearity: <0.5% distortion
typo @ fis = 1 kHz, Vis = 5 Vp.p, MAXIMUM RATINGS, Absolute·Maximum Values:
VDD-VSS ;;;>10 V, RL = 10 kQ DC SUPPL Y·VOLTAGE RANGE. IVDOI
_ Extremely low off-state switch leakage 0.5 to V DO +0,5 V
INPUT VOLTAGE RANGE. ALL INPUTS
resulting in very low offset current and DC INPUT CURRENT. ANY ONE INPUT IiNCLUOING TRANSMISSION GATEI ±10mA
high effective off-state resistance: POWER DISSIPATION PoER PACKAGE (Pol
100 pA typo @ VDD-VSS=18 V, TA=25 0 C For T A = -40 to +600 C (PACKAGE TYPE EI . . 500 mW
_ Extremely high control input impedance For T A = +60 to +85 C (PACKAGE TYPE EI Derate Linearly at 12 mW;oC to 200 mW
For T A = -55 to +100"C (PACKAGE TYPES 0, F. K) . . 500 mW
(control circuit isolated from signal circuit:
For T A = +100 to +125"C (PACKAGE TYPES D. F, K) Derate Linearly at 12 mW/oC to 200 mW
1012 Q typo
DEVICE DISSIPATION PER TRANSMISSION GATE
_ Low crosstalk between switches: FOR T A = FULL PACKAGE· TEMPERATURE RANGE IAII Package Types) 100mW
-50 dB typo @ fis = 0.9 MHz, R L = 1 kQ OPERATING·TEMPERATURE RANGE IT AI'
_ Matched control-input to signal-output PACKAGE TYPES D. F. K. H -55 to + 125:C
capacitance: PAC KAG E TYPE E --40 to +85 C
Reduces output signal transients STORAGE TEMPERATURE RANGE IT" I . -65 to +150 o C
_ Frequency response, switch on = 40 MHz LEAD TEMPERATURE lOURING SOLD~RINGI
(typ.) At distance 1/16± 1/32 inch (1.59 ±O.79mml from case for lOs max
_ 100% tested for quiescent current at 20 V
_ Maximum control input current of 1 IlA
SUPPLY VOL.TS, liDO- +115; 'Iss. 0
at 18 V over full package temperature AMBIENT TEMPERATURE (TA) ·2!1·C
range; 100 nA at 18 V at 25°C 10
_ 5-V, 10-V, and 15-V parametric ratings
Applications:
_ Analog signal switching/multiplexing
Signal gating - Modulator
If
Squelch control
Chopper
- Demodulator
- Com mutating switch
• Digital signal switching/multiplexing
_ CMOS logic implementation
Ii
_ Analog-to-digital & digital-to- • • .0
analog conversion INPUT SIGNAl. 'IOI..TS (VIS'
_ Digital control of frequency, impedance • Fig. 2- Typ. on-state characteristics for 1 of 4

Fig. 1- Typ. on-state characteristics for 1 of 4
phase, and analog-signal gain switches with VOO~+15V, VSS=OIl. switches with VOO=+10 V, VSS=O v.
103
CD4016B Types
ELECTRICAL CHARACTERISTICS SUPPLY YOLTS:VOO-+lhVss-O
.... BIENT TEMPERATURE' (Tj,I-IS-C
LIMITS AT INDICATED
TEMPERATURE (oC) U
Values at -55, +25, +125 Apply N
Characteristic Test Conditions to 0, F, K, H Packages I
Values at -40, +25, +85 Apply to T
E Package S
VIN VDD +25
Quiescent Device
(V) (V) -55 -40 +85 +125 Typ. Max.
0.5 5
0.10 10
0.25 0.25 7.5 7.5 0.01 0.25
0.5 0.5 15
, .,
INPUT SIGNAL. VOlTS (Vlsl
15 0.01 0.5
Current. 100 IJA Fig. 3- Typ. on·state characteristics for 1 of 4
0.15 15 1 1 30 30 0.01 1 switches with V00 =+S V. VSS =0 II.
0.20 20 5 5 150 150 0.02 5
Signal Inputs (Vis) and Output (Vos)
On·State VC=VOO
lvis=VOO or VSS 10 600 610 840 960 - 660
Resistance. ron RL = 10kH
Max. Returned Vis-4.75 to 5.75 \ 10 1870 1900 2380 12600 - 2000
to
VOO-VSS Vis=VOO or VSS 15 360 370 520 600 - 400 il
2 Vis=7.25 to 7.75 V 15 775 790 1080 1230 - 850
liOn·State
Resistance
5 - - - - 15 -
Between Any RL=10kH.VC=VOO 10 - - - - 10 - il INPUT SIGNAL. VOLTS l\ltsl
2 Switches.lir on 15 - - - - 5 - Fig. 4- Typ. on·state characteristics for 1 of 4

switches with VOO=+7.SV. VSs"'-7.S11.
Total Harmonic VC=VOO =5V. VSS=-5V.Vis(P·P)
Oistortion. = 5V (Sine wave centered on OV) - - - - 0.4 - %
THO RL =10 kil. lis=l kHz sine wave
-3dB Cutoff VC=VOO=5V. VSS=-5V.
Frequency
(Switch on)
Vis(p.P) =5V (Sine wave
centered on 0 V) RL=lkil.
- - - - 40 - MHz
-5odS Feed·
through VC=VSS= -5V. Vislp,pf5V
Frequency (Sine wave centered on V)
RL = 1 Ikil
- - - - 1.25 - ~Hz
(Switch olf)
Input/Output VC=OV
Leakage Current Vis = 18V. Vos=OV; 18 ±0.1 ±0.1 ±1 ±1 10-4 ±0.1 IJA I"'PUT SIGNAL VOLTS (VIS)
(Switch off) Vis=OV.
lis Max. Vos= l8V Fig. 5- Typ. on·state chal7lcteristics for 1 of 4
switches with VOO=+S V. VSS=-SV.
VCIA) =VOO- +5 V.
VC(S) = VSS = -5 V.
-50dS
Crosstalk Vis(A) = 5 V p•p • - - - - 0.9 - MHz SUPPLY YOLTS:Voo·.2!!V;Vss·-2.!lV
AMBIENT TEMPERATURE (TAl. 2S·C
Frequency SOil source
RL = 1 kil
RL = 200 kil
Propagation Vc = Vf.!f Vss = GNO.
5 - - - - 40 100
Oelay (Signal CL =5 p 10 - - - - 20 40 ns
I nput to Signal
Output) tpd
Vis = Square Wave
o to VOO 15 - - - - 15 30
"lr. If = 20 ns
., rl"''''fpo
X
Capacitance:
Input. Cis VOO=+5V - - - - 4 - ~v.
Output. COS VC=VSS=~V - - - - 4 - pF -3 -2 -I 0 I 2.
INPUT SIGNAL VOLTS (Vasl
S
ftCS-l!1HS
Feedthrough, Fig. 6- Typ. on·state characteristics for 1 of 4
Cios
- - - - 0.2 - switches with VOO=+2.S V, VSS=-2.SV.
104
CD4016B Types
ELECTRICAL CHARACTERISTICS (cont'd)
LIMITS AT INDICATED
TEMPERATURE (oC)
U
Characteristic Test Conditions Values at -55. +25. +125 Apply to
N
D, F, K, H Packages
I
Values at -40. +25. +85 Apply to
T
I +25
fir
E Package
S
(V) -55 -40 +85 +125 Typ. Max.
Control (VC)
Control Input Ilis l< lOpA INPUT SIGNAL VOLTS Iv,,1
Low Voltage. Vis = Vss, Vas ~ VDD 5,10.
and 0.9 0.9 0.4 0.4 - 0.7 V Fig. T- Typ. on-state characteristics asa function of
VILe (Max.) 15
temp. for 1 of4switches with V OD =+5 V,
Vis = VDD, Vas = VSS
VSS=-5V.
5 3.5 (Min.) SUPPLY VOLTS: "'00" 5, V55·-5
I
Control Input CONTROL VOI..TS tvel'-5
High Voltage. See Fig. 10 10 7 (Min.) V INPUT SIGNAL VOLTS 1'1,,1'5 Vp-f' SINE WA...E\I.77 RMS)
30 LOAD CAPACITANCE (CU"CfIXTURE +ChlETER"2.' .. 2.5-<\8pF
VIHC 15 11 (Min.) ?: ~::I~:~:~.~e~;TER NULLEO 0,,U+-'

1 -h't+tt-H-t-H
'0 "
~
Input Current. Vis'-;;; V~D :;
VDD - SS = 18V ±10-5 ±0.1 ~ -tiit--Hcttl J9 ~
liN (Max.) 18 0.1 to.l ±1 ±1 I1A ~
VCC'-;;; VDD - VSS
I III I,? ... ~
>
-;-VTr-r
Crosstalk (Con,
trollnputto
Vc = 10 V (Sq. Wave)
t r • tf = 20 ns 10 - - - - 50 - mV
"* ""4+Ht-+-lI. '--j~+H-t-fH+r+.f~"·
Signal Output) RL=10kQ
Turn·On t r • tf = 20 ns 5 - - - - 35 70 10'12.611 2 .&~022 .&:0)2 ·&l'o4

Propagation CL = 50 pF 10 - - - - 20 40 ns INPUT SIGNAL FREQUENCY Ifill kHz
Delay RL = 1 kQ
15 - - - - 15 30 Fig. 8 - Typ. feedthru vs. frequency - switch
Vis - VDB: VSS - GND. off.
R L = 1 k to gnd.
Maximum
=;
CL=50pF,
Control Input Vc = 10 VISquare
Repetition Rate wave centered on 5 V)
10 - - - - 10 - MHz s:-:~~~~~~~~s:~~P SIIE llilu.7~ JJ}I 3!5.!5
~
)c FIXTUI!E AND METER NULLED OUT
t r , tf = 20 ns, I IIII I Illi I I
VO'Voo
Vos=y,Vos@lkHz '0
~ " ...2... "
Input
e"'T:r~
:0
~ 20 ~ p 1.. 39 i
Capacitance. - - - - 5 7.5 I1F 2
CIN l
~
I
-;"111(\6
Vc' Vss
-=:-111(\
:t6~B1N~15~
"L5~ •
~ MODEL 91·CA
5
Switch Input Switch Qutp!'t
*§ ", \~p@.!
p
l'KJlTtlo;n~
Vo,IBI
4!1
lis (mA) Vos (V) ;OF4 SWITCHEsI""i~ "

VDD Vis
_55°C _40°C 25°ca +85°C +125°C Min. Max.
·1 , 10 10' 10 32 • 610 4
~. (V) 25°C* INPUT SIGNAL FREQUENCY 11;,1- U11
5 0 0.25 0.2 0.2 0.16 0.12 0.14 - 0.4 Fig. 9- Typical crosstalk between switch
5 5 -0.25 -0.2 -0.2 -0.16 -0.12 -0.14 4.6 - circuits in the same package.
10 0 0.62 0.5 0.5 0.4 0.3 0.35 - 0.5

10 10 -0'()'2 -0.5 -0.5 -0.4 -0.3 -0.35 9.5 - R F. VOLTMETER
BOONTON RAOIO
15 0 1.8 1.4 1.5 1.2 1 1.1 - 1.5 MODEL'I·CI.
OR EQUrv.
15 15 -1.8 -1.4 -1.5 -1.2 -1 -1.1 13.5 -
* Plastic packag~ • Ceramic package
- l i $.... _~ CD4016B
Vis ~L -_
IOF4SWITCHES
__ .,-~
IL-VO!!
, .lvis-vo,1
on ~ 92C5-30967 0.1 • I 10
INPUT SIGNAL FREQUENCY ttlll MHI
Fig. 10- Determination of ron as a test condition for control input FiiJ. 11 - Typical frequency response
high voltage (V/HC) specification. -switch on.
105
CD4016B Types
TYPICAL ON-8TATE RESISTANCE CHARACTERISTics. TA = 25°C
CHARAC· SUPPLY LOAD

TERISTIC' CONDITIONS CONDITIONS
RL = lkU RL = 10kU RL = 100kSl
VDD Vss VALUE Vis VALUE Vis VALUE Vis
(V) (V) (II) (V) (I!) (V) (!I) (V) ALL UNUSED TERMINALS
ARE CONNECTED TO Vas
200 +15 200 +15 180 +15
ron +15 0
200 0 200 0 200 0 Fig. 12 - Off.. tate switch input 0' output
ron (max.) +15 0 300 +11 300 +9.3 320 +9.2 leakage current test circuit.
290 +10 250 +10 240 +10
ron +10 0
290 0 250 0 300 0
ron (max.) +10 0 500 +7.4 560 +5.6 610 +5.5
860 + 5 470 + 5 450 + 5
ron + 5 0
600 0 580 0 800 0
ron (max.) + 5 0 1.7k +4.2 7k +2.9 33k +2.7 v..
200 +7.5 200 +7.5 180, +7.5
ron +7.5 -7.5
200 -7.5 200 -7.5 180 -7.5
ron (max.) +7.5 -7.5 290 '0.25 280 ±25 400 iO.25
260 + 5 250 + 5 240 + 5 ALL UNUSED TERMINALS ARE
+ 5 - 5 CONNECTED TO Vss
ron -5 -5
310 - 5 250 240
Fig. 13 - Test circuit for square·wave
Iron (max.) + 5 - 5 600 ±0.25 580 ±0.25 760 iO.25
response.
590 +2.5 450 +2.5 490 +2.5
ron +2.5 -2.5
720 -2.5 520 -2.5 520 -2.5
ron (max.) +2.5 -2.5 232k ±0.25 300k iO.25 870k iO.25
• Vanatlon from aperfect switch, ron = 0 o.
SCALE: X '" 0.2 msfOIV V = 2.0 VIOIV SCALE: X = 0.2 ms/OIV Y = 2.0 V/OIV
SCALE: X" 0.2 ms/DIV Y· 2.0 VIDIV VOO = Ve= tSV, VSS= -5V, RL= lQKU VOO = Vc = +2.SV. VSS = ·2.5V. RL = 10KS!
~~e ~5VJ:= <t7.5V, VSS = -7.5V, RL· lOKn CL" lSpF CL = lSpF
flS= 1 KHz VIS= 5Vpp liS = 1 KHz VIS = SV p.p
fIS·' KHz VIS"SVP-P DISTORTION = 0.4 % DISTORTION z 3 %
DISTORTION" 0.2 % 92CS-27614
92CS-27S13
92CS-27612
Fig. 15 - Typical sine wave response of VDD = Fig. 16 - Typical sine wsw ,esponse of VDD-
Fig. 14 - Typical sine wave response of VDD = +5 V, VSS=-5 V. +2.5 V, VSS = -2.5 V.
+7.5 V. VSS = -7.5 V.
/
, \
\
- -
SCALE: x .. 100 ns/DIV

" -
'\
y = 5.0VIOIV
SCALE: X = l00ns/DIV
92CS-27615 SCALE: X" l00ns,OIV
Y-2v/DIV
'( = 5.0V DIV
92CS-27616 92CS-27617
Fig. 17- Typical square waw response at Fig. 18 - Typical square wave response at VDD = Fig. 19 - Typical square wave ,esponse at VDD
VDD = Vc = +15 V, Vss ~ Gnd. VC=+IOV. Vss = Gnd. = VC=+5 V. Vss=Gnd.
106
CD4016B Types
1 ~I--- - -
I I- I !
ALL UNUSED TERMINALS

ARE CONNECTED TO IISS
lie· lOY PER DIV
vas· 02V PER 0111
ALL UNUSED TERMINALS ARE I lOOns PER 0111
CONNECTED TO Vss 92CS-27618
Fig.21 - Propagation delay time signal input
(al (bl 1V'SI to signal output IVOSI.
Fig.20 - Crosstalk-control input to signal output.
•
MEASURED ON BOONTON c.t.PItiClTANCE
BRIDGE MODEL lSA I1lII1d
Vo~~VC
tr.tf·ron.
Yo. Yc·-OV
YSS·-5Y
YDO-+SY
SWITCH THRESHOLD \U.TAGE IS DEFINED
AS THE VOLTAGE APPLIED TO A TRANS-
MISSION GATE CONTROL WHICH CAUSES
10 t£A OF TRANSMISSION GATE CURRENT.
ALL UNUSED TERMINALS ARE
CONNECTED TO VSS ALL UMJSED TERMINALS
ARE CONNECTED TO Vss
Fig.23 - Switch threshold voltage. Fig.24 - Capacitance C,OS and COS.

Fig. 22 - Max. control-input repetition rate.
Vo~~Vc Voo Dimensions and pad layout for CD4016BH

t r ,tf· 20ns
Voo
CONNECTED TO IISS
53-61
11.347-1.549)
Fig.25 - Turn-On propagation delay-control input.
(O.IO~:~~254) I
~______~ 49-57~
( 1.245-1.447)
92CS-350G3
Dimensions in parentheses are in millimeters and are The photographs and dimensions of each CMOS chip
derived from the basic inch dimensions as indicated. represent a chip when it is part of the water. When the
Grid graduations are in mils (10- 3 inchJ.
cleavage may vary with respect to the chip fece for
of -3 mifs to +16 mils applicable to the nominal
dimensions shown.
107
CD4017B, CD4022B Types
CMOS Counter/Dividers "0"
High-Voltage Types (20-Volt Rating) Features: "I"
CD4017B-Decade Counter' with • Fully static operation CLOCK 14 "2" !;i
0
10 Decoded Outputs • Medium-speed operation ...
CLOCK 13 "3" ~
~
INHIBIT
CD4022B-Octal Counter with 10 MHz (typ.) at VDD = 10 V RESET IS 10
"4" "
8 Dec~ded Outputs ~
The RCA·CD4017B and CD4022B are 5-
• Standardized, symmetrical output
characteristics
"5"
"s" .
'0
0
stage and 4·stage Johnson counters having
10 and 8 decoded outputs, respectively.
• 100% tested for quiescent current at 20 V "7" u ..
0
Inputs include a CLOCK, a RESET, and a • 5-V, 10-V, and 15-V parametric ratings "B"
VOO=16
CLOCK INHIBIT signal. Schmitt trigger • Meets all requirements of JEDEC Tentative "9"
Vss "6
action in the CLOCK input circuit provides Standard No. 13A, "Standard Specifications 12
CARRY
pulse shaping that allows unlimited clock for Description of 'B' Series CMOS Devices" OUT
input pulse rise and fall times.
App/ications: CD4017B
These counters are advanced one count at Functional Diagram
the positive clock signal transition if the • Decade counter/decimal decode display
CLOCK INHIBIT signal is low. Counter (CD4017B)
advancement via the clock line is inhibited • Binary counter/decoder
when the CLOCK INHIBIT signal is high. • Frequency division CLOCK "0"
"
A high RESET signal clears the counter to • Counter control/timers CLOCK 13 "I"
its zero count. Use of the Johnson counter INHIBIT
configuration permits high-speed operation,
• Divide-by-N counting RESET "2" §
2-input decode·gating and spike-free de-
coded outputs. Anti·lock gating is provided,
"
"3"
"4"
*
8
thus assuring proper counting sequence. The "5" ~
decoded outputs are normally low and go "6"
high only at their respective decoded time VOO=16 10 "7"
slot. Each decoded output remains high for VSS=B 12
one full clock cycle. A CARRY-OUT signal CARRY
OUT
completes one cycle every 10 clock input
cycles in the CD4017B or every 8 clock
input cycles in the CD4022B and is used to
CD4022B
Functional Diagram
For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges: I. voo
,.I. RESET
CHARACTERISTICS LIMITS UNITS
I. CLOCK
VDD 13 CLOCK INHIBIT
(V) Min_ Max. 12 CARRY OUT
9
Supply-Voltage Range (For T A = Full Package- 3
Vss
"
10
92CS.24459RI
5 - 2.5
Clock Input Frequency, fCl 10 - 5 MHz
15 - 5.5 TOPVtEW
5 200 - CD4017B
TERMINAL DIAGRAM
Clock Pulse Wi"th, tw 10 90 - ns
16 60 -
5
Clock Rise & Fall Time, trCl' tfCl 10
15
UNLIMITED' I.
2
I. Voo
RESET
" CLOCK
"
5 230 - 13 CLOCK INHIBIT
Clock Inhibit Setup Time, ts 10 100 - ns •

NC
12 CARRY OUT
15 70 - 3 "
10
Vss 9 NC
5 260 -
Reset Pulse Width, tRW 10 110 - ns
15 60 -
TOP VIEW
5 400 - NC - no connection
Reset Removal Time, t rem 10 280 - ns CD4022B
TERMINAL DIAGRAM
15 150 -
'Only if Pin 14 is used as the clock input. If Pin 13 is used asthe clock input and Pin 14 is tied high (for advancing
count on negative transition of the clock), rise and fall time should be:S 15 JJS.
108
CARRY OUT
CLOCK
RESET 11..________________________________
CLOCKINH~I~B~IT~ ______________________~~
"0"
"1"
"2"
______ __________________
~f]lL_ ~
"3"
"4"
______ ___________________
~f4lL_
D C2 D Q4 D Q5
____________ __________________
~f]lL_
"5"
"6"
______________ ________________
~f4lL_
•
______________ ~r,0L ____________
"7"
"8" ,...,1.._____________
a
"g" f4l
CARRY OUT
Fig. 2 - Timing diagram for CD4017B.
Vss
tt ALL INPUTS PROTECTED BY
cosmos PROTECTION NETWORK
4 CARRY OUT
CLOCK
f~~,~~ _____________________.-.J,...----,I.._______________
··0·' ----c>I1..____________--.JfO\l..________________--'TOL-
"1" ---IT1 m rI
'2' -1Ti .----zi'-______________
'.," ~ 1311..____________
'4"
________ ~~L ________________ _'~L_ ________
"5" _________ .-.Jm r51L_______
"6" ____________ ---'£61 ~
C~:~'y =====~==~"'~7;======:;::::==~f1L-~1
I)UT r-
Fig. 4 - Timing diagram for CD40228.
Voo
a vss
tt ALL INPUTS PROTECTED BY
92CL-28746R3
Fig. 3 - Logic diagram for CD40228.
109
CD40178, CD40228 Types
DC SUPPLY-VOLTAGE RANGE. (VDD)
(Voltages referenced to VSS Terminal) ................................................ -0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS ........................................... -0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ......••.•.•.•..........•..............•...•.•....... ±IO rnA
For TA = -40 to +60·C (PACKAGE TYPE E) ................................................. 500 mW
For T A =+60 to +85·C (PACKAGE TYPE E) ...........•••..•.• Derate Linearly at 12 mW/·C to 200 mW
For T A = -55 to +100· C (PACKAGE TYPES D. F. K) .......................................... 500 mW
For T A = +100 to +125·C (PACKAGE TYPES D. F. K) .......... Derate Linearly at 12 mW;oC to 200 mW
For T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) " " ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 100 mW
PACKAGE TYPES D. F. K. H ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' -55 to +125·C 10 ,.
DRAIN-la-SOURCE VOLTAGE 1VoSI-V
PACKAGETYPEE .................................................................. -40to+85·C
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +150·C Fig. 5- Typical output low (.ink) current
At distance 1!1fi±1/32 inch (1.59±0.79 mm) from case for 10 s max..••.•.•••......•.•.•....... +265·C
c
E
~
I
.,
ffi 12.5 GATE-TO-SOURCE VOLTAGE IYaS).'!SV
~ 10
STATIC ELECTRICAL CHARACTERISTICS •~ 7.5 10V
LIMITS AT INDICATED TEMPERATURES 1°C) u S

g
CHARAC- CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H, Packages I
N
~
~
•
TERISTIC Values at -40, +25, +85 Apply to E Package T g25
~
ov
+25 S
Vo VIN VDD :5 10 15
DRAIN-lO-SOURCE VOLTAGE IVosJ-V
(V) (V) IV) -55 -40 +85 +125 Min_ Typ. Max.
Fig. 6- Minimum output low (.ink) current
Ouiescent
- D,S 5 5 5 ISO' ISO' - 0'.04 5 characteristics.
Device - 0,10' 10' 10' 10' 300 30'0' - 0'.04 10' jJ.A
DRAIN-TQ-SOURCE VOLTAGE (VosJ-V
Current. - 0'.15 15 20' 20' 600 60'0' - 0'.0'4 20' -15 -10 -5
100 Max.
- 0.20' 20' 10'0' 10'0' 30'00' 30'00' - 0'.0'8 100
Output Low
0'.4 0'.5 5 0.64 0'.61 0'.42 0'.36 0'.51 1 -
(Sink) Current 0'.5 0'.10' 10' 1.6 1.5 1.1 0'.9 1.3 2.6 -
IOL Min. 1.5 0.15 15 4.2 4 2.8 2.4 3.4 6.8 - ..
-IOV
Output High
4.6 D,S 5 -0'.64 -0'.61 -0'.42 -0.36 -0'.51 -1 - mt i': .
(Source) 2.5 0'.5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - -'!!IV
Current. 9.5 0'.10' 10' -1.6 -1.5 -1.1 -0'.9 -1.3 -2.6 -
IOH Min.
13.5 0'.15 15 -4.2 -4 -2.8 -·2.4 -3.4 -6.8 -
Output Voltage: 0'.5 5 0'.0'5 - 0' 0.0'5
Low·Level. 0'.10' 10' 0'.0'5 - 0' 0.0'5 Fig. 7- Typical output high (source) current
characteristics.
VOL Max.
- 0'.15 15 0'.0'5 - 0' 0.0'5 V
DRAIN-TO-SOURCE VOLTAGE: IVDSI-Y
Output - 0'.5 5 4.95 4.95 5 - -15
AMBIENT TEMPERATUR£ IT,,)"ze"c
-10 -5
Voltage: 10' 9.95 9.95 10' -
0'.10' ~TO-SOURCE VOLTAGE I J--BY
High·Level.
VOH Min. - 0'.15 15 14.95 14.95 15 -
0'.5,4.5 - 5 1.5 - - 1.5
Input Low
Volta!Jt' 1,9 - 10' 3 - - 3
VIL Max. 1.5.13.5 - 15 4 - - 4 V
Input High 0'.5,4.5 - 5 3.5 3.5 - - "-IBV
Voltage, 1,9 - 10' 7 7 - -

VIHMin. - -
1.5.13.5 - 15 11 11
Input Current - ±ID-5 ±D.l jJ.A

liN Max.
- 0',18 18 ±0.1 ±0.1 ±1 ±1
Fig. 8- Minimum output high (source) current
characteristics.
110
At T A =25 0 C, Input t r, tt = 20 ns, CL =50 pF, RL =200 kn
CONDITIONS LIMITS
VDD(V) Min. Typ. Max.
CLOCKED OPERATION
5 - 325 650
Propagation Delay Time, tpH L, tpLH 10 - 135 270
Decode Out 15 - 85 170 ns
5 - 300 600
Carry Out 10 _. 125 250 I
LOAD CAPACITANCE ICLI-pF
15 - 80 160
Fig. 10 - Typical transition time as a function
Transition Time, tTHL' tTLH

5 - 100 200 of load capacitance.
Carry Out or Decode Out Line

10 - 50 100 ns
15 - 40 80
Maximum Clock Input Frequency, fCL *

5
10
2.5
5
5
10
-
- MHz
II
15 5.5 11 -
5 - 100 200
Minimum Clock Pulse Width, tw 10 - 45 90 ns
15 - 30 60
Clock Rise or Fall Time, trCL, tfCL 5,10,15 UNLIMITED
Minimum Clock Inhibit

5 - 115 230
ns
to Clock Setup Time, ts
10 - 50 100 LOAD CAPACITANCE ICL ) - pF 92CS-30945
15 - 35 70
Input Capacitance, CIN Any Input - 5 - pF function of load capacitance (clock
to decode output).
RESET OPERATION
AMBIENT fEMPERATURE I TA )- 25-C
Propagation Delay Time, tpHL' tpLH

5 - 265 530 ! 700
Carry Out or Decode Out Lines

10 - 115 230 ns ~
~
600
15 - 85 170 _0.
3
~ 500
5 - 130 260 w
Minimum Reset Pulse Width, tw 10 - 55 110 ns ~ 400
15 - 30 60 g~ 300
5 - 200 400 z
~ 200
Minimum Reset Removal Time 10 - 140 280 ns 10V
,"V
15 - 'If. 100
75 150
~
* Measured with respect to carry output line. 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (CLJ -pF 92C5-30946

function of load capacitance (clock
to carry-out).
CLOCK
10 AMBIENT TEMPERATURE
CLOCK
INHIBIT
RESET --+------,-,--------'1
DECODE 1-9
OUTPUT
DECODE MO" OR
CARRY
OUTPUT
\.. IpRLH 92C5-30948
10
DELAYS MEASURED BETWEEN 50 % LEVELS ON ALL WAVEFORMS 10
INPUT CLOCK FREQ "CL)-ItHz 12(S-30947
Fig. 9- Propagation delay, setup, and Fig. 13 - Typical dyanamic power dissipation as B
hold time waveforms. function of clock input frequency.
111
INPUTQVOO
OUTPUTS
INPUTS Voo INPUCS
Voo NOTE
o V,H
Vss ~
o ~
MEASURE INPUTS
SEQUENTIALL.Y, '-- ~
Vss TO BOTH Yoo ANOVSS' v~ ~
CONNECT ALL. UNUSED
INPUTS TO EITHER
Voo OR Vss NOTE:
VSS Vss COM~~:!T~~
OF INPUTS
92CS-2144'RI
VSS
Fig. 14 - Quiescent-devic~
Fig. 15 - input·leakage current. Fig. 16 -Input·voltage test circuit.
current test circuit
When the Nth decoded output is reached

.rCiii40i7ii'-l---_;g~TN •• (Nth clock pulse) the S·R flip flop (con-
'-CLOCK-:'-N structed from two NOR gates of the
CD4001 B) generates a reset pulse which
ALTERNATE COUT
clears the CD4017B or CD4022B to its zero
+-"=='t--""='--t+FOR N"2 TOlD count. At this time, if the Nth decoded out-
f"'CLOCK-:-N
put is greater than or equal to 6 in the CD-
4017B or 5 in the CD4022B, the COUT line
goes high to clock the next CD4017B or CD-
4022B counter section. The "0" decoded
92CS-30949
output also goes high at this time. Coinci-
9tCS~30950 dence of the clock low and decoded "0"
output low resets the S· R fl ip flop to enable
Fig. 18 - Divide by N counter IN'" 10) with N the CD4017B or CD4022B. If the Nth de-
Fig. 17 - Dynamic power dissipation test circuit. decoded au tpu ts. coded output is less than 6 (CD4017B) or 5
(CD4022B), the COUT line will not go high
and, therefore, cannot be used. In this case
"0" decoded output may be used to perform
the clocking function for the next counter.
92CS-3!5064
CD4017BH CD4022BH
The photographs and dimensions of Bach CMOS chip
represent IJ chip when it is part of the wafer. When the
chip, therefore, may differ slightly from the nomjnal
D,menSions In parentheses are In millimeters and dimens;onsshown. The user should considera tolerance
are deflved from the baSIC Inch dimensions as in- of -3 mils to +16 mils applicable to the nominal
dll:ated. ,Gfld graduations are in mils (10- 3 Inch). dimensions shown.
112
CD4018B Types
Features:
CMOS Presettable • Medium speed operation. . . . 10 MHz (typ.) at
Divide-By-~N' Counter VOO - VSS = 10 V
• Fully static operation
High-Voltage Types (20-Volt Rating) • Standardized, symmetrical output characteristics ~:~~~~ 10 • 01
• 5-V, 10-V, and 15·V parametric ratings
The RCA·CD40188 types consist of 5 • Maximum input current of 1 jJ.A at 18 V over full package· CLOCK
I.
O. ~
Johnson·Counter stages, buffered Q outputs temperature range; 100 nA at 18 V and 25°C 0
from each stage, and counter preset control Ii Noise margin (full package-temperature
DATA • 0, ...
0
...'"
gating. CLOCK, RESET, DATA, PRESET range) = 1 Vat VOO = 5 V IS
~
2 V at VOO = 10 V
RESET
" ii. " ~
ENA8LE, and 5 individual JAM inputs are "

2.5 Vat VOO = 15 V 13 Q5
provided. Divide by 10,8,6,4, or 2 counter • Meets all requirements ofJEOEC Tentative
configurations can be implemented by Standard No. 13A, "Standard Specifications
feeding the 05, 04, 03, 02, 01 signals, for Description of'S' Series CMOS Oevices" Vss
respectively, back to the DATA input. FUNCTIONAL DIAGRAM

Divide·by·9, 7, 5, or 3 counter configura·
tions can be implemented by the use of a Applications:
CD40118 to gate the feedback connection
to the DATA input. Divide·by functions
greater than 10 can be achieved by use of
• Fixed and programmable divide-by-10, 9, 8,
7, 6, 5, 4, 3, 2 counters
• Fixed and programmable counters greater
I
multiple CD4018B units. The counter is than 10
advanced one count at the positive clock· • Programmable decade counters
signal transition. Schmitt Trigger action on TERMINAL DIAGRAM
Top View • Divide-by-"N" counters/frequency
the clock line permits unlimited clock rise synthesizers
and fall times. A high RESET signal clears
DATA I. 16 voo • Frequency division
the counter to an all-zero condition. A high
JAM I 15 RESET • Counter control/timers
PRESET·ENABLE signal allows information JAM 2 14 CLOCK
on the JAM inputs to preset the counter. ~ 4 13 Q5
iii 5 12 JAM5
Anti·lock gating is provided to assure the Q3 6 II Q4
proper counting sequence. JAM3 10 PRESET ENABLE
Vss 9 JAM4
The CD40188 types are supplied in l6-lead
hermetic dual-in-line ceramic packages (D 92CS-24460

packages (E suffix), l6-lead ceramic flat
suffix).
MAXIMUM RATINGS, Absolute·Maximum Values:

DC SUPPLY·VOLTAGE RANGE, (V DD ,
(Voltages referenced to VSS Terminal) . . -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS. -0.5 to V DD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT . ±10mA
POWER DISSIPATION PoER PACKAGE (PO):
For T A = -40 to +600 C IPACKAGE TYPE E) . . . . . . . ''; 500 mW
For T A = +60 to +85 C IPACKAGE TYPE E) Derate Linearly at 12 mWI C to 200 mW
For T A =-55 to +100'C (PACKAGE TYPES 0, F, K) . . . . . . . .. 500 mW
For T A = +100 to +125'C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mWloC to 200 mW
FOR T A = FULL PACKAGE·TEMPERATURE RANGE (All Package Types) 100mW
OPERATING·TEMPERATURE RANGE ITA):
PACKAGE TYPES D. F. K. H . -55 to +125 0 C
PACKAGE TYPE E -40 to +85°C
STORAGE TEMPERATURE RANGE (Tst ) . . -65 to +1500 C
LEAD TEMPERATURE (DURING SOLD~RING):
At distance 1116 ± 1132 inch (1.59 ± 0.79 mm) from case for 105 ma •. . +265°C
113
CD4018B Types
RECOMMENDED OPERATING CONDITIONS at T A = 25°C, Unless Otherwise Specified
is always within the following ranges.
CHARACTERISTIC VDD Min. Max. UNITS

Supply Voltage Range (at T A = Full Package·
5 - 3
15 - 8.5
5 160 -
Clock Pulse Width, tw 10 70 - ns
15 50 -
5
Clock Rise & Fall Ti me, trCl,tfCl 10 Unlimited f.ls
15
5 40 -
Data Input Set·Up Time, ts 10 12 - ns
15 16 -
5 140 -
Data Input Hold Time, tH 10 80 - ns
15 60 -
5 160
Preset or Reset Pulse Width, tw 10 70 - ns
15 50 -
5 80 -
Preset or Reset Removal Ti me 10 30 - ns
15 20 -
"'R" 12 *
"--0--105
"
QS
CL as
PEPE
Fig. 1 - Logic diagram.
FfVDD ON
Dvss
* ALL INPUTS PROTECTED
BY COS/MOS INPUT
PROTECTION NETWORK
Fig. 2 - Detail of a typical stage.
114
CD4018B Types
STATIC ELECTRICAL CHARACTERISTICS AUSlENT TEMPERATURE (TA)o2'·C
LIMITS AT INDICATED TEMPERATURES (oC) U

N
CHARAC- CONDITIONS Values at -55, +25, +125 Apply 10 D, F, K, H Packa~ges I GATE-TO-SOURCE VOLTAGE (VGS'"I' v
TERISTIC Values at -40, +25, +S5 Apply to E Package T
+25 S
Vo VIN VDD
(VI (VI (VI -55 -40 +S5 +125 Min. Typ. Max.
,ov
- 0.5 5 5 5 150 150 - 0.04 5
Quiescent
Device - 0.10 10 10 10 300 300 - 0.04 10
I1A
Current, - 0.15 15 20 20 600 600 - 0.04 20
IDD Max.
- 0.20 20 100 100 3000 3000 - O.OS 100 5 10 IS
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Output low Fig. 3 - Typical output low (sink) current
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - characteristics.
IOlMin. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mfl
Output High
(Source)
Current,
IOH Min.
2.5
9.5
0,5
0,10 10
5 -2
-1.6
-1.S
-1.5
-1.3 -1.15 -1.6
-1.1 -0.9 -1.3
-3.2
-2.6
-
-
I
13.5 0,15 15 -4.2 -4 -2.8 -·2.4 -3.4 -6.8 -
Output Voltage:
- 0,5 5 0.05 - a 0.05
low-level, - 0,10 10 0.05 - a 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05 V
Output - 0,5 5 4.95 4.95 5 -

Voltage: - 0,10 10 9.95 9.95 10 - !!i 10 IS
DRAIN-lO-SOURCE VOLTAGE IVosl-V
High-level,
VOH Min. - 0,15 15 14.95 14.95 15 -
Fig. 4 - Minimum output/ow (sink) current
0.5,4.5 - 5 1.5 - 1.5 characteristics.
Input low
Voltage 1,9 - 10 3 - - 3
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
Vil Max. 1.5,13.5 - 15 4 - - 4 V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIHMin. 1.5,13.5 - 15 11 11 - -
Input Cu rrent ±10- 5 ±0.1 I1A
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 -
9lCS-l.Sloru

characteristics.
DRAIN-lO-SOURCE VOL.TAGE (Vosl-V

-15 -10 -,
•,
".
AMBIENT TEMPERATURE (TA,-25·C
GATE-lO-SOURCE VOLTAGE IVas'- -, v

t
-IOV
, .. -t .. ,-. 1:
,.
,ov
+•••
;.:.,'';: - .. i '5V
:
" HI!
l!iill
20 40 60 80
I!I LOAD CAPACITANCE (CL1-pF

Fig. 6 - Minimum output high (source) current Fig. "j - Typical transition rime as a function of function of load capacitance
characteristics. load capacitance. (CLOCK to QI.
115
CD4018B Types
DYNAMIC ELECTRICAL CHARATER ISTICS at T A = 25°C, Input tr,tf = 20 ns, F400 AMBIENT TEMPERATURE ITAI'25'~
CL =50pF, RL = 200 kQ
-_~ SUPPL'I'
tJ!!!ii~LoOl.~~
CHARACTERISTIC TEST CONDITIONS LIMITS UNITS
VDD (V) Min. Typ. Max.
CLOCKED OPERATION
5 - 200 400 15V:
Propagation Delay Time;
10 - 90 180 ns
tpLH, tpHL 15 - 65 130
Transition Time;
5 - 100 200 20 40 60
80
92C5-298049
100
10 - 50 100 ns Fig. 9 - Typical propagation delay time as a

tTHL,tTLH
15 - 40 80 function of load capacitance
(RESET to 0).
Maximum Clock Input
5 3 6 -
Frequency,
10 7 14 - MHz
fCL
15 8.5 17 -
Minimum Clock Pulse Width,

5 - 80 160
10 - 35 70 ns
tw
15 - 25 50
5
Clock Rise & Fall Time;
10 Unlimited Ils
trCL,tfCL
15
Minimum Data InputSet·Up

5 - 20 40
10
Time.
10 - 6 12 ns 2 468'0 2 2. 468 ,03 2 468'042 .. 68,0'
ts
15 - 3 6 CLOCK FREQUENCY lfcLI- kHt 92CS-29852
5 - 70 140 as a function of clock input
Minimum Data Input Hold frequency.
10 - 40 80 ns
Time, tH 15 - 30 60
Average Input Capacitance, CI Any Input - 5 7.5 pF
PRESET* OR RESET OPERATION

Propagation Delay Time; 5 - 275 550
Preset or Reset to 5 10 - 125 250 ns INPUTS
15 - 90 180 o
tpLH, tPHL Vss
Minimum Preset or Reset 5 - 80 160
Pulse Width, 10 - 35 70 ns
tw 15 - 25 50
Minimum Preset or Reset 5 - 40 80

'i2C$-21'40,'H
Removal Time 10 - 15 30 ns Vss
Fig. 11 - Quiescent device
15 - 10 20
current test circuit
• At PRESET ENABLE or JAM Inputs.
.~NP(JU'
'. =~"i:'
500,..F
Vss TO BOTH Yoo AND Yss'

CONNECT ALL UNUSED
IMtUTS 10 EITHER
Voo OR Yss'
·ss
9ZCS-ZM"IRI
92CS-29851
Fig. 12 - Input voltage test circuit. Fig. 13 - Input current test circuit. Fig. 14 - Dvnamic power dissipation test circuit.
116
CD4018B Types
EXTERNAL CONNECTIONS FOR DIVIDE
("DATA" INPUT TIED TO aS FOR DECADE COUNTER CONFIGURATION) BY 10,9, B, 7, 6, 5, 4, 3 OPERATION
DIVIDE BY 10
CLOCK 1..rt ~ rL rt.. ~ r"L rt- f\. r"L rt-rt- ~ ~ ~ 1.. rt- [L ~ '\. [1. rt. 1..r- DIVIDE BY 8
DIVIDE BY 6
DIVIDE BY 4
RESET -1\ DIVIDE BY 2
PRESET Irh DIVIDE BY 9

1/2 C0401lB
~
;-----------i
I I I I CONNECTED BACK TO -DATA"
II I I
'" I
1015'L ____________ JI
(SKIPS "ALL ·1'5" STATE I
Jam3
I
) !
I
DON'T CARE UNTIL -PRESET" GOES HIGH I
I ) OIVIOE BY 7
112 C04QII B
-3 :-----------1
~
:
I I
I--
CONNECTED BACK rO"DATA"
I I I I-' _ I (SKIPS "ALL·I'S" STATE I

I
II
I
I 04 IL ___________ JI
__ I : I I-'
~
-I- -,
DIVIDE BY 5
»--t>+-
112 C0401lB
;-----------~
I
I
I
~I--
r-
_
03
I
IL ___________ .JI
I
I
CONNECTED BACK TO "DATA-
(SKIPS "ALL·I's" STATE)
I
DIVIDE BY 3
112 CD401lB
;----------i
~
-,
I I CONNECTED BACK TO MDATA"

I I _ I (SKIPS "ALl-I'S" STATE)
I I I I
92SS-4)48R2
02 L
I __________ .JI
92CS-11011R3
Fig. 15 - Timing diagram.

Fig. 16 - External connections for divide by 10, 9~
8, 1, 5, 4, 3, 2 operation.
CL
.-----10
R
93
23621
'-----------j~-- CL-:-1
92CS-35270
~----------~.9~~~85:._._--------------~ 92CN-29853
Dimensions and pad layout for CD4018B~ Fig. 17 - Example of divide by 7.
DimensIOns In parentheses are In mIllimeters and

are derived from (he basIc Inch dimensions as in·
dlcated. Gnd graduations are in mils (10- 3 inch).
The photographs and dimensions 01 8ach CMOS chip
represent a chip whon it is part of tho wafer. Whon the
cleavage may vary with respect to the chip face (or
different chips. The actua' dimensions of the Isolated
chip, therefore, may differ slightly (rom the nominal
01 -3 mils to +76 mils applicable to the nominal
dimensions shown.
117
CD4019B Types
Features.-
CMOS Quad
• Medium-speed operation •••••
ANDIOR Select Gate ••• tpHL = tpLH = 60 ns (typ.) atCL =50pF, VDD = 10V
The RCA-CD40198 types consist of four • 5-V, 10-V, and 15-V parametric ratings
AND/OR select gate configurations, each • Meets all requirements of JEDEC Tentative Standard
consisting of two 2-input AND gates driving No_ 13A, "Standard Specifications for Description of'S'
a single 2-input OR gate. Selection is ac- Series CMOS Devices"
complished by control bits Ka and Kb. In
addition to selection of either channel A or • Maximum input current of 1 /lA at 18 V
over full package-temperature range; 100
channel 8 information, the control bits can
be applied simultaneously to accomplish nA at 18 V and 250 C
the logical A + 8 function. • Noise margin (full package-temperature
range) = 1 Vat VDD = 5 V CD4019B
The CD40198 types are supplied in l6-lead 2 V at VDD = 10 V FUNCTIONAL DIAGRAM
hermetic dual-in-line ceramic packages (D 2.5 Vat VDD= 15V
and F suffixes), l6-lead dual-in-line plastic
packages (E suffix), l6-lead ceramic flat
packages (K suffix), and in chip form (H Applications:
'J, suffix).
• AND-OR select gating
• Shift-right/shift-Ieft registers
MAXIMUM RATINGS, Absolute-Maximum Values: • True/complement selection
DC SUPPLY-VOLTAGE RANGE, (VDD) • AND/OR/Exclusive-OR selection
(Voltages referenced 10 VSS Terminal) ................................................ -0.5 to +20 V
DC INPUT CURRENT, ANY ONE INPUT ..................................................... ±10 mA
For TA = -40 to +6O"C (PACKAGE TYPE E) ................................................. 500 mW
For TA = +60 to +85·C (PACKAGE TYPE E) ...•...•... .•.•. .•• Derate Linearly al12 mWI"C 10 200 mW TERMINAL DIAGRAM
For TA = -5510 +l00·C (PACKAGE TYPES D, F, K) .......................................... 500 mW
Top View
For TA = +100 10 +l25·C (PACKAGE TYPES D, F, K) .......... Derale Linearly al12 mWI"C to 200 mW
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ..•....•..........•... 100 mW
B'
A'
,.
I. VDo
A.
OPERATING-TEMPERATURE RANGE (TA): B. K'
PACKAGE TYPES D, F, K, H ........................................................ -5510 +12S·C A2 "I. 04 c A4Ka+B4Kb
B2 12 D3-A3 Ko+ 93 Kb
PACKAGE TYPE E .................................................................. -4010 +85·C AI D2-A2Ko+92Kb
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -6510 +lS0·C B' "
'0 Ol-AI Ko+81 Kb
LEAD TEMPERATURE (DURING SOLDERING): VSS Ka
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. .. ....................... +265·C 92CS-24461
TRUTH TABLE
Ka Kb An Bn On
1 0 1 X 1 RECOMMENDED OPERATING CONDITIONS

1 Ii 0 X 0 VOO·,S
0 1 X 1 1 Vss -6
conditions should be selected so that operation
0
0
1
1
1
0
1
1
X
X
0
0
0
X
0
1
0
0
0
1
-----, is always within the following ranges:
CHARACTERISTIC VDD Min_ Max. Units

1 1 1 0 1 (VI
1 1 1 1 1 *84 I
-.-1-f.--
, __ ._.--.J Supply·Voltage Range
x = Don't Care fi2\ (For T A = Full Package
*A3~
_RVoo •
' :
'
To.NoRE
SIMILAR
CIRCUITS·
~03
~o2
E3vs
.. INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
".20-
*A'
"'.'0-
@-
92CS-552U
Fig. I-Logic diagram.
118
CD4019B Types
U
CONDITIONS Values ai-55, +25, +125 Apply 10 D, F, K, H Packages
N
CHARAC· Values at -40, +25, +85 Apply to E Package
I
TERISTIC +25
Vo VIN VDD T
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max. S
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2 I1A
Current, IDD - 0,15 15 4 4 120 120 - 0.02 4
Max. - 0,20 20 20 20 600 600 - 0.04 20 r
DRAIN-la-SOURCE VOLTAGE (VOsl-Y
Output low
(Sink)
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - Fig. 2 - Typical output low (.ink) current
Current
0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - characteristics,
IOl Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
Output High
(Source)
Current,
4.6
2.5
9.5
0,5
0,5
0,10
5 -0.64 -0.61 -0.42 -0.36 -0.51
5
10
-1
-2 -1.8 -1.3 -1.15 -1.6 -3.2
-1.6 -1.5 -1.1 -0.9 -1.3 -2.6
-
-
mA
I
IOH Min. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8
Output Voltage: - 0,5 5 0.05 - 0 0.05

Low·Level, - 0,10 10 0.05 - 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 - , r
DRAIN-lO-SOURCE VOL.TAGE lVosl-V
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 15 - Fig. 3 - Minimum output low (sink) current
characteristics.
Input Low 0.5,4.5 - 5 1.5 - - 1.5 DRAIN- TO-SOURCE VOLTAGE IYQsI ..... y
Voltage, 1,9 - 10 3 - - 3
VllMax. 1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIHMin. 1.5,13.5 - 15 11 11 - -
Input Current
liN Max. - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 I1A
9lCS'2"1~1"

characteristics. I
DRAIN-le-SOURCE VOL.TAGE {YOSI-Y
'O.
20 40 60
".
so KID
92C5-29883
Fig. 5 - Minimum output high (source) current Fig. 6 - Typical transition time as a function of Fig. 7 - Propagation delay time as a function
characteristics, load capacitance. of load capacitance.
119
CD4019B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 2SOC.lnputtr• tt = 20 ns. CL = 50 pF.
RL =200kO
LIMITS
TEST
CHARACTERISTIC CONDITIONS UNITS
VDD Min. Typ. Max.
(V) ~ ,
tpLH. tpHL
5
10
-
-
150
60
300
120 ns
2 •
.•
; '~~.=t~~f*~tt~-i--tH
15 - 50 100 '0
• 'lOti
5 - 100 200
Transition Time; 10 - 50 100 ns
tTHL. tTLH 15 - 40 80 Fig. 8 - Typical dynamic power dil$ipation
as a function of input frequency.
All Aand B
- 5 7.5 pF
Input Capacitance. CI N Inputs
Kaand Kb
Inputs
- 10 15 pF
VDD
VDO ,NPUTS ,--'---,

•
, ,.
,." . V'H 'NPUTQVDOOUTPUTS VDO
VDO
' N P D NOTE'
,.,.~~
3 V55
•, ........
o
~ '-fi'\--
0 ~
MEASURE INPUTS
SEQUENTIALLY,
•
1 "
10 CL
VIL =- Vas TO 80TH Vao MDVss
• NOTE:
CONNECT ALL UNUSED
WUTS 10 EITHER
VDO OR: VSS'
Vss w.N~~OMaINATION Vss
9ZCS~2988!1
92CS-2744Utl 'Its-27402
V55
'2C5-27401"1
Fig. 9 - Dynamic power dissipation Fig. 10 ~-Quiesc8ntde.ice Fig. 11- Input voltage rest circuit. Fig. 12 - Input currant test circuit.
test circuit. cu"ent test circuit.
TYPICAL APPLICATIONS
'fS" REGISTER "A" REGISTER

,,r------,,,
,, ,
, ,,
lE~..!.3.!' ~A.!~Y.J
(K o>
SELECT
-~_+t=l::;:=p=j:;==++=+:;:=l=t=h-t-
I
SELECT
{K"I
"B" REGISTER
,,
" .." REGISTER 1
,I
,,,
,L __
,
OUT OUT
2
OUT
, OUT
• 92CS-29886
Fig. 13 - AND/OR select gating. Fig. 14 - "Shift leftlshift right" register.
120
CD4019B Types
TYPICAL APPLICATIONS (CONT'D)

A,
a, ,
:[
rrfd,rrldl £, !: :: :
: :
: :
CD4001B
OR EOUIY.
: [
ii
CD4001B
OR EQUIY,
I:
::
CD4001S
OR EQUIV,
1
:
~:
ORr I
:1
II
::
II
II
£Q!I!Y> L-S~2::-' L:S--2:"-' L~-.l---'
----- - ---- - ----- --,,
CD4001B OR EQUIV.
,
I
__ J
(KGi
TRUE
SELECT
TRUTH TABLE
•
'[.J ,[oJ OUT
A·a
Aaa
,
OUT OUT OUT
3
OUT
'".8 92C5-2.9889
,
OUT OUT
2 ,
OUT OUT
4 92.CS-29888
Fig. 15 - AND/OR F.xclusive-OR selector. Fig. 16 - "True complement" selector.
o 30 40 60 70
'1 54- 62
( 1.372-1.5751
1_ 4-10
r--r0:i02-0.2541
~ _ _ _ _ _-:-:- 67-75=:-_ _ _--1""1
(1.702-1.9051
92CS-36092
The photographs and dimensions of '8ch CMOS chip

Dimensions and pad layout for CD4019BH represent a chip when it is part of the waf.r. When the
wal., ;s separated into Individual chips, the ang'. of
cleavage may vary with respect to the chip lace lor
different chips. The actus' dlmsnsions of the isolaled
chip, therefore. may differ slightly from the nominal
are derived from the basic inch dimensions as in- dimensions shown. The usef should consider a tolerance
dicated. Grid graduations are in mils (10- 3 inch). 01 -3 mils to +16 mils applicable to the nominal
dimensions shown.
121
CMOS Ripple-Carry Features: v••
• Medium-speed operation IS
Binary Counter IDividers • Fully static operation 10 9

01
• Buffered inputs and outputs INPUT
PULSES
7 a.
High-Voltage Types (20-Volt Rating) • 100% tested for quiescent current at 20 V 5 05
• Standardized, symmetrical output characteristics • as

CD4020B - 14 Stage 6
13
07
Q8
• Fully static operation ',"STAGE
RIPPLE
CD4024B - 7 Stage • Common reset COUNTER 12 Q9
14 alo
CD4040B - 12 Stage • 5-V, 10-V, and 15-V parametric ratings 15 all
I
012
RCA-CD4020B, CD4024B, and CD4040B
are ripple-carry binary counters. All counter over full package-temperature range; II , all
2
QI'
RESET
'stages are master-slave flip-flops., The state 100 nA at 18 V and 25°C
of a counter advances one count on the • Noise margin (over full package-tempera-
Vss 92C$.25D53R2
negative transition of each input pulse; a high ture range): 1 Vat VOD =5 V CD4020B
level on the RESET line resets the counter to FUNCTIONAL DIAGRAM
2VatVDO=10V
its all zeros state. Schmitt trigger action on 2.5 V at VOO = 15 V
the input-pulse line permits unlimited rise • Meets all requirements of JEOEC Tentative
and fall times. All inputs and outputs Standard No. 13A, "Standard Specifications
are buffered. for Description of 'B' Series CMOS Devices"
The CD4020B and CD4040B types are VDO
Applications:
• Control counters • Frequency dividers "
ceramic packages (0 and F suffixes), 16-lead 12
• Timers • Time·delay circuits 0,
dual-in-line plastic packages (E suffix), 16- INPUT I
lead ceramic flat packages (K suffix), and in PULSES " 0,
chip form (H suffix). a,

7 -STAGE
The CD40248 types are supplied in 14-lead RESET RIPPLE 0,
COUNTER
hermetic dual-in-line ceramic packages (0
a.
Q6
packages (K suffix), and in chip form (H 07
suffix).
NC=S,IO,13
Vos
92CS-25051R4
DC SUPPLY-VOLTAGE RANGE, (V DO) CD4024B
(Voltages referenced to VSS Terminal) ~.5to+20V FUNCTIONAL DIAGRAM
INPUT VOLTAGE RANGE, ALL INPUTS ~.5 to VDD +D.5 V
DC INPUT'CURRENT, ANY ONE INPUT ±lOmA
For TA • -40 to +60o C (PACKAGE TYPE E) • • • • • • • •. 500mW
For T A = +60 to +85 0 C (PACKAGE TYPE E) Derate Linearly at 12 mWfDC to 200 mW
Fot TA = -55 10 +IOO'C (PACKAGE TYPES 0, F, K) •••••••• , 500mW
For TA = +100 10+125'C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mW/oC to 200 mW
Voq
FOR ,TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) loomW IS
OPERATING-TEMPERATURE RANGE (TAl: 10 9 01
PACKAGE TYPES 0, F, K, H . • . • -55 to +1250 C INPUT
PULSES 7 02
PACKAGE TYPE E • -40 to +85 0 C 6 Q3
STORAGE TEMPERATURE RANGE (Tstg ) -65 to +1500 C 504
LEAD TEMPERATURE (DURING SOLDERINGI: 3 05
12-STAGE 2 06
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from case for lOs max. RIPPLE
COUNTER '07
13 as
TERMINAL ASSIGNMENTS 0"
4 010
IS all
1 012
RESET
C04020B C04024B C04040B v,, 92CS-29066A2
CD4040B
012
013
01.
2
3
,.
16 Voo
all
010
•
RESET
07 ""
12
Voo
Ne
01
01.
06
05
16
15
Voo
all
010
FUNCTIONAL DIAGRAM
as
05
07
"
"
12
II
OB
ag
RESET
as
Q5
Q'
•
5 10
02
Ne
03
07
04
03
I.
"
13
II
aB
ag
a. 10 .,. Vss Ne 02 10
V,S 01 V,S 01
TOP VIEW
TOP VIEW
NC- NO CONNECTION TOP VIEW
92CS-24462Rl
92CS-24466AI 92CS-20747R2:
122
RECOMMENDED OPERATING CONDITIONS at T A =25°C, Unless Otherwise Specified
is always within the following ranges:
CHARACTERISTIC VOD Min. Max. UNITS
Supply Voltage Range (at T A = Full Package·
5 - 3.5
Input·Pulse Frequency, f</l 10 - 8 MHz
15 - 12
Fig. 4 - Detail of typical flip·flop stage.
5 140 -
Input·Pulse Width, tw 10 60 - ns
15 40 -
5
Input·Pulse Rise or Fall Time, tr</l' tf</l 10 Unlimited fJS 11
15
I:::
5 200
Reset Pulse Width, tw 10
15
80
60
- ns
II I
5 350 -
Reset Removal Time, tREM 10 150 - ns
15 100 -
Fig. 5 - Typical output low 'sink) current

characteristics.
Llz-~):;J
~
DD ..
___ INPUTS
PROTECTED BY
COS/MOS PROTECTION y~-~y
NETWORK QI 04 QI3 014
vss
I
~
DD
__ *INPUTS Fig. 6 - Minimum output low 'sink) current
PROTECTED BY
COS/MOS PROTECTION
characteristics.
NETWORK 01 07
Vss
.
~
DD
___ INPUTS
PROTECTED BY
COS/Mas PROTECTION
. NETWORK 01 012
Vss
Fig. 3 - Logic diagram for CD4040B. Fig. 7 - Typical output high 'SOUTes) current
characteristics.
123
STATIC ELECTRICAL CHARACTERISTICS ORAIN-TO~SOURC£ YOl.TAGE IVos)-V

-Ie
AMBIENT TEMPERATURE ITAI-2S·C
-10
-"
CONDITIONS Values al-55, +25, +125 Apply 10 D, F, K, H Packages GATE-TO-SOURCE VOlTAGE tYos)- -5 v 1I
CHARACTER- Value. at -40, +25; +85 Apply to E Packege
ISTIC +25
UNITS -5!
I
Vo VIN VDD
(VI (V) (V) -55 -40 +85 +125 Min. Typ. Max.
-IOV
Quiescent Device 0,5 5 5 5 150 150 0.04 5 -DE
~
Current, 0,10 10 10 10 300 300 0.04 10
100 Max. JlA
0,15 15 20 20 600 600 0.04 20
0,20 20 100 100 3000 3000 0.08 100
-1!lV
151
~
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 g
(Sink) Current 0.5 0,10 10 1.6 1.5 .1.1 0.9 1.3 2.6
IOlMin.
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 rnA
Output High characteristics.
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2
Current, -1.6 -1.5 -1.1 -0.9 -1.3 -2.6
9.5 0,10 10
IOHMin.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8
Output Voltage: 0,5 5 0.05 0 0.05
low·Level, 0.05 a 0.05
0,10 10
VOL Max.
0,15 15 0.05 0 0.05
V
Output Voltage: 0,5 5 4.95 4.95 5
High·level. 0,10 10 9.95 9.95 10
VOH Min. 14.95 15
0,15 15 14.95
Input Low 0.5,4.5 5 1.5 1.5
Voltage, 1,9 10 3 3
Vil Max.
1.5,13.5 15 4 4
V
Input High 0.5,4.5 5 3.5 3.5
LOAD CAPACITANCE (CL'-pF 'J2CS-24322
Voltage, 1,9 10 7 7
VIH Min. 1.5,13.5 15 11 11 load capacitance.
I nput Current ±10- 5
0,18 18 ±0.1 ±1 ±0.1 JlA
liN Max.
9091
88-96
12 236-2 438}
IO~:b02541 ~
f..----.... 64-72 92CM-30160
·626-1.8281
Dimensions and Pad Layout for CD4024BH.
Dimensions and Pad Layout for CD4020BH. Dimensions and The photographs and dimensions of each CMOS chip
pad layout for CD4040BH are identical. represent a chip when it is part of the wafer. When the
wafer ;s separated into individual chips. the angle of
Dimensions in parentheses are in millimeters and different chips. The actual dimensions of the isolated
are derived from the basic inch dimensions as in- chip. therefore. may differ slightly from the nominal
dicated. Grid graduations are in mils (7tr 3 inch). dimensions shown. The user should consider a tolerance
dimensions shown.
124
DYNAMIC ELECTRICAL CHARACTERISTICS at TA ; 25°C, Input t r, tf; 20 ns, AMBIENT TEMPERATURE (TA)· 25-C
CL; 50 pF, RL ; 200 kQ
LIMITS
CHARACTERISTIC TEST VDD UNITS
CONDITIONS (VI Min_ Typ_ Max_
Input-Pulse Operation
5 - 180 360
Propagation Delay Time, ¢ to '0
01 Out; tpHL. tpLH 10 - 80 160 ns

15 - 65 130
20 40 60 eo 100
5 - 100 200 LOAOCAPACITANCE ICL.I-pF 92CS-30156
°n to On+ 1; 10 - 40 80 ns Fig. 10 - Typical propagation delay time as a
tpHL. tpLH function of load capacitance
15 - 30 60 l¢toO/).
5 - 100 200
Transition Time.
tTHL. tTLH
10 - 50 100 ns
Minimum Input-Pulse
15
5
-
-
40
70
80
140
I
Width. tw
10 - 30 60 ns
15 - 20 40
Input-Pulse Rise or Fall +0 Unlimited fJ.s

Time. t r¢. tf¢ ~
5 3.5 7 - 2468102468102246810324681042468105
Maximum Input-Pulse
Frequency. f¢
10 8 16 - MHz INPUT PULSE FREQU£NC'1 It.l-kH, 92CS-J0151
15 12 24 - Fig. 11 - Typical dynamic power dissipation as a

function of input pulse frequency for
CD4020B.
Input Capacitance. CI Any Input - 5 7.5 pF
Reset Operation
5 - 140 280
Propagation Delay
Time. tpHL
10 - 60 120 ns
15 - 50 100
Minimum Reset Pulse

5 - 100 200
Width, tw
10 - 40 80 ns
15 - 30 60
5 - 175 350
Reset Removal Time.
10 - 75 150 ns
tREM
15 - 50 100 Fig. 12 - Dynamic power dissipation test circuit
for CD4020B.
INPUTS
DD
o Voo INPuV
( J s NOTE.
Vss ~ MEASURE INPUTS
o - ~ SEQUENTIALLY,
Vss TO BOTH Voo AND Vss·
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS·
Vss
92CS-27441RI
Vss
Fig. 13 - Quiescent device
current test circuit. Fig. 14 - Input voltage test circuits. Fig. 15 - Input current test circuit.
125
CMOS Voo
Decade Counters/Dividers CLOCK . "
12 b ~
High-Voltage Types (20-Volt Rating) .013 c}"~
CLOCK
With Decoded 7-Segment Display Outputs and: INHIBIT 9 d ~
" .. 8
Display Enable - CD4026B AESET • \!l
• I h
Ripple Blanking - CD4033B 7,
, CARRVOUT
Features:
• Counter and 7-segment decoding in one package DISPLAY DISPLAy
The RCA-CD4026B and CD4033B each con-

sist of a 5-stage Johnson decade counter
• Easily interfaced with 7-segment display types
• Fully static counter operation: DC to 6 MHz (typ.)
ENABLE
IN
..
ENABLE
OUT
UNGATED ·C·
SEGMENT
and an output decoder which converts the at VDD=10 V Vss 92C:!I-2!OT8AI
Johnson code to a 7-segment decoded out- • Ideal for low-power displays
put for driving one stage in a numerical CD4026B
• Display enable output (CD4026B) FUNCTIONAL DIAGRAM
display.
These devices are particularly advantageous • "Ripple blanking" and lamp test (CD4033B)
in display applications where low power • 100% tested for quiescent current at 20 V
dissipation and/or low package count are • Standardized, symmetrical output
important. characteristics
Inputs common to both types are CLOCK, • 5-V, 10·V, and 15-V parametric ratings
RESET, & CLOCK INHIBIT; common • Schmitt-triggered clock inputs
outputs are CARRY OUT and the seven • Meets all requirements of JEDEC Tentative CLOCK
decoded outputs (a, b, c, d, e, f, gJ. Addi· Standard No.13A, "Standard Specifications 12 •
~
tional inputs and outputs for the CD4026B
include DISPLAY ENABLE input and
Applications CLOCK
.. c
!:;
0
DISPLAY ENABLE and UNGATED "C· INHIBIT "'"
SEGMENT" outputs. Signals peculiar to the
CD4033B are RIPPLE·BLANKING INPUT
AND LAMP TEST INPUT and a RIPPLE-
• Decade counting 7-segment decimal
display
• Frequency division 7·segment decimal
RESET " ."
d
"0
~
BLANKING OUTPUT. displays I.

A high RESET signal clears the decade
counter to its zero count. The counter is
• Clocks, watches, timers
LAMP
TEST •
5 CARRY
OUT
(e.g. ';'60, .;. 60, .;. 12 counter/display)
advanced one count at the positive clock
signal transition if the CLOCK INHIBIT • Counter/display driver for meter RIPPLE
•
RIPPLE
BLK. BLK.
signal is low. Counter advancement via the applications I. OUT.
clock line is inhibited when the CLOCK vss

92CS-250761t1
INHIBIT signal is high. The CLOCK INHI· CD4033B
BIT signal can be used as a negative·edge FUNCTIONAL DIAGRAM
clock if the clock line is held high. Antilock
gating is provided on the JOHNSON counter,
thus assuring proper counting sequence. The
CARRY·OUT (Cgut ) signal completes one
cycle every ten CLOCK I NPUT cycles and segment display device used for representing
is used Y:l clock the succeeding decade di· the decimal numbers 0 to 9. The 7 -segment
rectly in a multi·decade counting chain. outputs go high on selection in the CD4033B;
The seven decoded outputs (a, b, c, d, e, f, g) in the CD4026B these outputs go high only TERMINAL DIAGRAMS
illuminate the proper segments in a seven when the DISPLAY ENABLE IN is high. Top View
CLOCK
CL.OCK INHIBIT
I.
2
I,.. Voo
RESET
DISPLAY ENABLE IN UNGATED "c" SEGMENT OUT
DISPLAY ENABLE OUT "13
CARRY OUT 12
MAXIMUM RATINGS. Absolute-Maximum Values:
,I
"
10
Vss
(Voltages referenced to VSS Terminal) ...•••...•..•...•....•........•..•••.••..•••. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS .........••...•...•..••.•.•.•...•..•..•• -0.5 to VDD +0.5 V 92CS_24469RI
DC INPUT CURRENT, ANY ONE INPUT .•.•......•.•.•.•......••.•....•••...••.•..••••••. ±10 rnA

CD4026B
For T A = -40 to +60'C (PACKAGE TYPE E) •...••.•...•••..••.......•..•••.••.••.•..•••. 500 mW
For T A = +60 to +65'C (PACKAGE TYPE E) .....•.•.•••.•. Derate Linearly at 12 mW/'C to 200 mW
Top View
For TA = -55 to +100'C (PACKAGE TYPES 0, F, K) ........•....•..•••.••.•••.•..•.••..•• 500 mW CLOCK I. I. Voo
For T A = +100 to +125'C (PACKAGE TYPES 0, F, K) ....... Derate Linearly at 12 mW/'C to 200 mW CLOCK INHIBIT 2 IS RESET
DEVICE DISSIPATION PER OUTPUT TRANSISTOR RIPPLE BLANKING IN 3 'L.AMP TEST
RIPPLE BLANKING OUT "13
For TA =FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...•..••••••••••.. 100 mW CARRY OUT 12
OPERATING-TEMPERATURE RANGE (TA): I
PACKAGE TYPES 0, F, K, H .•.....•.••••..•........•.•.••.••.•.•...•••....•.•... -55 to +125·C • "
10
Vss 9
PACKAGE TYPE E ...•.•..•........••.•.•..••..••......•.....•.. , ••. , ••.•.•.••... -40 to +85'C
STORAGE TEMPERATURE RANGE (T stg) ...........••.•••.•••..••.......••.•••.•• -65 to +150·C 92CS-24475RI
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max...•....••.•••••••.••.. +265'C CD4033B
126
RECOMMENDED OPERATING CONDITIONS CD4026B
For maximum reliability, nominal operating conditions should be selected so that operation is When the DISPLAY ENABLE IN is low the
seven decoded outputs are forced low reo
always within the following ranges:
gardless of the state of the counter. Acti·
LIMITS vation of' the display only when required
CHARACTERISTIC VDD UNITS results in significant power savings. This
IV) MIN. MAX. system also facilitates implementation of
Supply·Voltage Range (For T A = Full Package display·charaGter mUltiplexing.
Temperature Range) 3 18 V The CARRY OUT and UNGATED "C·
SEGMENT" signals are not gated by the
Clock Input Frequency, fCl 5 - 2.5 DISPLAY ENABLE and therefore are avail·
10 - 5.5 MHz able continuously. This feature is are·
15 - 8 quirement in implementation of certain di·
Clock Pulse Width, vider functions such as divide·by·60 and
tv..cl 5 220 - divide·by·12.
10 100 -
15 80 - CD4033B
The CD4033B has provisions for automatic
Clock Rise and Fall Time, trCl' tfCl 5 - blanking of the non·significant zeros in a
10 - Unlimited multi·digit decimal number which results in
15 - an easily readable display consistent with
Clock Inhibit Set Up Time, tsu 5
10
15
200
50
30
-
-
-
ns
normal writing practice. For example, the
number 0050.0700 in an eight digit display
would be displayed as 50.07. Zero suppres·
sian on the integer side is obtained by con-
I
Reset Pulse Width, tw 5 200 - necting the RBI terminal of the CD4033B
10 100 - associated with the most significant digit in
15 50 - the display to a low-level voltage and con-
necting the RBO terminal of that stage to
Reset Removal Time 5 30 - the RBI terminal of the CD4033B in the
10 15 - next-lower significant position in the dis·
15 10 - play. This procedure is continued for each
succeeding CD4033B on the integer side of
STATIC ELECTRICAL CHARACTERISTICS the display.
On the fraction side of the display the RBI
LIMITS AT INDICATED TEMPERATURES (OC) of the CD4033B associated with the least
CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H Packages significant bit is connected to a low·level
CHARACTER· Values at -40, +25, +85 Apply to E Package voltage and the RBO of that CD4033B is
ISTIC UNITS
+25 connected to the RBI terminal of the
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max. CD4033B in the next more·significant·bit
position. Again, this procedure is continued
for all CD4033B's on the fraction side of the
Current, - 0,10 10 10 10 300 300 - 0.04 10 display.
IDD Max. IJA
- 0,15 15 20 20 600 600 - 0.04 20 I n a purely fractional number the zero
- 0,20 20 100 100 3000 3000 - 0.08 100 immediately preceding the decimal point can
be displayed by connecting the RBI of that
Output low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - stage to a high level voltage (instead of to the
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - RBO of the next more-significant-stage).
IOl Min. 4 2.8 2.4 6.8 - For example: optional zero -+ 0.7346.
1.5 0,15 15 4.2 3.4
rnA Likewise, the zero in a number such as 763.0
Output High 4.6 0.5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 -
can be displayed by connecting the RBI of
(Source) 2.5 0.5 5 -2 -1.8 -1.3 -1.15 -1.6 3.2 the CD4033B associated with it to a high·
Current, -1.5 -1.1 -0.9 -1.3 2.6 level voltage.
9.5 0,10 10 -1.6
IOH Min. Ripple blanking of non-significant zeros
13.5 0.15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8
provides an appreciable savings in display
Output Voltage: - 0,5 5 0.05 - 0 0.05
power.
Low-Level,
VOL Max.
- 0,10 10 0.05 - 0 0.05 The CD4033B has a lAMP TEST input
- 0,15 15 0.05 0 0.05 which, when connected to a high-level volt-
V
Output Voltage: - 0.5 5 4.95 4.95 5 - age, overrides normal decoder operation and
High·level, 10 enables a check to be made on possible
- 0.10 10 9.95 9.95
VOH Min. display malfunctions by putting the seven
- 0,15 15 14.95 14.95 15 - outputs in the high state.
Input low 0.5.4.5 - 5 1.5 - 1.5
The CD4026B- and CD4033B-series types
Voltage. 1.9 - 10 3 - - 3 aresupplied in 16-lead hermetic dual-in-line
Vil Max. - - ceramic packages (D and F suffixes). 16-
1.5,13.5 - 15 4 4
V lead dual-in-line plastic packages (E suffix),
Input High 0.5,4.5 - 5 3.5 3.5
16-lead ceramic flat packages (K suffix),
Voltage. 1,9 - 10 7 7 - - and in chip form (H suffix).
VIH Min. 1.5,13.5 - 15 11 11 - -
Input Current
- 0,18 18 ±D.l ±0.1 ±1 ±1 - ±10- 5 ±0.1 IJA
liN Max.
127
COUNT 0 I I I2 I 3 41"
CL
RESET
CLOCK
INHIBIT
DISPLAY
ENABLE IN
DISPLAY
>-----'''-0 SEGMENT
UNGATED "e· ENABLE OUT
,
*CLOCK~I
D CL
* CLOCK
INHIBIT 2
"il
CARRY OUT
•
UNGATED
"e· SEG.
*~~~~ ~3_ _ _ _ _ _ _ _ _ _ _ _ _ _~ 4 DISPLAY

IN v ;»---+----------<j ENABLE
£li
Fig. 3 - CD40268 timing diagram.
I. OUT
VooO VDD
CLOCK Jl.n.JLrLrlJ"l.JruUlJ""LfULrLnJ"l.JfLn
GND0 8 * ALL INPUTS PAOTECTED ---- SEGMENT
BY COS/Mas INPUT DESIGNATIONS RESET,L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
PROTECTION NETWORK
Vss
~~g~--------~~~----~----
~~:; -----------',.----,~-------
Fig. 1 - CD40268 logic diagram. RBI------------------------__L-________
COUT
(CLOCK-:-'IOJ - - - - L -_ _ _r-------,._ _ _. . J -
SEGMENT
DESIGNATIONS
5 COUT
ICLOCK+IOI '~---------~
RBO _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
.... "," .~
Ol23YS6lB901 B YS6lB9 12
92CS-29084
*~CLOCK
.CLOCK
INHIBIT 2
D
11
CL
~
o D ,
*RBIC3>-_ _ _ _ _ _ _ _ _ _ _ _ _ _L../ CL_= a:
VODQ
I. * ALLINPUTS PROTECTED
BY COS/MOS INPUT
~VDD
RBO _ Q
R CL
CL
-l..r>o- CL
GND08 PROTECTION NETWORK.
~vss Fig. 5 - Detail of typical flip-flop stage for both types.

Fig. 2 - CD40338 logic diagram.
DRAIN-TO-SOURCE VOLTAGE (VcsJ-V
'~I,E,N,l -I!I -10 -5

AMBIENT TEMPERATURE (TA'-2!1·C
It GATE-TO-SOURCE VOLTAGE (VGS)--5V

d
-IO~
~
I
ffi
-15 ~
-IOV
-20~
-15V
I I
CRAIN-TO-SOURCE VOLTAGE (VosJ-V ORAIN- TO-SOURCE VOLTAGE
Fig. 6 - Typical n-channel output low (sink) Fig. 7 - Minimum n~hannel output low (sink) Fig. 8 - Typical p·channel output high (source)
current characteristics. current characteristics, current characteristics.
128
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25"C, Input tr , t,= 20ns, -IS -10 -5
AMBIENT TEMP£RATURE (lAI-25-C
CL =50pF, RL =200kfl.
TEST
CONDITIONS LIMITS
VDD -10'0'
(V) Min. Typ. Max.
CLOCKED OPERATION
-15'0'
Propagation Delay Time; tpLH, tPHL 5 - 250 500
Carry·Out line 10 - 100 200
15 - 75 150
5 - 350 700
Fig. 9 - Minimum p-channel output high (source)
Decode Outlines 10 - 125 250 ns current characteristics.
15 - 90 180
•
Transition Time; tTHL' tTLH 5 - 100 200
Carry·Out line 10 - 50 100
15 - 25 50
Maximum Clock Input Frequen~y, fCLA 5 2.5 5 -
10 5.5 11 - MHz
15 8 16 -
Min. Clock Pulse Width, tw 5 - 110 220 'OV
10 - 50 100
15 - 40 80
20 40 60 00
Clock and Clock Inhibit Rise or Fall Time;
trCL, tfCL
r2- Unlimited

92CS-,.705
rlQ.- ns
function of load capacitance for
15 decoded outputs.
Average Input Capacitance, CIN Any Input - 5 7 pF AMBIENT TEMPERATURE ITA I-ZS-C
RESET OPERATION
Propagation Delay Time; 5 - 275 550
To Carry·Out line, tpLH 10 - 120 240
15 - 80 160
To Decode Out Lines, tpHL' tpLH 5 - 300 600
10 - 125 250
15 - 90 180 ns
Min. Reset Pulse Width, tw 5 - 100 120
10 - 50 100 20 ~ 60
~ ~
92CS-31104
15 - 25 50 Fig. 11 - Typical propagation delay time as a

Min. Reset Removal Time 5 - a 30 function of load capacitance for
carry-out outputs.
10 - a 15
15 - 0 10
... Measured with respect to carrv-out line.
46810121416
SUPPLY VOLTAGE (VODI-V 92CS-StTQ3
Fig.. 12 - Tvpical maximum clock input-frequency

as a function of supply voltage.
129
Voo
TEST PEFORMEO WITH
THE FOLLOWING SEQUENCE OF
111"5 AND IIOlia AT EACH INPUT
SI S2 S3 S4 S5
I 000 0
10100
o 0 I 0 I
o I
* DISCONNECT
FOR CD4026B
PIN 14
92CS-31706
10 2 468102 2 "68103 2 "68'0" 2 "6~05

CLOCK INPUT~FREQUENCY ffeL.I-MHz 92CS·3,701 Fig. 15 - Quiescent device current.
Fig. 13 - Typical power dissipation as a function
of clock input frequency. 92C5- 31702
Fig. 14 - Dynamic power dissipation test circuit

for CD4033B.
INTERFACING THE CD4026B AND CD4033B WITH COMMERCIALLY AVAILABLE

LIGHT EMITTING DIODE DISPLAYS
MONSANTO MAN 3 MONSANTO MAN I rMANI---' 92CS-27441RI

OR EQUIVAL.ENT OR EQUIVAL.ENT I A I
(LOW POWER) VDD Fig. 16 - Input voltage.
VOO
I-+-:
I I IF I
I I I
CLOCK I I I
I I I
INHIBIT
I I I
RESET R I I I
Voo NOTE:
G I
L ____ --'
~
MEASURE INPUTS
SEQUENTIALLY.
Veo ~ 3.5 V VSS TO BOTH VOO AND VSS·
IFItI 5 mA/SEGMENT Ie Z: 0.4 mA
CONNECT ALL UNUSED
100% DUTY CYCLE INPUTS TO EITHER
IF~ 12 mA/Seg.IIOO"loOUTYCYClEI
R~VP-V8E-VF (LEol VDD OR VSS'
Pdt (MINI~30
ILED WHERE Vp'INPUT PULSE VeE I SAT! 5 0.5 V VSS
'IF ~ ~~~~~Do?C8f 92CS-31708
Ra "OO-VeE tsatl-vFtLEDI
ILED 92C5-31709
WHERE "Fa FORWARD DROP ACROSS DIODE Fig. 17 - Input current.
88 -96
(2.235 - 2.438)
~1---(O.lO~~_~254)_ 104 -112

(2.642 - 2.845)
----J 92CS-3I70001
S2.CS-32207
Dimensions and pad layout for CD4033B.

Dimensions and pad layout for CD4026B. The photographs and dimensions of each CMOS chip
represent B Chip when it is part of the wafer. When the
DimenSions Ifl paren theses are Ifl millimeters and Cleavage may vary with respect to the chip face for
are deflved from the baSIC Iflch dimensions as in- different chips. The actual dimensions of the isolated
dicated. Gfld graduations are Ifl mils (10--- 3 inch). chip, therefore, may differ slightly from the nominal
dimensions shown.
130
INTERFACING THE CD4026B AND CD4033B WITH COMMERCIALLY AVAILABLE
7·SEGMENT DISPLAY DEVICES*
(Refer to RCA Application Note ICAN·6733 for detailed interfacing information)
VT
liT INCANDESCENT READOUTS

RCA Numilron DA2000 Series
TUBE REOUIREMENTS
VT ;:: 3.5-5V
IT .., 24 rnA Segment
ASSUMED CD4049UB
TRANSISTOR
CHARACTERISTICS @Vee ;: 10 V (min.)
8de (min.) ?! 25 Vo "0" S 2v
VeE(SOI.)S n.sv IT :8mA (min,)
Vr::3.S V T06 V
: VOO '" 8 V (min.)
•
Ie'" 1m'" (min.)
CD4049UB
IT'" 24m.4. (min.) @Vee = 10 V (min.)
Yo"O" 5 0.6 V
IT'" 8 mol (min,)
LOW-POWER INCANDESCENT READOUTS ASSUMED
PINLITES INC-5eries 0 and R TRANSISTOR
TUBE ReaUIREMENTS VT(V) mNSegment
CHARACTERISTICS @V ee =6V (min.)
Ode (min.l:i!: 30 Yo"O" 5 I,V
0-03-15 1.5 B VeE(sol.IS n.SY
0-04-30 3 B IT = SmA (min.)
0-06.-30 3 8 • Vee> 3.5 V (min.)
Yr::::I.5 V TO 3.S V
R-R3-20 2 4.3 Ie ~ 0.25 mA (mift.)
R-R4--30 3 4.3 IT ~ 7.5 mA (min.)
92CM-31707
• The interfacing buffers shown, while a necessity with the CD4026A and CD4033A, are not required when
using the .oS" devices; the "B" outputs (~10 times the "A" outputs) can drive most display devices
directly especially at voltages above 10 V.
WITH VON"BV MEDIUM BRIGHTNESS

VT '" 1JOV DC
~_ _ _ _ _VDD '~~~~~~~~~NT i~~H~~:i~~R~~ND
NOTICEBLE GLOW IS VOFF;: 4.5 V
C04026B/
CD4033B
CLOCK r ~ _ _ _ _ _- ,
13.5V INHIBIT 7
V~~~~E SEGMENTS ~---...,
NEON READOUT INIXIE TUBE"I

1. Aleo Electronics - MG 19
RESET
..L_ _ _ _~.yVss
l
2. Burroughs - 85971. 87971, B8971 114.5V
TUBE REOUIREMENTS VTIVdcl rnA Segment

LOW VOLTAGE VACUUM FLUORESCENT
Aleo MG19. . lBO . 0.5
READOUTS
Burroughs 85971 . 170 • 3
BurroughsB7971,88971. 170. 1. Tung-Sol DIGIVAC S/G t Type DT1700fA or DT1705C
2. Nippon Electric (NEe); Type DG12E or L091S
... (Trademark) Burroughs Corp.
TUBE REQUIREMENTS: 100 to 300 pA/segment
TRANSISTOR CHARACTERISTICS at tube voltages of 12 V to 25 V depending on
Leakage with transistor cutoff - 0.05 rnA required brightness Filament requirement 45 mA
VIBRICER. • .. > VT at 1.6 V. ac or de.
Ode (min.) > 30 92CS-31710
* (Trademark) Wagner Electric Co.
92C5-31711
131
CD40278 Types
Features:
CMOS Dual J-K • Set-Reset capability
Master-Slave Flip-Flop • Static flip-flop operation - retains state indefinitely
with clock level either "high" or "low"
High-Voltage Types (20-Volt Rating) • Medium speed operation - 16 MHz (typ.) clock toggle
rate at 10 V
The RCA-C04027B is a single monolithic
chip integrated circuit containing two iden-
tical complementary-symmetry J-K master- • 100% tested for quiescent current at 20 V
slave flip-flops. Each flip-flop has provi- • Maximum input current of 1 IlA at 18 V over
sions for individual J, K, Set, Reset, ang full package-temperature range; 100 nA at
Clock input signals. Buffered Q and Q 18 V and 25 0 C
signals are provided as outputs. This input-
output arrangement provides for compatible • Noise margin (over full package-
operation with the RCA-CD4013B dual D- temperature range):
type flip-flop. 1 Vat VDD = 5 V
Functional Diagram
The CD4027B is useful in performing con- 2 Vat VDD = 10 V
trol, register, and toggle functions. Logic 2.5 V at VDD = 15 V
levels present at the J and K inputs along
with internal self-steering control the state
of each flip-flop; changes in the flip-flop
Standard No. 13A. "Standard SpeCIfications
state are synchronous with the positive-
going transition of the clock pulse. Set and
reset functions are independent of the clock Applications:
and are initiated when a high level signal is • Registers, counters, control circuits
present at either the Set or Reset input.
The CD4027B types are supplied in 16-lead
packages (E suffixl.16-lead ceramic flat
packages (K suffix). and in chip form (H
suffix). I.
I.
02 vo o
Q2 2 " 01
MAXIMUM RATINGS. Absolute-Maximum Values: CLOCK 2 " "Q1
DC SUPPLY-VOLTAGE RANGE. (VDD) RESET2 13 CLDCK I
INPUT VOLTAGE RANGE. ALL INPUTS .....................•...•.•............... -0.5 to VDD +0.5 V
'2
J2
5ETZ
12
"
10
.,
RESET I
JI
DC INPUT CURRENT. ANY ONE INPUT ................•...................•................ ±10 mA
POWER DtSSIPATION PER PACKAGE (PO):
vss
TOP VIEW
• SETI
For TA = -40 to +60'C (PACKAGE TYPE E) ................................................. 500 mW 92CS_2441'O
For TA = +60 to +85'C (PACKAGE TYPE E) ................... Derate Linearly at 12 mW/'C to 200 mW
For TA =-55 to +100'C (PACKAGE TYPES D. F. K) ......•..................................• 500 mW
TERMINAL ASSIGNMENT
For TA = +100 to +125'C (PACKAGE TYPES D. F. K) .......... Derate Linearly at 12 mW/'C to 200 mW
ForT A =FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW
OPERA TING-TEMPERATURE RANGE (TA):
PACKAGE TYPES D. F. K. H ........................................................ -55 to +125'C
PACKAGE TYPE E .................................................................. -40 to +85'C
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +150'C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max. . ....................•... +265'C
* RESETr-------~----------------------------------------------__,
4 (1210-+------1 )<>-------r-------------------------------4
PRESENT STATE
, ,
, 0
0 0
. ,,- ....
OOTPUT
./
NEXT STATE
OUTPUTS
0 0 ./
./
./
, , "- . 0
r, ,
* SET
71.10--------4 ~oo LOGIC I-HIGH LEVEL
LOGIC Q. LOW LEVEL
R CL 92CN-2755IRI
* C'::OCK r--..... t ~ t
*ALLINM
3fI3)~
PROTECTED BY Vss
COS/MOS PROTECTION
NETWORK
Fig_1 - Logic diagram and truth table for CD40278 (one of two identical J-K flip flops).
132
CD40278 Types
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
LIMITS
All
CHARACTERISTIC Packages UNITS
VDD
(VI Min. Max.
(For TA = Full Package Temperature Rangel
- 3 18 V
DRAIN-lO-SOURCE VOLTAGE lVoSI-V
5 200 -
Data Setup Time ts 10 75 - ns
Fig.2 - Typical output low (sink}
15 50 - current characteristics.
5 140 -
•
Clock Pulse Width tw 10 60 - ns
15 40 -
5 3.5
Clock Input Frequency (Toggle Model fCl 10 dc 8 MHz
15 12
5 - 45
Clock Rise or Fall Time trCl *, tfCl 10 - 5 J,ts
15 - 2
5 180 -
Set or Reset Pulse Width tw 10 80 - ns
15 50 -
DAAIN-TO-SOURCE VOLTAGE (Vosl-V
If more than one unit is cascaded in a parallel clocked operation, trCl should be made less
than or equal to the sum of the fixed propagation delay time at 15 pF and the transition Fig.3 - Minimum output low (sink}
time of the output driving stage for the estimated capacitive load. current characteristics.
DRAIN- TO-SOURCE VOLTAGE (Vns)-V DRAIN-lO-SOURCE VOLTAGE eVosl-v

-15 -10 -5 -1!5 -10 -5
AMBIENT TEMPERATURE ITA»-Z5·C 10 : AMBIENT TEMPERATURE ITA '-Z5·C
At.tI81ENT TEII,F£RATURE ITA'-25·C
GATE-TO-SOURC[ VOLTAGE 1Vc;s)--5V
-IOV -lOY
~ / y~
-15V ~
ii
"
. 10:
2
I
Fig.4 - Typical output high (source} Fig.5 - Minimum output high (source}
current characteristics. current characteristics. Fig.6 - Tvpical power dissipation vs. frequency.
INPUTOVDOOUTPUTS .
Vss
INPUTS
Yeo 1NPUOS
VDO NOTE V,H
'-- ~
~ ~:~~:;I!~~~S v~ J:
Yss TO BOTH VOD AND Vss'
CONNECT ALL UNUSm
INPUTS 10 EITHER NOTE:
TEST ANV ONE INPUT,
"'DO OR Vss ' Vss WITH OTHER INPUTS AT
Vss Yoo ORVss'
Vss
nCS-2740IAI
Fig.7,- Input cu"ent test circuit. Fig.s - Input·voltage test circuit. Fig.9, - Quiescent device current test circuit.
133
CD4027B Types

Values 81 -55, +25, +125 Apply to D, F, K, H Pkgs.
CHARAC·
CONDITIONS Values at -40,+25,+85 Apply to E Pkgs. UNITS
TERISTIC
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
/lA
Current - 0,15 15 4 4 120 120 - 0.02 4
100 Max. - 0,20 20 20 20 600 600 - 0.04 20
Output Low
(Sink) 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Current, 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 - mA
Output High 4.6 D,S 5 -0.64 0.61 -0.42 -0.36 -0.51 -1
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2
+-=--
-
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Volt-
age: - 0,5 5 0.05 - 0 0.05
Low-Level, - 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output Volt-
age: - 0,5 5 4.95 4.95 5 -
High- Level, - 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
Input
Current, - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 /lA
liN Max.
Dimensions in millimeters are derived from the basic inch dimensions

as indic8ted. Grid graduations are in mils (10- 3 ).

represent a chip when it is part of the wafer. When the
60-68 cleavage may vary with respect to the chip face for
(1.524-1.727\ differsnt chips. The actual dimensions of the isolated
chip, therefore. mey differ slightly from the nominal
dimensions shown.
79-8~~ ________~1
14----------(:-:2-.007-2.209\ Dimensions and Pad Layout for CD4027BH
92CS-35059
134
CD4027B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C; Input t r • It = 20 ns.
CL =50 pF. RL = 200 kQ
LIMITS
CHARACTE RISTIC All Packages UNITS
VDD
(V) Min. Typ. Max.
Propagation Delay Time: 5 - 150 300
Clock to Q or Q Outputs 10 - 65 130 ns
tpHL. tpLH 15 - 45 90
5 - 150 300
Set to Q or Reset to Q tpLH 10 - 65 130 ns 92C5-Z7~5Z
15 - 45 90 Fig. to - Typical propagation delay time VS'.

5 - 200 400 load capacitance (CLOCK or SET
to 0, CLOCK or RESET to Q.
Set to Q or Reset to Q tpHL 10 - 85 170 ns
•
15 - 60 120
5 - 100 200
Transition Time tTHL· tTLH 10 - 50 100 ns
15 - 40 80
Maximum Clock Input

5 3.5 7 -
Frequency# (Toggle Mode) 10 8 16 - MHz
tCL 15 12 24 -
5 - 70 140
Minimum Clock Pulse Width tw 10 - 30 60 ns
15 - 20 40
Minimum Set or Reset Pulse

5 - 90 180
Width tw
10 - 40 80 ns Fig./1- - Typical propagation delaY.Jime vso
load capacitance (SET to Q or
15 - 25 50 RESET to 0).
5 - 100 200
Minimum Data Setup Time ts 10 - 35 75 ns
15 - 25 50
Clock Input Rise or Fall Time

5 - - 45
10 - - 5 /.IS
trCL. ttCL
15 - - 2 "
Input Capacitance CI - 5 7.5 pF
# Inputt,,1t = 5ns.
SUPPLY VOLTAGE t'"ool-V
Fig.12- Typical maximum clOCk rrequency VS'.

supply voltage (toggle mode).
50 pF
16
15 (5°i
r:50PF
14
1 4
5
13
12
1=
50 PF
II
7 10
e 9
PULSE
L---------------~~__i GEN
92CS-36061
Fig. 13-Dynamic power dissipation test

circuit.
135
CD4028B Types
CMOS Features:
• BCO-to-decimal decoding or binary-to-octal decoding
BCD-to-Decimal Decoder • High decoded output drive capability VDD
• "Positive logic" inputs and outputs_ ...

..... decoded outputs go high on selection
• Medium-speed operation .... ~3~;;ll'l : :
tpHL' tpLH =80 ns (typ.) @VOO = 10 V
The RCA-C0402BB types are BCD-to-
decimal or binary-to· octal decoders consist- • Standardized, symmetrical output characteristics
BCD
INPUT':. I.",
ing of buffering on all 4 inputs, decoding· • 100% tested for quiescent current at 20 V , II D
logic gates, and 10 output buffers. A BCD • Maxi mum input current of 1 I1A at 18 V
code applied to the four inputs, A to D, over full package-temperature range;
results in a high level at the selected one of 100 nAat 18 V and 250 C
10 decimal decoded outputs. Similarly, a • Noise margin (over full package- CD4028B
3-bit binary code applied to inputs A through temperature range): FUNCTIONAL DIAGRAM
C is decoded in octal code at output 0 to 7 1 Vat VOO = 5 V
if D = "0". High drive capability is provided 2 Vat VOO =10 V
at all outputs to enhance dc and dynamic 2.5 Vat VOO = 15 V
performance in high fan-out applications. • 5-V, 10-V, and 15-V parametric ratings
The CD402BB-Series types are supplied in • Meets all requirements of JEOEC
l6-lead hermetic dual-in-line ceramic pack- Tentative Standard No. 13A, "Standard
ages (D and F suffixes), l6-lead dual-in-line Specifications for Oescription of 'B' I. voo
plastic packages (E suffix), l6-lead ceramic Series CMOS Devices"
4
• •
0 3
"
15 3
flat packages (K suffix), and in chip form (H Applications: t • "

13
suffix). Ii C-ode conversion • Indicator-tube decoder

9
S
•• I.
• Address decoding-memory selection control • t "
10
Vss 9
92CS_24471
Top View
TERMINAL DIAGRAM
TABLE I - TRUTH TABLE
DC B A 0 1 2 3 4 5 6 7 B 9
0 o0 0 1 0 0 0 0 0 0 0 0 0
0 o0 1 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 o 0 0 0 0 0
0 0 1 1 0 0 0 1 o 0 0 0 0 0
~
v0 * ALL INPUTS ARE PROTECTED
BY COSIMOS PROTECTION
0 1 0 0 000 0 1 0 0 0 0 0
----- NETWORK. 0 1 0 1 0 0 0 0 0 1 0 0 0 0
92CM-28612
0 1 1 o
0 0 0 0 0 1 o 0 0 0
Fig. , - Logic diagram. 0 1 1 1 0 0 0 0 0 0 o 1 0 0
vss 1 0 0 0 0 0 0 0 0 0 0 0 1 0
MAXIMUM RATINGS, Absolute-Maximum Values: 1 0 0 1 0 0 0 0 0 0 0 0 0 1
(Voltages referenced to VSS Terminal) ....................................................... -0.5 to +20 V
1 0 1 0 0 0 0 o
0 0 o 0 0 0
INPUT VOLTAGE RANGE, ALLINPUTS ................................................... -0.5 to VOD +0.5 V
1 0 1 1 0 0 0 o
0 0 o 0 0 0
DC INPUT CURRENT. ANY ONE INPUT ............................................................. ±10 mA 1 1 0 0 0 0 o
0 0 0 o 0 0 0
POWER DISSIPATION PER PACKAGE (PD): 1 1 0 1 0 0 0 0 0 0 o 0 0 0
For T A • -40-to +6O"C (PACKAGE TYPE E) ........................................................ SOO mW 1 1 0 0 0 0 0 0 0 0
1 0 0 0
For TA • +60 to +85'C (PACKAGE TYPE E) •.• , ....•••...••••••....•• Derate Llnesrly at 12 mWI'C to 200 mW
For T A • -55 to +100' C (PACKAGE TYPES D. F. K) .................................................. 500 mW 1 1 1 1 0 0 0 o 0 0 0 0 0 0
ForTA • +100 to +l25'C (PACKAGE TYPES D, F, K) .................. Derate Linearly at 12 mWI'C to 200 mW
I • HIGH LEVEL o· LOW LEVEL
For T A • FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .••••.••••••.••••.•.••.•••••• 100 mW
PACKAGE TYPES D, F, K. H ................................................................ -55 to +125'C
PACKAGE TYPE E •••.•••.•••..••..••...••••.•••••..••••.•..•...•.•..••••..••.•....•.••.•.•• -40 to +85'C
STORAGE TEMPERATURE RANGE (Tstg) ...................................... : .............. -65 to +15O'C
At distance 1/16± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.................................. +265'C
136
CD4028B Types
LIMITS
MIN. MAX.
Supply,Voltage Range
=
(For T A Full Package
Temperature Rang(!) 3 18 V
, ,
DRAIN-lO-SOURCE VOLTAGE !VOSI-V
LIMITS AT INDICATED TEMPERATURES (OCI Fig. 2 - Typical output low Isink)
Values at -55, +25, +125 Apply to D, F, K, H Packag'e.- current characteristics.
CONDITIONS
CHARACTER· V.lue•• t .....0. +25. +85 Apply to E Poe"'",
ISTIC UNITS
+25
Vo VIN VDD
..... 0 Typ.
AMeIEN~ TEMPE~~TURE~TAI'2~·C: ::1 :::: IT: ...
-55 +85 +125 Min. Max. :::::1:: :::11::::1::::1:::: :::: ::::
II
(VI (VI (VI : .. ,
Quiescent Device - a,s 5 5 5 150 150 - 0.04 5 :::: J: :::: :::: :::: :::: :'f: :::: :::
Current,
100 Max.
- 0,10 10 10 10 300 300 - 0.04 10
IJA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0.5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sinkl Current 0.5 0.10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min.
1.5 0.15 15 4.2 4 2.8 2.4 34 6.8 -
Output High 4.6 0.5 5 -0.64 -0.61 -0.42 -0.36 -0.51 1 - mA
(Sourcel
Current,
2.5 0.5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - !I 10 I!I
IOH Min.
9.5 0.10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - DRAIN-lO-SOURCE VOLTAGE (I.'051-V
13.5 0.15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - Fig. 3 - Minimum output low (sink J
Output Voltage; - 0.5 5 0.05 - 0 0.05 current characteristics.
Low·Level.
VOL Max. - 0.10 10 0.05 - 0 0.05
- 0.15 15 0.05 - 0 0.05
V
Output Voltage: - 0.5 5 4.95 4.95 5 -
High·Level. - 0.10 10 9.95 9.95 10 -
VOH Min.
- 0.15 15 14.95 14.95 15 -
Input Low 0.5.4.5 - 5 1.5 - - 1.5
Voltage.
VIL Max.
1.9 - 10 3 - - 3
1.5.13.5 - 15 4 - - 4
V
Input High 0.5.4.5 - 5 3.5 3.5 - -
Voltage. 1.9 - 10 7 7 - -
VIH Min. 1.5.13.5 - 15 11 11 - -
Input Current
liN Max. - 0.18 18 ±0.1 ±0.1 ±1 ±1 - .±1O- 5 ±0.1 IJA
Fig. 4 - Typical propagation delay time as

a function of load capacitance.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 0 C.CL = 50 pF.

Input t,.1f = 20 ns, RL = 200 kn ,
DRAIN-10-SOURCE VOL1AGE \VosJ-V
TEST CONDITIONS LIMITS

VDDIV) Typ. Max.
Propagation Delay Time: 5 175 350 ns

tpHL' tpLH 10 80 160
15 60 120
5 100 200
Transition Time 10 50 100 ns
tTHL. tTLH 15 40 80
Input Capacitance. CIN - 5 7.5 pF
Fig. 5 - Typical output high (source)

137
CD4028B Types
TABLE II - CODE CONVERSION CHART
INPUT CODES
Hexa_ Decimal
Decimal
INPUTS >- '" '" OUTPUT NUMBER
a:
1-< 1->- ~~>-
u<
z~
W'
-z -< UX xa:
"'a: w
~~
DeB A 'l'- .tel <~
... '" wel 0 1 2 3 4 5 6 7 89101112131415
o 0 o 0 0 0 0 o 1 0 o 0 o0 0 o 0 0 0 0 0 0 0 0
000 1 1 1 1 1 0 1 o 0 o0 o0 0 000 0 0 0 0
0 0 1 0 2 3 0 2 2 0 0 1 0 o 0 0 .00 000 0 o 0 0
0 0 1 1 3 2 0 3 3 o0 0 1 o0 0 o 0 o0 o0 0 o0
0 1 0 0 4 7 1 4 4 o0 o0 1 000 0 0 0 0 0 000
nel-uu,,!!
o1 0 1 5 6 2 3 0 000 o 1 000 0 000 000 current characteristics.

0 1 1 0 6 4 3 1 4 0 0 0 0 0 0 1 o 0 0 000 o 0 0
0 1 1 1 7 5 4 2 o0 0 o 0 0 o 1 o 0 o 0 0 0 0 0
1 o 0 o0 0 0 o 0 000 0 0
.·.·
0 8 15 5 0 000 1 ID AMBIENT TtMPERATURE (TA). 25"'C
1 0 0 1 9 14 6 5 0 0 0 0 o0 o0 0 1 0 000 0 0
1 0 1 0 10 12 7 9 6 0 000 o 0 000 0 1 0 000 0 ~I04. I II~
1 0 1 1 11 13 8 5 0 o 0 0 0 0 000 0 o 1 o 0 0 0 - .~
"o~
~
0 o 0 0 0 o 0 0 0 0 0 o 1 0 o 0 ~
1 1 0 0 12 8 9 5 6 ~ I-.~ 7~.,~
1 1 0 1 13 9 6 7 7 0 0 0 0 o0 0 0 0 0 o 0 0 1 0 0 ~ 10', ~
cY
!!i • ~
1 1 1 0 14 11 8 8 8 O. 0 0 0 0 000 0 0 0 o 0 o 1 0 II •
e 'I'
1 1 1 1 15 10 7 9 9 0 000 00000 0 o 0 0 0 0 1 E
/
I
CL -SOpF'
~I~ ----CL -I"F r=
L
10
·
•
I 2 418'0 2 4 2 4 "I~Z 4
11,02
UI I
",ef ' ..',r!
INPUT FREQUENCY (f)-IIHI
8ZCS-294IZ
YDO 1NPUOS NOW Vco Fig. 7 - Typical dynamic power dissipa·
tion as a function of input
~ ~::~~;I~~~~~S frequency.
'Iss TO BOTH YOD AND Yss'
CONNECT ALL UNUSED
INPUTS TO EITHER
YeD OR Vss'
Vss
TVflCAL APPLICATIONS
INPUT/
116 CD4069B
Fig. 8 - Typical transition time as a Voo
v," 'NPUTO.OuTPuTS
Y~L
'-- ~
:t
NOTE·
'Iss ~S:-N~"u~~OMBIN"TlON
"CI-aM'"
500,..F
Fig. 11 - Input voltage test circuit. Fig. 13 - Code conversion circuit.
vOD
.
Vss
INPUTS ,_L----, The circuit shown in Fig.13 converts any 4·
bit code to a decimal or hexadecimal code .
Table 2 shows a number of codes and the
decimal or hexadecimal number in these
codes which must be applied to the input
terminals of the CD4028B to select a partie·
ular output. For example: in order to get a
Fig. 10 - Dvnamic power dissipation high on output No. 8 the input must be
test circuit. Vss either an 8 expressed in 4·Bit Binary code, a
Fig. 12 - Quiescent device current 15 expressed in 4·Bit Gray code, or a 5 ex·
test circuit. pressed in Excess·3 code.
138
CD4028B Types
"(Trademark) Burroughs Corp.
Fig. 14 - Neon readout (Nixie Tube·) display application.
•
Fig. 15 - 6·bit binary to '·of·64 address decoder.
71-79
1.804-2.006)
CD4028BH
DIMENSIONS AND PAD LAYOUT
Dimensions in parentheses are in millimeters and are represent a chip when it is parr of the wafer. When the
derived from the basic inch dimensions as indicated. waler is separated into individual chips. the angle 01
Grid graduations are in mils 110- 3 inch). clsavage may vsry with respect to the chip face for
different chips. The actual dimensions 01 the isolated
chip. therefore. may differ slightly from the nominal
dimensions shown. The user should considers tolerancs
of -3 mils to +16 mils applicable 10 the nominal
dimensions shown.
139
CD4029B Types
CMOS Presettable Features:
• Medium-speed operation ___ 8 MHz (typ_1 PRESET
ENABLE
Up/Down Counter @ Cl = 50 pF and VDD-VSS = 10 V

• MUlti-package parallel clocking for synchronous
high speed output response or ripple clocking
Binary or BCD-Decade for slow clock input rise and fall times BINARVI
High-Voltage Types !20-Volt Rating) • "Preset Enable" and individual" Jam" inputs provided DECADE 9
• Binary or decade up/down counting ~IO

The RCA-CD4029B consists of a four-stage • BCD outputs in decade mode
binary or BCD-decade up/down counter with ~15
provisions for look-ahead carry in both • 5-V, 10-V, and 15-V parametric ratings
counting modes_ The inputs consist of a • Standardized, symmetrical output charac-
single CLOCK, CARRY-IN (CLOCK EN- teristics Vss
92CS-17190R3
ABLE), BINARY/DECADE, UP/DOWN, PRE- • Maximum input current of 1 /.IA at 18 V
CD4029B
SET ENABLE, and four individual JAM sig- over full package-temperature range;
100 nA at 18 V and 25 0 C FUNCTIONAL DIAGRAM
nals_ 01, 02, 03, 04 and a CARRY OUT
• Noise margin (over full package-tempera-
signal are provided as outputs. ture rangel
A high PRESET ENABLE signal allows 1 Vat VOO = 5 V
2 V at VDO = 10 V
information on the JAM INPUTS to preset
2_5 Vat VOD = 15 V
the counter to any state asynchronously with
the clock. A Iowan each JAM line, when the • Meets all requirements of JEDEC Tentative
PRESET-ENABLE signal is high, resets the Standard No. 13A, "Standard Specifications
counter to its zero count. The counter is for Description of 'B' Series CMOS Devices"
advanced one count at the positive transition
of the clock when the CARRY-IN and PRE- Applications:
SET ENABLE signals are low. Advancement • Programmable binary and decade
is inhibited when the CARRY-IN or PRESET counting/frequency synthesizers-BCD output
ENABLE signals are high. The CAR RY -OUT • Analog to digital and digital to
signal is normally high and goes low when analog conversion
the counter reaches its maximum count in • Up/Down binary counting
the UP mode or the minimum count in the • Magnitude and sign generation
DOWN .mode provided the CARRY-IN sig- • Up/Down decade counting
nal is low. The CARRY-IN signal in the low • Difference counting
state can thus be considered a CLOCK
ENABLE. The CARRY-IN terminal must be
connected to VSS when not in use.
Binary counting is accomplished when the
BINARY!DECADE input is high; the counter RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted_ For maximum
counts in the decade mode when the BI- reliability, nominal operating conditions should be selected so that operation is always within the
NARY/DECADE input is low. The counter following ranges:
counts up when the UP/DOWN input is LIMITS
CHARACTERISTIC VDD UNITS
high, and down when the UP/DOWN input
(VI Min. Max.
is low. MUltiple packages can be connected
in either a parallel-clocking or a ripple- Supply-Voltage Range (For T A = Full Package-
clocking arrangement as shown in Fig. 17. Temperature Range) - 3 18 V
Parallel clocking provides synchronous con- 5 60 -

Setup Time tSU:
trol and hence faster response from all
Carry-In
10 20 -
counting outputs. Ripple-clocking allows for 15 12 -
longer clock input rise and fall times.
5 340 -
The CD4029B-series types are supplied in
l6-lead ceramic dual-in-line plastic pack- U/D or B/D 10 140 -
ages (E suffix), l6-lead ceramic flat packages 15 100 - ns
(K suffix), and in chip form (H suffix). 5 180 -
Clock Pulse Width, tw 10 90 -
15 60 -
5 130 -
CD4029B Terminal Diagram Preset Enable Pulse Width, tw 10 70 -
15 50 -
. PRESET ENABLE I. I.
,. VDD
-
o'
JAM4
JAMI
•
3 I.
13
CLOCK
03
JAM 3
Clock Input Frequency, fCl
5
10
15
-
-
2
4
5.5
MHz
CARRY IN JAM2
01 " 02
CARRY OUT "
10 UP/DOWN
5 -
Vss BINARY I DECADE Clock Rise and Fall Time, trCl, tfCl 10 - 15 /.Is
15 -
140
CD4029B Types

DC SUPPL Y-VOL TAGE RANGE, (VDD)
(Voltages referenced to VSS Terminal) """'''''''''''',''', ..... " ...... "....... -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS .".".""."."",,"""""",,.,," -0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT"" "". ". ". " " " " " " " " "". " " " ",,"" ±10 mA
For TA = -40 to +60°C (PACKAGE TYPE E) " " " " " " " " " " " . " " " " " " . , , " " , , . 500 mW
For TA =+60 to +B5°C (PACKAGE TYPE E) ............... Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +loo°C (PACKAGE TYPES 0, F, K) " " . " " " " " . " " " " " " . " , , . , , .. 500 mW
For TA = +100 to +125°C (PACKAGE TYPES D. F, K) ....... Derate Linearly at 12 mW/oC to 200 mW
~ 10
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .........•.•.•.... 100 mW 5 ,
PACKAGE TYPES 0, F, K, H "."."""."." ...... " " " " " " " " , , , , .. ,,",,. -55 to +125°C
PACKAGE TYPE E ." .............................. " ................... "." ..•. -40 to +85°C
DRALN-10~SOURCE "
VOLTAGE (VDSI-V
STORAGE TEMPERATURE RANGE (Tstg) ."." ........... " ...... " ..•...... " ... -65 to +150°C Fig. 1 - Typ;caJ output low (sink) current
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max........•...•.......... +265°C
CHARAC- CONDITIONS
Values al -55, +25, +125 Apply 10 D, F, K, H Packages
U
N
I
~ AM""" TEMP'Riilii
,
E
~6
"~125
~
.,
~
~
g
10
7.5
15
I [I]
i1i'iiiiil
1111111111111'
'JJ,I,'JJJ1UID, VOLTAGE tvos"'"
H1T
•
§ 25
Vo
(V)
VIN VDD
(V) (V) -55 -40 +85 +125
+25
Typ. Max.
S
ill
5 10 ,5
Min. DRAIN-la-SOURCE VOLTAGE (V051-V
- 0,5 5 5 5 150 150 - 0.04 5 Fig. 2 - Minimum output low (sink) current
Quiescent characteristics.
Device - 0,10 10 10 10 300 300 - 0.04 10
p.A
Current, - 0,15 15 20 20 600 600 - 0.04 20 DRAIN-TO-SOURCE VOLTAGE (V05)-\1
100 Max.
- 0,20 20 100 100 3000 3000 - 0.08 100
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -

Output Low
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mil

Output High
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0.15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
- 0,5 5 0.05 - 0 0.05
Output Voltage:
Low·Level, - 0,10 10 0.05 - 0 0.05 Fig. 3 - Typical output high (source) current
VOL Max. characteristics.
- 0,15 15 0.05 - 0 0.05
V
DRAIN-TO-SOURCE VOLTAGE IVos)-V
Output - 0,5 5 4.95 4.95 5 -
-" -'0 -, 0
Voltage: AMBIENT TEMPERATURE ITAI-25-C
High·Level,
- 0,10 10 9.95 9.95 10 -
tttttttttW!.
GATE-TO-SQURCE VO~T~E (VGS)' -5 v
VOH Min. - 0,15 15 14.95 14.95 15 -

-,
0.5,4.5 - 5 1.5 - - 1.5
Input Low
Voltage 1,9 - 10 3 - - 3
~U! , ·0
VIL Max. 1.5,13.5 - 15 4 - - 4
V
Input High
0.5,4.5 - 5 3.5 3.5 - - '-15 V
Voltage, 1,9 - 10 7 7 - - ."

1- 11l1l1
VIHMin.
1.5,13.5 - 15 11 11 - - , ,
Input Current
II Ililll
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 p.A
liN Max. Fig. 4 - Minimum output high (source) current
characteri$tics.
141
CD4029B Types
,--«1----i--~~~~~--- •.
C
-Jr~r-+-~-------+------~+-~+===~=====~
CAPACITANCE (CLl-pF
Fig. 5 - Typica' transition time as B function of
load capacitance.
fi
TRUTH TABLE
~
vo
CLO-", TE PE J Q a
,
*ALL INPUTS ARE PROTECTED
_
CL
E'
TE 0
.
x x
0
0
,
0
x 0
, ,
0
Q
VSS
BY COSIMOS INPUT PROTECTION
NETWORK
92CL·28675 R1
Q
.
X
.r
X
, ,
x
0
, X
X
Q
Q
0
Q NC
Q Nt
X-DON" CARE
Fig. 9 - ,Logic diagram.
Fig. 6 - Typical p_tion delay times as a func·

tion of load capilCitanco (0 output).
LOAD CAPACITANCEfCL,J-pf 92CS."720

Fig. 7 - Typical propagation dolay time as a func·
tion of load capacitance (carry outputl.
4, A"IIENT
r-- .
TEWE1ifj-ITA).e
- -- ---t- o!'".!..
,
~IO"
r-
==.
. I II ~I
]:J . ..~
.. ~
~~•
?z . --.~
- ...'
~.
I?-~
i~
~
"'
. --.'=-"-r.,1.fr.v/
. (I
;J.
f • - CL -'0 pf
:= ,, 1 1 1 1
• CL-I'5 pI __
, 1 1 1 1
. ..
1 1 1 1
,. z 4
IIII
e.·
I
COUNT 9 110
1
1
11 112 17
1
1
6 5 14 I 3
1
1
1
1
10 ,0'
9ZCM-17192R:i!
CLOCK FREQUENCY C'a..l-'HI lieS-tin,
Fig. 8 - Typical power dissipation as a function Fig. 10 - Timing diagram-binary mode.
of frequency.
142
CD4029B Types
92CS-17195R2
Fig. 11 - Conversion of clock up, clock down

input signals to clock and up/down
input signals.
The CD4029B CLOCK and UP/DOWN inputs

are used directly in most applications. In
applications where CLOCK UP and CLOCK
CONTROL
INPUT
BIN/DEC
LOGIC
LEVEL ACTION
BINARY COUNT
DOWN inputs are provided, conversion to
the CD4029B CLOCK and UP/DOWN inputs
can easily be realized by use of the circuit
II
(BID) DECADE COUNT
in Fig. 11.
04 UP/DOWN UP COUNT
(U/D) DOWN COUNT
CD4029B changes count on positive transi·
PRESET ENABLE JAM IN
(PEl NO JAM tions of CLOCK UP or CLOCK DOWN
NO COUNTER inputs. For the gate configuration shown
AOVANCE AT POS.
CARRY IN icY)
CLOCK TRANSITION below, when counting up the CLOCK DOWN
(CL.OCK ENABLE) ADVANCE COUNTER
AT POS. CLOCK
input must be maintained high and conversely
TRANSITION
when counting down the CLOCK UP illPLIt
must be maintained high.
Fig. 9 - Logic diagram (cont'd).
I ,
~-+--~~~~~+-~-+--~~-+--~+-~~--~~-+~~:~
I I
I ,
:--7-~~--+-~-7~--7-~~--+-~~--~+-~~--+-~-7~:r-:
~~7-+-+-~~~-7-+~~--~7-7-+-+-~~~-7~U-:-
I
,
I I I I
I I I I
IL..L......!--.! 11"1"
I I . I I I I
~:=+::~+==+~::+=~=+'~~'
I"'~~':=+::~+=~=+::~+=~-:I~
I
IIUI
I I
I
I
I I
I
1
I
I
I
I~
I
I
I
I
I
I
I
I I I I [ I I 1 1 I I
7:eI9:81716:54 32:1 °1°1916:7
I I I I I I I I I I
nCM-1719:3R3
Fig. 12 - Timing diagram-decade mode.
143
CD4029B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A • 25°C. Input tr.t, =20 ns.

Cl ~50pF.Rl =200kn

VDD(VI Min. !yp. Max.
Clocked Oparation
Propagation Delay Time: tpHl' tpLH 5 - 250 500
a Output 10 - 120 240
15 - 90 180
92C~-29722
5 - 280 560
Carry Output 10 - 130 260 Fig. 13 - Power dissipation test circu;f.
15 95 190 ns
5 - 100 200
Transition Time: tTHl' tTlH 10 - 50 100
a Outputs. Carry Output 15 - 40 80
5 - 90 180
Minimum Clock Pulse Width. tw 10 - 45 90
15 30 60
5 - - 15 INPUTS
Clock Rise & Fall Time, trCl, ttCl ** 10 - - 15 /JS °
Vss
15 - - 15
Minimum Setup Times, ts

.. 5 - 170 340
ns
8/0 or UfO 10 - 70 140
15 - 50 100
5 2 4 -
Maximum Clock Input Frequency, tCl 10 4 8 - MHz VSS
15 5.5 11 -
Fig. 14 - Ouiescent-device current test circuit.
Input Capaci tanee, CIN Any Input - 5 7.5 pF
Preset Enable
5 - 235 470
Propagation Delay Time: tpHl, tpLH 10 - 100 200
a Outputs 15 - 80 160
5 - 320 640 VDO
Carry Output 10 - 145 290
15 - 105 210 ,NPUTOOUTPUTS
ns
- V'H
5 65 130
'-- ~
Minimum Preset Enable Pulse Width, tw 10
15
-
-
35
25
70
50
V~L :t
Minimum Preset Enable Removal
5 - 100 200
vss
NOTE
TEST ANY COMBINATION
10 - 55 110 OF" INPUTS
Time. t rem * -
15 40 80 92CS-27441FiI
Carry Input Fig. 15 - Input voltage test circuit.
Propagation Delay Time·: tpHl' tplH 5 - 170 340

Carry Output 10 - 70 140 ns
15 - 50 100
5 - 25 50 ns
Min. HOLD Time
tH *** Carry In
~
10 - 15 30
15 - 12 25
5 - 100 200 ns
Min Set-Up Time
fs*** Carry In 10
15
-
-
35
30
70
60 l Voo
~
INPUV
C S NOTE
DD
~:;~i::,~~~~~S
Vss TO BOTH Voo AND Vss
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR Vss·
* from Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge. Vss
** If more than one Unit IS r:ascaded In the parallel clocked application, trCL should be made less than or
equal to the sum of the fixed propagation delay.n 15 pF and the transition time of the carry output
driving stage for the estimated capacitive load. This measurement was made with a decouplina capacitor Fig. 16 - Input current test circuit.
(>1 ~F) between VOO and VSS' ***From Carry In to Clock Edge
144
CD4029B Types
·PARALLEL CLOCKING"
U~OOWN>_-----1--------------------~~====::::==~--------~---------------+
~~~~~~ >-------j--....------------------t--..------------------+--_.-------------+
UP'D
C1: CD4029 n>, p------Qn CD4029

....
BID
CLOCK >------i--~------------------t-~------------------t--4-------------+
g~~~r>------4--------------------~~--------------------~---------------*
• CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch
pulse resulting from differential delays of different CD4029B IC's. These negative-
going glitches do not affect proper CD4029B operation. However. if the CARRY OUT
signals are used to trigger other edge-sensitive logic devices, such as FF's or counters,
the CARRY OUT signals should be gated with the clock signal using a 2·input OR gate
I
such as C04071B.
UP/DOWN >_-----.----------------------=;"~R'=P=PL=E=CL=O=CK='N=G="=---------_.----------------..
~:i~~~ >-------t--....------------------t--..------------------+---.-------------*
UWD
CI.
BID
>_------+--+----------....-1 92CL-Z8176Rt
____...l----------------..
CLOCK
BINARY/>
DECADE ______ .L____________--====±=======~
Ripple Clocking Mode:
The Up/Down control can be changed at any count. The only restriction on changing
the Up/Down control is that the clock input to the first counting stage must be high.
For cascading counters operating in a fixed up-count or down-count mode, the OR
gates are not required between stages, and CO is connected directly to the CL input of
the next stage with Ci grounded.
Fig. 71- Cascading counter packages.
10 20 30 40 50 60 70 eo 90 100 108

Dimensions and pad layout for CD4029B_ represent a chip when it ;s part of the wafer. When the
are derived from the basic inch dimensions as in- chip, therefore, may differ slightly from fhe nominal
dicated. Grid graduations are in mils (10- 3 inch). dimensions shown. The user should consider a tolerance
dimensions shown_
145
CD4030B Types
CMOS Features:
• Medium-speed operation-tpHL, tpLH = 65 ns (typ.) at
Quad Exclusive-OR Gate VDD = 10 V, CL = 50 pF • J
High-Voltage Types (20-Volt Rating) 4 K
.• 5-V, 10-V, and 15-\,,"parametric ratings
The RCA·CD4030B types consist of four in-- •• Maximum input current of 1 /lA at 18 V over full package-
dependent Exclusive·OR gates. The CD4030B temperature range; 100 nA at 1.8 V and 25° C " M
provides the system designer with a means • Noise margin (over full package-temperature
for direct implementation of the Exclusive· range):
OR function. 1 Vat VDD = 5 V VSS·7
VOO-14
The CD4030B types are supplied in 14-lead 2VatVDD=10V 92CS-30051
hermetic dual-in-line ceramic packages (D 2.5 Vat VDD = 15 V

CD4030B
and F suffixes), 14-lead dual-in-line plastic • Meets all requirements of JEDEC Tentative FUNCTIONAL DIAGRAM
packages (E suffix). 14-lead ceramic flat Standard No. 13A, "Standard Specifications
packages (K suffix). and in chip form (H for Description of '8' Series CMOS Devices" Applications:
suffix).
• Even and odd-parity generators and checkers
MAXIMUM RATINGS, Absolute-Maximum Values: • Logical comparators
DC SUPPLY -VOLTAGE RANGE, (VDD) • Adders/subtractors
(Vollages referenoed 10 VSS Terminal) ............................................. -O.Slo +20 V
• General logic functions
INPUT VOLTAGE RANGE. ALL INPUTS ........................................ -O.Slo VDD +O.S V
DC INPUT CURRENT, ANY ONE INPUT .................................................. ±10 mA
For TA = -4010 +60'C (PACKAGE TYPE E) ............................................. SOO mW
For TA = +6010 +85'C (PACKAGE TYPE E) ............... Derale Linearly al12 mWI'C 10 200 mW
For TA = -SSlo +100'C (PACKAGE TYPES D, F, K) ...................................... SOO mW
For TA = +100 10 +12S'C (PACKAGE TYPES D. F, K) ....... Derale Linearly al12 mWI'C 10 200 mW
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ....•.....•....... 100 mW
PACKAGE TYPES D, F, K, H ..................................................... -5510 +125'C
PACKAGE TYPE E ............................................................... -4010 +BS'C TERMINAL DIAGRAM
STORAGE TEMPERATURE RANGE (Tstg) ......................................... -6510 +lS0'C Top View
AI dislance 1/16± 1/32 inch (1.S9±0.79 mm) from case for lOs max.........•.....•...•... +26S'C
RECOMMENDED OPERATING CONDITIONS A I 14 Voo

B 2 13 H
J. AESB 3 12 G
K'C~O 4 II M'GESH
5 10 L'EESF
LIMITS
CHARACTERISTIC UNITS 0 6 9 F
MIN. MAX. V55 7 8 E
Supply·Voltage Range (For T A = Full Package TOP VIEW

3 18 V 92CS-24473RI
Temperature Range)
TRUTH TABLE FOR ONE OF

FOUR IDENTICAL GATES
A B J
0 0 0
1 0 1
0 1 1
P::~ECTED ~
1 1 0
I = HIGH LEVEL
*'NPUTS __ Vss Vss 0= LOW LEVEL
BY COS/MOS
PROTECTION NETWORK
Fig. 1 - Schematic diagram (1 of 4 identical

Vss 92CS-30052 gatesl.
146
CD4030B Types
U
N
CHARAC- Va'lues at -40, +25, +85 Apply 10 E Package
I
TERISTIC +25 T
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max. S
Quiescent - 0,5 5 1 1 30 30 - 0.02 1

Device - 0,10 10 2 2 60 60 - 0.02 2 iJ.A
Current,lDD - 0,15 15 4 4 120 120 - 0.02 4
Max. - 0,20 20 20 20 600 600 - 0.04 20 I ,
DRAIN-lO-SOURCE VOLTAGE1IJosl-1J
Output Low
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink)
Current
0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - Fig. 2 - Typical output low (sink) current
characteristics.
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - AMBIENT TEMPERATURE (TAlo25"C
Output High
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
mA +
I
Current,
IOH Min.
9.5
13.5
0,10
0,15
10
15
-l.B
-4.2
-1.5
-4
-1.1
-2.8
-0.9
-2.4
-1.3 -2.B
-3.4 -B.8 .i
~15
'2 .5
.. f
GATE TO-SOURCE VOLTAGE (V05'015V
I-t + +-t.
- 0,5 5 0.05 - 0 0.05 a 10 ,"

Output Voltage:
Low-Level, - 0,10 10 0.05 - 0.05 10V
VOL Max. - 0,15 15 0.05 - 0 0.05

V
Output Voltage: - 0,5 5 4_95 4.95 5 - ,v
High-Level, - 0,10 10 9.95 9_95 10 - 5 10 15
DRAIN-lO-SOURCE VOLTAGE Nasi-V
VOH Min. - 0,15 15 14.95 14_95 15 -
Input Low 0.5.4.5 - 5 1.5 - - 1.5 Fig. 3 - Minimum output low (sink) current
- - characteristics.
Voltage, 1,9 10 3 - 3
VILMax. 1.5,13.5 - 15 4 - - 4 DRAIN-lO-SOURCE VOLTAGE IVDSI-V
I I
V
Input High 0.5,4_5 - 5 3.5 3.5 - -
Voltage. 1,9 - 10 7 7 - -
VIHMin. 1.5,13.5 - 15 11 11 - -
Input Current
'IN Max. - 0,18 18 ±O.l ±0.1 ±1 ±l - ±10- 5 ±O.l ',llA

characteristics.
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =25°C; Input t r , If = 20 ns, DRAIN-lO-SOURCE VOLTAGE tVosl-V
CL = 50 pF, RL = 200 K!2 -,

CONDITIONS
CHARACTERISTIC LIMITS UNITS
VDD
(V) Typ. Max.
5 140 280
Propagation Delay Time, tpLH, tpHL 10 65 130 ns
15 50 100
5 100 200
Transition Time, tTHL, tTLH 10 50 100 ns
15 40 80
Input Capacitance, Any Input 7.5 pF Fig. 5 - Minimum output high (source) current
CIN 5
characteristics.
147
CD4030B Types
.
1 0 P U T O V o OUTPUTS
o
INPUTS
.'--
V,H
Vss
Vil
~ -
-=-
NOTE;
Vss ~S:-N",~~~OMaINATION
92CS-27441RI
Fig. 11 - Input·voltage test

circuit.
Fig. 10 - Quiescent·device current
CAPACITANCE (CL)-pF 'J2tS*Mm test circuit.
Fig. 6 - Typical transition rime as a function of
load capacitance.
VDO 1 N P UVoo
O S NOTE
~ MEASURE tNPUTS
o ~ SEQUENTIAL,LY.
Vss TO BOTH Voo ANOVSS
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS
VSS
92CS-300!S5
Fig. 12 - Input-current test Fig. 13 - Dynamic power dissipation test

LOAD CAPACITANCE ICLJ-pF circuit. circuit.
Fig. 7 - Typical propagation delay time as a function
of load capacitance.
AMBIENT TEMPERATURE (TA )·25-C

LOAD CAPACITANCE ICL~:50 pF
!5 10 15 20
SUPPLY VOLTAGE 1Vool-V

of supply voltage. "
.e . ,
~IO'+---+
92CS-35057
Dimensions and pad layout for CD4030BH.
~I~'~'~----~~~~~--+------r----~
i : wafer is separated into individual chips, the angle of
i,o'~~~~~-4-----+---1---~ are derived from the basic inch dimensions as in-
• t dicated. Grid graduations are in mils (10-- 3 inch). chip, therefore, may differ slightly from the nominal
it , dimensions shown. The user should considera tolerance
~ I~~~~---r~--T----;----~
: of -3 mils to +16 mils applicable to the nominal
dimensions shown.
10-12
1,12 .... 2 "6',2 ... ',2 .... 2 ... 1ib"
INPUT FREQUENCY itII-kHI
Fig. 9 - typical dynamic power dissipation as a
function of input frequency.
(
148
CD4031 B Types
CMOS 64-Stage Features:

• Fully static operation: DC to 12 MHz typo @ VDD-VSS
Static Shift Register = 15 V DATA I
IN
I~
High-Voltage Types (20-Volt Rating) • Standard TTL drive capability on Q output MODE 10 CONTROL 64
. CONT LOGIC STAGES DATA
OUT
• Recirculation capability
• Three cascading modes:
•
The RCA-CD4031 B is a static shift register Direct clocking for high-speed operation
that contains 64 D-type, master-slave flip- Delayed clocking for reduced clock drive requirements
flop stages and one stage which is aD-type Additional 1/2 stage for slow clocks
master flip-flop only (referred to as a 112
• 100% tested for quiescent current at 20 V DELAYED
stage)_ CLOCK
• Maximum input current of 1 J.lA at 18 V Voo'" 16 OUT
The logic level present at the DATA input is over full package·temperature range; 100 nA
\Iss = e
Ne", :3,4,11,12,13,14
transferred into the first stage and shifted at 18 V and 25 0 C
one stage at each positive-going clock transi- FUNCTIONAL DIAGRAM
• Noise margin (over full package·temperature
tion. Maximum clock frequencies up to range)
12 Megahertz (typical) can be obtained. Be- 1 Vat VDD = 5 V
cause fully static operation is allowed, infor·
mation can be permanently stored with the
clock line in either the low or high state. The
2 VatVDD = 10 V
2.5 VatVDD = 15 V INPUT CONTROL CIRCUIT TRUTH TABLE
BIT INTO
I
• 5·V, 10-V, and 15-V parametric ratings DATA RECIRC. MODE
CD4031B has a MODE CONTROL input STAGE I
• Meets all requirements of JEDEC Tenta-
that, when in the high state, allows operation
tive Standard No. 13A, "Standard Specifi- 1 X 0 1
in the recirculating mode. The MODE CON- cations for Description of 'B' Series CMOS
TROL input can also be used to select be- 0 X 0 0
Devices"
tween two separate data sources. Register X 1 1 1
packages can be cascaded and the clock Applications:
X 0 1 0
lines driven directly for high·speed qperation. • Serial shift registers
Alternatively, a delayed clock output (CLD) • Time delay circuits
is provided that enables cascading register TYPICAL STAGE TRUTH TABLE
packages while allowing reduced clock drive
Dau CL Data + 1
fan-out and transition·time requirements. A
third cascading option makes use of the 0' 0 J 0
output from the 112 stage, which is available
on the next negative-going transition of the
1 ..r 1
clock after the 0 output occurs. This delayed

output, like the delayed clock CLD, is used
conditions should be selected so that
operation is alwavs within the following ranges:
X
"- NC
with clocks having slow rise and fall times. LIMITS TRUTH TABLE FOR OUTPUT FROM Q'
(TERMINAL 5)
CHARACTERISTIC Min. Max. UNITS
The CD4031 B types-are slJPplied in 16-lead
Supply· Voltage Range Data + 64 CL Data + 64Y2
hermetic dual-in-line ceram1c packages (0
(For T A=Full Package- 3 18 V
and F suffixes). 16-lead plastic dual-in-line
Temperature Range) 0 \... 0

1 \... 1
suffix). X J NC
1 = HIGH LEVEL 0= LOW LEVEL

DC SUPPLY-VOLTAGE RANGE, (VDD) X = ~ON'T CARE NC = NO CHANGE
(Voltages referenced to VSSTerminal) ,.,,,,,,,,,,,,.,,,,.,,,,,.,,, ... ,.,,,,,,,,,,, -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS."""""."" .. " " .... "".".", .. , -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT,,,,,,,,,,,,,,,,.,,,,,,,,,,.,,,,,,,,,,,,,,,,,,,, .. ±10 mA
I.
RECIRCU-
For TA = -40 to +60°C (PACKAGE TYPE E) """,,,,,,,,,,,,,,.,,,,,,,,,,,,,,,,,,,,,,,, 500 mW LATE
OATAIN2 VOO
For TA = +60 to +85°C (PACKAGE TYPE E) ",.",.""", Derate Linearly at 12 mwrc to 200 mW CL IN 15 DATA IN I
For TA = -55 to +100°C (PACKAGE TYPES D, F, K) .,.".,."",,,,,,,,,,,,,,, .. ,,,,,,,,, 500 mW NC { "
13
For TA = +100 to +125°C (PACKAGE TYPES D, F, K) ""'" Derate Linearly at 12 mwrc to 200 mW 0' 12 tNC
DEVICE DISSIPATION PER OUTPUT TRANSISTOR Q
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ,.",."" ... , ... , 100 mW 0 10 MOUE CONTROL
OPERATING-TEMPERATURE RANGE (T A): VS5 9 CLo
PACKAGE TYPES D, F, K, H "',."""',.,."." ... " ... ""'''''''".",, .... ,, -55 to +125°C TOP VIEW
PACKAGE TYPE E ,,,,,,,,,,,,,,,,,,,.,,,,, ",,,.,,,,,,,.,,,,,,,,,,,,,,, "",,,,. -40 to +85°C NC~ NO CONNECTION
nCS-29065RI
STORAGE TEMPERATURE RANGE (T stg) " " " " . " " .. "",,,,,,,,,, .. ,,,,.,,.,, -65 to +150° C
LEAD TEMPERATURE (DURING SOLDERING): TERMINAL ASSIGNMENT
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 5 max. " " .. ".""",,,,, .. +265°C
149
CD4031 B Types

Values at -55, +25, +125 Apply to 0, F, K, H Packages
CONDITIONS Values at -40, +25, +85, Apply to E Package UNITS
CHARACTERISTIC +25
Vo VIN VDD
(V) (V) (V) >-li5 -40 +85 +125 Min. Typ. Max.
Ouiescent Device - '0,5 5 '5 5 150 15t! - 0.04 5
Current, - 0,10 10 TO 10 300 300 - 0.04 10 fJA
100 Max. 0,15 15 20 20 600 600 - 0.04 20
_. 0.20 20 100 100 3000 3000 - 0.08 100
Output Low (Sink) 0.4 0.5 5 2.56 2.44 1.68 1.44 2.04 4 -
Current IOL Min. 0,10 10 4.4 5.2 -
0.5 6.4 6 3.6 10.4
Q
1.5 0,15 15 16.8 16 11.2 9.6 13.6 27.2 - DRA,IN-lO-SOURCE VOLTAGE IVos)-V
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - Fig, 2 - Typical output low (sink)
Q, Q', CLD 0.5 0,10 10 1.6 ·1.5 1.1 0.9 1.3 2.6 - current characteristics (0 sink
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 mA current = 4X ordinate).
Output High (Source) 4.6 a,s 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 -
Cur,.!:.nt, IOH Min. 2.5 0,5 5 2 ··1.8 -1.3 -1.15 -1.6 -3.2 -
Q, Q, Q', CLD
9.5 0,10 10 ·1.6 -1.5 -1,1 -0.9 -1.3 -2.6 -
13.5 0,15 15 4.2 4 -2.8 -2.4 -3.4 -6.8 -
Ou tpu t Vol tage: - 0,5 5 0.05 - a 0.05
Low·Level, 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05 V
Output Voltage: a,s 5 4.95 4.95 5 -
High·Level, 0,10 10 9.95 9.95 10
VOH Min. 0,15 15 14.95 14.95 15
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 .- 15 4 - - 4 V DRAIN-lO-SOURCE VOLTAGE IVDS)-V
Input High 0.5,4.5 .-
5 3.5 3.5 - -
Voltage. 1,9 10 7 7 - - Fig. 3 - Minimum output low (sinkl
VIH Min. 1.5,13.5 - 15 11 11 -- - current characteristics (Q sink
Input Current current := 4X ordinate).
liN Max. 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 fJA DRAIN-TO-SOURCE VOLTAGE (Vosl-V
Fig, 4 - Typical output high (.<ource)

DRAIN-TO-SOURCE VOLTAGE tVosl-V
-15 -10 -5
~
AMBIENT TEMPERATURE CTA)-25·C
2 CL
CLOCK GATE-TO-SOURCE VOLTAGEt\': 1--5V
9 CLD
EL
1£ --
00
V55
* PROTECTED
ALL. INPUTS ARE
BY
COS/MOS PROTECTION
NETWORK
·d,. ••'-15J!V
C1 , .
...iF'., mill
-IOV
: t
CL

Fig, 5 - Minimum output high (sourcel
150
CD4031 B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 2SOC'lnput tr,t,= 20 ns,

CL =50pF, RL =200kfl.
Clock to 0: tpH l' tplH; 10 - 110 220 ns
Clock to Q, tpLH 15 - 90 180
Clock to Q', tpHl, tPlH;
5 - 190 380
Clock to Q, tpHl
10 - 80 160 ns
15 - 65 130
40 60 8 100
5 - 100 200 LOAD CAPACITANCE ICL l-pF 92CS'302~4
Clock to ClD 10 - 50 100 ns Fig. 6 - Typical propagation delay time as a function

15 - 40 80 of load capacitance Isee table).
Transition Time, tTHl' tTlH

5 - 100 200
(Any Output, except Q, tTH l)
10 - 50 100 ns
Q, tTHl
15
5
10
-
-
-
40
50
25
80
100
50 ns
I
15 - 20 40
5 - 30 60
Minimum Data Setup Time. ts 10 - 15 30 ns
15 - 10 20
5 - 30 60
Minimum Data Hold Time, tH 10 - 15 30 ns
15 - 10 20
5 - 120 240
Minimum Clock Pulse Width, tw 10 - 50 100 ns LOAD CAPACITANCE ICU-pF 92CS- 302':15
15 - 40 80 Fig. 7 - Typical propagation delay time as a function

of load capacitance Isee table).
tCl
..
Maximum Clock Input Frequency.
5
10
15
2
5
6
4
10
12
-
-
-
MHz
trCl. ttCl
.
Clock Input Rise or Fall Time,
5
10
15
-
-
-
-
-
-
1000
1000
200
J.I.S
Input Capacitance. CIN

(Any Input)
- - 5 7.5 pF
*If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or
equal to the sum of the propagation delay at 50 pF and the transition time of the output driving stage.
**Maximum Clock Frequency for Cascaded Units;
a) Using Delayed Clock Feature in Recirculation Mode:
1
f x= where n = number of packages
ma (n.ll C LO prop. delay + Q prop. delay + set·up time
bl Not Using Delayed Clock:
92CS-24'22
1 Fig. 8 - Typical transition time as B function of
'max; propagation delay + set·up tim. load capacitance (except 0, tTHL)'
151
CD4031 B Types
:
4
AM81~I'tT TEM ERAT RE
ITAI- 2S-C--ttttt;~
VDD
• ,~
,'/
J:>i,IOKa
,~'k~
I • ~~ ,0 ~
,f 4 ~¥ ~;p
~ h~~
.
2
~q.¢
Z
/
~ ''Ii
f 4'
~
4
2 II
_ _ _ CL-I!5pF
i l
:
4
. CL-!50pF
LOAD CAPACITANCE ICLI-pf"

10
2
2 "ea
10
, ... , ...
100 IK
II
10K
CLOCK INPUT FREQUENCY (fell-kHz
2
1111 I
• GG 2 ...
92CS.30Z,.,IU
Fig. 9 - Typical transition time 8S a function of Fig. 10 - Typical dynamic power dissipation as a -=- vss
fCL
NOTE; P.G.I" fel; P.G.2· 4
load capacitance (0, tTHLI. function of clock input frequency.
VDD
VDD
! INPUTS r--~-'
CLOCK DRIVER
___ • _ _ _ _ •• _ _ _._ _ _ _ _ _ _ _ _ _ _ _.....J
MODE CONTROL Voo' RECIRCULATION

92C5-29063
GNO' NEW OATA
V55
Fig. 12 - Cascading using direct clocking for high·speed oparation
(see clock rise and fall time requirement). Fig. 13 - Ouiescent-device·
Yoo ,NPUDS
VDO NOTE'
~~
1
MEASURE INPUTS
o ~ SEQUENTIALLY,
eLOCI< Vss TO BOTH Yoo AND Vss'
DRIVER CONNECT ALL UNUSED
INPUTS TO EITHER
DELAYED YDO OR Vss'
CLOCt<
TO CLOCK * FOR RECIRCULATION MODE ONLY MODE CONTROL: VOO"RECIRCULATION VSS
NEW DATA FF TO DELAY DATA UNTIL GNO ~ NEW OATA
INTO FIRST FIRST REGISTER DELAYED CLOCKING 92CS·ZT40Z
REGISTER
HAS OCCURRED.
9ZCS-29062R!
Fig. 75 - Input·leakage current.

Fig. 14 - Cascading using delayed clocking for reduced clock drive requirements.
VDD
! Q'
'NPUTQVDD
OUTPUTS
V,H
'-- ~
Y~ ~
MODE CONTROL Voo· RECIRCULATION
9ZCS-29064
GND· NEW OATA VSS NOTTE~sr ANY
9ZCS-Zl'44UU COMBINATION
OF INPUTS
Fig. 16 - Cascading using half-clock-pulse delayed data output (0'1 to permit

use of slow rise and fall time clock input<. Fig. t7 - Input·voltage test circuit.
152
CD4031 B Types
I
136 -144
(3.454 -3.658) 92CM- 30259RI
Dimensions and pad layout for CD40378.

D,menSIons m parentheses are in millimeters and The photographs and dimensions 01 each CMOS Chip
are derived from the basic Inch d,mensions as in- represent a chip when it is part of the wafer. When the
dicated. Grid graduations .ue II) mds fla- 3 inch), wafer is separated into individual chips, the angle of
cleavage may vary with respect to the Chip laCB for
chip. therefore, may dlfle' slightly from the nominal
dimensions shown. The user should consider B tolerance
dimensions shown.
153
CMOS
.,
'I-"'-_-r---,
Triple Serial Adders INVERT I

SUM 2
Positive Logic Adder - CD4032B • I nvert inputs on all adders for sum complementing
applications
Negative Logic Adder - CD4038B • Fully static operation. • _ _ dc to 10 MHz (typ_)
@VDD=10V
• Single-phase clocking
The'RCA-CD4032B and CD4038B types
consist of three serial adder circuits with • Standardized, symmetrical output characteristics
"SS"e
common CLOCK and CARRY-RESET in- • 100% tested for quiescent current at 20 V "co '16
puts. Each adder has provisions for two • 5-V, 10-V, and 15-V parametric ratings
92CS-I'I'66:5
serial DATA INPUT signals and an IN- CD4032B, CD4038B

• Maximum input current of lilA at 18 V
VERT command signal. When the com- FUNCTIONAL DIAGRAM
over full package-temperature range;
mand signal is a logical "1", the sum is
100 nA at 18 V and 25°C
complemented. Data words enter the adder
with the least significant bit first; the sign • Noise margin (over full package-tempera-
bit trails. The output is the MOD 2 sum of ture range I
the input bits plus the carry from the pre- 1 Vat VDD = 5 V
vious bit position. The carry is only added Applications:
2 V at VDD = 10 V
at the positive-going ciock transition for the • Serial arithmetic units
2_5 V at VDD = 15 V • Digital correlators
CD4032B or at the negative-going ciock for
the 'CD4038B, thus. for spike-free operation • Meets all requirements of JEDEC Tentative • Digital datalink computers
the input data transitions should occur as Standard No. 13A, "Standard Specifications • Flight control computers
soon as possible after the triggering edge_ for Description of 'B' Series CMOS Devices" • Digital servo control systems
The CARRY is reset to a logical "0" at the
end of each word by applying a logical "1"
signal 'to a CARRY-RESET input one-bit-
position before the application of the first
bit of the next word.
The CD4032'B and CD4038B types are sup- DC SUPPLY -VOLTAGE RANGE. (VDD)
plied in l6-lead hermetic dual-in-line ceramic (VoHages referenced 10 VSS Terminal) _. __ ... _. _. _______ . ___ .. _. _... _. _. _..... _.. _. -0.510 +20 V
packages(D and Fsuffixes). l6-lead dual-in- INPUT VOLTAGE RANGE. ALL INPUTS __ ..... _. _____ . ___ . _.... ___ ... _. ___ ..... -0.5 10 VDD +0.5 V
line plastic packages (E suffix). l6-lead DC INPUT CURRENT. ANYONE INPUT __ ._._. _. _._._ ... _. _....... _... _. ____ .. __ ... _._. _. _ ±10mA
ceramic flat packages (K suffix). and in chip POWER DISSIPATION PER PACKAGE (PO):
form (H suffix). ForTA = -40 to +6O"C (PACKAGE TYPE E) .. _____ ._. _. ____ . _. _._. _. _._ .. _____ . _. _. ___ .. 500 mW
For TA = +60 10 +85·C (PACKAGE TYPE E) _....... _. __ ... Derale Linearly at 12 mWI"C 10 200 mW
ForTA = -5510 +l00·C (PACKAGE TYPES O. F. K) ._. _. _........ _. _...... _. ___ .. __ ._ ._ .. 500 mW
ForTA = +10010 +125·C (PACKAGE TYPES D. F. K) __ ._ ... Derale Linearly al12 mWI"Clo 200mW
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types). _. _._. __ ... _..... 100 mW
OPERATING-TEMPERATURE RANGE (TA): ,
PACKAGE TYPES D. F. K. H _. _..... _........ _._ ....... __ ......... _... _. _... _" __ -5510 +125·C
PACKAGE TYPE E _._ ......... __ ._ ... _. _._. _. _____ .. _... ___ . __ .... __ . _. _.... _... _ -4010 +8S·C
STORAGE TEMPERATURE RANGE (TsIg) . _. _._ ........ __ . _.. _..... _. _. _. __ . __ .. __ -8510 +150·C
CD4032B, CD4038B AI distance 1/16± 1/32 inch (1.59± 0.79 mm) 'rom case for lOs max_ ._. _... ___ ... __ ... ___ . +285·C
TERMINAL DIAGRAM
SUM 3 16 voo
INVERT 3 15 .3
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Unless Otherwise Specified
CLOCK B3 For maximum reliability, nominal operating conditions should be selected so that operation
5UM2 "13 .2
lNVERT2 12 B2
is always within the following ranges_
r:ARRY RESET
INVERT I "
10 .,
BI
CHARACTERISTIC VOD Min_ Max_ UNITS
VSS SUM I
Supply Voltage Range (at T A - Full Package-Temperature
TOP VIEW
92CS_24474RI
Range) 3 18 V
5 - 2.5
Clock Input Frequency. fCl 10 - 5 MHz
15 - 7.5
5 - 500
Clock I nput Rise or Fall Time, trCl. tfCl 10 - 500 IlS
15 - 500
Data Input Set-Up Time,

5 200 -
Clock to A or B Inputs tsu 10 80 - ns
15 60
154
LIMITS AT INDICATED TEMPERATURES (oC) u
N
CHARAC· CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H, Packages I
+25 S
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
- 0,5 5 5 5 150 150 - 0.04 5
Quiescent
Device - 0,10 10 10 10 300 300 - 0.04 10 p.A
Current, - 0,15 15 20 20 600 600 - 0.04 20
IDD Max.
- 0,20 20 100 100 3000 3000 - 0.08 100
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -

Output Low
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
Output High
4.6 0,5 5 -0.64 -0.61 ·-0.42 -0.36 -0.51 -1 - mJl
(Source)
Current,
IOH Min.
2.5
9.5
0,5
0,10 10
5 -2
-1.6
-1.8
-1.5
-4
-1.3 ':"'1.15
-1.1
-2.8
-0.9
-1.6
-1.3
-3.2
-2.6
-
-
-
I
13.5 0,15 15 -4.2 -·2.4 -3.4 -6.8
Output Voltage: - 0,5 5 0.05 - 0 0.05

Low·Level, - 0,10 10 0.05 - 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05 V
Output - 0,5 5 4.95 4.95 5 -
Voltage: - 0,10 10 9.95 9.95 10 -
High·Level,
VOH Min. - 0,15 15 14.95 14.95 15 -
0.5,4.5 - 5 1.5 - - 1.5
Input Low
Voltage 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 - 15 4 - - 4 V
Input High 0.5,4.5 - 5 3.5 3.5 - -

Voltage, 1,9 - 10 7 7 - -
VIH Min. -
1.5,13.5 - 15 11 11 -
Input Current ±10- 5 ±0.1 p.A
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 -
- WORD I+WO~D2 WORD 3+WORO 4-
g_ _
CL
INVERT
CARRY
-l-+-+-+--+-+-.f..-f-I-tiIIIIH
RESET
SUM
] ~~DERS
- - TRUE SUM - - COMPLEMENTED SUM
Voo WORD I 0.011 LIDO" +60 WORD 3 1.10110 II. -31

WORO 2 0.0'10010" +50 WORO 4 1.1001110--50
*
CLOCK ;;.3_ _ _ _-1 >-____-+-_ 2 a3 0.1101110 . . no 1.0101001 "-87
Fig.2 - CD40328 timing diagram.

VSS
* BY
COS/MOS PROTECTION
NETWORK
92CM-29082R2
Fig. 1 - CD4032B logic diagram of one of three serial adders.
155
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input tr , tf = 20 ns,
CL =50pF, RL =200kn

':m~t~
Propagation Delay Time: tpHL. tpLH 5 - 260 520 lt1t:7:-c
A,B, Carry Reset, or Invert Inputs to 10 - 120 240 ns ·"0\1" -
Sum Outputs 15 - 90 180

5 - 325 650
'V
Clock Input to Sum Outputs 10 - 175 350 ns
15 - 150 300 10 15
ORAtN-10-S0URCE VOLTAGE (Vest-V
5 - 100 200
Transition Time: tTHL, tTLH 10 - 50 100 ns characteristics.
15 - 40 80
Minimum Data Input Setup Time, tsu
5 - 125 200
-
Clock to A or B Inputs
10
15 -
50 80
40 60
ns
·•
I
~1'5
5 2.5 4.5 -
Maximum Clock Input Frequency, fCL 10 5 10 - MHz i 12,5
GATE-TO-SOURCE VOLTAGE {VGS,-I!lV
15 7.5 15 - a 10
~
5 - - 500 IOV
·
1.'
Clock Input Risear Fall Time, trCL,tfCL * 10 - - 500 f.ls g ,
15 - 500
·
-
§ 25 5V
Input Capacitance, CIN (Any Input) - 5 7.5 pF
'5 10 15
* If more than one unitis cascaded trCL should be made less than or equal to the sum of the transition time CRAIN-TO-SOURCE VOLTAGE (Vosl-V
and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
Fig. 6 - Minimum output low {sink} current
characteristics.
'* 10'- - - - - AoI5"E'RI------------------------·! DRAIN-TO-SOURCE VOLTAGE IVosl-V
AI -~SUM' -15
AMBIENT TEMPERATURE (TAI=25-C
-10 -5
I'
*61 111 - !
I I
: I
I
I
* I ~--.::===+=1=='j
INVERTI~_=_==_~-_.:_===
CARR~.§.~~_4l
RESET ~ c!-~j-
ho
'ADOERS
ROD
>-r"" ~~>-----t-- J2 a,
* BY
4ss
COS/MOS PROTECTION
characteristics.
NETWORK
92CM-29083RI DRAIN-TO-SOURCE VOlTAGE (Vasl-V
Fig. 3 - CD40388 logic diagram of one of three serial adders. -1'5
AMBIENT TEMPERATURE (TA,,-2S·C
-10 -,
GATE -TO- SOURCE VOL~GE (~Sl. -5 V
-- WOAD :+WORD2 -._. -WORD 3+WORD 4--"
CL -IOV
INVERT
CARRY
-tttttttl~l=l=l=l=i=i=t_i=
RESET t
SUM "-1'5 V
~ TRUE S U M - - - COMPLEMENTED SUM- fHilI

WORD I 1.1000011 --61
WORD Z 1.100 II 01 =-51
1.0010000 a-112
WORD 3 0.0100100 =+36
WORD 4 0.0110001 -+49
0.1010101 -+85
IIi mil!
Fig.4 - CD40388 timing diagram. characteristics.
156
AMBIENT TEMPERATURE ITA) - 25·C
10V
I5V
20 40 60
LOAD CAPACITA~CE (CLJ-pF 10 2 46~022 103 Z 68,04 Z 4158 ,05
CLOCK I~PUT FREQUENCY "CL)- kHz .2CS-30541
Fig. 11 - Typical dynamic power dissipation as a
Fig. 9 - Typical transition time as a function of Fig. 10 - Tvpical propagation delay times as a
function of clock input frequency.
load capacitance. function of load capacitance (A, 8,
carry reset or invert to SUM).
I
16
15
PUL.SE
GEN. I INPUTQVOOOUTPUTS
'L "
12 V,H
II
10
~ ~
'L v~ ~
NOTE.
=Yss Yss TEST ANY COMBINATION
OF INPUTS
P.G I- fel
9ZCS-21441RI
PG.2- fiL.
Fig. 12 - Dynamic power dissipation test Fig. 13 - Input voltage test circuit. Fig. 14 - Input current test circuit.
circuit.
Voo
INPUTS
o
Vss
Vss
9iCS 2740Hfl
Fig. 15 - Quiescent·device current test circuit.

are derived from the basic inch dimensions as in·
dicated. Grid graduations are in mils (Hr 3 inch).
The photographs and dimenSIons of each CMOS chip
repressnt a chip when it ;s part of the wafer. When Ihe
waler is seperated into individual chips, the angle of
of -3 mils 10 +16 mils applicable to the nominal Dimensions and pad layout for CD4032BH,' dimensions and pad layout for
dimensions shown. CD40388H are identical.
157
CD4034B Types
CMOS a-Stage Static
.Bidirectional Parallel/Serial
Input/Output Bus Register
51-------,
AE
High-Voltage Types '20-Volt Ratlng) AI.
AIS
PIS
CL-L_ _--'
The RCA-CD4034B is a static eight-stage Applications:

parallel-or serial-input parallel-output regis-
• Parallel Input/Parallel Output,
ter. It can be used to: Parallel Input/Serial Output,
Serial Input/Parallel Output,
1) bidirectionally transfer parallel informa:
Serial Input/Serial Output Register
tion between two buses, 2) conven serial
• Shift right/shift left register
data to parallel form and direct the parallel
• Shift right/shift left with parallel loading
data to either of two buses, 3) store (recircu-
• Address register
late) parallel data, or 4) accept parallel data
• Buffer register 92CS~2910B
from either of two buses and convert that Functional Diagram
• Bus system register with enable parallel
data to serial form. Inputs that control the
Iines at bus side
operations include a single-phase CLOCK
• Double bus register system
(Cl), A DATA ENABLE (AE), ASYNCHRO-
NOUS/SYNCHRONOUS (A/S), A-BUSTO-
• Up-Down Johnson or ring counter Features:
• Pseudo-random code generators • Bidirectional parallel data input
B-BUS/B-BUS-TOABUS (A/B), and PAR-
• Sample and hold register (storage, • Parallel or serial inputs/parallel outputs
ALLEL/SERIAL (P/S).
counting, display)
• Asynchronous or synchronous parallel
Data inputs include 16 bidirectional parallel • Frequency and phase comparator data loading
data lines of which the eight A data lines are • Parallel data-input enable on "A" data
inputs (3-state outputs) and the B data lines SERIAL OPERATION lines (3-state output)
are outputs (inputs) depending on the signal A low PIS signal allows serial data to transfer • Data recirculation for register expansion
level on the A/B input. I n addition, an input into the register synchronously with the • Multipackage register expansion
for SERIAL DATA is also provided. positive transition of the clock. The A/S in- • Fully static operation dc-to-l0 MHz (typ.)
All register stages are D-type master-slave put is internally disabled when the register is at VDD = 10 V
flip-flops with separate master and slave in the serial mode (asynchronous serial opera- • Standardized, symmetrical output
tion is not allowed). characteristics
clock inputs generated internally to allow
synchronous or asynchronous data transfer The serial data appears as output data on • 5-V, 10-V, and 15-V parametric ratings
from master to slave. Isolation from external either the B lines (when A/B is high) or the
noise and the effects of loading is provided • Maximum input current of lilA at 18 V
A lines (when A/B is low and the AE signal over full package-temperature range;
by output buffering. 100 nA at 18 V and 25 0 C
is high).
PARAllEL OPERATION • Noise margin (over full package-temperature
Register expansion can be accomplished by
range):
A high PIS input signal allows data transfer simply cascading CD4034B packages.
1 Vat VDD =5 V
into the register via the parallel data lines The CD4034B types are supplied in 24-lead 2 Vat VDD = 10 V
synchronously with the positive transition dual-in-line ceramic packages (0 and F suf- 2.5 Vat VDD = 15 V
of the clock provided the A/S input is low. fixes), 24-lead dual-in-line plastiC packages • Meets all requirements of JEDEC Tentative
If the A/S input is high the transfer is in- (E suffix), 24-lead ceramic flat packages (K Standard No. 13A, "Standard Specifications
dependent of the clock. The direction of
suffix), and in chip form (H suffix). for Description of 'B' Series CIVIOS Devices"
data flow is ,controlled by the A/B input.
When this signal is high the A data lines are MAXIMUM RATINGS, Absolute-Maximum Values:
inputs (and B data lines are outputs); lowa DC SUPPLY -VOLTAGE RANGE, (VDD)
A/B signal reverses the direction of data flow. (Voltages referenced to VSS Terminal) ............................................. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................ -0.5 to VDD +0.5 Y
The AE input is an additional feature which DC INPUT CURRENT, ANY ONE INPUT .................................................. ±10 mA
allows many registers to feed data to a POWER DISSIPATION PER PACKAGE (PD):
common bus. The A DATA lines are enabled For TA = -40 to +60'C (PACKAGE TYPE E) ............................................. 500 mW
ForTA = +60 to +85'C (PACKAGE TYPE E) ............... Derate Linearly at 12 mWrCto 200 mW
only when this signal is high.
For TA = -55 to +100' C (PACKAGE TYPES D. F, K) ...................................... 500 mW
Data storage through recirculation of data in For TA = +100 to +125'C (PACKAGE TYPES D, F, K) ....... Derate, Linearly at 12 mwrc to 200 mW
each register stage is accomplished by mak-
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................. 100 mW
ing the A/B signal high and the AE signal OPERATING-TEMPERATURE RANGE (TA):
low. PACKAGE TYPES D, F. K. H ..................................................... -55 to +125'C
PACKAGE TYPE E ............................................................... -40 to +85'C
STORAGE TEMPERATURE RANGE (Tstg) ......................................... -65 to +150'C
At distance 1/16± 1/32 inch (1.59± 0.79 mm) from case for 10s max....................... +265'C
158
CD4034B Types
RECOMMENDED OPERATING CONDITIONS at T A =25 0 C, Except as Noted. 'A" OR"S"
DATA
For maximum reliability, nominal operating conditions should be selected so that INPUTS

"S"OR"A" ITLH ~:~_90%LDO
VDD LIMITS DATA ________ ----50%
CHARACTERISTIC UNITS *t
.:O:::UT:.;,'.:.UT:':'_-f_ _ ____ 10%0
(V) Min. Max.
Supply·Voltage Range (For T A = Full Package-
Data Setup Time, ts 5 160 -

Fig. 2 - Asynchronous operation propagation
Serial Data to Clock 10 60 - ns
delay time and transition time.
15 40 -
5 50 -
Parallel Data to Clock 10 30 - ns
15 20 - ,Veo
----=-90%
- - _ _ _ 50%
5 350 - -----10% 0
15 80 -
I
5 2
Clock Input Frequency, fCl 10 dc 5 MHz
15 7 OUTPUT
.
Clock Input Rise or Fall Time, trCl, tf Cl ' 5.10.15 - 15
If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time
Ils
* INPUT REFERS TO ANY OF THE "A" OR "B" DATA INPUTS, "~'ENABLE,

and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. SERIAL INPUT, AlB, PIS. OR AlS INPUTS
**tSLH AND 'SHL ARE SET-UP TIMES
Fig. 3 - Synchronous operation propagation

delay times, transition times, and
set-up times_
ROD
*
Ys.
INPUTS PROTECTED BY
ClOCK~
ENA~lE~
COS/MOS PROTECTION
NETWORk '" n...n
AlB 1- =======::::::=:,-- ~
'" n'--__---Jn'--_ _ _ _ _ _-'r--

St:.:t L
9.::CS·':9!09RI
~
Fig. 1 - Steering logic diagram_ "~
.en Il.SL
FLIP-FLOP TRUTH TABLE "~
A41l Il.SL
INPUTS OUTPI,JT ,,~
D Q AS!! Il.SL
elM Cls ,,~
"n'--____________________
'-
.F
\.... 0 0 ~1l.SL
'- 0
INVALID
0
'- J 0
x
CONDITION
.. rl-------c______________..Jr--unL
.F J 0 ".~
"I r-vLJ
'- '- 1 1 ,,~
. ~
.J '- 1 1
_ I_ _ B DATA LINES ARE OUTPUTS ~lI~f:l~E-'
INVALID OUTPUTS
'- 1 = High Level

J
0= Low Level
1 r.ONDITION
x = Don't Care
Fjg. 4 - Timjng djagram.
159
CD4034B Types
AMBIENT TEMPERATURE (TA)·25°C
LIMITS AT INDICATED TEMPERATURES (OCI IU
N
CHARAC- CONDITIONS Values at -55, +25, +125Applyto D, F, K, H Packages I
TERISTIC Values at -40, +25, +115 Apply to E Package T GATE-lO-SOURCE VOLTAGE (VGsl'15 V
~
z
+25 S ~ 25
Vo VIN VDD
(VI (VI (VI -55 -40 +85 +125 Min. Typ. Max. ~ 20
- 0,5 5 5 5 150 150 - 0.04 5

Ouiescent
- 10 300 300 - 0.04 10
3"
Device 0,10 10 10 J.l.A ~ 10
Current, - 0,15 15 20 20 600 600 - 0.04 20 5 5

IDD Max.
- 0,20 20 100 100 3000 3000 - 0.08 100
5 10 15
DRAIN-lO-SOURCE VOLTAGE (VosJ-V
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Output Low Fig. 5 - Typical output low (sink)
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - current characteristics.
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mJl

Output High
(Sourcel 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0.10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - GATE-lO-SOURCE VOLTAGE (VGS1~15V
~ 12.5
IOH Min.
13.5 0.15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - G 10
0.05 ~
- 0,5 5 0.05 - 0 <Ii 7.5
·IOV
Output Voltage:
Low-Level, - 0,10 10 0.05 - 0 0.05 •3 5
VOL Max. - 0,15 15 0.05 - 0 0.05 "g2_5
.- f - - V 5V
Output - 0,5 5 4.95 4.95 5 -

5 10 15
Voltage: - 0,10 10 9.95 9_95 10 -
DRAIN-TO-SOURCE VOLTAGE (VDS)-V
High-Level, Fig. 6 - Minimum output low (sink)

VOH Min. - 0,15 15 14.95 14_95 15 -
0.5,4.5 - 5 1.5 - - 1.5 DRAIN-TO-SOURCE VOLTAGE (Vos)-V
Input Low -15 -10 -5
Voltage 1,9 - 10 3 - - 3 AMBIENT TEMPERATURE (TAl'25"C
VILMax. ~~EI_T~-SOJRCE VOLTAGE (VGSl'-5V

1.5,13.5 - 15 4 - - 4 V
0.5,4.5 - 5 3.5 3.5 - -
Input High
Voltage, 1,9 - 10 7 7 - - -15
VIHMin.
1.5,13.5 - 15 11 11 - - -IOV -20
~25
In put Current'
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 J.l.A
liN Max. -'0
3-State
Output
Leakage 0,18 0,18 18 ±O.4 ±0.4 ±12 ±12 - ±10-4 ±0.4 J.l.A
Current Fig. 7 - Typical output high (source)
lOUT Max. current characteristics.
* All inputs except A and B Lines.

I ~ ~ro AMBIENT TEMPERATURE T~ -25'C

-15 -10 -5
AMBIENT TEMPERATURE (TA)~25·C
1±±:I±±±l±H-ttttt-tttt
GATE-lO-SOURCE VOLTAGE (Ves)' -5 v
-IOV
-~
I5V
'-15 V
20 30 40 50 60 70 80 90
lOAO CAPAClTA~CE (Cll - pF 92CS.~OI52

function of load capacitance [A(B)
parallel Data Input to B(A) parallel
Fig. 8 - Minimum output high (source) Fig. 9 - Typical transition time as a function Data Output, synchronous or
current characteristics. of load capacitance. asynchronous}.
160
CD4034B Types
ONE OF EIGHT SlAGES

I----~-------------------
I A,
I ~--__~l___________
I
I K 0'
I
I
I
FiOD
Y . as a function af clack frequency.
PROTECTION NETWORK
ON SERIAL DATA INPUT
II Voo
II
92CM-Z9110RZ
Fig. 11 - Register stage logic diagram 11 of 8 s,tages). I.

fCL
10
.-
fCL
13
I. 12
TRUTH TABLE FOR REGISTER INPUT·LEVELS AND

RESULTING REGISTER OPERATION
-=-Vss
92CS-301!54
"A"
Enable PIS AlB AIS Operation' Fig. 13 - Dynamic power dissipation
test circuit.
0 0 Serial Mode; Synch. Serial Data Input, "A" Parallel Data Outputs
0 X
Disabled
0 0 1 X Serial Mode; Synch. Serial Data Inp~t, "8" Parallel Data Output
Parallel Mode; "8" Synch. Parallel Data Inputs. "A" Parallel Data
0 1 0 0
Outputs Disabled INPUTS
o
Parallel Mode; "8" Asynch. Parallel Data Inputs, "A" Parallel Datd Vss
0 1 0 1 Outputs Disabled
0 Parallel Mode; "A" Parallel Data Inputs Disabled, "8" Parallel Data
1 1 0
Outputs, Synch. Data Recirculation
Parallel Mode; "A" Parallel Data Inputs Disabled, "8" Parallel Data
0 1 1 1
Outputs, Asynch. Data Recirculation
1 0 0 X Serial Mode; Synch. Serial Data Input, "A" Parallel Data Output
1 0 1 X Serial Mode; Synch. Serial Data Input, "8" Parallel Data Output
Fig. 14- Ouiescent·device·current test circuit.
Parallel Mode; "8" Synch. Parallel Data Input, "A" Parallel Data
1 1 0 0
Output
Parallel Mode; "8" Asynch. Parallel Data Input, "A" Parallel Data
1 1 0 1
Output
Parallel Mode; "A" Synch. Parallel Data Input, "8" Parallel Data
1 1 1 0 Voo Voo S NOTE'
1NPUO
Output
1 1 1 1
Parallel Mode; "A" Asynch. Parallel Data Input, "8" Parallel Data ~ ~i~US~N~'~~~~~S
Output Vss TO BOTH Voo ANOVSS'
CONNECT ALL UNUSED
·Outputs ch,mge elt positive transition of clock in the serial mode and when the A/S control input 15 "low" INPUTS TO EITHER
Voo OR VSS'
in the parullL-j mode. During tri.lnsfer from parnllel to serial operation A/S should
fern;]in low in order to prevent Os transfer into Flip Flops, Vss
1 " HIGH LEVEL 0= LOW LEVEL x = DON'T CARE

Fig. 15 - Input-current test circuit.
161
CD4034B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C; Input tr,t, =20 ns,
CL =50pF,RL =200kn
LIMITS INPUTQVCO
OUTPUTS
CHARACTERISTIC
VDD
UNITS V,N
(V) Min. Typ. Max.
........... ~
Propagation Delay Time, tpHL. tpLH 5 - 350 700 V~L :t
A(B) Parallel Data In to 10 - 120 240 ns
B(A) Parallel Data Out 15 - 85 170 NOTE:
Serial to Parallel Data Out Vss 6~SYN'p't~~OMBINATION
92C5-2744IRI
3-State Propagation Delay Time. tPLZ' tpHZ' 5 - 200 400 Fig. 16 - Input·voltage test circuit.
AlB or AE to "A" OUT tpZl. tpZH 10 - 80 160 ns
15 - 60 120 Applications
5 - 100 200
Transition Time. tTHl. tTlH 10 - 50 100 ns
15 - 40 80
Minimum Data Setup Time. tsu 5 - 80 160
Serial Data to'Clock 10 - 30 60 ns
15 - 20 40
5 - 25 50
Parallel Data to Clock 10 - 15 30 ns
15 - 10 20
Minimum High·level Pulse Width. tw

5 - 175 350 Fig. 17 - 16·bit parallel in /parallel out,
AE. PIS. AIS
10 - 70 140 ns parallel inlserial out, serial in/
15 - 40 80 parallel out, serial in/serial out
register.
5 2 4 -
Maximum Clock Frequency. fCl 10 5 10 - MHz
15 7 14 -
5 - 125 250
Minimum Clock Pulse Width. tw 10 - 50 100 ns
15 - 35 70
Maximum Clock Rise or Fall Time. trCl. tfCl' 5.10.15 - - 15 IlS
Input Capacitance. (Any Input) CIN - - 5 7.5 pF
*If more than one unit is cascaded, trCL should be made less than or equal to the sum of the transition time
and the fixed propagation delay of the output of the driving stage for the estimated'capacitive load.
A/.~=±======:::::::t======:::
Fig. 18 - 16-bit serial in/gated p;!rallel out
DOUBLE - BUS SYSTEM register.
(ENABLE INPUTS ON BOTH SIDES)
,------,
I :
I
I MEMORY
UNIT
I
I
I
I
I
L_____ .-J
~-------l ,--------,
I I AE I I
I I
I
I
I PERIPHERAL Y REG
~~;l Z REG ARITHME.TlC
I
I
I
UNIT UNIT
~~~j
I I
I CD4034 CD4034 I
I
I
L ______ J L _____ .-JI
The "A" enable (AE) and AlB signals control all
combinations of transfer between the registers B(U~NL~~i~ 92CM-19197RI
and bus systems. Fig, 19 - Single· and double-bus systems.
162
CD4034B Types
SHIFT LEFT OUTPUT
"A" ~NABLE
SHIFT
LEFTI
'--" iE
PIS
~~.FT
IGHT
= "A"PARALLEL DATA-i "to"PARALLEL DATAe{
FLO 11rfrfJrfrt, I rf rf rf rf rf ~ 1, SH:iuTT::~HT

SHIFT
RIGHT
NPur
"
SI
, L SI
A'
,
REG I
CD4Q3<1
-=;:
r---"
PIS
MS
~PIS
,--. AIS
-C~!g3~
CLOCK
CL
AlB I , ...... C~/B , , SHIFT
AIS
PARAL.LEL
ENTRY * I---
* ~."
CL
Fig. 21 - N·stage shift register with fixed serial
output line.
A'
I __ A PARALLEL OATA_ 8 I __ A PARALLEL DATA __ 8

A' A' SAMPLE I HOLD
~SI ~SI
•
PIS PIS
VDO L AIS
REG. 3
CD1034
VDO--C AIS
REG. 4
CD4034
SERIAL DATA
Cl Cl
AlB 1_8 PARALLEL OATA-8 Ale 1_8 PARALLEL DATA_8 YDD
AIS
rrTTTTTT TTr TT T TT
CLOCK
- =
A "High" ("Low") on the shift Left/Shift into registers 1 and 2. Other logic schemes PIS
Right input allows serial data on the Shift may be used in place of registers 3 and 4 for TO DISPLAY ETC
Left Input (Shift Right Input) to enter the parallel loading. 92CS-19211RI
register on the positive transition of the When parallel inputs are not used Reg. 3 and
clock signal. A "high" on the "A" Enable Fig. 22 - Sample and hold register-serial/
4 and associated logic are not required. parallel in-parallel out.
Input disables the "A" parallel data lines on
Reg. 1 and 2 and enables the "A" data lines * Shift left input must be disabled during parallel
on registers 3 and 4 and allows parallel data entry.
Fig. 20 - Shift right/shift left with parallel inputs.
8 I.
.
24 a VDD
~7 2 23
:; 3 22 7 ~
I.I.
21
~ 2D 5 ::l
11
2 ~ ~
=rrJ I
I.I.
17
2.°
l;:t
I.
"A" ENABLE
SERIAL INPUT 10 CLOCK
AlB
VSS "12 13
AIS
PIS
TOP VIEW
TERMINAL DIAGRAM
107
2.718)
Dimensions in paren theses are in millimeters and
dicated. Grid graduations are in mils (10-- 3 inch).

represent a chip when It Is part of the wafer. When the
wafer is separated into individual chips. the engle 01
cleavage may vary with respect to the chip lace lor
dimensions shown.
163
CD4035B Types
Features:
CMOS 4-Stage • 4·Stage clocked shift operation PARALLEL IN
Parallel In/Parallel Out • Synchronous parallel·entry on all 4 stages

• JK inputs on first stage
:1' 10(2 J3 1214\
Shift Register • Asynchronous True/Complement control ER.

IN
f~
xL
with J-K Serial Inputs and True/ on all outputs CLKL
Complement Outputs • Static flip·flop operation; Master·slave p/sL 4-STAGE REGISTER

configuration TieL
High-Voltage Types (20-Volt Rating) • Buffered inputs and outputs RESET L
• High speed - 12 MHz (typ.) at VDD = 10 V ,
The RCA·CD4035B is a four·stage clocked
signal serial register with provision for syn·
VOO-16
\Iss =8
\ 0 1/0 1
TT
0.(02 03/03-
'3
0
Q4/ 4 1
chronous PARALLEL inputs to each stage TIC' OUT
characteristics 92CS- 290~4Rl
and· SERIAL inputs to the first stage via
JK logic. Register stages 2, 3, and 4 are • 5·V, 10-V, and 15·V parametric ratings
FUNCTIONAL DIAGRAM
coupled in a serial D flip·flop configuration • Meets all requirements of JEDEC Tentative
when the register is in the serial mode Standard No. 13A, "Standard Specifications
(PARALLEL/SERIAL control lowl. for Description of "B" Series CMOS IA.BIEN· PE."!
Parallel entry into each register stage is per· Devices"
mitted when the PARALLEL/SERIAL con·
trol is high. Applications: I-SOl
In the parallel or serial mode information is • Counters, Registers

transferred on positive clock transitions. Arithmetic·unit registers
When the TRUE/COMPLEMENT control is Shift-left - shift right registe~s
high, the true contents of the register are
available at the output terminals. When the Serial-to-parallel/parallel-to·serial
TRUE/COMPLEMENT control is low, the conversions
outputs are the complements of the data in • Sequence generation
the register. The TRUE/COMPLEMENT • Control circu its
control functions asynchronously with reo
• Code conversion
spect to the CLOCK ·signal. ORA1N-TO-SQURCE VOLTAGE (Vosl-V
JK input logic is provided on the first stage FI RST STAGE TRUTH TABLE
Fig. 1 - Typical output low Isink)
SERIAL input to minimize logic require· tn-I (INPUTS) In (OUTPUTS)
ments particularly in counting and sequence· CL J K R On-I Qn
generation applications. With JK inputs
connected together, the first stage becomes
J 0 X 0 0 0
a D flip·flop. An asynchronous common

RESET is also provided.
-' I X 0 0 I
,
C
E
The CD4035B types are supplied in 16-lead -'

F
X
I
0
0
0
0 On-I
I 0
On-l ~gg~E
~15
~ GATE-TO-SOURCE VOLTAGE (VGS)-15Y
~12.5
and F suffixes), 16-lead dual-in-line plastic ..r X , 0 , , B 10
\.. X X 0 On-I On-I ,ov
suffix). X X X I X 0
5 10 15
DRAIN-TO-SOURCE VOL.TAGE (VosJ-V
Fig. 2 - Minimum output low Isink)

DC SUPPL Y -VOLTAGE RANGE, (VDD) ,
DRAIN-TO-SOURCE VOlTAGE(Vosl-Y
(Voltages referenced to VSS Terminal) ............................................. -0.5 to +20 V

INPUT VOLTAGE RANGE, ALL INPUTS ........................................ -0.5 to VDD +0.5 V
For TA = -40·to +60'C (PACKAGE TYPE E) ............................................. 500 mW
For TA = +60 to +85'C (PACKAGE TYPE E) •.............. Derate Linearly at 12 mwrc to 200 mW
For TA = -55 to +l00'C (PACKAGE TYPES D, F. K) ...................................... 500 mW
For TA = +l00to +125'C (PACKAGE TYPES D, F, K) ••...•. Derate Linearly at 12 mwrc to 200 mW
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...•.•............ 100 mW
PACKAGE TYPES D, F, K, H ..................................................... -55 to +125'C
PACKAGE TYPE E ............................................................... -40 to +85'C
STORAGE TEMPERATURE RANGE (Tstg) ............. • . .. . . . .. . . . .. . .. • . . .. . • .... -65 to +150"C
At distance 1/16± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max....................... +265'C Fig. 3 - Typical output high Isource)
164
CD4035B Types
DRAIN~TO-SOURCE VOL.TAGE IVos)-V
-I~ -10 -~
ANBIENT TEMPERATURE tTA)'2~·C
fiDD GATE-TO-SOURCE VOL.TAGE (Y(;s'.-S II
* BY
Y ss
AL.L INPUTS ARE PROTECTED
COSINOS PROTECTION
-IOV
NETWORK
-15V

.!t
~T
I'-- rr::::=- T current characteristics.
TAUE!
COMPLEMENT
PlS_O'SEAIAl MODE
T/c-I-TRUE OUTPUTS 04/04
I
D~P~-p
L
P!
Q
Typical Stage Detail Logic
Fig. 4 - Logic diagram. Fig. 6 - Typical transition time as a function of

load capacitance.

,
VDO
(V) MIN. MAX.
Supply·Voltage Range (For T A = Full
Package·Temperature Range)
Data Setup Time, tS: 5
3
220
18
-
V
II
LOAD CAPACITANCE (CL.I- pF 92CS-30362
J/K lines 10 80 - ns
15 60 -
Fig. 7 - Typical propagation delay times as a func-
5 140 - tion of load capacitance (0 output).
Parallel·ln Lines 10 50 - ns
AMBIENT TEMPERATURE ITA)- 25-C
15 40 - LOAD CAPACITANCE (CLI- ~O pF
5 200 -
15 60 -
5 2
Clock Input Frequency, fCl 10 de 6 MHz
15 8
5 - 15
Clock Rise or Fall Time, trCl, tfCl: 10 -- 15 )1S
15 - 15
5 250 - 10
" 20
Reset Pulse Width, tw 10 110 - ns SUPPLY VOLTAGE {VOD)-V
92CS-3036'l1
15 80 - Fig. 8 - Typical maximum clock Input frequency

as a function of supply voltage.
165
CD4035B Types
LIMITS AT INDICATED TEMPERATURES rCI U
N
.. +__. -
IOE~ AMBIENT TEMPERATURE (TA I: 25°C
t ' ~ IIII t-
CHARAC· CONDITIONS ~IO~
Values aI-55, +25, +125 Apply 10 D, F, K, H, Packages I
TERISTIC ~ ! - -- I r~,~~V. I-
Values at -40, +25, +85 Apply to E Package T I 4,'V'V ~
u , -1- t-
Vo VIN VDD
+25 S ~
z
10·
•
~~i~';L VJ<,4
(VI (VI (V) -55 -40 +85 +125 Min. Typ. Max.
o , r r= ov/V =L1' r-
~ 4 -,;;-" ]ZP'
~ 2 ,,l 1/]}'
- 150
.,
0,5 5 5 5 150 - 0.04 5 Ci 10 3 1
Quiescent
~ ~ CV l5 pF
Device - 0,10 10 10 10 300 300 - 0.04 10
MA
~
t-- - ~fj' - - --- ---CL'50pf-
Current,
100 Max.
-
-
0,15
0,20
15
20 100
20 20
100
600
3000
600
3000
-
-
0.04
0.08
20
100
I<i- , 4 . .,10
CLOCK
lL
10 10
W.l-4ll
" 10
INPUT FREQUENCY (feLl-kHz
. 1
0.4 0,5 5 0.64 0,61 0.42 0.36 0.51 1 -

Output Low Fig. 9 - Typical dynamic power dissipation as a
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - function of clock input frequency.
IOl Min. 0,15 2.8 --
1.5 15 4.2 4 2.4 3.4 6.8
Voo
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mt
Output High
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 -1.6 -1.5 -1,1 -0.9 -2.6 -
10 -1.3
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
- 0,5 5 0.05 - 0 0.05

Output Voltage:
low·Level, 0,10 10 0.05 - 0 0.05
VOL Max. 0.05
0,15 15 005 0 V
Output -- 0,5 5 4.95 4.95 5
Voltage: 0,10 10 9.95 9.95 10 92C$-30365
High· level,
VOH Min. 0,15 15 14.95 14.95 15 -
0.5,4.5 5 1.5 - 1.5
Input low
Voltage 1,9 10 3 - 3
VDo
VllMax. 1.5,13.5 15 4 .. 4 V
0.5,4.5 5 3.5 3.5 - INPUTS
Input High o
Voltage, 7 7 - - V55
1,9 10
VIH Min. - ..
1.5,135 15 11 11
Input Current ±1 ±1 ±10- 5 ±0.1 MA

0,18 18 ±D.l ±0.1 -
liN Max.
100
V55
Fig. 11 - Quiescent-device current test circuit.
LEFT
SHIFT
INPUT
LEfT/RIGHT PIS
4 J
Voo RIGHT
SHIFT
INPUT 3 K
INPUTQOUTPUTS liDO 1NPOUS
Voo NOTE CLOCK CL C04035
=--
V,H
V tL
~I ~
Vss
~:;~~:;1~~~~~5
TO BOTH Voo ANO Vss
CONNECT AL.L UNUSED
TRUE/CQMPL:
RESET
2 TIC
INPUTS TO EITHER
NOTE:
Voo OR Yss
Vss ~~STNAp~~~OMBINATION
V55
92CS-I')974F11
Fig. 12 - Input-voltage test ~ircuit. Fig. 13 - Input-current test circuit. Fig. 14 - Shift left/shift right register.
166
CD4035B Types
At TA ; 25"C. Input t r • tf; 20ns. CL ; 50 pF. RL ; 200 krl.
TEST
)----~---<)P/S LIMITS
CONDITIONS
CHARACTERISTICS UNITS
VDD
(VI Min. Typ. Max.
>-+_----------0 pI-'
CLOCKED OPERATION
5 - 250 500
pI-3
tpHL' tplH
10 - 100 200 ns
15 - 75 150
>-----oPI-4 5 - 100 200

Transition Time:
10 - 50 100 ns
\Using Couleur's Technique (BIDECI.... a tTHl· tTlH
15 - 40 80
'binary number (most significant bit. MSBI
first is shifted and processed. such that the
5 - 100 200
BCD equivalent is obtained when the last
binary bit is clocked into the register. The
CD4035B. with the correct conversion
Minimum Clock Pulse Width. tw 10
15
5.10.
-
-
45
30
90
60
ns
II
logic. can also be used as a BCD·to·binary Clock Rise or Fall Time. trCL, tfCl * - - 15 /J.s
15
converter.
5 - 110 220
Minimum Setup Time:
10 - 40 80 ns
J/K Lines
AThe basic rule is: If a 4 or less is in a decade. 15 - 30 60
shift with the next clock pulse; if a 5 or greater 5 - 70 140
is in a decade, add 3 and then shift at the next
clock pulse. For more information refer to Parallel·ln-Lines 10 - 25 50 ns
"IRE TRANSACTIONS ON ELECTRONIC
15 - 20 40
COMPUTERS". Dec. 1958. Pages 313-316.
5 2 4 -
Fig. 15-BIDEClogic. Maximum Clock Frequency. fCl 10 6 12 - MHz
15 8 16 -
I nput Capacitance. CI N Anylnput - 5 7.5 pF
RESET OPERATION
5 - 230 460
tpHl' tplH
10 - 100 200 ns
2 TIC
15 - 80 160
6 CL CD4035
4 J 4'STAGE REGISTER 5 - 125 250
3 K
5 R
Minimum Reset Pulse Width. tw 10 - 55 110 ns
0,
15 - 40 40
. .IS cascaded trCL should be made less than or equal to the sum of the transition
..
*If more than one Unit
time and the fixed propagation delay of the output of the driving stage for the estimated capacitive
load.
Control'" E = a
°1 03 °4 °1 03 °4
A 8 C 0 A B C 0
0 a 0 0 0 15 1 , 1 1
1 1 0 0 0 14 0 1 1 1
2
5 1
a 1
a
0
1
0
0
13 1
10 0
.,
o 1
0
1
1
10 a 1 0 1 5 1 o 1 0
4 a 0 1 0 11 1 1 0 1
9 1 0 a 1 6 0 1 1 0
3 1 1 0 0 12 a o 1 1
6 a 1 1 0 9 1 o 0 1
13 1 0 1 1 2 0 1 0 0
11 1 1 0 1 4 0 a 1 0
7 1 1 1 0 8 0 a a 1
14 0 1 1 1 1 o 0 0
12 0 0 1 3 1 1 0 0
8 0 0 0 7 1 1 1 0
92CS-19973RI Using a control line (e) two different state sequences can be generated.
For example, suppose the following two sequences are desired on
command (control line E)
Fig. 16(al - Double sequence generator.
Fig. 16(b) - State sequences.
167
CD40358 Types
.1 lot lit 12t .1 lof lit 12'
H=i'.
PI-I PI-2 PI-3 Pl-4 PI-' PI-2 PI"5 PI-4
.----! PIS ,.---! PIS
CLOCK
CARRY
INPUT
VDD
~
~
~,
• CL
1..-2 K
2 TIC
C04035
UNITS REGISTER ..... .• CL
~p:/C
CD40!!5
TENS REGISTER
RESET.~
• R QI Q2 Q, Qo QI Q2 Q, Qo
1 I 15 10 I. I IS 10 13
~]"CD UNITS ~}C o T£ NS

OUT
OU T
' - - - PIS '--- PIS

CARRY CARRY
BCD UNITS FORWARD
BCD TENS
IfORWAR~ TO
NEXT
t SIDEe LOGIC) (BIDEt LOGIC) 0 ECADE
FIG.7 FIG.7
PI-2 P1-2
TO PI-3 TO PI-3
UNITS TENS
£GISTER PI-4 REGISTER PI-O
92CS-19911RZ
Fig. 17 - Binary·to-BCD converter.
83-91 TERMINAL DIAGRAM

(2.109-2.311) Top View
OIl~1 I. 16 Voo
TRUE/COMP. 2 15 021G2
RESET
•, 3
•
5
I.
13
12
03/~
04/~
PI-4
c:LOCIC 6 PI-3
PfS "
10 PI-2
IIss • Pl-'
HC5-20745R1
The photographs and dimension, of each CMOS chip

represent a chip when it is par' of the wa/er. When the
Dimensions and pad layout for CD4035BH. waler ;s separated into Individual chips, the angle 01
cleavage may vary with respect to the chip f.ce for
different chips. The actua' dimensions of the isolated
Dimensions in parentheses are in millimeters and dimensions shown. The user should consider a tolerance
are derived from the baSI(: inch dImensions as in- of -3 mils to +16 mils applicable 10 the nominal
dicated. Grid graduations are in mils (1o-- 3 inch). dimensions shown.
168
CD4041 UB Types.
CMOS Quad Features:

• Balanced sink and source current; approximately 4 times
True/Complement Buffer standard "B" drive
• Equalized delay to true and complement outputs
High Voltage Types (20-Volt Rating)
• Maximum input current of 1 IlA at 18 V over
full package temperature range; 100 nA at
The RCA-CD4041 UB types are quad true! 18 V and 25 0 C
complement buffers consisting of n- and
p-channel units having low channel resistance • S-V, 10-V, and 15-V parametric ratings C
'~B
K=C
K
and high current (sourcing and sinking) 9

• Meets all requirements of JEDEC Tentative L
capability. The CD4041UB is intended for Standard No. 13A, "Standard Specifications L=t
use as a buffer, line driver, or CMOS-to-TTL for Description of '8' Series CMOS Devices"
driver, It can be used as an ultra-low power
resistor-network driver for AID and DfA con-
version, as a transmission-line driver, and in
other applications where high noise immun- Applications:
ity and low power dissipation are primary • High current sourcelsink driver
design requirements. • CMOS-to-DTLITTL Converter Buffer
I neCD4041UBtypesaresupplied in 14-lead
hermetic dual-In-line ceramic packages (D
•
•
•
Display driver
MOS clock driver
Resistor network driver
E=A
F"A
G=B
I. I.
13
12
Voo
0
N=O
.'0
II
packages (K suffix), and in chip form (H (Ladder or weighted R) H=8 10
9 L=t
suffix). • Buffer vss K=C
• Transmission line driver
MAXIMUM RATINGS, Absolute-Maximum Values: 92CS-20755R1
(Vollages referenced io VSS Terminal) ............................................. -0.510 +20 V
TOP VIEW
INPUT VOLTAGE RANGE, ALL INPUTS ........................................ -0.510 VDD +0.5 V TERMINAL ASSIGNMENT
ForTA ; -4010 +6O"C (PACKAGE TYPE E) ............................................. 500mW
ForTA ; +60lo+85"C (PACKAGE TYPE E) ............... Derale Linearlyal 12 mWrClo 200mW voo
For TA = -55 to +l00"C (PACKAGE TYPES 0, F, K) ...................................... 500 mW
ForTA = +10010 +125"C (PACKAGE TYPES 0, F, K) ....... Derate Linearly at 12 mW/"Clo 200 mW & J O TRUE
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ..•......•.....•.• 100 mW
PACKAGE TYPES 0, F, K, H ..................................................... -55 to +125"C
5lJ
9 9
rPUT
PACKAGE TYPE E ............................................................... -40 to +85°C Vss Vss Vss

STORAGE TEMPERATURE RANGE (Tstg) ......................................... -85 10 +150°C
AI distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max....................... +265°C
*ALL INPUTS PROTECTED
BY COS/MaS INPUT
PROTECTION NETWORK
II' r;t
COOFlEMENT
!~ygUT
operation is always within the following range:
:r. 9 Vss
CHARACTERISTIC LIMITS UNITS Fig. t - Schematic diagram t of 4 buffers.

Min. Max.
Supply-Voltage Range (For TA=Full Package-

ORAIN-TD-SQURCE VOLTAGE (VoS)-V
I~ IGATE-TO-SlURCE vou
II
="
DRAIN-TO-SOURC£ VOlTAGE DRAIN-TO-SOURCE VOLTAGE (VOSI-V
Fig.2 - TVPical output low 'sink) current Fig.3 - Minimum low (sink) current Fig.4 - TVpical output high 'source) current
169
CD4041UB Types
STATIC ELECTRICAL CHARACTERISTICS ORAIN~TO-SOURCE VOLTAGE (Vos)-V
LIMITS AT INDICATED TEMPERATURES (OCI

Values at-55, +25, +125 Apply to D, F, K, H, Packages
CHARAC·
CONDITIONS Values at -40,+25.-i65 Apply to E Pkgs. UNITS
TERISTIC
Vo VIN VDD +25
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
Jl.A
Current - 0,15 15 4 4 120 120 - 0.02 4
IDD Max. - 0,20 20 20 20 600 600 0.04 20
Output low
(Sink) 0.4 0,5 5 2.1 1.8 1.3 1.2 1.6 3.2 :..
Current, 0.5 0,10 10 6.25 5.6 4 3.5 5 10 - Fig.5 - Minimum output high (source)
IOl Min.
Output High
1.5
4.6
0,15
0,5
15
5
24
-2.1·
23
-1.8
15.5 13 19 38 --
rnA
-1.3 -1.2 -1.6 -3.2 . -
(Source) 2.5 0,5 5 -8.4 -6.7 -5.3 -4.6 -6.4 -12.8
Current, 9.5 0,10 10 -6.25 -5.6 -4 -3.5 -5 -Hi
IOH Min. 13.5 0,15 15 -24 -23 -15.5 -13 -19 -38 -
Output Volt·
age: - 0,5 5 0.05 - 0 0.05
low· level , - 0,10 10 0.05 - a 0.05
VOL Max. - 0,15 15 0.05 - a 0.05
V
Output Volt·
age: - 0,5 5 4.95 4.95 5 -
High· level, - 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 15 - LOAD CAPACITANCE (CLI-pF
Input low 0.5,4.5 - 5 1 - - 1 Fig.6 - Typical propagation delay time

VI. load capacitance.
Voltage, 1,9 - 10 2 - - 2
VIL Max. 1.5,13.5 - 15 2.5 - - 2.5
V
Input High 0.5,4.5 - 5 4 4 - -
Voltage, 1,9 - 10 8 8 - -
VIH Min. 1.5,13.5 - 15 12.5 12.5 - -
Input
Current, - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 Jl.A
liN Max.
'!::~''''''
20
,"
o ~ ~ ~ ~ 00 ro 00 ~ 00
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25°C, Input tr.tt =20 ns.
CL = 50 pF. RL = 200 kn. Fig.7 - Typical transition time VS.
load capacitance.
ALL TYPES
CONDITIONS
LIMITS SUPfI'LY VOLTAGE (~ODI.15V
VDD
Volts Typ. Max.
12
Propagation Delay Time: 5 60 120 ~
>
V -IOV
~
10 35 70 ns
.
10
tPHL, AMBIENT TEMPERATURE
tTAI·~'"C
tPLH 15 25 50 ~
~
5 40 80
.,y
Transition Time
tTHL,
tTLH
10
15
20
15
40
30
ns
I .....
,y
Input Capacitance CIN Any Input 15 22.5 pF
10 12 14 II II
INPUT VOlTAGlIVI I-V
Fig.S - Minimum and maximum transfer

characteristics - true output.
170
CD4041UB Types
VDO
,"PUTGOUTPUTS
V,H
'-- ~
'v V~L r
NOTE:
TEST ANY ONE INPUT,
"'00 OR Vss'
INPUT VOLTAGE lVII-V
92C5~ ZlS63&Rl
Fig.9 - Minimum and maximum transfer Fig. 13 - Input voltage test circuit.
characteristics - complement output.
Fig.tt - Typical power dissipation vs

frequency per output pair.
~
.!. ,
II
.e:,c'o",I,----I--+-:--:-I---J.. ----+-----1
VOO INPUTS
o
V55 1100 1NPUOS
Voo NOTE.
~ MEASURE INPUTS
o ~ SEQUENTIALLY,
Vss TO BOTH VDD AHOYss'
CONNECT ALL UNUSED
INI='UTS TO EITHER
10 A ,ol to3 104 10' 4 108 10'

00
Vss
YOOORVSS'
INPlJr RISE AND FALL. TI"'E (t"lf i-nl
t2CS-3U14 Vss
Fig. to - Typical power dissipation vs. input Fig. 12 - Quiescent device current test circuit. Fig. 14 - Input-Ieakage-current test circuit.
rise & fall time per output pair.
Dimensions and pad layout for the CD4041 UBH

derived (rom the basic inch dimensions as indicated
Grid graduations are in mils (10-3 inch).

represent a chip when it is part 01 the wafer. When the
cleavage may vary with respect to the chip lace for
of -3 mils to +16 mils applicabla to the nominal
dimensions shown.
79-87
(2.007-2.209)
171
CD40428 Types
.,
CMOS
Quad Clocked HO" Latch
Features:
• Clock polarity control
• Q and Q outputs 02
.,
0,
02
• Common clock
High-Voltage Types (20-Volt Rating) • Low power TTL compatible a2
• Standardized symmetrical output characteristics D.
13
Cl. "
The RCA-CD4042B types contain four latch
circuits, each strobed by a common clock.
• Maximum input current of 1 p.A at 18 V over
full package-temperature range; 100 nA at ,. D. O.
18 V and 25 0 C
Complementary buffered outputs are availa- • 5-V, 10-V, and 15-V parametric ratings
ble from each circuit. The impedance of the • Noise margin (o.ver full package
n· and p-channel output devices is balanced temperature range):
POLARITY
and all outputs are electrically identical.
Information present at the data input is
1 Vat VDD =5 V • O:::----I~
2 V at VDD = 10 V VDD~
transferred to outputs Q and IT during the 2.5 Vat VDD = 15 V Vss 0"- CD4042B
CLOCK level which is programmed by the • Meets all requirements of JEDEC Tentative FUNCTIONAL DIAGRAM
POLARITY input. For POLARITY = 0 the Standard No. 13A, "Standard Specifications
transfer occurs during the 0 CLOCK level
and for POLARITY = 1 the transfer occurs
for Description of 'B' Series CMOS Devices" Q4
QI
,.
2 "
If
voo
a-
during the 1 CLOCK level. The outputs
follow the data input providing the CLOCK Applications: III
il,
•
4
14
,S
DO
D.
CLOCK 5 '2 iii
and POLARITY levels defined above are
present. When a CLOCK transition occurs • Buffer storage POLAflT\'
D2
6
7 "
'0
,.
03
(positive for POLARITY = 0 and negative

• Holding register
• General digital logic
Vss • iii
for POLARITY = 1) the information present TOP VIE.
at the input during the CLOCK transition is ftCS-2P7!IIR1
retained at the outputs until an opposite TERMINAL ASSIGNMENT
CLOCK transition occurs. STATIC ELECTRICAL CHARACTERISTICS
The G04042B types are supplied in IS-lead
hermetic dual-in~line ceramic packages (0 LIMITS AT INDICATED TEMPERATURES (OCI
and F suffixes), 16-lead'duait-ln-line plastic Values at -55, +25, +125 Apply to O"F, K, H Pkgl.
package (E. suffix), 16-lead ceramic flat CHARAC-
package {K suffix), and in chip form (H TERISTIC
Vo VIN VDO +25
suffix).
Quiesce,lt - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
/lA
Current - 0,15 15 4 4 120 120 - 0.02 4
100 Max. - 0,20 20 20 20 600 600 - 0.04 20
Output Low
(Sink) 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Current, 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
'.01 Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 - mA
Output High 4.6 0,5 5 0.64 0.61 -0.42 -0.36 -0.51 1 -
(Source) 2.5 0.5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1;1 -0.9 -1.3 -2.6 -
IOH Min. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Volt·
age: - 0,5 5 0.05 - 0 0.05
Low· Level , - 0,10 10 0.05 - 0 0.05
g --
OO
Vss
,,,,.,,,,,,,,
*ALL INPUTS ARE

PROTECTEO BY
COS/MOS PROTECTION
NETWORK
VOL Max.
Output Volt·
age:
High· Level,
VOH Min.
Input Low
Voltage,
-
-
-
-
0.5,4.5
1,9
0,15
0,5
0,10
0,15
-
-
15
5
10
15
5
10
0.05
4.95
9.95
14.95
1.5
3
4.95
9.95
14.95
-
-
-
5
0
10
15
-
-
0.05
1.5
3
-
-
V
VIL Max. 1.5,13.5 - 15 4 - - 4

V
CLOCK POLARITY Q
Input High 0.5,4.5 - 5 3.5 3.5 - -
0 0 0 Voltage, .1,9 - 10 7 7 - -
..F
1
0
1
LATCH
0
VIH Min. 1.5,13.5 - 15 11 11 - -
Input
\... 1 LATCH Current, - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 /lA
FIg. 1 - LogiC block diagram and
liN Max.
truth table.
172
CD40428 Types
MAXIMUM RATINGS, Absolute-Maximum Values: AMBIENT TENPERA.TURE (TA'-ZS·C

(Voltages referenced to VSS Terminal) ......... _. . .. . . . .. . .. ......... .. ... . .... . . .. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................ -0.5 to VDD +0.5 V GATE-lO-SOURCE VOLTAGE {VGSI.I~ v
DC INPUT CURRENT, ANY ONE INPUT .................................................. ±10 rnA
For TA = -40 to +60°C (PACKAGE TYPE E) ............................................. 500 mW
For T A = +60 to +85°C (PACKAGE TYPE E) •.............. Derate Linearly at 12 mWfOC to 200 mW
10V
For TA = -55 to +100°C (PACKAGE TYPES 0, F, K) ...................................... 500 mW
g
For T A = +100 to +125°C (PACKAGE TYPES 0, F, K) ....... Derate Linearly at 12 mW/oC to 200 mW
~ 10
For TA =FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................. 100 mW g 5 ,v
OPERATING-TEMPERATURE RANGE (T A):
PACKAGE TYPES 0, F, K, H ..................................................... -55 to +125°C 10
ORAIN-lO-SOURCE VOLTAGE (VDSI-V
PACKAGE TYPE E ............................................................... -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) ......................................... -65 to +150°C
characteristics.
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max....................... +265°C
RECOMMENDED OPERATING CONDITIONS at T A = 25°C, Except as Noted,

For maximum reliability, nominal operating conditions should be selected so that JI5
operation is always within the following ranges: GATE-TO-SOURCE VOLTAGE (VGS)"15 V
~12.5
LIMITS a
VDD 10
CHARACTER ISTIC ALL TYPES UNITS
10V
(V)
Min. Max.
Supply· Voltage Range
(For T A=Full Package - 3 18 V
Temperature Range)
5 200 - 5 10
DRAIN-TO-SOURCE VOLTAGE ('1051-'1
15

15 60 - Fig. 3 - Minimum output low (sink) current
characteristics.
5 50 -
Setup Time, ts 10 30 - ns
DRAIN- TO-SOURCE VOLTAGE (VDS)-V
15 25 - -'0
AMBIENT TEMPERATURE (TA)'25"C
5 120 -
- lli:lli:I±±'G:':At!TE+>_T~ VOLTAGE (VGSI'-5V
Hold Time, tH 10 60 ns
15 50 -
Clock Rise or Fall 5,10 Not rise or fall
f-LS j ::t
Time: tr ' tf 15 time sensitive.
-10'1

DRAIN-lQ-SOURCE VOLTAGE (VOSI-V
·5
AMBIENT TEMPERATURE (TA)-25-C
l,t! HI I:: H: j'

I~
E ht
t'
~:!:li
.:+! 1;,," I::: Ii
....
-10'1
t:
~ tn :8
:::t: 100
.+ -t-
..
''-
:W- - I:; w;:, .i.* [; i:

: ~
1ft rn ::: r !:l :iU :
,tl; [iii i Hi iii " ;It

T. , 20 30 40 50
lOAD CAPACITANCE (Cli -
60 70
pF
60 90
LOAD CAPACITANCE (ell - pf
Fig. 5 - Minimum output high (source) Fig. 6 - Typical propagation delay time vs. Fig. 7 - Typical propagation delay time vs.
current characteristics. load capacitance-data to Q. load capacitance-data to O.
173
CD4042B Types
DYNAMIC ELECTRICAL CHARACTERISTICSatTA = 25°C;lnPUttr ,tt= 20 ns, CL = 50pF,

RL =200 Kn
LIMITS
VDD
(VI
Typ. Max.
Propagation Delay 5 110 220
Time: tpHL, tpLH 10 55 110 ns
Data In to a 15 40 80
5 150 300
Data Into Q 10 75 150 ns
15 50 100
LOAD CAPACITANCE (eLI - pF
5 225 450
Clock to a 10 100 200 ns
Fig. 8 - Typical propagation delay time vs.
load capacitance-clock to 0
15 80 160
5 250 500
Clock to Q 10 115 230 ns
15 90 180
5 100 200
Transition
10 50 100 ns
Time: tTHL, tTLH
15 40 80
Minimum Clock 5 100 200

Pulse Width, tw 10 50 100 ns
15 30 60
5 60 120
Minimum Hold Time, tH 10 30 60 ns
15 25 50
5 0 50
Minimum Setup
10 0 30 ns
Time,ts
15 0 25
lOAD CAPACITANCE (Cll - pF
Clock Input Rise or Fa" 5,10 Not rise or fall
time sensitive. jJS Fig. 9 - Typical propagation delay time vs.
Time: t,. tf 15
Input Capacitance, CI N
load capacitance-clock to a:
(Any Input)
- 5 7.5 pF
NOTE I
{
CLgLCK ----,N::OT:'' 2:-:I___----!.------- LOAD CAPACITANCE
CL-15pF
I CL'50PF
16ill1
,
DATA I
i I
I I
10' 104 10 e
INPUT FREQUENCY-Hz
106
IN~UT t-'sTtH ....1 92CS-3093IRI
LATQt HIGHI I Fig. 10 - Typical power dissipation VI. capacitance.

~I ~-+-----
frequency.
Q{~
OUTPUT I
I
I I
I
I
INPUTS 'NPUTOVDO
OUTPUTS
r~f:::~A I o
Vss V,H
'-- ~
tpHL' tpLH
CLTOQORO
V~L :r
NOTES: NOTE:
I. FOR POSITIVE CLOCK EDGE, INPUT DATA IS LATCHED WHEN
DO Vss ~~STN~"u;~OMBINATION
POLARITY IS LOW.
2. FOR NEGATIVE CL.OCK EDGE, INPUT DATA IS LATCHED WHEN
POLARITY IS HIGH. 92CS-27441RI
92CS-2?630 Vss
Fig. 12 - Dynamic test parameters. Fig. 13 - Qu;escent device current test circuit. Fig. 14 -Input voltage test circuit.
174
CD4042B Types
DD
VDO INPu(Js
V NOTE'
~ ~:~~~:;I!~~~~S
Vss TO BOTH Yoo ANO Vss'
CONNECT ALL UfiUSEO
INPUTS TO EITHER
VOD OR Vss'
Vss
Fig. 15 -Input current test circuit.
Chip Photograph, Dimensions, and Pad Layout
•
dicated. Grid graduations are in mils (1(J3 inch).
The photographs and dimensions of Bach CMOS chip

(spresent B chip when it Is part of tha wafer. When the
walef Is separated into individual chips, the angle of
cleavage may va,y with respect to the chip facB for
different chips. The actual dimenSIons of the isolated
chip, therefore. may differ slightly from the nominel
dimensions shown. The USBr should consider a tolsrance
ciimensions shown.
175
CMOS Quad 3-State Features:

• 3-state outputs with common output
RIS latches ENABLE
• Separate SET and RESET inputs for
Quad NOR RIS Latch - CD4043B each latch
Quad NAND RIS Latch - CD4044B • NOR and NAND configurations
• Standardized symmetrical output
The RCA-CD4043B types are quad cross- characteristics
coupled 3-state CMOS NOR latches and the • 100% tested for quiescent current at 20 V
CD4044B types are quad cross-coupled 3- • Maximum input current of 1 IlA at 18 V over
state CMOS NAND latches. Each latch has a
separate Q output and individual SET and
18 V and 25 0 C
RESET inputs. The Q outputs are controlled
• Noise margin (over full package temperature CD40438
by a common ENABLE input. A logic "1" or
range): 1 Vat VDD = 5 V FUNCTIONAL DIAGRAM
high on the ENABLE input connects the
latch states to the Q outputs. A logic "0" or 2VatVDD = 10 V
low on the ENABLE input disconnects the 2.5VatVDD=15V
latch states from the Q outputs, resulting in • Meets all requirements of JEDEC Tentative R,
an open circuit condition on the Q outputs. Standard No. 13A, "Standard Specifications SI
The ppen circuit feature allows common bus- for Description of 'B' Series CMOS Devices"
ing of the outputs. Applications: R,
5,
The CD4043B and CD4044B types are sup-
plied in 16-lead hermetic dual-in-line cer- • Holding register in multi-register system
amic packages (D and F suffixes). 16-lead • Four' bits of independent storage with 5,
dual-in-Iine plastic packages (E suffix). 16- output ENABLE

R4
lead ceramic flat packages (K suffix), and in • Strobed register 04
54
chip form (H suffix). • General digital logic
• CD4043B for positive logic systems ENABLE NC
JD
• CD4044B lor negative logic systems
r'
9
04
01
I.
2
I.
"
VDD
R4
04
NC
I. 16
15
VDD
54
.~E
, E Vss E:L Voo
SI
ENABLE
14
"12
54
NC
53
51
RI
ENABLE
R2
"
"
12
01
R3
53
E 52
" R3
"
CD40438
VDD -Uvss R2
vss
10
9
0'
0'
52
Vss
10
9
DO
0'
l d"-l__ ~
BY cosmos INPUT
PROTECTION NETWORIi
TOP VIEW
NC' NO CONNECTION
CD4043B
92CS-2A476RI
TOP
NC' NO CONNECTION
CD4044B
VIEW
~"
E
9Vss
S R E
X X 0
o 0 1
Q
oc'
S R E
x x 0 oc'
1 1 1
Q
NC'
*5~:
NC'
1 0 1 1 0 1 1 1
0 1 1 0 1 0 1 0
CD40448 1 1 1 c, 0 0 1 c,c,
·OPEN CIRCUIT ·OPEN CIRCUIT
Fig. 1 - Logic diagrams. +NO CHANGE +NO CHANGE
6 DOMINATED BYS"', INPUT 66 DOMINATED BY R"'O INPUT
92CS-20211 92CS-20212
MAXIMUM RATINGS, Absolute-Maximum Values: CD4043B
CD4044B
DC SUPPLY-VOLTAGE RANGE. (VDD) TRUTH TABLES
(Voltages referenced to VSS Terminal) ................................................ -0.5 to +20 V Recommended Operating Conditions T A =25 0 C
INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -0.5 to VDD +0.5 V For maximum reliability, nominal operating
DC INPUT CURRENT, ANY ONE INPUT ....................... . ......................... ±10 mA conditions should be selected so that opera-
POWER DISSIPATION PER PACKAGE (PD): tion is always within the following ranges
For TA = -40 to +60°C (PACKAGE TYPE E) ................................................. 500 mW
For TA =+60 to +85°C (PACKAGE TYPE E) ................... Derate Linearly at 12 mWfOC to 200 mW Characteristic VOD Min. Max. Units
For TA =-55 to +100°C (PACKAGE TYPES D, F, K) .......................................... 500 mW (V)
For T A =+100 to +125°C (PACKAGE TYPES D, F, K) .......... Derate Linearly at 12 mWfOC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR: Supply-Voltage Range
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW (T A = Full Package
PACKAGE TYPES D, F, K, H ........................................................ -55 to +125°C
PACKAGE TYPE E .................................................................. -40 to +85°C SET Dr RESET 5 160 -
STORAGE TEMPERATURE RANGE (T stg) ............................................. -65 to +150°C Pulse Width, tw 10 80 - ns
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. . .................... +265°C 15 40 -
176
LIMITS AT INDICATED TEMPERATURES laC)
CONDITIONS Values aI-55, +25, +125 Apply 10 D, F, K, H Packages
ISTIC UNITS
Vo VIN VDD +25
IV) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Current, - 0,10 10 2 2 60 60 - 0.02 2
IDD Max. IlA
- 0,15 15 4 4 120 120 - 0.02 4
- 0,20 20 20 20 600 600 - 0.04 20
Output Low 0.4 D,S 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min.
1.5 0,15 15 4.2 4 2.B 2.4 3.4 6.B -
Output High 4.6 D,S 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
(Source) 2.5 D,S 5 -2 -l.B -1.3 -1.15 -1.6 -3.2 -
Current,
IOH Min.
9.5
13.5
0,10
0,15
10
15
-1.6
-4.2
-1.5
-4
-1.1
-2.B
-0.9
-2.4
-1.3
-3.4
-2.6
-6.B
-
- I
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low·Level,
- 0,10 10 0.05 - 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - D,S 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min. 15 -
- 0,15 15 14.95 14.95
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage,
VIL Max.
1,9 - 10 3 - - 3
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,3.5 - 15 11 11 - -
Input Current
- O,lB 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 IlA
liN Max.
3·State Output
Leakage Current O,lB O,lB lB ±0.4 ±0.4 ±12 ±12 - ±1O-4 ±OA Il A
lOUT Max.
CRAIN-TO-SOURCE VOLTAGE (VoSI-V

-15
AMBIENT TEMPERATURE ITA'-Z5"C
-5
GATE-TO-SOURCE VOLTAGE (VGs)--!5V

-5
.
f
GATE-TO-SOURCE VOLTAGE (VGS)=15 V -10 §~
-15 ~
~ -10'1
-20~
e 7.5
10V
~
~ 5
~ 10
o -15'1
6 5 5V § 25 5V
10 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS)~V DRAIN-TO-SOURCE VOLTAGE (Vpsl-V
Fig. 2 - Typical output low (sink) Fig. 3 - Minimum output low (sink) Fig. 4 - Typical output high (source)
current characteristics. current characteristics. current characteristics.
177
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25" C; Input tr, tf= 20ns, DRAIN-TO-SOURCE VOLTAGE, (V05)-1/
I
CL =50pF, RL=200KO
LIMITS
VDD
(VI TYP. MAX.
Propagation Delay 5 150 300

Time: tpHL, tpLH 10 70 140 ns
SET or RESET to Q 15 50 100
3·Stat8 Propagation Delay 5 115 230
Time: ENABLE to Q 10 55 110 ns
tpHZ, tpZH 15 40 80
5 90 180 Fig. 5 - Minimum output high (source)
tpLZ, tpZL 10 50 100 ns
15 35 70
tTHL, tTLH 10 50 100 ns
15 40 80
Minimum 5 80 160
SET or RESET 10 40 80 ns
Pulse Width, tw 15 20 40
Input Capacitance,
(Any Input)
- 5 7.5 pF
CIN
TEST CIRCUITS
Fig. 6 - Typical transition time liS.

load capacitance.
INPUTS
o
Vss
LOAO CAPACITANC
CL-15 pF
CL; 50 pF
10'
IN~UT FR~QUENCY-Hz
Vss
Fig. 7 - Typical propagation delay time Fig. 8 - Typical power dissipation v••
w. load clIpacitance-SET, frequency.
RESET to Q, Q. Fig. 9 - Quiescent device current.
:~UTO'"-;__ y~NPu(Js.
'. =.~::c'::'
YOD
OUTPUT
Vss TO BOTH Yoo AND Vss'

CONNECT ALL UNUSED
NOTE: ...urS 10 EITHER
Vss ~~S:-NAp~~OMBINATICIH Yss Yeo OR Vss'
9ZCS-27404IRI
YDD
Fig. 10 - Input voltage. Fig. 11 - Input current. Fig. 12- Switch bounce eliminator.
178
~
VOD
I. TEST IN
tpHZ Voo VSS

IN
Vss
EPIIABL.E
50% 50%
VS5
"I.
13
tpL.Z Vss Voo Vee
I PZH Vee V5 S Vss
ENABL.E 12 IN
II iN IKn tpZl VS5 Voo Veo
10 f-+.-"N\,-{) z· HIGH IMPEDANCE
Vss
Fig. 13 - ENABL E propagation delay time test circuit and waveforms.
CHIP PHOTOGRAPHS
DIMENSIONS AND PAD LAYOUTS
I
"
, C04043
I
I
I_ _ _ _ _ _ .JI
50 60 65
I
L.OAO A
I I ENABL.E A o - - - - - - - - - - J - - - - . J
l 74-82
(1.880-2.082)
"
"
"
3 C04043
"
10
213 C04009
I."
3 C04043 10
7
92C5-21750
"
"
ENABL.E C 0---------+-----'
CD4043BH
"
"3 C04043 10
LOAD D
ENABL.E o o - - - - -_ _ _-+_---.J
RESET
Fig. 14 - Multiple bus storage.

Grid graduations are in mils (10- 3 inch).

represent a chip when It is part of the wafer. When the
92C5-27751 wafer ;5 separated into individual chips, the angle of
chip. therefore, may differ slIghtly from the nominal
CD4044BH dimensions shown. The user should consider 8 tolerance
of -3 mils to --16 mils applicable to the nominal
dimensions shown.
179
CD4045B Types
CMOS 21-Stage Counter

The RCA-CD40456 is a timing circuit con- Features:

sisting of 21 counter stages, two output- • Very low operating dissipation
shaping flip-flops, two inverter output drivers, <1 mW (typ.) @VOO = 5 V, ftjJ = 1 MHz
and input inverters for use in a crystal oscil- • Output drivers with sink or source capability
lator. The CD40456 configuration provides 7 mA (typ.) @ VOO = 5 V
• Medium speed (typ.) . . . ftjJ=25 MHz@VDO=10V
21 flip·flop counting stages, and two flip- • 100% tested for quiescent current at 20 V
flops for shaping the output waveform for a • 5-V, 10-V, and 15-V parametric ratings
VOD'3 4,5,6,9,10,11,12,13'
3.125% duty cycle. Push-pull operation is • Meets all requirements of JEDEC Tentative Standard VSS'I4
provided by the inverter output drivers. No. 13A, Standard Specifications for Oescripiton of
'6' Series CMOS Devices"
The first inverter is intended for use as a FUNCTIONAL DIAGRAM
crystal oscillator/amplifier. However, it may
be used as a normal logic inverter if desired.
A crystal oscillator circuit can be made less MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (VDDI
sensitive to voltage-supply variations by the
use of source resistors. In this device, the INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to V DD +0.5 V
sources of the p and n transistors have been DC INPUT CURRENT, ANY ONE INPUT ±10mA
brought out to package terminals. If external POWER DISSIPATION PER PACKAGE (PDI:
resistors are not required, the sources must For T A = -40 to +60 0 C (PACKAGE TYPE EI .. .. ... 500mW
For T A = +60 to +85 0 C (PACKAGE TYPE EI . . Derate Linearly at 12 mW/oC to 200 mW
be shorted to their respective substrates (Sp For TA = -55 to +100o C (PACKAGE TYPES D, F, KI . . . . . . . .. 500mW
to VDD, Sn to VSS). See Fig. 1. The first For TA = +100 to +125 0 C (PACKAGE TYPES 0, F, K). Derate Linearly at 12 mW/oC to 200 mW
inverter in conjunction with an outboard DEVICE DISSIPATION PER OUTPUT TRANSISTOR
inverter, such as 1/6 CD4069, and AX, CX, FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl 100mW
and RS can also be used to construct an OPERATING· TEMPERATURE RANGE IT AI:
PACKAGE TYPES 0, F, K, H . -55 to +125 0 C
RC oscillator. The following data is supplied PACKAGE TYPE E . -40 to +85 0 C
as a guide in the selection of values for RX, STORAGE TEMPERATURE RANGE (Tstgl -65 to +150°C
RS' and C x used in Fig. 11: LEAD TEMPERATURE (DURING SOLDERINGI:
1. RX max = 10 Mil with RS = 10 Mil At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max.
and C x = 50 pF
2. C X max = 25 f..LF with RS = 560 kil
and RX = 50 kil
dual-in-line ceramic packages (D and F
suffixes). 16-lead dual-in-line plastic pack- 1·-----------------------;
ages (E suffix). 16-lead ceramic flat packages
(K suffix). and in chip form (H suffix). V:DI I
Applications:
• Oigital equipment in which ultra-low dissi-
pation and/or operation using a battery
source is required.
• Accurate timing from a crystal oscillator
for timing applications such as wall clocks,
table clocks, automobile clocks, and digital RS
timing references in any circuit requiring = 2.097152.

accurately timed outputs at various inter- MH,
vals in the counting sequence.

• Driving miniature synchronous motors,
stepping motors, or external bipolar tran- cx
sistors in push-pull fashion. I
14 -~
Vss
L EXTERNAL
COMPONENTS
~
REfER TO APPLICATION NOTE

ICAN6086 1FORTHE CHOICE Of
OSCILLATOR COMPONENT VALUES SCHEMAT,e OF
FIRST INvERTER
AND TYPICAL OSCILLATOR CURRENTS
Fig. 1 - CD40458 and outboard components in a tvpical 21 -stage counter application.
180
CD4045B Types
liMITS AT INDICATED TEMPERATURES (OC) U
Values at-55, +25, +125 Apply to D, F, K, H Packages N
CONDITIONS Values at -40.+25,+85, Apply to E Package I
CHARACTERISTIC
Vo VIN ~DD +25 T
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max. S
Current, IDD Max. - 0.10 10 10 10 300 300 0.04 - 10
p.A
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output low (Sink) 0.4 0,5 5 4.5 4.3 2.9 2.5 3.6 7 -
Current IOl Min. 0.5 0,10 10 11.2 10.5 7.7 6.3 9.1 18 -
1.5 0,15 15 29.4 28 19.6 16.8 23.8 47
mA -
Output High (Source) 4.6 0.5 5 -4.5 -4.3 -2:9 -2.5 -3.6 -7 -
Current, IOH Min. 9.5 0,10 10 Hl.2 -10.5 -7.7 -6.3 -9.1 -18 -
-
II
13.5 0,15 15 r29.4 -28 -19.6 -16.8 -23.8 -47
Pin 15 Output 0.4,4.6 0,5 5 - +0.1 +0.18 -
Low and High 0.5.9.5 0.10 10 - ±0.2 ±0.3 - mA
Current. IOL,IOH 1.5.13.5 0,15 15 - ±0.5 ±1 -
Output Voltage: - 0.5 5 0.05 - - 0.05
Low· Level. - 0.10 10 0.05 - - 0.05
VOL Max. - 0.15 15 0.05 - - 0.05
V
Output Voltage: - 0.5 5 4.95 4.95 5 - -
High-Level. - 0,10 10 9.95 9.95 10 -
VOH Min. - 0.15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage 1.9 - 10 3 - - 3
VIL Max. 1.5.13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage. 1.9 - 10 7 7 - -
VIHMin. 1.5.13.5 - 15 11 11 - -
Input .current
liN Max.
- 0.18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 to.l p.A

For maximum ~iabllity, nominal operating conditions should be selected so that operation is
always within the following ranges
VDD LIMITS
(V) Min. Max.
Supply-Voltage Range (For TA = Full Package·
Temperature Range)
- 3 18 V
5 - 100
Minimum Input-Pulse Width. tw 10 - 50 ns
15 - 40
Maximum Input-Pulse Frequency. ft/l

5 5 -
(External Pulse SOurce)
10 12 - MHz
15 15 -
181
CD4045B Types
DYNAMIC ~LECTRICAL CHARACTERISTICS at TA = 25°C; Input t r • tf = 20 ns.
CL=50pF. RL=200kn
TEST LIMITS
CHARACTERISTIC CONDITIONS VDD UNITS
V Min. Typ. Max.
Propagation Delay Time: 5 - 2.2 5.5
¢I to y or y+d out 10 - 0.9 2.7 JJS
tpHL' tpLH 15 - 0.65 2
Transition Time: 5 - 25 50
10 - 13 25
tTHL' tTLH 15 - 10 20
ns
DRAIN-TO-SOURCE VCLTAGE IVOSI-V
92CS-31340
Fig. 2 - Typical output low (sink! current
Minimum Input·Pulse Width 5 - SO 100 characteristics.
10 - 25 50
tw 15 - 20 40
Input·Pulse Rise or Fall Time: 5 - - SOO
10 - - 500 JJS
t r¢. tf¢ 15 - - 500
Maximum Input·Pulse 5 5 10 -
Frequency: 10 12 25 - MHz
(External Pulse Source) fq, 15 15 30 -
Input Capacitance. CIN Any Input - 5 7.5 pF
Variation of Output Frequency 5 - 0.05 -
(Unit·to·Unit) t = 5 MHz 10 .- 0.03 - %
15 - 0.1 - DRAiN-TO-SOURCE VOLTAGE IVOsl-V
RC Oscillator Operation HeS-"'''1
Fig. 3 - Minimum output low (sink! current
Maximum Oscillator Frequency RX=50kn. 5 45 60 75 characteristics.
(See Fig. 11) RS=56(tkn. 10 45 60 75 kHz
tosc CX=50pF 15 45 60 75
DRAIN-TO-SOURCE VOLTAGE IVQsI-Y DRAIN-lO-SOURCE VOLTAGE IV05I-v
1
SUPPLY VOLTAGE (VOOI-V 92<:S-,.,"4
Fig. 6 - 'Typical propagation delay time 8S a
function of supply voltage (<P, to y
92C$-:5I'''2 or y+dout .s. VOrY'
9eeS-lIS'"
Fig. 4 - Typical output high (source! current Fig. 5 - Minimum output high (source!
characteristics.
0.01
10 2468022.68,0,2468104246810,246110'
r 2 "6810 2 "68r02 2 "6810,2 "'110.2 "68 SUPPLY VOLTAGE CVooJ-V CAPACITANCE (Cxl-" 92CS-'513"7
INPUT FREQUENCY UfI'-'Hr Fig. 9 - Typical RC oscillstor frequency a. a
Fig. 7 - Typical power dissipation as a function of Fig. 8 - Typical meximum input'pulse frequency function of capacitance (CX).
input frequency (27 counting stages!. as a function of supply voltage. Sse Fig. 11.
182
CD4045B Types
"OO"5,IO,OR 1511
CX"50pf
f-+--hH-J---'~-H RS"I NQ
~ Voo
l~~~~tt~~~~~~~~~~
INPUTS
I
~ :~ "
1~f-+--h~--f--H~-1~~++-+~-tH
o
Vss
~ )~~~ft~~~~~~~~~~~~
0.1
TO COUNTER
1 2 4 6810 2 4 Ii IK:J2 2 4 61103 2 4 68 104

RES\S'TANC(. tRX}-kQ 9lC$-2740IRI
Fig. 10 - Typical RC oscillator frequency as a Fig. 11 - Typical RC circuit. Fig. 12 - Quiescent-device-current test circuit.
function of resistance (R XJ,
See Fig. 11.
NOTE:
MEASURE INPUTS
SEQUENTIALLY"
TO BOTH Voo AND VSS'
•
CONNECT ALL UNUSEO
~ __.--_...J INPUTS TO EITHER
Voo OR VSS'
92CS -2 7441 R 1
VSS 92C$-27402
Fig. 13 - Noise-immunity test circuit. Fig. 14 - Input-leakage-current test circuit. Fig. 75 - Dynamic power diSSipation test circuit.
TERMINAL DIAGRAM
Top View
5p I. IS +,
Voo
5N 2 15
14
I~
·0
VSS
12
No{
II
10 }C
y+d 9
'32CS_2447BA2
NC- NO CONNECTION
NOTE Observe power-supply terminal connec-

tions, VOO is terminal No. 3and VSS is
terminal No. 14 (not 16 and 8 ,espec-
tively. a. in other CD4000B Series 16-lead
device.1.
92CM-3135!5
Dimensions and pad layout for CD4045B.

wafer is separated Into individual chips, the angla of
Dimensions in paren theses are in millimet.rs .nd cleavage may vary with respect to the chip 'ace for
are derived from the basic inch dimensions ., in-
dicated. Grid graduation, are in mil, 3 inch). ,,0- different chips. The actual dimensions of the isolated
of -3 mils to +16 mils applicable to the nomfnal
dimensions shown.
183
CD4046B Types
CMOS Micropower Features:
~
• Very low power consumption:
Phase-Locked Loop 70 }J.W (typ.) at VCO fo = 10 kHz, VOO =5 V
PHASE
PULSES
PHASE COMP
I. 16 YDD
ZENER
• Operating frequency range up to 1.4 MHz (typ,) lOUT 2
The RCA-CD40468 CMOS Micropower ~ATcwt 5
"
14 SIGNAL IN
at VOD = 10 V, RI = 5 kU e_
Phase-Locked Loop (PLL) consists of a low-
power, linear voltage-controlled oscillator • Low frequency drift: 0.04%fC !typ.) at VDO = 10 V
veo OUT • IS
PHASE
II OUT
(VCO) and two different phase comparators • Choice of two phase comparators:
INHIBIT
• I. R2 TO Yss
having a common signal-input amplifier and Exclusive·OR network (I)

CICIJ
•
T
" RI TO Yss
DEMOOULATOII
a common comparator input. A 5.2-V zener Edge-controlled memory network with phase-pulse
C1(2)
"' OUT
diode is provided for supply regulation if
necessary_
output for lock indication (II) ·so • • VCO IN
• High VCO linearity: <1% (typ,) at VDD = 10 V TOP VIEW

The CD40468 types are supplied in 16-lead
ceramic dual-in-line packages (D and F • VCO inhibit control for ON-OFF keying
tlCS-10757AI
suffixes), 16-lead dual-in-line plastic pack- and ultra-low standby power con-
ages (E suffix), 16-lead ceramic flat packages sumption TERMINAL ASSIGNMENT
(K suffix), and in chip form (H suffix). • Source-follower output of VCO control
input (Demod. output)
VCO Section • Zener diode to assist supply regulation Applications:
The VCO requires one external capacitor C1 • Standardized, symmetrical output • FM demodulator and modulator
and one or two external resistors (Rl or Rl characteristics • Frequency synthesis and multiplication
and R2). Resistor Rl and capacitor Cl
• 100%' tested for quiescent current at 20 V • Frequency discri minator
determine the frequency range of the VCO
and resistor R2 enables the VCO to have a • 5-V, 10-V, and 15-V parametric ratings • Data synchronization
frequency offset if required. The high input • Meets all requirements of JEDEC Tentative • Voltage-to-frequency conversion
impedance (10 12U) of the VCO simplifies Standard No. 13A,"Standard Specifications • Tone decoding
the design of low-pass filters by permitting for Description of 'B' Series CMOS Devices" • FSK - Modems
the designer a wide choice of resistor-to- • Signal conditioning
capacitor ratios. In order not to load the • (See ICAN·6101) "RCA COS/MOS
low-pass filter, a source-follower output of Phase-Locked Loop - A Versatile
the VCO input voltage is provided at terminal Building Block for Micropower
10 (DEMODULATED OUTPUT). If this Digital and Analog Applications"
terminal is used, a load resistor (RS) of 10
kU or more should be connected from this
terminal to VSS. If unused this terminal
should be left open. The VCO can be con-
nected either directly or through frequency
dividers to the comparator input of the
phase comparators_ A full COS/MOS logic
swing is available at the output of the VCO
and allows direct coupling to COS/MOS Fi OO
LIss
frequency dividers such as the RCA-CD4024,
CD4018, CD4020, CD4022, CD4029, and
CD4059. One or more CD4018 (Preset-
table bivide·by:1'iI Counter) or CD4029 (Pre- * BY
All INPUTS ARE PROTECTED
settable Up/Down C,ounterl, or C04059A COS/MOS PROTECTION
NETWORK
(Programmable Divide-by-"N" Counter), to-
gether with the C04046B (Phase-Locked
Loop) can be used to build a micropower
low-frequency synthesizer_ A logic 0 on the
INHIBIT input "enables" the VCO and the 92CS-29172
source follower, while a logic 1 "turns off"

both to minimize stand-by power consump- Fig. i - COS/MOS phase·locked loop block diagram.
tion_

DC SUPPLY-VOLTAGE RANGE, (VDD) Phase Comparators
(Voltages referenced to VSS Terminal) ............................... ,............. -0,5 to +20 V The phase-comparator signal input (terminal
INPUT VOLTAGE RANGE, ALL INPUTS ............................. ,.......... -0.5 to VDD +0.5 V 14) can be direct-coupled provided the signal
DC INPUT CURRENT, ANY ONE INPUT .................................................. ±10 mA swing is within COS/MOS logic levels [logic
POWER DISSIPATION PER PACKAGE (PD): "0" <;;30% (VOD-VSS), logic "1" ;;. 70%
For TA = -40 to +60' C (PACKAGE TYPE E) ............................................. 500 mW (VDO-VSS) J. For smaller swings the signal
For TA = +60 to +85'C (PACKAGE TYPE E) ......•......• , Derate Linearly at 12 mwrc to 200 mW must be capacitively coupled to the self-
For TA = -55 to +l00'C (PACKAGE TYPES D, F, K) ............ _.... _..... __ ............. 500 mW biasing amplifier at the signal input.
For TA = +100 to +125'C (PACKAGE TYPES D, F, K) .....•. Derate Linearly at 12 mwrc to 200 mW Phase comparator I is an exclusive-OR net-
DEVICE DISSIPATION PER OUTPUT TRANSISTOR work; it operates analagously to an over-
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................. l00mW driven balanced mixer. To maximize the lock
OPERATING-TEMPERATURE RANGE (TA): range, the signal- and comparator·input fre·
PACKAGE TYPES D. F, K, H ..•.. '................................................ -55 to +125'C quencies must have a 50% duty cycle. With
PACKAGE TYPE E ............................................................... -40 to +85'C no signal or noise on the signal input, this
STORAGE TEMPERATURE RANGE (Tstg) ......................................... -65 to +150"C phase comparator has an average output
LEAD TEMPERATURE (DURING SOLDERING): voltage equal to VOO/2. The low-pass filter
At distance 1/16 ± 1132 inch (1.59 ± 0.79 mm) from case for lOs max.................. , ..•. +265'C connected to the output of phase comparator
184
CD4046B Types
RECOMMENDED OPERATING CONDITIONS at TA = Full Package-Temperature Range I supplies the averaged voltage to the VCO
input, and causes the VCO to oscillate at the
For maximum reliability, nominal operating corviitions should be selected so that center frequency (fa).
The frequency range of input signals on
LIMITS which the PLL will lock if it was initially
CHARACTERISTIC UNITS out of lock is defined as the frequency cap-
Min_ Max_ ture range (2fcl.
Supply-Voltage Range VCO Section: The frequency range of input signals on
As Fixed Oscillator 3 18 which the loop will stay locked if it was
Phased-Lack-Loop Operation 5 18 initially in lock is defined as the frequency
V
lock range (2fL). The capture range is 0;;; the
Supply-Voltage Range Phase Comparator Section: lock range.
Comparators 3 18 With phase comparator I the range of fre-
VCO Operation 5 18 quencies over which the PLL can acquire
lock (capture range) is dependent on the
low-pass-filter characteristics, and can be
made as large as the lock range. Phase-com-
The selected external components must be parator I enables a PLL system to remain
DESIGN INFORMATION in lock in spite of high amounts of noise
within the following ranges:
This information is a guide for approximating 5 H2O;;; Rl, R2, RSo;;; 1 Mn in the input signal.
I
the values of external components for the Cl ;;'100pF atVDD;;'5 V; One characteristic of this type of phase com-
CD4046A in a Phase-Lacked-Loop system_ Cl ;;. 50 pF at VDD-;;. 10 V parator is that it may lock onto input fre-
quencies that are close to harmonics of the
VCO center-frequency. A second charac·
Phase
teristic is that the phase angle between the
Characteristics Comparator Design Information signal and the comparator input varies be-
Used tween 0 0 and 1800 , and is 900 at the center
VCO WITHOUT OFFSET veo WITH OFFSET frequency. Fig. 2 shows the typical, trian-
R2=oo gular, phase·to-output response characteristic
of phase-comparator I. Typical waveforms
for a CMOS phase-locked-loop employ-
ing phase comparator I in locked condition
'-~
t:c
of fa is shown in Fig. 3.
f - _ 2fL
IQ --
VCO Frequency 1 12fL I
I I
fNIN
YDOI2 Yoo ...... v••
veo INPUT YOLTAGE YCO INPUT VOLTAGE
92($-20012111
VDD
V·OUTPUT
VOLTAGE
2 Same as for No.1 O~

-' VDD/2
For No.Signal Input 1 VCO will adjust to center frequency, fa

2 VCO will adjust to lowest operating frequency, fmin o 90· 180-
SIGNAL-TO- COMPARATOR
2 fL = full VCO frequency range INPUTS PHASE DIFFERENCE
Frequency Lock 1
2 fL - fmax-fmin
Range, 2 fL Fig.2 - Phase-comparator I characteristics
2 Same as for No.1 at low-pass filter output.
Frequency Capture
I.
R' OUT
(I), (2)·
Range, 2 fC
1
~ 2fC"'- -rrfL
rr 71
- lt SIGNAL INPUT ITEAM. 14}
veo OUT PUT (TE RM 41 •
COMPARATOR INPUT
ITER.,31
I.
R' OUT
PHASE COMPARATOR I
t
Loop Filter OUTPUT (TERM. 2)
For 2 fC, see Ref. (2) veo
Component lNPIJT ITERM.9Ia
-LOW-PASS FILTER
-vss
Selection ~C2 OUTPUT
92C$-21901
Fig. 3- Typical waveforms for CMOS phase-locked
2 fC = fL loop employing phase comparator in locked
condition of f o.
Phase Angle Between 900 at center frequency (fa) approximating 0 0
1
Signal and Comparator and 1800 at ends of lock range (2 fL) Phase-comparator II is an edge-controlled
2 Always 00 in lock digital memory network. I t consists of four
flip-flop stages, control gating, and a three-
Locks On Harmonic of 1 Ves
state output circuit comprising p- and n-type
Center Frequency 2 No drivers having a common output node. When
Signal Input 1 High the p-MOS or noMOS drivers are ON they
Noise Rejection pull the output up to VDD or down to
2 Low
VSS, respectively. This type of phase com-
parator acts only on the positive edges of
.For further information, see the signal and comparator inputs. The duty
(1) F. Gardner, "Phase-Lock Techniques" John Wiley and Sons, New York, 1966 cycles of the signal and comparator inputs
(2) G. S. Moschytz, "Miniaturized RC Filters Using Phase-Locked Loop", BSTJ, May, 1965. are not important since positive transitions
185
CD4046B Types

LIMITS AT INDICATED TEMPERATURE (Oel U
CHARAC· CONDITIONS Values at-55, +25, +125 Apply to D, F, K, H Packages N
TERISTIC Values at -40. +25. +85 Apply to E Package I
T
Vo VIN VDD +25 S
VCOSaction
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1
(Sinkl Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6
IOLMin. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 0.51 1 mA
(Sourcel 2.5 0,5 5 -2 -1.8 -1.3 -1.15 1.6 3.2
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 1.3 2.6
IOHMin. 13.5 0.15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: Term. 4 0,5 5 0.05 - 0 0.05
Low-Level, driving 0,10 10 0.05 - 0 0.05
VOL Max. CMOS 0,15 15 0.05 - 0 0.05 V
Output 0,5 5 4.95 4.95 5
Voltage: e.g. 010 10 9.95 9.95 10
High·Level, Term.3 0,15 15 14.95 14.95 15 -
VOH Min.
Input Cu rrent
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - 10-5 ±0..1 p.A
Phase Comparator Section

Total Device - 0,5 5 0.2 - 0.1 0.2
Current, 100 Max. - 0,10 10 1 - 0.5 1 mA
Term. 14 open, - 0,15 15 1.5 - 0.75 1.5
Term.5=VOO -
- 0,20 20 4 2 4
- 0,5 5 20 - 10 20
Term. 14 = Vss - 0,10 10 40 - 20 40 p.A
or VOO, Term. 5 - 0,15 15 80 40 80
=VOO
- 0,20 20 160 - 80 160
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -

(Sinkl Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOLMin. 1.5 0,1& 15 4.2 4 2.8 2.4 3.4 6.8 -
Output High 4.6 0,5 5 "-0.64 -0.61 -0.42 r-0.36 H>.51 -1 - mA
(Sourcel 2.5 0,5 5 -2 -1.8 -1.3 r-1.15 -1.6 -3.2 -
Current 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 .,.
IOHMin.
13.5 0,15 15 -4.2 -4 -2.8 -~.4 -3.4 -6.8 -
DC·Coupled
. Signal Input and
Comparator Input
Voltage Sensitivity 0.5,4.5 - 5 1.5 - - 1.5
Low Level 1,9 - 10 3 - - 3
VIL Max. 1.5,laS- - 15 4 - - 4 V
High Level 0.5,4.5 - 5 3.5 3.5 - -
VIHMin. 1,9 - 10 7 7 - -
1.513.5 - 15 11 11 - -
control the PLL system utilizing this type of the time. If the signal-input frequency input frequencies are the same, but the
of' comparator. If' the signal-input fre· is lower than the comparator-input frequen- signal input lags the comparator input in
quency is higher than the comparator-input cy, the n-type output driver is maintained phase, the n-type output driver is main·
frequency, the p-type output driver is main- ON most of the time, and both the nand tained ON for a time corresponding to the
tained ON most of the time, and both the p drivers OFF (3 state) the remainder of phase difference. If the signal- and com-
nand p drivers OFF (3 state) the remainder the time. If the signal- and comparator- parator-input frequencies are the same, but
186
CD4046B Types
STATIC ELECTRICAL CHARACTERISTICS the comparator input lags the signal in phase,
the p-type output driver is maintained ON
LIMITS AT INDICATED TEMPERATURE (oCI U for a time corresponding to the phase dif-
CHARAC· CONDITIONS Values aI-55, +25, +125 Apply 10 D, F, K, H Packages N ference. Subsequently, the capacitor voltage
TERISTIC Values at -40, +25, +85 Apply to E Package I of the low-pass filter connected to this phase
T comparator is adjusted until the signal and
+25 S comparator inputs are equal in both phase
Vo VIN VDD
(VI (VI (VI -55 -40 +85 +125 Min. Typ. Max. and frequency. At this stable point both p-
and n-type output drivers remain OFF and
Phase Comparator Section (cont'dl thus the phase comparator output becomes
Input Current an open circuit and holds the voltage on the
capacitor of the low-pass filter constant.
liN Max. - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 jJ.A Moreover the signal at the "phase pulses"
(except Term. 141 output is a high level which can be used for
3·State Leakage indicating a locked condition. Thus, for
Current, ±O.t ±O.t ±O.2 ±to-' phase comparator II, no phase difference
0,18 0,18 18 ±O.2 - ±D.t jJ.A exists between signal and comparator input
lOUT Max. over the full VCO frequency range. More-
"Limit determined by minimum feasible leakage current measurement for automatic testing. over. the power dissipation due to the low-
pass filter is reduced when this type of phase
comparator is used because both the p- and
n-type output drivers are OFF for most of
the signal input cycle. It should be noted
that the PLL lock range for this type of phase
comparator is equal to the capture range,
ELECTRICAL CHARACTERISTICS at TA = 25°C independent of the low-pass filter. With no
signal present at the signal input, the VCO
CHARAC· LIMITS is adjusted to its lowest frequency for phase
TERISTIC TEST CONDITIONS ALL TYPES comparator II. Fig. 10 shows typical wave-
VDD UNITS forms for a CMOS PLL employing phase
(VI Min. TVD. M~x comparator II in a locked condition.
VCOSection
Operating Power
fo = 10 kHz Rl = 1 Mn 5 - 70 140
Dissipation, PD R2 = 00 VDD 10 - 800 1600 jJ.W
VCOIW - - 15 - 3000 6000
2 AMBIENT TEMPERATURE (TA ). 25·C
VCOIN.VOO/2,R2 _CD,INHIBIT -Vss
Maximum Cl=50 pF 5 0.3 0.6 -

Operating R2 = 00 Rl = 10 kn 10 0.6 1.2 -
Frequency f max VCOIN=VDD 15 0.8 1.6 - MHz
Cl = 50pF 5 0.5 0.8 -
R2 = 00 R t = 5 kn 10 1 1.4 -
VCOIN=VDD 15 1.4 2.4 -
Center Frequency
(fol and Frequency
Range
Programmable with external components R 1, R2. and Cl
(fmax-fmin) 10-4 10.3 10.2 10.1 10
See Design Information veo TIMING CAPACITOR (CII-,.F 92($-3034'
Fig. 4 - Tvpical center frequency as a function of
VCOIN= 2.5V±0.3V, Rl=10 kn 5 - 1.7 - CI and RI at VDD =5 V, 10 V, and 15 II.
=5V±1 V, = 100kn 10 - 0.5 -
Linearity =5V± 2.5V. =400kn 10 - 4 - %
=7.5V±1.5V, = 100kn 15 - 0.5 -
=7.5V±5V, = 1 Mn 15 - 7 -
Temperature -
Frequency 5 - ±0.12 -
Stability: 10 - ±0.04 - f lo3k--'&-...:.o~
No Frequency 15 - ±0.015 - :;.
~ I04',=--Sl..~:s::.I~~
Offset fMIN = 0
%fC ~
~ IO)'b--+-..::5lI.,.,......::s::k-
Frequency 5 - ±0.09 -
Offset 10 - ±0.07 - ~
~ IOz''=-_-l-_-l_....c~
fMIN ;0 15 - ±0.03 - ~
Output Duty 10b--+---+--1-":
Cycle 5.10.15 - 50 - %
10-3 10-4 10-3 10-2 10-1 10
Output Transftion 5 - 100 200 veo TIMING CAPACITOR (CIl-,.F 92CS-30353
Times, 10 - 50 100 ns Fig. 5 - Center frequency as a function of C1 and

tTHL' tTLH 15 - 40 80 R1 fer ambienJ temperatures of
-55 Cta 125 C.
187
CD40468 Types
ELECTRICAL CHARACTERISTICS at TA = 25°C
CHARAC· LIMITS
TERISTIC TEST CONDITIONS VDD ALL TYPES UNITS
(V) Min.' Typ. Max.
VCOSection (cont'd)
Source· Follower lOY
Output (Demodu· 5 - 1.8 2.5 ~~~~~ -~~~~~~~,~
lated Output) : RS> 10 kG 10 - 1.8 2.5 V lOY
IV
Offset Voltage 15 - 1.8 2.5 -+----~~~~,.Y
(VCOIN-VDEM) •••• lOY
IO~S Mr. IO-J 110'"' 10""1" I ..

RS=100 kG VCOI N = 2.5±0.3 V 5 - 0.3 - 'leO T'IiINO CAMC.TOIt ICII- .. ' tac......
Linearity =300kG
=500kG
=5±2.5V
=7.5±5V
10
15
-
-
0.7
0.9
-- % Fig. 6 - Typlu/ frequency offlllt'". function of
Ct lind R2 for VDD ·5 V, 10 V, .nd
tSV.
Zener Diode
Voltage (V z)
IZ=50j.tA 4.45 5.5 ~.15 V
Zener Dynamic
Resistance, Rz IZ= 1 mA - 40 - G
i
Phase Comparator Section j
Term. 14 (SIGNAL
IN) Input
5
10
1
0.2
2
0.4
-
- MG
~
Resistance R14 15 0.1 0.2 -
AC Coupled 1':r--+----+-----1I--+"....
Signal Input 5 - 180 360
Voltage Sensi· fiN = 100 kHz, 10-6 10-4 10- 1 10*1 10""1 I ID
sine wave
10 - 330 660 mV vel) TIIlINO c;APAClTOR tcu-,.~c.. _
tivity* (peak· 15 - 900 1800
to·peak) Fig. 7 - FrequtmCy offl"U•• fUnction of
CI lind R2 for•.-mIIillnt !!fmptJ"
Propagation Delay IIrutrJlQf-S6 Ct" 12trC.
Times, Terms. 14 5 - 225 450
to13: High to 10 - 100 200 n5
Low Level, tpH L
15 - 65 130
Low to High 5 - 350 700

~.~----4------+------~----1
Level, tpLH 10 - 150 300' ns I I
15 - 100 200 ~
3·State Propagation j
Delay Times,
Terms. 14 to 13:
High Level to
5
10
15
-
-
-
225
100
95
450
200
190
ns .
••
I
High Impedance,
tpHZ 0.01
Low Level to 5 - 285 570

High Impedance, 10 - 130 260 ns
tpLZ 15 - 95 190
Input Rise or Fall
Times, t r , tf See Fig. 5 for Phase Compo II
5 - - 50
Comparator output loading
10 - - 1 j.ts
Input, Term. 3
15 - - 0.3
Signal Input,
S - - 500
Term. 14 10 - - 20 j.ts
15 - - 2.5
Output Transition
5 - 100 200
I:--------+---=.....!!I- IO ..
10 - 50 100 ns
,~,
Times, tTHL, tTLH 15 - 40 80 10
• For sine wave, the frequency must be greater than 10 kHz for Phase Comparator 11. 10 '101·'" • 'to' I " . '10"
..-,. ~ •. "'If,.
Fig. 9 - Typ/cll/ VCO fJD- di"ifllltion.t wntn
frequtmCy '". function of R I,
188
CD4046B Types
SIGNAL INPUT ITERM 141
4
'I.
veo OUTPUT (TERM ~ 1 0 I 10'~;;::_--;:--f------f--------i
COMPARATOR INPUT
(TERM 31
PHASE COMPARATOR n
VD
: Kn
?z
OUTPUT (TERM 131 _JL- -- - -il- - - - -u- -"._~~~~ PHASE
COMPARATOR n
13 20 Kll ~ 104b--=~=-P'""''''''~
OUTPUT
VCO INPUT (TERM 9)' II 12-----VOO
2Kn ~
-Vss
~ LOW-PASS FILTER
OUTPUT
~ 103b----"'''''''1<:::c----''''''"I
PHASE PULSE ITERM I) ~1-!------;u--u-~~~~ Vss

92CS-303$$ ~
NOTE. ~~~~~~~~NI~''1 SAT~~~~N CIRCUIT 92CS20011R2 ~ 102b-----t----~
F;g. 70 -- Typical waveforms for COS/MOS phase-locked loop Fig. 11 - Phase comparator II
employing phase comparator II in locked condition. output loading circuit. 10
10 ," 10'
, " 10' , " 10'
R2-kD
Fig. 12 - Typical VCO power dissipation at f MIN
as a function of R2.
'I.I AMBIENT TEMPERATURE (TA}o25-C
! :::~~N~O~~~:~~~~U~E (TA)OZS-Cl
VDD
...~
VCO IN oVOO/2, RI-R2-co
C
'" 10,
z
i'? ~.
I
~
I
.
,
~- ,,- '0,
2011,0
13
~
~J I
2 k.D VOUT
~ \fc)L. r04GE Ow
. -·~':':f"OO]O'"" >, AMBIENT TEMPERATURE CTAloZ5-cl
*~ F--- ~
~
10
3 ~;
'w
~~ 1038
,
,,-
~'\:-4~
~ .~
Vss
OUTPUT CIRCUIT
VOO"IOV,VC0 1N "5Vtl V,RZ"IO I
~
~
102
~
~~
00
~; 10'8
,
~
/'
~
.. ~
z
w
~
10 I-______
:
+-______ I--_____+------~
~ 10 8~ 6 CI'50 pF
~ ~_ 4
,
. ."
~ ij,lOOpF
~ t)( ~~
I
, J , , , 10
, 468 , .68 10' f------J.------f;!~~-+-_;c.'"'
1000 pF
10 "
RI -k.D
" 10' 10' 10
SIGNAL INPUT FREQUENCY t 'IN) -11Hz 92CS- 303!10
• f(4vl+!t6V} ~ 0 .....
10 ' - , - - ' - - -:..~-~-:.:.:--...,
" -'(5'.1) ~"r-
Fig. 13 -- Typical source follower power Fig. 14 -- AC-coupled signal input voltage as a % LINEARITY ° _0_._ X 100 0.01 ~F
dissipation as a function of Rs. function of signal input frequency. 10-1 I I to II
10-12 468 1 ' 468 10 ' 4 6B 102 ' 468103
RI- kG 92CS-3034!1
Fig. 15 -- Typical VCO linearity as a function of

RI and CI at V DD = 10 V.
i 10:1------_+-------I-------+-----~
~
b
- CI-!!i~PF I~PF O.I~)
96-104
(2.438-2.642) ~~ "'-./
IB,I---,-.-.~f(6~vf.!~.,~!.~V~!~~~~~;;::----+--_"~~~
0 ,
4 ,'o-fC7.5 V) " 1000 pF

%LINEAR::Y_~11100 ~:~~:F
2 4 68
" I 10
RI-kG
Fig. 16 - Typical VCO linearity as a function of

RI and CI at V DD = 15 V.

are derived from the basic Inch dimenSIons as in-
dicated. Gnd graduations are in mils (10- 3 inch).
represent 8 chip when it is part of the wafer. When the
waler is separated into individual chips, the angle of
cleavage may vary with respect to the chip face lor
92CM-36467 different chips. The actua' dimensions o( the isolated
dimensions shown.
189
CD4047B Types
CMOS Low-Power Features:

• Low power consumption: special CMOS
Monostable/Astable oscillator configuration
• Monostable (one-shot) or astable (free-running)
MuItivibrator operation
• True and complemented buffered outputs
V DD
R :: OSCOUT
• Only one external Rand C required R-C COMMON 12 RE~RIGGER
High Voltage Types (20-Volt Rating) • Buffered inputs ASTABLE
• 100% tested for quiescent current at 20 V ASTABLE
-TRIGGER
: :~ Q
The· RCA-CD4047B consists of a gat able • Standardized, symmetrical output 9 +T~'G~~SRE T
astable multivibrator with logic techni- characteristics Vss 8
ques incorporated to permit positive or • 5-V, 10-V, and 15-V parametric ratings
TOP VIEW
negative edge-triggered monostable • Meets all requirements of JEDEC
multivibrator action with retriggering and Tentative Standard No. 13B, 92CS-2143iRI
external counting options. "Standard Specifications for
Description of 'B'
Inputs include + TRIGGER, -TRIGGER, Terminal Diagram
Series CMOS Devices"
ASTABLE, ASTABLE, RETRIGGER, and
EXTERNAL RESET. Buffered outputs are Monostable Multivibrator Features:
C, 0, and OSCILLATOR. In all modes of • Positive- or negative-edge trigger • Oscillator output available
operation, and external capacitor must be • Output pulse width independent of • Good astable frequency stability:
connected between C-Timing and RC- trigger pulse duration Frequency deviation:
Common terminals, and an external • Retriggerable option for pulse width = ± 2% + 0.03%/"C @ 100 kHz
resistor must be connected between the expansion = ± 0.5% + 0.015%I·C @ 10 kHz
R-Timing and RC-Common terminals. • Internal power-on reset circuit (circuits "trimmed" to frequency
Astable operation is enabled by a high • Long pulse widths possible using small VDD = 10 V ± 10%)
level on the ASTABLE input or a low level RC components by means of exter-
on the ASTABLE input, or both. Th~ nal counter provision
period of the square wave at the 0 and 0 • Fast recovery time essentially indepen- Applications:
Outputs in this mode of operation is a dent of pulse width Digital equipment where low-power
function of the external components • Pulse-width accuracy maintained at dissipation andlor high noise immunity
employed. "True" input pulses on the duty cycles approaching 100% are primary design requirements:
ASTABLE input or "Complement" pulses
on the ASTABLE input allow the circuit to • Envelope detection
be used as a gatable multivibrator. The • Frequency multiplication
Astable Multivibrator Features: • Frequency diviSion
OSCILLATOR output period will be half of
• Free-running or gatable operating • Frequency discriminators
the 0 terminal output in the astable modes
mode. However, a 50% duty cycle is not • Timing circuits
• 50% duty cycle • Time-delay applications
guaranteed at this output.
The CD4047B triggers in the monostable
mode when a positive-going edge occurs on
the + TRIGGER-input while the -TRIGGER is RECOMMENDED OPERATING CONDITIONS
held low. Input pu Ises may be of any duration
For maximum reliability, nominal operating conditions should be selected so
relative to the output pulse.
that operation is always within the following ranges:
If retrigger capability is desired, the LIMITS
RETRIGGER input is pulsed. The retrig- CHARACTERISTIC UNITS
MIN_ I MAX,
gerable mode of operation is limited ~o
Supply-Voltage Range (For TA - Full Package-Temperature
positive-going edge. The CD4047B Will
retrigger as long as the RETRIGGER-input
Is hiQh, with or without transitions (See
RanQe) 3 18
NOTE: IF AT 15 V OPERATION A 10 MQ RESISTOR IS USED THE OPERATING
I V
Fig. 34). TEMPERATURE SHOULD BE BETWEEN -25'C and 100'C

An external countdown option can be im-
plemented by coupling "0" to an external
"N" counter and resetting the counter
with the trigger pulse. The counter output MAXIMUM RATINGS. AbSOlute-Maximum Values:
pulse is fed back to the ASTABLE input DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltages referenced to VSS Terminal) ........ _................•. _........ ... .•. ...... -0.5 to +20 V
and h~s a duration equal to N times the
INPUT VOLTAGE RANGE, ALL INPUTS .. _. _.................. _................... -0.5 to VDD +0.5 V
period of the multivibrator.
DC INPUT CURRENT, ANY ONE INPUT ..•................•• _...................•......•. _.. ±10 mA
A high level on the EXTERNAL RESET in- POWER DISSIPATION PER PACKAGE (PD):
put assures no output pulse during an For T A = -40 to +60· C (PACKAGE TYPE E) ................. _............................... 500 mW
"ON" power condition. This input can For T A =+60 to +85·C (PACKAGE TYPE E) ....••....•....•... Derate Linearly at 12 mW/·C to 200 mW
also be activated to terminate the output For TA = -55 to +l00·C (PACKAGE TYPES D, F, K) .......................................... 500 mW
pulse at any time, for monostable opera- For T A = +100 to +125·C (PACKAGE TYPES D, F, K) ...... _... Derate Linearly at 12 mW/·C to 200 mW
tion, whenever VDD is applied, an internal DEVICE DISSIPATION PER OUTPUT TRANSISTOR:
power-on reset circuit will clock the Oout- For T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) . _.................... 100 mW
put low within one output period (tM)' OPERATING-TEMPERATURE RANGE (T A):
The CD4047B-Series types are supplied in PACKAGE TYPES D, F, K, H ........................................................ -55 to +125·C
14-lead hermetic dual-in-line ceramic pack- PACKAGE TYPE E .................................................................. -40 to +85·C
ages (D and F suffixes), 14-lead dual-in-line STORAGE TEMPERATURE RANGE (T stg) ..... _....................................... -65 to +150·C
plastic packages (E suffix), 14-lead ceramic LEAD TEMPERATURE (DURING SOLDERING):
flat packages (K suffix), and in chip form (H At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.......................... +265·C
suffix).
190
CD40478 Types
CD4047B FUNCTIONAL TERMINAL CONNECTIONS
NOTE: IN ALL CASES EXTERNAL RESISTOR BETWEEN TERMINALS 2 AND 3&
EXTERNAL 'CAPACITOR BETWEEN TERMINALS 1 AND 3&
TERMINAL CONNECTIONS OUTPUT OUTPUT PERIOD
FUNCTION TOVDD TOVSS INPUT PULSE OR
TO FROM PULSE WIDTH
Astable Multivibrator:
Free Running 4,5,6,14 7,8,9,12 - 10,11,13 tA (10,11) = 4.40 RC
True Gating 4,6,14 7,8,9,12 5 10,11,13 tA (13) = 2.20 RC#
Complement Gating 6,14 5,7,8,9,12 4 10,11,13
Monostable Multivibrator:
Positive·Edge Trigger 4,14 5,6,7,9,12 8 10,11
Negative-Edge Trigger 4,8,14
Retriggerable
External Countdown
4,14
14
5,7,9,12
5,6,7,9
5,6,7,8,9,12
. -
6
8,12
10,11
10,11
10,11
1M (10,11) =2.48 RC
... See Text.

# First positive 'h cycle pulse·width= 2.48 RC, see Note on Page 10.
•
• Input Pulse to Reset of External Counting Chip External Counting Chip Output To Terminal 4
C-TlMING
'--R';- - - -
I COMMON
I
)--"A::cST,-,A:!B::!C:.!:E'---t-I~ AST AS l E
GATE
CONTROL
4 ASTABLE
L _____ _
92CS-29071
Fig. 1-CD40478 logic block diagram.
RETRIGGER
+TRIGGER
-TRIGGER
VDD@-
VS5@--
EXTERNAL
RESET
* INPUTS PROTECTED BY
COS/MOS PROTECTION
NETWORK
a ---
VDD
V5S
~ ____
DD
** PROTECTION
CAUTION: TERMINAL 315 MORE
SPECIAL RC COMMON
Vss
NETWORK
SENSITIVE TO STATIC
ELECTRICAL DISCHARGE.
EXTRA HANDLING PRE-
CAUTIONS ARE RECOMMENDED.
92CM -2lf042RI
Fig. 2-CD40478 logic diagram.
191
CD40478 Types
DRAIN-lD-SDURCE VOLTAGE (VosI-V
-15 -10 -5
AMBIENT TEMPERATURE (TA'-2S·C
o GATE-TO SOURCE VOLTAGE (V(;S'--5V
U
CL
a: o
RI R2
FFI, FF3
CL
-15V
-IOV
.....,.----__ 0
't2CS- ~4 ~201l4
Fig. 6-Typical output high (source) current

characteristics.

FF2, FF4
AMBIENT TEMPERATURE
-15
ITAI~25·C
-10 -,
GATE-TO-SOURCE VOL.TAGE IVGS'--5 V
CL
(b)
92CM- 29040
Fig. 3-Detaillogic diagram for flip-flops FFI and FF3 (a) and for flip-flops FF2 and FF4 (b). lOY
AMSIENT TEMPERATURE (TA).25-C
-15 V
4
•
I
~15
GATE TO ·SOURCE VOLTAGE (VGSI-15V
~12.5
~ 10 Fig. 7-Minimum output high (source) ~~;;~~t3

characteristics.
~ lOY
§ 7.5
~
9 ,
§~ 2.5 'Y
I 5 10 15
DRAIN-lO-SOURCE VOLTAGE IVosl-V DRAIN-lO-SOURCE VOLTAGE (VoSI-V
Fig. 4-Typical output low (sink) current Fig. 5-Minimum output low (sink) current
lOY
characteristics. characteristics.

CHARAC- CONDITIONS Values at-55, +25, +125 Apply to D,F,K,H Packages
TERIS- Values at ·40, + 25, + 85 Apply to E Package
w ~ ~ ~ ~
TICS Vo VIN VDD 25 UNITS LOAD CAPACITANCE ICL1-pF
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max. Fig. 8- Typical propagation delay time as a
function of load capacitance (Astable,
Quiescent - 0,5 5 1 1 30 30 - 0.02 1 Astable to Q, c:iJ.
Device Cur· - 0,10 10 2 2 60 60 - 0.02 2
,..A
rent,IDD - 0,15 15 4 4 120 120 - 0.02 4
Max. - 0,20 20 20 20 600 600 - 0.04 20
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Low (Sink) 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
Current
IOLMin.
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
mA
OUtput High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 1
\OV
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - "
IOHMin. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Volt- - 0,5 5 0.05 - 0 0.05 20 40 60 80 100
age: Low- - 0,10 10 0.05 0 - 0.05
V
LOAD CAPACITANCE ICL1-pF
Fig. 9- Typical propagation delay time as a
Level VOL
Max.
-
I 0,15 15 0.05 - 0 0.05 function of load capacitance (+ or
- trigger to Q, 01.
192
CD4047B Types
STATIC ELECTRICAL CHARACTERISTICS (CONTINUED) I AMBIENT TEMPERATURE
LIMITS AT INDICATED TEMPERATURES ('C)

CHARAC· CONDITIONS Values ai-55, +25, +125 Apply 10 0, F, K, H Packages
TERIS·
TICS
Output Volt·
Vo
(VI
VIN VDD
(V)
0.5
(V)
Values al ·40, + 25, + 85 Apply 10 E Package
-55/ -40 1 +85 1+125 Min. Typ. Max.

5 4.95 4.95
25
5
UNITS
-
Ii
'~
!Ill
age: High·
L..evel,VOH
Min.
-
010
0,15
10
15
9.95
14.95
9.95
14.95
10
15
-
- V
Ii
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, VIL 1,9 10 3 - - 3 U 10 CAl "TANe ·ICLI":-,.
Max. 1.5,13.5 - 15 4 4 V Fig. 10-Typical transition time as a function
Input High 0.5,4.5 - 5 3.5 3.5 - - of load capacitance.
Voltage, 1.9 - 10 7 7 -
VIH Min. 1.5,13.5 - 15 11 11 - - 4 AMBIENT TEMPERATURE ITA ,. 25-C
, ex· r"F
Input Cur·
rent liN
Max.
- 0,18 18 ±0.1! ±0.1! ±1 1±1 - ± 105 ±0.1 JAA II
\ ""
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 2S ·C, Input t r , tf = 20 ns,

CL = SOpF, RL = 200kQ ..
o 6 8 10 12 14 16 18 20
SUPPLY VOLTAGE 1'.1001-'.1
VDD LIMITS
(VI Min. Typ. Max. Fig. II-Typical astable oscillator or Q. Q
period accuracy vs. supply voltage.
Propagation Delay Time: tpHL, tpLH 5 - 200 400
Astable, Astable to Osc. Out
10 - 100 200
15 - 80 160 4 MBIENT TEMPERATURE ITA ,- 2!5"C
ex. 0.01 ,.F
Astable, Astable to Q, Q - 10
5 -
-
350
175
700
350
3
15 - 125 250
5 - 500 1000
+ or - Trigger to Q, Q 10 - 225 450
15 - 150 300
5 - 300 600 ~ -I
Retrigger to Q, Q 10 - 150 300 o
15 - 100 200
ns
2 -2
~
External Reset to Q, Q
5 250 500 -,
10 -
15 -
100
70
200
140 -. o 6 8 10 12 14 16 18 20
Transition Time: tTHL, tTLH

5 - 100 200 SUPPLY VOLTAGE (VDol-V
Osc. Out, Q, Q
10 - 50 100 Fig. 12- Typical astable oscillator or Q, "(f
15 - 40 80 period accuracy vs. supply voltage.
Minimum Input Pulse Width: tw

5 - 200 400
+ Trigger, - Trigger
10 - 80 160 8 AMBIENT TEMRERATURE (TA 1'2!5"C
15 - 50 100 ex -rooD pF
5 - 100 200
Reset 10 - 50 100
15 - 30 60 IOkA
5 - 300 600 I yo. AND 10Mn
Retrigger 10 - 115 230 IOOkn
15 - 75 150 ·2
5
Input Rise and Fall Time:
All Inputs
tr,tf 10 Unlimited jAs -.
Q or Q Deviation from 50%
15
5. - ±0.5 ±1
-.
Duty Factor
10 - ±0.5 ±1 % 6 8 10 12 14 16 18 W
15 - +0.1 +0.5 SUPPLY VOLTAGE IVool-V
Input Capacitance, CIN

Any
Input - 5 7.7 pF Fig. 13- Typical astable oscillator or Q,
period accuracy vs. supply voltage.
a-
193
CD4047B Types
ex.e.o! ",F
R -100 til.
-3 _ ~ , ~ ~ M " _ ,~ _
'"_ _ ~ , ~ ~ M ~ _ ~ ~
-2
__ ~ • ~ ~ M ~ •• ~ _
AMBIENT TEMPERATURE (TA )_·c AMBIENT TEMPERATURE (T A J- ·c AMBIENT TEMPERATURE (TA J_·C
Fig. 14- Typical astable oscil/ator or Q, 'Q Fig. 15- Typical astable oscil/ator or Q, Q Fig. 16-Typical astable oscillator or Q, if
period accuracy vs. ambient temper- period accuracy vs. ambient temper- period accuracy vs. ambient temper-
ature (ultra-low frequency). ature (low frequency). ature (medium frequency).
Cxs 1000 pF RX.IO ktl.

10 RX=10ktl. SUPPLY VOLTAGE (Voo'- 5V
>- 8
~
~ 6 "n
, IOkn
IOOkn
~ 10 10kn IMnAND 10Mn
Ikn
IOV.I~V
~ Rx,.IOO kn,IMn,IOMn
Q
Q
0.01 F,O.I,.F, I F
IOV AND 15V
~ 0
-4 -8
_ _ ~ , ~ ~ M ~ ~ ~ ~
~35 -15 5 25 45 65 85 105 125 145 0> 5 10 I!I 20 25

AMBIENT TEMPERATURE ITA )- ·c AMBIENT TEMPERATURE ITA J_·C
92~S"l2947
SUPPLY VOLTAGE (VDol-Y 92C5-52948
Fig. 17- Typical astable oscillator or Q, l1 Fig. 18- Typical astable oscillator or Q, Q Fig. 19- Typical output pulse-width variations
period accuracy vs. ambient temper- period accuracy vs. ambient vs. supply voltage.
ature (high-frequency). temperature.
I- 8 AMBIENT TEMPERATURE ITA )*25·C 8

8 AMBIENT TEMPERATURE ITA'=25°C ~ Rx=IOOkn
~ 6 ex = o.II'-F ~ 6 ex slOOO pF ~ 6 SUPPLY YOLTAGE tYoo)-' V
ffi ffi
~, ~ 4 ~ 4
i5 Ii g
~ 2 ~ 2
~ R 01 Mn AND IOn O.OOI,.F
~ ~
% 0
10 Mn IOkn,lOOkQ',1 MnAND IOMn IOOktl.
10 kSl
0.' F 0.'.
O.OII<F
RX_10kD.,IOOkn,IMtl.
0
'%
,~
10 15 20 ~ 5 10 15 20 2. -35 -15 25 45 65 85 '0'5 125 '45

SUPPLY VOLTAGE IVooJ-V SUPPL.Y VOLTAGE {VoOI-V AMBIENT TEMPERATURE ITA)-·C
Fig. 20- Typical output pulse· width variations Fig. 21- Typical output pulse-width Fig. 22- Typical output pulse-width variations
vs. supply voltage. variations vs. supply voltage. vs. ambient temperature.
CX·'OOOpF
ffiu 2
SUPPLY YOLTAGEIYOD)·'V.IOY
~
~ 0 fOOkn
RX-IMn
~
~ ..
, Mn
>-
~
~ -10 10M
-~
-55 -35, -15 5 25 45 65 85 105 125 145
AMBIENT, TEMPERATURE IT A )_·C AMBIENT TEMPERATURE I TA)-
AMBIENT TEMPERATURE ITA I-·C
Fig. 23- Typical output pulse-width variations Fig. 24- Typical output·pulse-width variations Fig. 25- Typical output pulse-width variations
vs. ambient temperature. vs. ambient temperature. vs. ambient temperature.
194
CD4047B Types
LO~ ASTABLE MOCE L06 ASTABLE MODE ASTABl.E MODE
SUPPLY VOLTAGE IVCC]'~V SUPPLY VOLTAGE IVOOI-IOV SUPPLY VOLTAG1E IVocl-15V
lO't--+--+-+-+--+--j---l 1O'
.
~
,
lO't--+--+-+-+--+---. ~.~ o.~
- v"
'0 , o·
, _"0·..___0
10 '0'
10'+-+-+---''-1---+--+--11--1 1O'
10'
100 _10 10Z 10:5 104 10° 101 10 2 10:5 10' 10 5 lif 10
, _10
, 10
, 10
, 10
,
OOR Q FREQUENCY III-Hz OOR 0: FREOUENCY CO-Hz Q OR Q FREQUENCY If 1 - Hz
Fig. 26- Typical power dissipation vs. output Fig. 27- Typical power dissipation vs. output Fig. 28-Typical power dissipation vs. output
frequency (V 00 = 5 Vi. frequency (VOO = 10 Vi. frequency (VOO = 15 Vi .
voo
o
vss
INPUTS
}-:"'o·~;
Voo
NOTE:
Voo
~
VSS
'-_-,--~...J
NOTE:
MEASURE INPUTS
SEQUENTIALLY,
CONNECT ALL UNUSED
INPUTS TO EITHER
•
VSS TEST ANY COMBINATION
OF INPUTS EXCEPT PIN 3 Voo OR VSS·
92CS·27441Rl VSS
Fig. 30-lnput·voltage test circuit. Fig. 31-lnput·leakage·current

Fig. 29-Qulescent device current test circuit.
test circuit.
VTR
1. Astable Mode Design Information Typ: VTR=0.5 VOO tA = 4.40 RC -RCln - - ;
A. Unlt·to·Unlt Transfer·Voltage Min: VTR=0.33 VOO tA = 4.62 RC 2VOO
Variations - The following analysis Max: VTR = 0.67 VOO tA = 4.62 RC
presents variations from unit to unit as a typically, t1' 1.38 RC
function of transfer·voltage (VTR) shift
(33% -67% VOO) for free·running thus IfitA - 4.40 Rclis used, the variation
(astable) operation. will be + 5%, 0% due to variations In
transfer voltage. (VTR)~VOO - VTR)
-RCln--':"'-':"'-~---
TERMINALI3~
B. Variations Due to VDO and Tempera- (2V OO - VTR)(2VOO)
TERMLNALIO~ ture Changes - In addlflon to variations
~IA-1 from unit to unit, the astable period varies
where tM = Monostable mode pulse.
with VOO and temperature. Typical varia·
92CS-20027
tions are presented In graphical form In width. Values for tM are as follows:
Fig. 32-Astable mode waveforms. Figs. 11 to 18 with 10 V as reference for
voltage variations curves and 25'C as Typ: VTR = 0.5 VOO tM=2.48 RC
reference for temperature variations Min: VTR=0.33 VOO' tM=2.71 RC
curves. Max: VTR = 0.67 VOO tM=2.48 RC
t1 -RC In _ _ __ II. Monostable Mode Design Information
The following analysis presents varia- thus isltM - 2.48 RCJ.iS used, the variation
VOO + VTR will be +9.3%, _Oo~ due to variations in
tions from unit to unit as a function of
typically, t1 1.1 RC transfer·voltage (VTR) shift (33% - 67% transfer voltage.
V DO) for one·shot (monostable) operation. Note:
Voo - VTR In the astable mode, the first positive half
-RC In cycle has a duration of tM; succeeding
2VOO - VTR durations are tA/2.
typically, t2 1.1 RC TERMtNALB~ In addition to variations from unit to unit,
the monostable pulse width varies with
TERMINAL 13 ~ VOO and temperature. These variations
are presented in graphical form in Fig. 19
TERMINALIO~
(VTR)(VOO - VTR) 92C5-20028 to 26 with 10 V as reference for voltage·
-2 RC In - - -_ _ _-.:...-.:..._ variation curves and 25'C as reference for
(VOO + VTR)(2VOO - VTR) Fig. 33-Monostable waveforms. temperature-variation curves.
195
CD4047B Types
III. Retrlgger Mode Operation larger than the CMOS "ON" resistance tion of leakage current in the circuit, as
The CD4047B can be used in the retrigger in series with it, which typically is hundreds shown in the static electrical
mode to extend the output·pulse duration, of ohms. In addition, with very large values characteristics. For dynamic operation,
or to compare the frequency of an input of R, some short-term instability with the power needed to charge the external
signal with that of the internal oscillator. respect to time may be noted. timing capacitor C is given by the follow·
In the retrigger mode the input pulse is ing formulae:
applied to terminal 12, and the output is The recommended values for these com- Astable Mode:
taken from terminal 10 or 11. As shown in ponents to maintain agreement with P = 2CV 2f. (Output at
Fig. 34 normal monostable action is ob· terminal No. 13)
tained when one retrigger pulse is ap·
plied. Extended pulse duration is obtain·
P =4CV2f. (Output at
terminal Nos. 10 and 11)
ed when more than one pulse is applied.
Monostable Mode:
j L p = (2.9CV2) (Duty Cycle)
T
OSCOUTPUT
TERMINAL 13
~"t 'Jiil!2.JiihL ~ ~
(Output at terminal Nos. 10 and 11)
'RE L
The circuit is designed so that most of the
Fig. 34-Retrigger-mode waveforms. total power is consumed in the external
components. In practice, the lower the
For two input pulses, tRE = t1' + t1 + previously calculated formulas without values of frequency and voltage used, the
212. For more than two pulses, the output trimming should be: closer the actual power dissipation will
pulse width Is an integral number of time C;;' 100 pF, up to any practical value, for be to the calculated value.
periods, with the first time period being astable modes; Because the power dissipation does not
t1' + tf!' typically, 2.48RC, and all subse- C;;' 1000 pF, up to any practical value for depend on R, a design for minimum power
quent time periods being t1 + t2, typical· dissipation would be a small value of C.
IY,2.2RC. monostable modes.
10kQ.;R.;1MQ The value of R would depend on the
desired period (within the limitations
IV. Extemal Counter Option VI. Power Consumption discussed above). See Figs. 27, 28, and 29
Time tM can be extended by any amount In the standby mode (Monostable or for typical power consumption in astable
with the use of external counting cir· Astable), power dissipation will be a func- mode.
cuitry. Advantages include digitally con-

trolled pulse duration, small timing
capacitors for long time periods, and ex·
tremely fast recovery time. A typical i m·
plementation is shown in Fig. 35. The
pulse duration at the output is
text = (N - 1) (tA) + (tM + tA/2)

where text = pulse duration of the
cir·
cuitry, and N is the number of counts
used.
92CS-29041
Fig. 35-lmplementation of external counter

option.
V. Tlming·Component Limitations
The capacitor used in the circuit should
be non·polarized and have low leakage
(I.e. the parallel reSistance of the
capacitor should be at least an order of
magnitude greater than the external
resistor used). There is no upper or lower Dimensions in parentheses are in millimeters and The photographs and dimensions of each CMOS chip
limit for either R or C value to maintain are derived from the basic inch dimensions as in· wafer is separated into individual chips. the angle of
oscillation. dicated. Grid graduations are in mils (10-3 inch). cleavage may vary with respect to the chip face for
However, in consideration of accuracy, C chip, therefore, may differ s/ighfly 'rom the nominal
must be much larger than the inherent dimensions shown. The user should consider a tolerance
stray capacitance in the system (unless of -3 mils to +16 mils applicable to the nominal
dimensions shown.
this capacitance can be measured and Dimensions and pad layout for CD4047B.
taken into account). R must be much
196
CD4048B Types
CMOS Multifunction BINARY CON TROt. INPUTS
FuNCTION CONTROL
Expandable a-Input Gate ---

t it KV 3-STATE
r-
K jb CONTROL
High-Voltage Types (20-Volt Rating) 10 7 9 2
14
INPUTS B - 13
c- 12
The RCA-CD4048B is an 8-input gate having 0-11
four control inputs_ Three binary control EXPANO- 15
inputs - Ka, Kb, and Kc - provide the In addition to the eight input lines, an I Ou~PUT
implementation of eight different logic func-
tions_ These functions are OR, NOR, AND,
NAND,OR/AND,OR/NAND,AND/OR and
EXPAND input is provided that permits the
user to increase the number of inputs into a
CD4048B (see Fig_ 2)_ For example, two
1'--
INPUTS F - 5
G- 4
H- ,
AND/NOR_ CD404BB's can be cascaded to provide a vss·a

A fourth control input, Kd, provides the l6-input multifunction gate_ When the VOO'16
user with a 3-state output_ When control in- EXPAND input is not used, it should be 'JltS-i'2('49
put Kd is high, the output is either a logic connected to VSS-

Functional Diagram
1 or a logic 0 depending on the inner states_ The CD4048B-series types are supplied in
When control input Kd is low, the output is 16-lead hermetic dual-in-line ceramic pack-
•
an open circuit_ This feature enables the ages (D and F suffixes), 16-lead dual-i n-line
user to connect this device to a common plastic packages (E suffix), 16-lead ceramic
bus line_ flat packages (K suffix), and in chip form (H
suffix). Features:
• Three-state output
MAXIMUM RATI NGS, Absolute-Maximum Values:
• Many logic functions available in one package
DC SUPPLY-VOLTAGE RANGE, (VCC)
(Voltages referenced to VSS Terminal) -0.5·to +20 V • Standardized, symmetrical output
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to VDD +0.5 V characteristics
DC INPUT CURRENT, ANY ONE INPUT ±10mA • 100% tested for quiescent current at 20 V
POWER DISSIPATION PER PACKAGE (Pol: • Maximum input current of 1 p.A at 18 V
For T A = -40 to +6QoC (PACKAGE TYPE EI •.••.. _ .. 500mW
For TA = +60 to +850 C (PACKAGE TYPE E) ·Derate Linearly at 12 mW/oC to 200 mW (full package-temperature range), 100 nA
For TA = -55 to +100'C (PACKAGE TYPES D, F, K) . • ___ • 500mW at 18 V and 25°C
For TA = +100 to +125'C (PACKAGE TYPES D, F, K) Derate Linearly at 12 mW/oC to 200 mW
• Noise margi n (full package-temperature
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) 100mW range) = 1 Vat VDD=5 V, 2 V at VDD
OPERATING-TEMPERATURE RANGE (TA): = 10 V, 2_5 Vat VDO=15 V
PACKAGE TYPES D, F, K, H -55 to +1250 C • 5-V, la-V, and 15-V parametric ratings
PACKAGE TYPE E _ _ . -40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstg )
• Meets all requirements of JEOEC Tentative
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING): Standard No_ 13A, "Standard Specifications
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max_ for Description of 'B' Series CMOS Devices"
Applications:
Ay
• Selection of up to 8 logic functions
NOR OR NAND ANa
• Digital control of logic
A~ A~ A~
C 0 C 0 C 0 • General-purpose gating logic
E , ; 0
E F E F - Decoding
G " G " G " G "
EXP EXP EXP EXP - Encoding
OR/AND OR/NAND ANDIOR AND/NOR
;~~~;~;~ Fig. 1 - Basic logic configurations.

92CM-12250
K.
J(OUTPUT)
INPurs1
Kb
4
•
6
16
"
"
"
10
VDO
EXPAND
"12 ~}INPUTS
K,
Vss 9 K,
TOP VIEW

For maximum reliability, nominal operating conditions should be selected so that TERMINAL ASSIGNMENT
LIMITS
CHARACTE R ISTIC UNITS
MIN. MAX.
Supply-Voltage Range (For TA = Full Package
3 18 V
Temperature Range)
197
CD4048B Types
K.
*Ka *Kb *Kc *Kd

II
~ ~ ~.
1:=
II
.------=----' ,T, ft ," _. VDD Ii
d
r
I I
ORAIN-TO-SOURCE VOLTAGE (Vcsl-V
g-"'." _. ,.~.
J
NETWORK
Vss
I I
DRAIN-TO-SOURCE VOLTAGE (Vasl-V
NOR NAND
"~
13
"
"I '
.
I
i Ka -Kb-Kc
0-0-0
DRA1N- TO- SOURCE VOLTAGE
-15
AMBIENT TEMPERATURE ITAt-25·C
-10
(Vasl-V
-5
GATE-TO-SOURCE VOLTAGE (1I65)--5V

AND OR ANDIOR
-IOV
AND/NOR ORINAND ORlAND

-15V
92CS-22252
Fig. 3 - Actual-circuit logic configurations. Fig. 8 - Typical output high (source)
DRAIN-TO-SOURCE VOL.TAGE tVosl-V
APPLICATIONS OF EXPAND INPUT
J (OUTPUTI
vDD
12-INPUT ORlAND GATE 92CS-20240

J = (A+B+C+O)' (E+F+G+H)· (XI +X2+X3+JC~)
Fig. 4 - 12-input OR/AND gate. Fig. 5 - 16-input NOR gatB. current characteristics.
198
CD4048B Types

CONDITIONS Values at -55, +25, +125 Apply 10 D, F, K, H Packages
CHARACTER- Values at -40, +25, +85 Apply to E Package
UNITS
ISTIC +25
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min_ Typ_ Max_
Quiescent Device - D,S 5 0.25 0.25 7.5 7.5 - 0.01 0.25

Current, - 0,10 10 0.5 0.5 15 15 - 0,01 0.5
IDD Max. _. /lA
0,15 15 1 1 30 30 - 0.01 1
- 0,20 20 5 5 150 150 - 0.02 5
40 60 80 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - CAPACITANCE (CL)-pF
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - Fig. 10 - Typical propagation delay time
IOL Min. (logic inputs to output)
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
rnA as a function of load capacitance.
Output High 4.6 D,S 5 -0.64 -0.61 -0042 -0.36 -0.51 -1 -
(Source) 2.5 D,S 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
Output Voltage:
Low-Level,
13.5
-
0,15
D,S
15
5
-4.2 -4
0.05
-2_8 -2.4 -3.4
-
-6.8
0
-
0.05
I
VOL Max.
- 0,10 10 0.05 - 0 0.05
.- 0,15 15 0.05 ~
0 0.05
V
High-Level. - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low ~.4_5 - 5 1.5 - - 1.5
Voltage. - 10 3 - - 3
1,9
. VIL Max.
1.5,13_5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. - -
1.5,13_5 - 15 11 11
I nput Current
0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 /lA
liN Max.
3-State Output Fig. 11 - Typical transition time vs. load capacitance.

0,18 0,18 18 ±Oo4 ±Oo4 ±12 ±12 - ±10-4 ±Oo4 /lA
Current, lOUT
IMPLEMENTATION OF EXPAND INPUT FOR 9 OR MORE INPUTS
OUTPUT FUNCTION OUTPUT BOOLEAN

·
10 : AMBIENT TEMPERATURE ITA I-25°C
FUNCTION NEEDED AT
EXPAND INPUT
EXPRESSION LOAD CAPACITAN~E I 'IC I'·1 50 "I.
• 2
-ti ~~.~
~o" ~~ YL
··
~
NOR OR J-(A+B+C+D+E+F+G+H)+(EXP) of
- .
z r,,"'" 4-
NOTE: S - 4,o.j-9' -,'-I-~
OR OR J=(A+B+C+D+E+F+G+H)+(EXP) 2
~J03
Refer to FUNCTION
~ ~
I~
AND NAND J=(ABCDEFGH)-(EXP) TRUTH TABLE for <; •
connection of unused ~ 2
NAND NAND J=(ABCDEFGH)-(EXP) 0 102.
inputs.
OR/AND NOR J=(A+B+C+D)-(E+F+G+H)'(EXP)
u
~
:P'
OR/NAND
AND/NOR
NOR
AND
J=(A+B+C+D)'(E+F+G+H)'(EXP)
J-(ABCD)+(EFGH)+(EXP)
!l 10
· ... ...
2
'I
ro
2
~
2
INPUT FREQENCY (tr l -

4 ••
~
2 4 ••
kHz
~
2 ...
92C5-31623
~
Fig. 12 - Typical power diSSipation as a function of

AND/OR AND J=(ABCD)+(EFGH)+(EXP) input frequency.
Note: ~EXP) designates the EXPAND functio:" (i.e., Xl+X2+ ... XN).
199
CD40488 Types
DYNAMIC CHARACTERISTICS at TA=250 C. CL =50 pF. Input t r .4=20 ns.
R L=200 kn unless otherwise specified
TEST CONDIT~ LIMITS
CHARACTERISTIC VDD All Package Types UNITS
V Typ. Max.
Propagation Delay: tpHL.tpLH 5 300 600
Inputs to Output and 10 150 300
Ka to Output 15 120 240
Kb to Output 5 225 450
10 85 170
15 55 110
Kc to Output 5 140 280
10 50 100
15 40 80
ns
Expand Input to Output 5 190 380
10 90 180
15 65 130
3·State Propagation Delay: 5 80 160
RL=l kn
Kd to Output tpHZ.tpLZ 10 35 70
See Fig.21
tpZH·tpZL 15 25 50
Transition Time: tTH L.tTLH 5 100 200
10 50 100
15 40 80
Input Capacitance: CI Any Input 5 7
pF
3·State Output Capacitance 5 10
FUNCTION TRUTH TABLE

Voo
OUTPUT UNUSED
BOOLEAN EXPRESSION Ka Kb Kc
FUNCTION INPUT*
NOR J A+B+C+D+E+F+G+H 0 0 0 VSS

OR J=A+8+C+D+E+F+G+H 0 0 1 VSS
OR/AND J=(A+8+C+D)-(E+F+G+H) 0 1 0 VSS
OR/NAND J-(A+B+C+D)-(E+F+G+H) 0 1 1 VSS
AND J=ABCDEFGH 1 0 0 VDD
NAND J=ABCDEFGH 1 0 1 VDD
AND/NOR J=ABCD+EFGH 1 1 0 VDD
AND/OR J=ABCD+EFGH 1 1 1 VDD
Kd=l Normal Inverter Action
Kd=O High Impedance Output
EXPAND Input=O * See Figs. 1,2,3.4, and 5.
TEST CIRCUITS· STATIC MEASUREMENTS
V oD
VCUTQVDOOUTP~UT: v~NPu(J'
'w ::~._
INPUTS , - - - - ' - - ,
o
Vss
o a ~ SEQUENTIALLY,
YIL - Vss TO BOTH VODANOVSS
-= CONNECT ALL UNUSED
INPUTS TO EITHER
NOTE Yoo OR Vss
VSS ~~srN~U~~OMBINATION VSS
92CS-21441RI
V55
Fig. 14 - Ouiescent device current Fig. 15 - Input voltage test Fig. 16 - Input current test circuit.
test circuit. circuit.
200
CD4048B Types
TEST CIRCUITS· DYNAMIC MEASUREMENTS
VDD
OUTPUT I.
~~'~5o";~ I.
10
INPUT
13
INPUT -50"1. JNPUT~50%
'. 12
"
10
9
OUTPUT OUTPUT ~=-~g~
tTHl -I ~ ~ ~tTLH
Vss 92CS-31671 92CS-22264 92CS-22265
Fig. 17 - Test circuit for 'PHL' Fig. 18 - Waveforms for tpHL Fig. 19 - Waveforms for tTHL
'THL- and 'TLH (AND) and tpHL (AND). and tTLH (AND).
measurements.
Voo
'-------4_o'
92C5-31674
92CS_31669 0VSS
Fig. 20 - Test circui' for 'PZL- 'PZH' 'PLZ' Fig. 21 - Waveforms for 'PZL' 'PZH'
and 'PHZ (AND). 'PLZ' and 'PHZ (AND).
o 10 20 30 40 50 60 70 77
Dimensions and pad layout for CD4048BH. The photographs and dimensions of Bach CMOS chip
represent B chip when it is part of the wa/ef. When the
wafer is separated Into individual chips. the angle of
Dimensions in parentheses are in millimetef$ and are cleavage may vary with respect to the chip face lor
derived from the basic inch dimensions as indicated. different chips. The actual dimensions 01 the isolated
Grid graduBtions are in mils (10-3 inchJ. chip, ,hat.fofe. may diller slightly from the nominal
dimensions shown. The user should consider a toleranca
of -3 mUs to +16 mils applicable to the nominal
dimensions shown.
201
CMOS A~ GoA
Hex Buffer/Converters Features: B~ Hoe
• High sink current for driving 2 TTL loads
• High-to-Iow level logic conversion c~ I>e
High-Voltage Types (20-Volt Rating) • 100% tested for quiescent current at 20 V
• Maximum input current of 1 IlA at 18 V over full package- o !{>E Joe
CD4049UB-lnverting Type temperature range; 100 nA at 18 V and 25°C
CD4050B-Non-lnverting Type • 5-, 10-, and 15-volt parametric ratings
~ 14.1',_ 15
"~L'F
Applications: Vee _,_
• CMOS to DTLlTTL hex converter Vss -"-
The RCA-CD4049UB and CD4050B are in- Ne -,3
verting and non-inverting hex buffers, respec- • CMOS current "sink" or "source'" NC -,6
tively, and feature logic-level conversion driver CD4049UB
using only one supply (voltage (VCC)' The • CMOS hlgh-to-Iow logic-level FUNCTIONAL DIAGRAM
input-signal high level (V IH ) can exceed the converter
VCC supply voltage when these devices are
used for logic-level conversions. These da-
vices are intended for use as CMOS to
DTLfTTL converters and can drive directly
two DTLfTTL loads. (VCC=5 V, VOL';;;0.4 V, MAXIMUM RATINGS, Absolute-Maximum Values:
and IOL;l! 3.3 mA.) DC SUPPLY-VOLTAGE RANGE, IVcc)
The CD4049UB and CD4050B are desivnated IVoltages referenced to VSS Terminal) -{l.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to +20.5 V
as replacements fur CD4009UB and CD401 OB,
DC INPUT CURRENT. ANY ONE INPUT ±IOmA
respectively. Because the CD4049U Band POWER DISSIPATION PER PACKAGE IPD):
CD4050B require only one power supply, For TA = -40 to +60 oC IPACKAGE TYPE E) . . . . . . . .. 500mW
they are preferred over the CD4009UB and For T A = +60 to +850 C IP!,CK!,GE TYPE E) . . . Derate Linearly at 12 mW,aC to 200 mW
CD40l0B and should be used in place of the For TA = -55 to +100"C (PACKAGE TYPES 0, F, K) . . ....... , 500mW
CD4009UB and CD40l0B in all inverter, cur- For TA = +100 to +1 25°C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mW/oC to 200 mW
rent driver, or logic·level conversion appli- DEVICE DISSIPATION PER OUTPUT TRANSISTOR
cations. In these applications the CD4049UB FOR TA = FULL PACKAGE·TEMPERATURE RANGE IAII Package Types) loomW
and CD4050B are pin compatible with the OPERATING·TEMPERATURE RANGE ITA):
CD4009UB and CD40l0B respectively, and PACKAGE TYPES D. F, K. H. . . . . . -55 to +1 25°C
can be substituted for these devices in existing ~ACKAGE TYPE E . . . . . . . . . -40 to +85 0 C
as well as in new designs. Terminal No. 16 is STORAGE TEMPERATURE RANGE ITstg ) . • -65 to +150°C
not connected internallyon the CD4049UB or lEAD TEMPERATURE lOURING SOLDERING):
CD4050B, therefore. connection to this At distance 1/16 ± 1132 inch 11.59 ±0.79 mm) from case for lOs ma •.
terminal is of no consequence to circuit
operation. For applications not requiring
high sink-current or voltage conversion, the RECOMMENDED OPERATING CONDITIONS at TA=25 0 C, Except as Noted.
CD4069UB Hex Inverter is recommended. For maximum reliability, nominal operating conditions should be selected so that
The CD4049UB and CD4050B types are
supplied in Ill-lead hermetic dual-in-line LIMITS
ceramic packages (0 and F suffixes), Ill- CHARACTERISTIC UNITS
Min. Max.
lead dual-in-line plastic packages (Esufflx),
11l-Iead ceramic flat packages (K suffix), Supply·Voltage Range (VCC) (For T A=Full Package·
3 18 V
and In chip form (H suffix). Temperature Range)
Input Voltage Range (VIN) Vee 18 V
*The CD4049 and CD4050 have high-to-low-level voltage conversion c,apahllllY hUI nol
low·to-high.level; therefore it is recommended that V 1N ~ Vee-
Vee
A
~ G·A
B~ H."
~ r·e
D~ JoO
Jl R
E~ "E
IN
r~ L"
Vee_'_
vss-"-
Ne :13
NC '16
vss \Iss
CD4050B
FUNCTIONAL DIAGRAM (0 ) I b)
92CS-20117RI
Fig. I-aJ Schematic diagram of C04049UB. 1 of 6 identica' units;
b) Schematic diagram of CD4050B, 1 of 6 identical units.
202
STATIC ELECTRICAL CHARACTERISTICS AMBIENT TENPERAT\JRE 1T.'-2:5"C
,SUPPLY VOLTAGE 1Vee'"!5 v
Limits At Indicated Temperatures (OC)

CHARAC· CONDITIONS Values at -55, +25, +125 Apply to 0, F, K, H Pkgs. UNITS
TERISTIC Values at -40,+25, +85 Apply to E Package
Vo VIN VCC -55 -40 +85 +125 +25 MA)lIMUM
(V) (V) (V) Min. Typ. Max.
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
/lA
Current, I DD - 0,15 15 4 4 120 120 - 0.02 4
Max. - 0,20 20 20 20 600 600 - 0.04 20 I 2 ,
Output Low 0.4 0,5 4.5 3.3 3.1 2.1 1.8 2.6 5.2 - INPUT VOLTAGE {Vxl-V
(Sink) 0.4 0,5 5 4 3.8 2.9 2.4 3.2 6.4 - Fig. 2-Minimum and maximum voltage
Current 0.5 0,10 10 10 9.6 6.6 5.6 8 16 - transfercllaracteristics for CD4049UB.
IOL Min. 1.5 0,15 15 26 25 20 18 24 48 -
rnA
•
Output High 4.6 0,5 5 0.81 -0.73 -0.58 -0.48 -0.65 -1.2 - ,
(Source) 2.5 0,5 5 -2.6 -2.4 -1.9 -1.55 -2.1 -3.9 -
'MB lENT TEMPERATURE ITA10Z50C\!
supp LY VOLTAGE 1Vcc"!! V ".
I
II ,.. III:!
',.
Current 9.5 0,1(\ 10 -2.0 -1.8 -1.35 -1.18 -1.65 -3.0 - Hili nl! !ll! 11:1 !i:! .t,.
IOH Min. 13.5 0,15
- 0,5
15 -5.2 -4.8 -3.5
0.05
-3.1 -4.3
-
-8.0
0
-
0.05 I . !H1l !I! III''' Hit :! I:::
t··,..
Output Voltage: 5
~ , :!d
t!MIN'MUM
l:i d!i 1'" /,
Low·Level, - 0,10 10 0.05 0 0.05
t, fT.. , . ..,
i •••
• 'MAXIMUM
I·',
VOL Max. - 0,15 15 0.05 - 0 0.05 ~ , n 1:1! :::: ;t:: .... II.'
V ~ ,.. .... I.t·

I'"
Output Voltage: - 0,5 5 4.95 4.95 5 -

, t:: .... ,I,· .... ,...
.... ,,' '1',
!:~ ~
High·Level, - 0,10 10 9.95 9.95 10 - li
VOH Min. - 0,15 15 14.95 14.95 15 - Hit t· ..
• I, I;:: .... .... 11"

, .... ..j' ....
INPUT VOLTAGE !V11-V
Input Low
4.5 - 5 1 - - 1
Voltage: Fig. 3-Minimum and maximum voltage
9 - 10 2 - - 2
transfer characteristics for CD4050B.
VILMax. - -
13.5 - 15 2.5 2.5
CD4049UB
Input Low AMBIENT TEMPERATURE ITA"
0.5 - 5 1.5 - - 1.5
Voltage: - -
1 - 10 3 3
VIL Max.
- 4 - - 4
t
1.5 15
CD4050B
V
Input High
0.5 - 5 4 4 - -
Voltage:
1 - 10 8 B - -
VIH Min.
1.5 - 15 12.5 12.5 - -
CD4049UB
Input High
4.5 - 5 3.5 3.5 - -
Voltage:
9 - 10 7 7 - -
VIH Min.
13.5 - 15 11 11 .- - I 2 3 4 5 6 7
CD4050B ORAIN-TO-SOURCE VOLTAGE tVosl-V
Input Current, ±1O-5

- 0,18 18 ±0.11 ±0.1 ±1 ±1 .- ±0.1 /lA Fig. 4 - Typical output low (sink) current
liN Max. charac teristics.
_A - : , " . ' . '~•• _.v,O."·.. EI:VOSI-'

I AMBIENT TEMPERATURE IT. i.
IOLTAGE.
DRAIN-TO-SOURCE VOLTAGE eVOSl-V

9ZCS-27483AI 92CS·2748:1RI
Fig. 5 - Minimum output low (sink J current Fig. 6 - Typical output high (source) current Fig. 7 - Minimum output high (source) current
drain characteristics. characteristics. characteristics.
203
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=25 0 C; Input t"tf=20 ns,
CL=50pF, RL=200kn
LIMITS
CHARACTERISTIC CONDITIONS ALL PKGS. UNITS
VIN VCC Typ. Max.
Propagation Delay Time: 5 5 60 120
Low·to·High, tpLH 10 10 32 65
CD4049UB 10 5 45 90
15 15 25 50
15 5 45 90
/1S
5 5 70 140
10 10 40 80
CD4050B 10 5 45 90 Fig. 8 - Typical voltage transfer charac-
15 15 30 60 teristics8S a function of temperature
for CD4049UB.
15 5 40 80
High·to·Low, tpHL 5 5 32 65
10 10 20 40
CD4049UB 10 5 15 30
15 15 15 30
15 5 10 20
IlS
5 5 55 110
10 10 22 55
CD4050B 10 5 50 100
15 15 15 30
15 5 50 100
Transition Time: 5 5 80 160
Low·to·High, tTLH 10 10 40 80 INPUT VOLTAGE IV11-V
15 15 30 60
IlS Fig. 9 - Typical voltage transfer charac-
5 5 30 60
teristics as a function of temper-
High·to·Low, tTHL 10 10 20 40 __ .~IJ!"-f~ r::.~4050B.
15 15 15 30 10 ~BIENT TEMPERATURE
Input Capacitance, CI N
CD4049UB - - 15 22.5.
pF
CD4050B - - 5 7.5
10 2 .. 6 8102 2 .. 6110S 2 4 6 8 10• 2 4 6810s

INPUT FREQUENCY (t1 kHl:
,zea-IMI.
Fig. 10 - Typical power dissipation vs. frequency
characteristics.
::. 10. AM81ENT TEMPERATURE ITA '·2~·C ~ ::, 'M.".T TEMPER.TURE IT. I'''',
Vee
l,o~
t Vee
~
~
6 104
INPUTS
~
o
~ Vss
~ 103 ~
~
~ 102 ~
~
*
10 10' 10 10' Vss
INPUT RISE AND FALL TIME 11,,1, J -nl INPUT RISE AND FALL TIME II, ,If 1 - l i t '9lCS-204'!t IA 2
Fig. 11 - Typical power dissipation VS. input Fig. 12 - Typical power dissipation Vi. Fig. 13 - Quiescent device current
rise and fall times per inverter for input rise and fall times per test circuit.
CD4049UB. inverter for CD4050B.
204
COS/Mas 10 II LEVEL TO OTL/TTL 5 V LEvEL
Yee • 5 v
Vee
J:~:~URE
COS/Mas OUTPUT
TO OTL/TTL
I.. :N____--ic 04049
INPUTOvee
OUTPUTS
vee INPU~S J N PUTS
V'H
~
t INPUTS
~ ~ SEQUENTIALLY,
IJIL l TO BOTH Vee ANOVSS

CONNECT ALL UNUSED
NOTE.
TEST ANY ONE INPUT,
I ~;cu~ :~:ITHER IN TERMINAL - 3,5,7,9.II,ORI4
OUT TERMINAL- 2,4,6,IO,I2,OR 15
'.ISS WITH OTHER INPUTS AT Vss
Vee OR'VSS Yee TERMINAl- I
'Vss TERMINAl- a 92CS-ZOlllfll
Fig. 14 - Input voltage test circuit. Fig. 15 - Input current test circuit.
Fig. 16 - Logic-level conversion application.
•
CHIP PHOTOGRAPHS
\
DIMENSIONS AND PAD LAYOUTS
71-79 65 -73
(1.803-2.0061 ( 1.651-1.854)
20
92CM-33556 CD4050BH
CD4049UBH
Dimensions in parentheses 8re in millimeters and are represent a chip when it is par' of the wafer. When the
derived from the basic inch dimensions as indicated. wafer is separated into individual chIps, the angle of
Grid graduations are in mils (10- 3 inchJ. cleavage may vary with respect to the chip face for
chip, ,therefore, may differ slightly from the nominal
dimensiom,shown. The user should considers tolerance
of -3 mils to +16 mils appficab/e to the nominal
dimensions shown.
Voo
Vee ,. ,. Ne vee ,. ,. Ne
G=l
A
2 15
, LoF G;A
,. L-'
,S
F
H="B
•
,.<:"
"
12
Ne
" .·r HoB
"
'2 .-.
Ne
•
e "
10 J'"
I=e
e "
'0 JOO
Vss 9 Vss 0
CllNClUDES
NC. NO CONNECTION 92CS_24480AI NC· NO CONNECTION 92CS.244Blfll f'IKTUflE CAPACITANCE
CD4049UB CD4050B Fig. 17 - Dynamic power dissipation test clrcuil.
205
CD4051 B, CD4052B, CD40538 Types
CMOS Analog
Multiplexers/Demultiplexers·
With Logic-Level Conversion C~:~~~sJ: = :: =~I
~. I. Voo
High-Voltages Types (20-Volt Rating)

Applications:
• Analog and digital multiplexing and demultiplexing
COM OJT/IN -
CHI~~~;S ,;
lNH -
=:3
6
13 -
12-3
II -
o~*
A
VEE _ 7 10 - 8
• A/O and 0/A conversion • Signal gating Vss - 8 9-C
CD4051B - Single a-Channel If CHANNELS ,)2C5<"4-492
CD4052B - Differential 4-Channel Features: IN/OUT
CD4053B - Triple 2-Channel • Wide range of digital and analog signal

levels: digital 3 to 20 V, analog to CD4051B
RCA-C04051 B, C04052B, and C04053B 20 Vp _p Terminal Assignment
analog multiplexers/demultiplexers are digi- • Low ON resistance: 125 n (typ.) over 15
tally controlled analog switches having low Vp_p signal-input range for VOO-VEE = 15 V
ON impedance and very low OFF leakage
current. Control of analog signals up to • High OFF resistance: channel leakage of
20 V peak-to-peak can be achieved by digi- ±100 pA (typ.) @ VOO-VEE = 18 V
tal signal amplitudes of 4.5 to 20 V (if • Logic-level conversion for digital addressing
VOO-VSS = 3 V, a VOO-VEE of up to 13 signals of 3 to 20 V (VOO-VSS = 3 to 20
V can be controlled; for VOO-VEE level VI to switch analog signals to 20 V Pop
differences above 13 V, a VOO-VSS of at (VOO-VEE = 20 VI; see introductory text
least 4.5 V is required). For example, if
VOO=+4.5V, VSS=O, and VEE = -13.5 V,
• Matched switch characteristics: RON =
5 n (typ.1 for VOO-VEE = 15 V YCHANNELS
lNIOUT 2
10 I. I. Voo
~ t X Cl~~~~~LS
analog signals from -13.5 V to +4.5 V can • Very low quiescent power dissipation under COMMON "y" OUT lIN '""
be controlled by digital inputs of 0 to 5 V. under all digital-control input and supply Y CHANNELS 13 13 ·COMMON"X·OUT/IN
These multiplexer circuits dissipate extremely conditions: 0.2 p.W (typ_1 @ VOO-VSS =
INIOUT . I
INH
12 0,3 X CHANNELS
lNIOUT
low quiescent power over the full VOO-VSS VOO-VEE = 10 V VEE "
10 A
Vss
and VOO-VEE supplv-voltage ranges, inde-
• Binary address decoding on chip
pendent of the logic state of the control 92CS-24483
signals. When a logic "1" is present at the • 5-, 10-, and 15-V parametric ratings CD4052B
inhibit input terminal all channels are off. • 100% tested for quiescent current at 20 V Terminal Assignment
The C04051 B is a single 8-channel multi- • Maximum input current of 1 p.A at 18 V
over full package temperature range;
plexer having three binary control inputs, A,
B, and C, and an inhibit input_ The three 100 nA at 18N and 25°C
binary signals select 1 of 8 channels to be • Break-before-make switching eliminates
turned on, and connect one of the 8 inputs channel overlap
to the output_
The C040528 is a dfferential 4-channel multi- RECOMMENOED OPERATING CONOITIONS AT TA =25 0 C (Unless Otherwise Specified I
plexer having two binary control inputs, A
and B, and an inhibit input. The two binary For maximum reliability, nominal operating conditions should be selected so that operation
input signals select 1 of 4 pairs of channels is always within the fol/owing ranges. Values shown apply to aI/ types except as noted.
to be turned on and connect the analog in-
~uts to the outputs_ CHARACTERISTIC VDO Min. Max_ Units
The C04053B is a triple 2-channel multi- Supply-Voltage Range * In certain applications. the external load-resistor
plexer having three separate digital control (TA = Full Package- - 3 18 V current may include both VOO and signal-line
components. To avoid drawing VOO current
inputs, A, 8, and C, and an inhibit input. Temp. Range) when switch current flows into the transmission
gate inputs. the voltage drop across the bidirec-
Each control input selects one of a pair of Multiplexer Switch Input tional switch must not exceed 0.8 volt 'calcu-
channels which are connected in a single- Current Capability* - - 25 mA lated from RON values shown in ELECTRICAL
pole double-throw configuration. CHARACTERISTICS CHART). No VDD cur-
Output Load Resistance - 100 - n rent will flow through RL if the switch current
flows into terminal 3 on the C04051; terminals
The C04051 B, C04052B, and C04053B are 3 and 13 on the CD4052; terminals 4.14. and 15
supplied in f6-lead ceramic dual-in-line on the CD4053.
. packages (0 and F suffixes), 16-lead plaslic
dual-in-line packages (E suffix). 16-lead I. I. voo
ceramic flal packages (K suffix). and in chip
form (H suffix). !""
IN/OUT bl
OUTIIN CX or CY
2
"
"
OUTIIN b~orby
OUTIIN alloray
IN/OUTCX "
12 ::, INIOUT
1M! A
VEE "
10
VSS
•
* When these devices are used as demultiplexers, 92CS-24484
the "CHANNEL IN/OUT" terminals are the
CD4053B
outputs and the "COMMON OUT/IN" terminals
are the inputs. Terminal Assignment
206
CD4051 B, CD4052B, CD4053B Types
DC SUPPLY·VOL TAGE RANGE. (V DD )
(V:oltages referenced t9 VSS or VEE- whichever is more negative) -0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS. -0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT . ±10mA
For T A = -40 to +600 C (PACKAGE TYPE E) . . . . . . . ., 500 mW
For T A = +60 to +850 C (PACKAGE TYPE E) • . Derate Linearly at 12 mW/oC to 200 mW
For T A = -55 to +100°C (PACKAGE TYPES D. F, K) . . • . . • . . • . . . . • . . 500 mW
For TA =+100 to +125°C (PACKAGE TYPES D, F, K) . • • . • Derate Linearly at 12 mW/oC to 200 mW ~ 200
DEVICE DISSIPATION PER OUTPUT TRANSISTOR z
:i 100
G
OPERATING·TEMPERATURE RANGE ITA): o
PACKAGE TYPES D, F. K, H • • • . . • . • • . • . . • • . • . . . .• -55 to +125° C -4 -3 -2 -I 0 I
INPUT SIGNAL VOLTAGE (VIS) - V
PACKAGE TYPE E . • • . • . . • . • • . . . -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg ) -65 to +1500 C Fig.4 - Typical channel ON resistance VI input
LEAD TEMPERATURE (DURING SOLDERING): signal voltage (all types).
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 nim) from case for lOs max. +2650 C
•
6 VOD
q SUPPLY VOLTAGE (VDD-VEEI-IOV
I 300
~
~2~ AMBIENT TEMPERATURE
(TA)- +12S·C
COMMON tl
LOGIC
BINARY
TO ,
OUrllN :i 200
in
LEVEL IOF8
~ 150
C • • CONVERSION DECODER
WITH
INHIBIT z
0 100
INH 6 • ~
~ 50
-10 -1.5 -S -2.S 0 2.5 1.' 10

8 VSS 7 VEE INPUT SIGNAL VOLTAGE (Vi') - V
Fig. 1 - Functional diagram of CD40518. Fig.5 - Typical channel ON resistance VI. input
signal voltage (all types).
X CHANNELS IN/OUT
I
6 VOO "I 600~rrHtHH+H+rrH+HH+~+H++~~~

z
COMMON X
g 5ooH;fHtHllHB
OUT/IN
"'u
A 0 *
LOGIC
BINARY
TO
e
~300
400
B 9 * LEVEL
CONVERSION
I OF 4
DECODER
COMMON Y
OUTIIN z
WITH 0200
lNH 6 *
~
INHIBIT
~ 100
G 0
-10
INPUT SIGNAL VOLTAGE (Vis) - V
Y CHANNELS IN/OUT 92CS-27074RI
Fig.S - Typical channel ON resistance VI. input
Fig. 2 - Functional diagram of CD40528. signal voltage (all types).
.I 300
SUPPLY VOLTAGE (VOO-VEEI.IS V
:!I ': ;1:: u:·!t:
Z0
~250
III !I!!!. "j.
tl
~200 AMBI ENT TEMPERATURE
!I! 1 ::1 ll!
(TAl - +125·C
iii! !;
;
z
~
150
100
qm
;t~~;~m
I;
· ... S!5·C·· .
:i .0
G
0
.7.5 . 1111111111
- 10 - 2.5 0 2.S
INPUT SIGNAL VOLTAGE (Vi. I -
1.5
V
10
UCS-200871t3
Fig.7 - Typical channel ON resistance vs, input
Fig. 3 - Functional diagram of CD40538. signal voltage lall types).
207
ELECTRICAL CHARACTERISTICS
LIMITS at Indicatad Temperature (OC)
CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H Pkgs.
CHARAC- Vi. VEE Vss VDD Values .al -40, +25, +85 apply to E pkgs.
TERISTIC Units
(V) (VI (V) (V)
-55 -40 +85 +125 1 +25
Min. Typ. Max.
SIGNAL INPUTS (Vi.) AND OUTPUTS (VOS)
Quiescent Device 5 5 5 150 150 - 0.04 5 vA
Current, I DO 10 10 10 300 300 - 0.04 10
Max. 15 20 20 600 600 - 0.04 20
20 100 100 3000 3000 - 0.08 100
INPUT SIGNAL VOLTAGE !Vlsl-VOLTS
On-State
Resistance Fig.8 - Typical ON characteristics for
0';;; Vis';;; VOO 850 7 of 8 channels (CD40518i.
0 0 5 :800 1200 1300 - 470 1050
ron Max. 0 0 10 310 330 520 550 - 180 400 n
0 0 15 200 210 300 320 - 125 240
Change in On-
State Resistance
(Between Any
Two Channels) 0 0 5 - - - - - 15 -
l!J. ron 0 0 10 - - - - - 10 - n
0 0 15 - - - - - 5 -
OFF Channel
Leakage Current:
Any Channel
OFF Max. 0 0 18 ±100' ±1000' - ±'0.01 ilOO'
All Cha~~els
nA '0 1 10 102 105
SWITCHING FREQUENCY!tI-kHz
OFF (Common
OUT/IN) Max.
Fig.9 - Typical dynamic power dissipation
Capacitance : vs. switching frequency (CD40518i.
Input, Cis - - - - - 5 -
Output, Cos
~ - - - - - 30 - pF
CD4052 -5 -5 5 - - - - - 18 -
Ci54i)53 - - - - - 9 -
Feedthrough,
Cios
- - - - - 0.2 -
Propagation Delay
Time (Signal In·
put to Output VDD RL:' 200kQ 5 - - - - - 30 60
.n.. CL =50 pF 10 - - - - - 15 30 ns
tr,tf = 20ns 15 - - - - - 10 20
• Determined by minimum feasible leakage measurement for automatic testing.
10 102 10:5
SWITCHING FREQUENCY (f)-.Hz
'0'
Fig. to - Typical dynamic power dissipation

vs. switching frequency (CD40528i.
.
~
10" AMBIENT TEMPEAATURE!T,,' • 25-C
ALTERNATING ~o'" ANO "," PATTER
LOAD CAPACITANCE!C I • so pF
I~I,.
R4f!fJHj
lllll 111
Voo· +15 V Yoo' +7.5 V
0------,
Voo' +5 V
f .~
I Ht~..1 ;; ." W~ TEST CIRCUIT
~ IO]~
-
~
4t, ~-h:
II
, 3
CD4053 2
•
12
c,
: ,
I• "
,0' 6
~
"
~
CL '1511F VEE' -10 V IIEE' -5 V
.}::J
.
'Iss' OV
1,1 ,,1 Idl
" '0 ,0' '0 10
, '"
The ADDRESS (digital-control inputsl and INHIBIT logiC levels are: 92CS-IOOet!lA1
SWITCHING FREQU(NCY(fl- kHI
SiteS-2ZnORI
"0" = VSS and "I" = VDD. The analog signal (through the TGI may
Fig. 11 - Typical dynamic power dissipation swing from VEE to Voo.
vs. switching frequency (CD4053BJ. Fig. 72 - Typical bias voltage••
208
ELECTRICAL CHARACTERISTICS (Cont'd) INPUT STATES

"ON" CHANNEL(S)
INHIBIT C B A
LIMITS at Indicated Temperature (DC)
CONDITIONS Values al -55, +25, +125 Apply to D, F, K, H, Pkg CD4061B
CHARAC· Vis VEE VSS VDD Values at -40,+25,+85, apply to E pkgs 0 0 0 0 0
TERISTIC Uniu
(V) (VI (VI (V) +25 0 1
-55 -40 +85 +125 0 0 1
Min. Typ. Max. 0 0 1 0 2
CONTROL (ADDRESS or INHIBIT) Vc 0 0 1 1 3
Input Low 0 1 0 0 4
Voltage, VIL 0 1 0 1 5
Max. VEE=VSS 5 1.5 - - 1.5 0 1 1 0 6
=VDD
thru RL =1 k!1 10 3 - - 3
0 1 1 1 7
to VSS
15 4 - - 4
X X X NONE
Input High
Voltage, V I H
lk!1
115< 2 J.1.A
5
10
3.5
7
3.5
7
-
- - V 1
CD4062B
on all OFF
Min. Channels 15 11 11 - - INHIBIT B A
0 0 0 Ox, 0"
Input Current,
liN Max.
VIN = 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 }.J.A 0
0
0
0
1
1
1
0
1
lx,ly
2x,2y
3x,3y
I
Propagation Ir, If = 20 ns. CL =50 pF
Delay Time: 1 X X NONE
RL = lk n
Address·ta· CD4053B
Signal OUT
0 0 5 - - - - - 450 720 INHIBIT AorB
(Channels ON
0 0 10 - - - - - 160 320
ns or C
or OFF) See
0 0 15 - - - - - 120 240
0 0 ax or bx or ex
Figs.14,lS,18
-S 0 5 - - - - - 225 450
0 1 ay or by or cy
RL = 1k n,CL = 50 pF 1 X NONE
Inhibil-Io-
I r • If = 20 ns
Signal OUT X = Don't care
(Channellurn-
0 0 5 - - - - - 400 720
Fig. 13 - Truth tabl•••
ing ON)
0 0 10 - - - - - 160 320
ns
--0 0 15 - - - - - 120 240
See Fig. 14 -10 0 5 - - - 200 400
RL = lk n,CL = 50 pF
Inhibil-Io-
I r • If =20 ns
Signal OUT
(Channellurn- 0 0 5 - - - - - 200 450
ing OFF) 0 0 10 - - - - 90 210
ns
0 0 15 - - - - - 70 160
See Fig. 15 -10 0 5 - - - - - 130 300
Input
Capacitance, CI N
(Any Address
- - - - - 5 7.5 pF
92CS-27042RI
or I nhibit Input)
Fig.14 - Waveforms, channel baing

turned ON (RL C 1 kfl.).
TEST CI RCUITS
.--_ _ _ _-tVOO r--_ _ _ _---i VOO
16 16
15 15
14 100
13
"
"
Fig. 15 - Waveforms, channel being

turned OFF (RL = lk n). Fig. 16 - OFF channel leakage current - any channel OFF.
209
CD40518, CD40528, CD40538 Types
TEST CIRCUITS (Cont'd)
ELECTRICAL CHARACTERISTICS (Cont'd)
TEST CONDITIONS LIMITS ,.-_ _ _-;VDD
CHARACTERISTIC Vis VDD RL TYPICAL UNITS

(V) (V) (kO) VALUE
Cutoff (-3-dB)
5- 10 1 CD40S3 30
Frequency VEE = Vss, Vos at Common OUT/IN CD40S2 25 MHz
Channel ON CD4051 20
(Sine Wave Input) 20iog Vos = -3dB
Vis Vos at Any Channel 60
~ 5
~
~
Total Harmonic
Distortion, S-
10
IS
10
~
0.12
%
VEE = VSS,
THO
fis = 1 kHz sine wave
,.-___-;V DD
-40-dB
5- I 10 I 1 CD4053 8
Feedthrough VEE = VSS, Vos at Common OUT/IN CD40S2 10 I.
Frequency CD4051 12 MHz
Vos
(All Channels OFF) 20 log Vis =-4OdB Vos at Any Channel 8
Between Any 2 Channels 3

Between Measured on Common 6
5- 10 1 Sections
-4Q.dB Measured on Any
CD4052
Signal Crosstalk, VEE = VSS, Channel 10
Only
Frequency Vos
2010g- =-4OdB Between
Vis Any 2 In Pin 2, Out Pin 14 2.5
Sections MHz
In Pin 15, Out Pin 14 6 VDD
CD4053 r-----1
Only I.
I~
- 10 10#
VEE=O,VSS=O, tr,tf "13
Address-or-Inhibit- mV 12
65
to Signal Crosstalk =20 ns, Vc = VDD (Peak)
- Vss(Square Wave)
- Peak-to-peak voltage symmetrical about VDO - VEE

2 Fig. 17 - OFF channelloakage current-all
# Both ends of channel channels OFF.
voo VDD
OUTPUT
vo~
Vss CLOCK
IN
~ ~ ~
CD40SI CD4Q52 C04053
Fig. 78 - Propagation delay - address input to signal output.
I.
15
Voo
VDD
"13
12
"
10
Vss Vss Vss

1 PHL AND lPLH 1 PHL AND t PLH t.PHL AND tpLH
CD4051 CD4052 CD4053

'jtc:S-2!045
Fig. 19 - Propagation delay - inhibit input to signal output.
210
TEST CIRCUITS (Cont'd)
'DO 'DO
I. I.
15 15
I. I.
" "
12
92:CS-30932 92C5- 30933

MEASURE < 2 iJoA ON ALL MEASURE <: 2 1-"'''' v" ... lL MEASURE <: 2 p.A ON ALL
"OFF" CHANNELS (e_g. CHANNEL 6) "OFF" CHANNELS (e,g CHANNEL 2x) "OFF" CHANNELS (e_g CHANNEL by)
Fig.21 - Quiescent device current.
Fig. 20 - Input voltage test circuits (noise immunity).
'DO
I
KEITHLEY
VDD 160 DIGITAL
MULTIMETER
x-v VOO
L-____~~------~~PLOTTER
~
Vss
NOTE:
NOTE; MEASURE INPUTS
MEASURE INPUTS SEQUENTIALLY, TO BOTH
92CS -22716
SEQUENTIALLY. TO BOTH VOO AND \Iss CONNECT
Vao AND VSS CONNECT ALL UNUSED INPUTS TO
ALL UNUSED INPUTS TO 92CS-27048 EITHER VOO OR VSS.
Fig.22 - Channel ON resistance EITHER Vao OR \Iss
measurement circuit.
Fig. 23 - Input current.
5 V p-p
rv
5 II p-p
rv -+-fOFFH--.--{
COMMON
r"\....J
92C5-27049 92C5- 27050
Fig.24 - Feedthrough (all types). Fig.25 - Crosstalk between any two channels (all types).
~ v p-p
r"\....J DIFFERENTIAL CD4052 CD4052
SIGNALS
COMMUNICATIONS
LINK
D1FF. OEMULTIPLEXING
MULTIPLEXING
92CS-27051
92.CS-270:52
Fig.26 - Crosstalk between duals or triplets
(CD4052B, CD4053B). Fig.27 - Typical time..cfivision application of the CD4052B.
211
SPECIAL CONSIDERATIONS 102.
In applications where separate power sources
are used to drive VOO and the signal inputs,
the VOO current capability should exceed.
VOO/Rl (Rl = effective external load). This
provision avoids permanent current flow or
clamp aClion on the VOO supply when power
is applied or removed from the CD4051 B
C04052B, or CD4053B. ' 94
2..388)
92CM-35069
Dimen.ion. and pad layout for CD4051BH.

The photographs and dimensions of sach CMOS chip
represent 8 chip when it is part 01 the wafer. When the
wsfer is separated into individual chips, the angl8 of
chip. therefore. may differ slightly flom the nominal
dimensions shown.
Grid Graduations are in Mils (10- 3 inch).
88
8~
'1
o (0 2.0 30 40 50 60 70
82 -90
(2.083-2.2861.
~--------~~y--~~~ 92CS-35067
92CS-35068
Dimensions and pad layout for CD4052BH. Dimensions and pad layout for CD4053BH.
212
CMOS Liquid-Crystal Features:

• Operation 01 liquid crystals with CMOS
Display Drivers circuits provides ultra-low-power displays
High-Voltage Types (20-Volt Rating) • Equivalent ac output drive for liquid- STROBE I. I.
CD4054B - 4-Segment Display Driver
crystal displays - no external capacitor required
BCD \ ~~ - ~ ""
CD4055B - BCD to 7-Segment Decoder/Driver with • Voltage doubling across display, e.g.
VDD - VEE ~ 18 V results in effective
INPUTS I
;~ : " 12
"Display-Frequency" Output
CD4056B - BCD to 7-Segment Decoder/Driver with
36 V POp drive across selected display
DIS, FREQ IN
VEE "
10
segments Vss 9
Strobed-Latch Function
• Low- or high-output level de drive for "* 7-SEGMENT
OUTPUTS
The RCA CD4055B and CD4056B types are other types of displays
single-digit BCD-to-l-segment decoder/driver • On-chip logic·level conversion for different
circuits that provide level-shifting functions input- and output-level swings
on the chip. This feature permits the BCD • Full decoding of all input combinations: CD4056B
input-signal swings (VDD to VSSI to be the 0-9, L, H, P, A,-, and blank positions Terminal Assignment
same as or different from the l-segment • Strobed-latch function-CD40548 Series
output-signal swings (VDD to VEE). For
example, the BCD input-signal swings (VDD
and CD40568 Series
I. I.
I
VDD
• DISPLAY-FREQUENCY (DF) output STROBE 4
to VSS) may be as small as 0 to -3 V, where-
as the output-display drive-signal swing (VDD
for liquid-crystal common-line drive signal-
CD4055B Series (CD40548 Series also:
DISPLAY FREO.IN
OUT4
OUT3
2
,. '5 'N'
STROBE 3
to VEE) may be as large as from 0 to -15V. see introductory text) OUT2 " '2
'N'
STROBE2
OUT I
If VDD to VEE exceeds 15 V, VDD toVSS
should be at least 4V (0 to -4VI.
• Maximum input current of 1 /JA at 18 V
VEE " '0
'N2
STROBE I
Vss 'N'
The l-segment outputs are controlled by over full package temperature range;
the DISPLAY-FREQUENCY (DF) input 100 nA at 18 V and 25 0 C
which causes the selected segment outputs • Noise margin (over full package temper-
to be low, high, or a square-wave output ature range): CD40548 Terminal Assignment
(for liquid-crystal displays). When the DF 1 Vat VDD ~ 5 V
input is low the output segments will be 2 V at VDD ~ 10 V
,.
,.
VDD
high when selected by the BCD inputs. 2.5 V at VDD ~ 15 V DISPLAY FREQ. OUT 'S
l~ ,
'5
When the DF input is high, the output • 5-V, 10-V, and 15-V parametric ratings BCD 2!
segments will be low when selected by the
BCD inputs. When a square-wave is present
IN-PUTS ~
20 " :, f
'2
7-SEGMENT
OUTPUTS
at the DF input, the selected segments will

Applications DISPLAY FREQ. IN
"
VEE '0 b
have a square-wave output that is 1BOo out • Ganeral,purpose displays Vss 9
of phase with the DF input. Those segments • Calculators and meters

92CS-2<l496
which are not selected will have a square- • Wall and table clocks
wave output that is in phase with the input. • Industrial control panels CD40558 Terminal Assignment
DF square-wave repetition rates for liquid- • Portable lab instruments
crystal displays usually range from 30 Hz • Panel meters transferred from input to output by placing
(well above flicker rate) to 200 Hz (well a high voltage level at the strobe input. A
• Auto dashboard displays
below the upper limit of the liquid-crystal low voltage level at the strobe input latches
• Appliance control panels
frequency response). The CD4055B pro- the data input and the corresponding output
vides a level-shifted high-amplitude DF out- ing the corresponding input and strobe lines segments remain selected (or non-selected)
put which is required for driving the common to a low and high level, respectively and while the strobe is low.
electrode in liquid-crystal displays. The applying a square wave to DFIN' The Whenever the level-shifting function is re-
CD4056B provides a strobed-latch function CD40548 may also be utilized for logic-level quired, the CD40558 can be used by itself
at the BCD inputs. Decoding of all input "up conversion" or "down conversion". For to drive a liquid-crystal display (Fig.16 and
combinations on the CD4055B and CD4056B example, input-signal swings (VDD to VSS) Fig.201. The CD4056B, however, must be
provides displays of 0 to 9 as well as L, P, frum +5 to 0 V can be converted to output- used together with a CD4054B to provide
H, A, -, and a blank position.
signal swings (VDD to VEE) of +5 to -5 V. the common DF output (Fig.19). The capa-
The level-shifted function on all three types bility of extending the voltage swing on the
The CD4054B provides level shifting similar permits the use of different input- and out- negative end (this voltage cannot be extended
to the CD4055B and CD4056B independently put-signal swings. The input swings from a on the positive end) can be used to advantage
strobed latches, and common DF control on low level of VSS to a high level of VDD while in the setup of Fig.1B. Fig.,17 is common
the output swings from a low level of VEE to to all three types.
4 signal lines. The CD40548 is intended to
provide drive-signal compatibility with the the same high level of VDD. Thus, the input The CD4054B-, CD4055B-, and CD4056B-
CD4055B and CD4056B 7 -segment decoder and output swings can be selected indepen· series types are available In 16-lead ceramic
types for the decimal point, colon, polarity, dently of each other over a 3-to-18 V range. dual-in-llne packages (D and F suffixes), 16-
and similar display lines. A level-shifted VSS may be connected to VEE when no lead plastic packages (E suffix), 16-lead
high-amplitude DF output can be obtained level-shift function is required. ceramic flat packages (K suffix), and in chip
from any CD40548 output line by connect- For the CD40548 and CD40568, data are form (H suffix).
213
7~SEG·
OUT,
VOD DIS PLAY-

'==::---+-r--'J)l FREQ.OUT
4
VDO Fig.4 - Typical propagation delay time va.
ALL INPUTS ARE load capacitanca, for CD40548.
PROTECTED BY
CMOS PROTECTION
NETWORK AU. INPUTS ARE
PROTECTED BY
CMOS PROTECTION
NETWORK
Vss
92C8-20090R3
92C8-20092R2
Fig. 1 - CD40548 functional diagram.
Fig.2 - CD40558 functional diagram.
,0 5 ALL INPUTS ARE

PROTECTED BY
BCO
[ " , CMOS PROTEcnON
NETWORK LOAD CAPACITANCE (CI.J- pF
INPUTS 22
7- Voo Fig.5 - Typical propagation dalBY time vs. 10Bd

SEGMENT
STROBE
" I
OUTPUTS capacitance for CD4055 and CD40568.
~~~~~~y- 6
92CS-20091 R3
Fig.3 - CD40568 functional diagram.
TRUTH TABLE FOR CD4055B and CD4056B
DISPLAY
INPUT CODE OUTPUT STATE
CHARAC·
23 22 2' 20 a b C d • f 9
,
TER
,, LOAD CAPACITANCE Ie L J- pF
0 0 0 0 1 1 1 1 1 1 0 92.CS-28"'90RI
I
0 0 0 1 0 1 1 0 0 0 0 ,, Fig.6 - Typical transition time v£.
load capacitance.
0 0 1 0 1 1 0 1 1 0 1
,
-
I
0 0 1 1 1 1 1 1 0 0 1 ,,
-
0 1 0 0 0 1 1
,- ,,
0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
,- ,
0 1 1 0 1 0 1 1 1 1 1
,,- ,
0 1 1 1 1 1 1 0 0 0 0 ,,
1 0 0 0 1 1 1 1 1 1 1 '-'I Hf -+ri- --
1 0 0 1 1 1 1 1 0 1 1
,
'- ,, LOAD CAPACITANCE leLI-50 pF
1 0 1 0 0 0 0 1 1 1 0
,
,
- - - CL~15pF
1 0 1 1 0 1 1 0 1 1 1 :-: jj:l:LfllJH-
1 1 0 0 1 1 0 0 1 1 1
,,-' 10 2 '" 61022 46 103 2 46 10",2 4 6 10,
1 1 0 1 1 1 1 0 1 1 1
,,-,, INPUT CLOCK FREQUENCY (tCLI-kHz
1 1 1 0 0 0 0 0 0 0 1 - Fig.7 - Typical input clock frequency vs.

power dissipation.
1 1 1 1 0 0 0 0 0 0 0 BLANK
214
CD4054B. CD4055B, CD4056B Types
AM81ENT TEMPERATURE (TA )-ZS"C
(Voltages referenced to VSS Terminal) ......... _...................................... -0.5 to +20 V
DC INPUT CURRENT, ANY ONE INPUT ., ................................................... ±to mA
For T A = -40 to +60°C (PACKAGE TYPE E) ................................................. 500 mW
ForTA = +60 to +85°C (PACKAGE TYPE E) ................... Derate Linearly at 12 mW/oC to 200 mW
For T A =-55 to +100°C (PACKAGE TYPES 0, F, K) .......................................... 500 mW
ForTA = +100 to +125°C (PACKAGE TYPES 0, F, K) ... , ...... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR: 'i
~ 10
For T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW
OPERATING-TEMPERATURE RANGE (TA): a 5
PACKAGE TYPES 0, F, K, H ........................................................ -55 to +125°C
PACKAGE TYPE E .................................................................. -40 to +85°C 5 10 15
ORA1N-TO-SOURCE VOLTAGE lVosl-V
ZO
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +150°C 92.CS-35983

Fig.8 - Typical n-channel output low (sink)
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max .......................... +265°C
•
STATIC ELECTRICAL CHARACTERISTICS AM81ENT TEMPERATURE ITA) -Z5"C
~
LIMITS E
J
CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H, Packages ~ 15
Characteristic VEE VSS V IN V DD Values at -4cP, +2SO.+8S o C Apply to £ Package tl

Vo Units
~IZ.5
(V) (V) (V) (V) (V) +25 0 C
-55 0 -40 0 +85° +125° Min. Typ. Max. B 10
Quiescent Device -5 a 5 5 150 150 - 0.04 5 )1A ¥iii 7.5 GATE-TO-SOURCE VOLTAGE {VGS'-15 V
a
~
0 10
Current, I DO
MAX. 0 a 15
10
20
300 300
600 600
-
-
0.04
0.04
10
20 ~
5 IOV
a 0 20 100 3000 3000 - 0.08 100
~
I- 2.5
Output Voltage: il
0 a as 5 0.05 _. 0 0.05 5 ~ 15 W
DRAIN-TO-SOUR E VOLTAGE {Vosl-V
Low Level, VOL 0 0 010 10 0.05 -- 0 0.05 92.CS- S5982
MAX. 0 0 015 15 0.05 -- 0 0.05
V Fig.9 - Minimum n-channel output low (sink)
0 0 05 5 4.95 4.95 5 - current characteristics.
High Level, VOH a 0 010 10 0.95 9.95 10
MIN. a 0 0,15 15 14.95 14.95 15 _.-
ORAIN-TO"'SOURCE VOLTAGE (VDsl-V
0.5, -15 -10 -5
Input Low AM81ENT TEMPERATURE (TA)-2S·C
Voltage,
a a 4.5 5 1.0 - - 1.5
VIL MAX. a a 1,9 10 3 - 3
0 01.5,13.5 15 4 - - 4
V
Input High -5 0 0.5,4.5 5 3.5 3.5 - --
Voltage, a oI 1,9 10 7 7 - GATE TO-SOURCE VOLTAGE (VGS)-
VIH IVIIN. 0 01.5,13.5 15 11 11 - -IOV
Output Low
(Sink) -5 0 -4.5 5 0.98 0.92 0.67 0.55 0,8 1.6 -
-15V
Current, IOL a a 0.5 10 0.98 0.92 0.67 0.55 0.8 1.6 -
a a 1.5 15 3.6 3.4 2.4 2 2.9 5.8

mA
Output High 5 a 4.5 5 -0.6 - 0.55 ·-0.35 0.3 --0.45 -0.9 -
92CS-33194RI
(Source) a 0 9.5 10 - 0.6 -0.55 -0.35 -0.3 ·-0.45 -0.9 - Fig. 10 - Typical p-channel output high (source)
Current, IOH a a 13.5 15 -·1.9 1.8 1.2 -1.1 --1.5 --3 -
I nput Current, DRAIN-TO-SOURCE VOLTAGE IVos)-V

0 0 - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 )1A
liN -15 -10 -5
AMBIENT TEMPERATURE ITAj=25°C
INPUTS Voo
GATE-TO-SOURCE VOLTAGE (VGS)~
o
Vss
V,H
INPUTOOUTPUTS -IOV
'--- ~
VIOL r -15,~
NOTE:
vss TEST ANY COMBINATION
OF INPUTS
92CS-Z7441RI
Fig. 13 - Minimum p·channel output high

Fig. 11 - Quiescent-device-current test circuit. Fig. 12 - Input-voltage test circuit. (source) current characteristics.
215
DYNAMIC ELECTRICAL CHARACTERISTICSatTA = 25°C, CL = 50 pF, Input t"tf = 20 ns,
RL = 200 kU
VOD lNPu(
VOO
J s NOTE,
LIMITS
CONDITIONS
ALL PACKAGE TYPES ~ ~i~~~N~'~~~~~S
VEE VSS VDD \Iss Voo ANO \Iss'
CHARACTERISTIC CD4055,CD4056 UNITS
TO BOTH
CD4054 CONNECT ALL UNUSED
(V) (V) (V) INPUTS TO EITHER
Typ. Max. Typ. Max. "00 OR Vss'
Vss
Propagation Delay Time, -5 0 5 400 800 650 1300
tpHL,tPLH 0 0 10 340 680 575 1150 ns
(Any I nput to Any Output) 0 0 15 250 500 375 750 Fig. 14 - Input-current test circuit.
-5 0 5 100 200 100 200
Transition Time, tTHL,tTLH
0 0 10 100 200 100 200 ns
(Any Output)
0 0 15 75 150 75 150
-5 0 5 110 220 110 220
Minimum Data Setup
0 0 10 50 100 50 100 ns
Time, tS'
15 35 70 35 70 50%~
DATA:.:i1 , ~
I ~50% 50%~
-5 0 5 110 220 110 220
Width, tw
.
Minimum Strobe Pulse
0
0
0
0
10
15
50
35
100
70
50
35
100
70
ns
STROBE
Irl'f=20~_$~ 's ~ " '--
92CS-27053
(Any Input)
- - - 5 7.5 5 7.5 pF
Fig. 15 - Data setup time and strobe
* CD4054 and CD4056 only. pulse duration.
RECOMMENDED OPERATING CONDITIONS at T A = 25°C (Unless otherwise specified)

is always within the following ranges.
VEE VSS VDD LIMITS

(V) (V) (V) Min. Max.
Supply Voltage Range: LEVEL'~
SHIFTED
OFOUT , DFOUT
(At T A = Full Package 3 18 V
....... p DISPLAY
Temperature Range)
DISPLAY TT 't-t--r::>-o DRIVER SEGMENT
-5 0 5 220 - g~~1R,.T ! r;::r r~~~UQT)

V"
INPUT t--n
Setup Time (t s)- 0 0 10 100 - ns (0 TOol
0 0 15 70 - (HIGH-SELECT) DFOUl
92CS- 20093RI
1,1
-5 0 5 220 -
Strobe Pulse Width (tW)- 0 0 10 100 - ns
0 0 15 70 -
• For CD4054 and CD4056 only.
OFOUl Voo n n n n n n n n n nn n
vn...J U U U U U U U U U U U L
_ _ Vo
DFOUl
VEE
VOO r - - - - - ,
SEGMENT IN yEEJ
VOO
SEGMENT OUT
VEE
OF'N -OISPLA V-FREQUENCY INPUT 92CS- 20094FII

OFOUl_ LEVEL- SHIFTED DISPLAY- FREQUENCY OUTPUT
LlQUID- CRYSTAL
COMMON ELECTRODE 92CS-200'l5R~ '01
Fig. 16 - Clock display: VOO ~ 0 V, VSS ~5 V, VEE ~ -15 V, OF/N = 30 Hz square wave.
Fig. 17 - Display-driver circuit for one segment /ine

and waveforms.
216
No.4 No· No. No·
ANALOG INPUTS (!5V) 2 3 4
I STROBE O.R o.p C.P
ANALOG OUTPUTS
I (.is VI
!J2CS-200!J6R2
Fig. 18 - Digital (0 to +5 Vi to bidirectional analog

control (+5 to -5 Vi lovel shifter.
•
Voo
OF OUT
Fig. 19 - TypicaI3Y2-digit liquid-crystal display.'
VDD=+5 V. VSS=D V. VEE=-ID V.
OFIN = 30 Hz square wave.
CQ4055
OFIN·3gvH~~~~~~~C~AVEI
92CS- 2008'3 R2 OFOUT • g~~~~~- :~~~~i~g~
Fig.20 - Singlo.tJigit Iiquid·crystal display.
92CS-27058
Fig.21 - Conversion of "H" display to "F" display.

represent a chip when it is pari of tha wafer. When the
wafer Is separated into Individual chips, the angle of In addition to the letters L, H, P, and In a similar manner the letters C, E, J, and
c/eavllge may v.ry with respect to the chip face for
different chips. The actual dimensions of the isolated A (See the truth table), five other letters U can be displayed. These circuits can also
chip, therefore, may differ slightly from the nominal can be displayed through the use of simple be used to drive LED displays provided the
dimensions shown. The user should consider a tolerance exclusive-DR gates have sufficient output-
logiC circuits preceding and following the
dimensions shown. CD4055B or CD4056B devices. Fig.21 is an current drive.
example of a circuit that converts an "H" The letters B, 0, G, I, 0, and S may be rep-
display (code 1011) to an "F" display. resented by the codes for numbers 8, 0, 6,
One condition that must be met is that 1. 0, and 5, respectively, when there is pre-
Grid graduations are in mils f1tr3 inch). VEE=VSS. If VEE#VSS, the CD4054B must knowledge that only letters are to be dis-
be used to level shift in the appropriate places. played_
)Jmension. and pad layout for CD4D54BH. Dimensions and pad layout for CD4055BH Dimensions and pad layout for CD40568H
217
CD4060B Types
CMOS 14-Stage Ripple-

Carry Binary Counter/Divider Q4
and Oscillator Q5

Features:
• 12 MHz clock rate at 15 V
The RCA-CD4060B consists of an oscillator • Common reset
section and 14 ripple·carry binary counter • Fully static operation
stages. The oscillator configuration allows
design of either RC or crystal oscillator • Buffered inputs and outputs
circuits. A RESET input is provided which • Schmitt trigger input-pulse line
resets the counter to the all·O's state and • 100% tested for quiescent current at 20 V FUNCTIONAL DIAGRAM
disables the oscillator. A high level on the • Standardized, symmetrical output
RESET line accomplishes the reset function. characteristics
All counter ~tages are master·slave flip·flops. • 5-V, 10-V, and 15-V parametric ratings
The state of the counter is advanced one
step in binary order on the negative transi· • Meets all r~quirements of JEDEC Tentative
Standard No. 13B, "Standard Specifica·
tion of I/> I (and 1/>0). Ali inputs and outputs tions for description of "B" Series CMOS
are fully buffered. Schmitt trigger action Devices"
on the input·pulse line permits unlimited
input-pulse rise and fall times. Oscillator Features: Applications
The CD40S0B-series types are supplied in • All active components on chip • Control counters
l6-lead hermeticdual-in-line ceramic pack- • RC or crystal oscillator configuration
ages (D and Fsuffixes), 16-lead dual-in-line • Timers
plastic pa'ckages (E suffix), IS-lead ceramic • RC oscillator frequency of 690 kHz • Frequency dividers
flat packages (K suffix). and in chip form (H min. at 15 V • Time.(\elay circuits
suffix).
*
~14 QI4
FF2-FFI3 I FFI4
+z +14 Qi4
L R
QI4
Q4!QIO
QI2,QI3
• R-HIGH DOMINATES I RESETS ALL STAGES)
• COUNTER ADVANCES ONE BINARY COUNT
~VDD * BYALLCOS/MOS
INPUTS ARE PROTECTED
PROTECTION
92CS-29072
ON EACH NEGATIVE - GOING TRANSITION NETWORK

Fig. 2 - Detail of typical flip·flop stage.
~vss
OF +I lAND +0)
92CM-29074R2
AMBIENT TEMPERATURE (TAI~2!5·C

DC SUPPLY·VOLTAGE RANGE, IVODI
lVoltages referenced to VSS Terminal) -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to VDD +0.5 V GATE-lO-SOURCE VOLTAGE {VGS)"'5 v
POWER DISSIP1'oTION PER PACKAGE !POl:
For TA =-40 to +60 0 C IPACKAGE TYPE EI . . . . . .. . 500mW
For TA = +60 to +8S o C !PACKAGE TYPE EI Derate Linearly at 12 mW/oC to 200 mW
ForTA = -55 10 +100'C (PACKAGE TYPES 0, F, K). . • • • • • . . . , • . . . . 500mW ,ov
ForTA = +10010 +125'C (PACKAGE TYPES 0, F! ~).' • • . Derate Linearly at 12 mW/oC to 200 mW 9
DEVICE DISSIPATION PER OUTPUT TRANSISTOR 5 10
FOR TA" FULL PACKAGE·TEMPERATURE RANGE IAII Package Type,1 100mW ~
OPERATlNG·TEMPERATURE RANGE IT AI.
5 , 'v
PACKAGE TYPES 0, F, K, H . . • . . . . . . . . . . . • . . • . . • . . . . • -5510 +125'C
5 10 15
PACKAGE TYPE E. . . . . . . . . . . . • . • . . . . • . . • . . . . • • • . . . . . . -4010 +85'C DRAIN-lO-SOURCE VOLTAGE (Vosl-V
STORAGE TEM'PERATURE RANGE ITstgl -65 to + 150°C
LEAD TEMPERATURE lOURING SOLDERINGI, Fig. 3 - Typical n-channel output low (sink)
At distance 1/16 ~ 1/32 Inch t 1.59 + 0.79 mm) from case for 10 s max. current'characteristics.
218
CD4060B Types

LIMITS AT INDICATED T.EMPERATURES (oCI u .E
CHARAC-
TERISTIC
CONDITIONS
N
Values at -55, +25, +125 Apply to 0, F, K, H, Packages I
:s
I
15
T ~ 12.5
+25 S
Vo VIN VDD il 10
(VI (V) (V) -55 -40 +85 +125 Min. Typ. Mall. ~ 10V
~ 7.5
Quiescent
- 0,5 5 5 5 150 150 - 0.04 5 •g 5
Device - 0,10 10 10 10 300 300 - 0.04 10 p.A ~

§ 25 .V
Current, - 0,15 15 20 20 600 - 600 0.04 20
100 Max.
- 0,20 20 100 100 3000 3000 - 0.08 100 ~ 10 15
DRAIN-lO-SOURCE VOLTAGE IV051-\I
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - Fig. 4 - Minimum n-channel output low (sink)
Output Low current characteristics.
(Sink)OJrrent*, 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
10L Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
Output High
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mJ! ORAIN-TO-SOURCE VOLTAGE Nasi-v
I
(Source)
Current* ,
10H Min.
2.5
9.5
0,5
0,10
5
10
-2 -1.8
-1.6 -1.5
-1.3 -1.15 -1.6
-1.1 -0.9 -1.3
-3.2
-2.6
-
- I
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low·Level, - 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05 V
Output - 0,5 5 4.95 4.95 5 -
Voltage:
High·Level,
- 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 15 - Fig. 5 - Typical p-channel output high (source)
Input Low
0.5,4.5 - 5 1.5 - - 1.5 current characteristics.
Voltage 1,9 - 10 3 - - 3
VILMall. r· 5,13.5 - 15 4 - - 4
V
DRAIN-lO-SOURCE VOLTAGE IV051-V
Input High 0.5,4.5 - 5 3.5 3.5 - -

Voltage, 1,9 - 10 7 7 - -
VIHMin.
1.5,13.5 - 15 11 11 - -
Input Current
liN Max .
- 0,18 18 ±0.1 ±O.l ±1 ±1 - ±10-5 ±0.1 .p.A
• Oata not applicable to terminal 9 or 10.

For maximum reliability, nominal operating conditions should be selected so that operation is
always within the fol/owing ranges Fig. 6 - Minimum p-channel output high (source)
LIMITS current characteristics.
CHARACTERISTIC VOl) UNITS
MIN. MAX.
Supply·Voltage Range (For TA = Full Package - 3 18 V
Temperature Range)
5 100 -
Input·Pulse Width, tw (f = 100 kHz) 10 40 - ns
15 30 -
5
Input-Pulse Rise Time and Fall Time, trq,' tfq, 10 Unlimited
15
5 - 3.5
Input·Pulse Frequency, frfJI (External pulse source) 10 - 8 MHz
15 - 12
5 120 - LOAD CAPACITANCE LI-pF 92CS-31249
Reset Pulse Width, tw 10 60 - ns Fig. 7 - Typical propagation delay time (On to On+1 J
15 40 - as a function of load capacitance.
219
CD4060B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =25°C, Input tI , tf =20 ns,
1
.. AMBIENT TEMPERATURE(TA)-2'·C
=50 pF, RL = 200 kn

;~t~:l:iti~-
CL
700
.:1
TEST LIMITS
VDD MIN. TYP. MAX.
(V) suPPLY vOLTAGE (VDDI~5V:~
Input·Pulse Operation
Propagation Delay 5 - 370 740

Time,l/>I to 04 Out; 10 - 150 300
tPHL, tPLH 15 - 100 200
Propagation Delay 5 - 100 200 20 40 60 80 100
Time. On to On+l; 10 - 50 100 92CS-312!!O
Fig. 8 - Typical propagation delay time (,pI to 04

tpHL. tPLH 15 - 40 80 Output) as a function of load capacitance.
Transition Time. 5 - 100 200

tTHL. tTLH 10 - 50 100 ns
15 - 40 80
Min. Input·Pulse 5 - 50 100
f= 100kHz
Width, tw 10 - 20 40
15 - 15 30
Input-Pulse Rise & Fall 5
Time, trl/>' tfl/> 10 Unlimited
15
Max. Input-Pulse 5 3.5 7 -
Frequency, fl/>I
(External pulse 10 8 16 - MHz
source) 15 12 24 - Fig. 9 - Typical transition time as a function
Input Capacitance, C, Any Input - 5 7.5 pF
Reset Operation
I ~ AMBIENT TEMPERATURE (TA )-Z5·C
Propagation Delay 5 - 180 360 4 , - - LOAD CAPACITANCE (CL~50pF
Time, tPHL 10 - 80 160

15 - 50 100 ns
Minimum Reset 5 - 60 120
Pulse Width, tw 10 - 30 60
15 - 20 40
~ IO! .. t
! :
I~ ,
~0.1 -;--468 1 i! 468102 2 468103 2 468 104
INPUT FREQUENCY (t+II-ItHz 92CS-31251

Voo
500,.F
·s ·x
C XTAL-C I+C2+ CSTRAY
RC - ~~~~gij~tREQUENCY
NOTE! RS -CURRENT LIMITING
RSIS 2RX TO IOR X
92'CS-31253
T-2·2 .xCx
92CS-31U2RI
92CS-312!!4
Fig. 11 - Dynamic power dissipation test circuit. Fig. 12 - Typical RC circuit. Fig. 13 - Typical crystal circuit.
220
CD4060B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 250 C, Input t r , tt = 20 ns,
CL = 50 pF, RL = 200 kn [cont'd]
VOO
INPUTS
LIMITS
o
TEST UNITS V5S
CHARACTERISTIC VDD
CONDITIONS
(V) Min. Typ. Max.
RC Operation
Cx = 200 pF. 5 18 21.5 25
Variation of Fre-
RS = 560 kn, 10 20 23 26
quency (Unit-to-Unit)
RX=50kn 15 21.1 24 27 Vss
kHz
Variation of Fre- Cx = 200 pF. Fig. 14 - Quiescent device current.
5Vto 10 V - - 2
quency with voltage RS = 560 kn.
10Vto15V - - 1
change (Same Unit) RX = 50 kn
RX max. Cx = 10IlF 5 - - 20
= 50 IlF 10 - - 20 Mn
= 10 IlF 15 - - 10 INPUTQVIlO
OUTPUTS
Cx max. RX = 500 kn
= 300 kn
5
10
-
-
-
-
1000
50 IlF
V ,H
v~
0",..... ~
~
I
= 300 kn 15 - - 50
NOTE:
Maximum Oscillator RX = 5 kn 10 530 650 810 vss TEST ANY COMBINATION
kHz OF INPUTS
Frequency' CX=15pF 15 690 800 940 92CS-21441RI
Drive Current at Fig. 15 - Input voltage.

Pin 9 (For Oscillator
Design) VO=0.4V 5 0.16 0.35 -
IOL -0.5 V 10 0.42 0.8 -
= 1.5 V 15 1 2 - mA
Voo INPUO
VOO S NOTE.
Vo = 4.6 V 5 -0.16 -0.35 -
IOH =9.5 V 10 -0.42 -0.8 - ~ ~:~j~:i,~~~~~S
= 13.5V 15 -2 - Vss TO BOTH Voo ANO VSS'
-1 CONNECT ALL UNUSEO
INPUTS TO EITHER
'Re oscillator applications are not recommended at supply voltages below 7 V for RX < 50 kCl. Voo OR VSS'
V5S
Fig. 16 - Input current.
TERMINAL DIAGRAM
I.
I.
012 IS VDO
013 15 010
.I
01. OB
OS
05 "
12
00
RESET
07
O. "
10 .0
VSS ·0
(TOP VIEW)
92CS-23161R2
DimenSIons In parentheses are In millimeters and

are derived from the basIc Inch dimensions as in·
dlcated. Grid graduations are in mils (10- 3 inch).

wafer is s9parated into indiVidual chips. the angle of
92CM-35106 cleavage may vary with respect to the chip face for
chip. therefor9. may differ slightly from the nominal
dimensions shown. The user should considera tolerance
Dimensions and pad layout for CD4060B. dimensions shown.
221
CD4063B Types
CMOS 4-Bit Magnitude
Comparator
o
High Voltage Types (20-Volt Rating) Features:
• Expansion to 8, 12, 16.... 4N bits by cascading units WORD A
The RCA-CD4063B is a 4·bit magnitude com·
parator designed for use in computer and
• Medium·speed operation: CASCADING
INPUTS
rA>B
A_e
lAce
A>B
A-a
AC8
logic applications that require the comparison compares two 4-bit words WORDB 4
of two 4·bit words. This logic circuit detet· in 250 ns (typ.) at 10 V
mines whether one 4·bit word (Binary or • 100% tested for quiescent current at 20 V
BCD) is "less than", "equal to", or "greater • Standardized symmetrical output characteristics
92CS-:M't6
than" a second 4·bit word.
• 5-V, 10-V, and 15·V parametric ratings
The CD4063B has eight comparing inputs
(A3, B3, through AO, BO), three outputs (A • Maximum input current of 1 p.A at 18 V
FUNCTIONAL DIAGRAM
< B, A = B, A > B) and three cascading inputs over full package temperature rangej
(A < B, A = B, A> B) that permit systems 100 nA at 18 Vand 25°C
designers to expand the comparator function • Noise margin (full package temperature range)
to B, 12, 16 . . . 4N bits. When a single
CD4063B is used, the cascading inputs are range) = 1 V at VDD = 5 V B. I. I. VOO
connected as follows: (A < B) = low, (A = B) 2 V at VDD = 10 V (A<B)'N 2 15 A.
=high, (A> B) = low. 2.5 V at VDD = 15 V
(A-SlIN
CA>B)IN
•
4
14 B2
02
For words longer than 4 bits, CD4063B de· • Meets all requirements of JEDEC Tentative (A>B1O UT 5 "
12 AI
vices may be cascaded by connecting the
outputs of the less·significant comparator to
'A'BlouT
,AcBIOUT 7
8
"
10
9
BI
AD
Vss BO
the corresponding cascading inputs of the (TOP VIEW)
more·significant comparator. Cascadir)g in· Applications: 92CS-24'2~,
puts (A < B, A = B, and A > B) on the • Servo motor controls • Process controllers TERMINAL ASSIGNMENT
least significant comparator are connected to
a low, a high, and a low level, respectively.
The CD40638 types are supplied in 16-lead
hermetic dual-in-line ceramic packages (D MAXIMUM RATINGS,Absolute-Maximum Values:
and F suffixes), 16-lead dual-in-line plastic DC SUPPLY·VOLTAGE RANGE, (V DD)
package (E suffix), 16-lead ceramic flat (Voltages referenced to VSS Terminal) -0.5 to +20 V
package' (K suffix), and in chip form (H INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to VDO +0.5 V
suffix). This device is pin-compatible with DC INPUT CURRENT, ANY ONE INPUT ±10mA
the standard 7485 TTL type. POWER DISSIPATION PER PACKAGE (PO);
For T A = -40 to +60 0 C (PACKAGE TYPE E) . • • • • • • .• 500mW
For TA = +60 to +85 0 C (PACKAGE TYPE E) . Derate Linearly at 12 mWloC to 200 mW
For TA = -55 to +100'C (PACKAGE TYPES 0, F, K) . . • • • • • •• 500mW
For TA = +100 to +125'C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mWloC to 200 mW
OPERATlNG·TEMPERATURE RANGE (TA);
PACKAGE TYPES 0, F, K. H -55 to +1250 C
PACKAGE TYPE E • -40 to +850 C
STORAGE TEMPERATURE RANGE (Tstg ) -65 to +1500 C
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for lOs max.

LIMITS IpTOTAl .. tp (f~P~T~RE) + 2M tp (f:p~':i'E).A' VDD ,"10V
CHARACTERISTIC Min. Max. UNITS 13STAGESI
Supply· Voltage Range :250+12 x 200)"650 mITVP.1
(For T A=Full Package· 3 18 V
Temperature Range) Fig. 1 - Typical speed characteristics of a 12·bit comparator.
222
CD4063B Types

CHARACTER· Values at -40, +25; +85 Apply to E Package
ISTIC UNITS
Vo VIN VDO +25
Current, - 0,10 10 10 10 300 300 - 0.04 10
JlA
100 Max.
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - O.OB 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sinkl Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min.
1.5 0,15 15 4.2 4 2.B 2.4 3.4 6.B -
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
•
(Sourcel
Current,
2.5 0,5 5 -2 -1.B -1.3 -1.15 -1.6 -3.2 -
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.B -2.4 -3.4 -6.B -
Output Voltage: - 0,5 5 0.05 - a 0.05
Low·Level,
VOL Max.
- 0.10 10 0.05 - 0 0.05
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - a,s 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage,
VIL Max.
1,9 . - 10 3 - - 3
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,13.5 - IS 11 II - -
Input Current
liN Max.
- O,IB lB ±O.I ±0.1 ±I ±I - ±10- 5 ±O.I JJ.A
TRUTH TABLE
INPUTS
OUTPUTS
COMPARING CASCADING
A3, B3 A2, B2 AI, Bl AO, BO AB AB
A3>B3 X X X X X X 0 0 1
A3 = B3 A2>B2 X X X X X 0 a 1
A3= B3 A2 = B2 Al >Bl X X X X 0 0 1
A3 = B3 A2 = B2 Al = Bl AO>BO X X X 0 0 1
A3 = B3 A2 = B2 I Al = 81 AO = BO 0 0 1 0 a 1
A3= B3 A2 = B2 Al = 81 AO = BO 0 1 0 0 1 0
A3 = 83 A2 = B2 Al = 81 AO= BO 1 0 0 1 0 0
A3 = 83 A2 = B2 Al = 81 AO<BO X X X 1 0 0
A3= B3 A2 = B2 Al<Bl X X X X 1 0 0
A3 = B3 A2< B2 X X X X X 1 0 0
A3< 83 X X X X X X 1 0 0
X = Don't Care Logic 1 ; HIgh Level LogIC 0 = Low Level
223
CD4063B Types
.1;;------ - ----- ---1

·3 i GATE-TO-SQURCE VOLTAGE (YoS)·I~ V
I
I ,ov
~ 10
~ . ov
5 10 15
DRAIN-tO-SOURCE VOLTAGE (Vosl-V
COMPARING Fig. 3 - Tvpical output low (sink)

INPUTS
.,
A,
i
' DRAIN-tO-SOURCE VOLTAGE
80
AO
I
'
Fig. 4 - Minimum output low-(sink)
I, ·0
Ao
I
'
DRAIN-lO-SOURCE VOLTAGE !Vosl-V
* BY THE
ALL INPUTS PROTECTED '~~~~
- ______________II -15
AMBIENT TEMPERATURE (TA)-2S-C
-10 -5
COS/MOS PROTECTION
NETWORK GATE-YO-SOURCE VOLTAGE (Vosl-·5V
92CL-3093~

-lOY
-I!~V

At TA =25'C; Input t r, tf= 20ns, CL =50pF, RL =200kn
Fig. 5 - Tvpical output high (source)
ALL TYPES
TEST CONDITIONS DRAIN-tO-SOURCE IiOLTAGE (VDSI-V
LIMITS
CHARACTERISTIC UNITS -15 -10 -,
VDD AMBIENT TEIif>ERATURE ITAI' 25'C
Volts Typ. Max. GATE-TO-SOURCE VOLTAGE (Vosl- -, v
Propagation Delay Time: 5 625 1250 -,

Comparing Inputs to 10 250 500
Outputs, tpHL' tpLH 15 175 350
., ns -IOV
-0
5 500 1000
Cascading Inputs to 10 200 400
Outputs, tpHL. tpLH 15 140 280 "-15V
-"
5 100 200
Transition Time. 10 50 100 ns
tTHL' tTLH 15 40 80
Input Capacitance, CIN Any Input 5 7.5 pF Fig. 6 - Minimum output high (source)
224
CD4063B Types
'" AMBIENT TEMPERATURE (TA). 25"C
I 1500
:11 I . LOA D CA~17ANCE I~Ll ~ ~o pF
~
]1250 \\1
' , Iii I!II!!! Ui
~ 1000
ii'
I; , I
"
'I,
, 1:1j II
~
S 750
ill 1
i I
~ !I' I
!
I 25°1 Ii-
.00
;1 II
o
10 20 40 $0 60 70
~
0 2.' . 7.' '0 12.5
SUPPLY VOL.TAGE (Voo)-V
I. IT.5 20
lOAD CAPACITANCE (Cll-pF
Fig. 7 - Typical propagation delay time

Fig. 8 -. Typical propagation delay time vs. supply
vs. load capacitance ("comparing Fig. 9 - Typical transition time vs. load capacitance.
voltage ("comparing inputs to outputs). U
inputs" to outputs).
Vco
~
Vss
1NPUO'
'.
Vss
:;:~ ~ ..
SEQUENTIALLY,
TO BOTH Voo ANDVss'
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS'
•
'ttCS-U402
0.1 2 ""1 I! ."10 I 4 1 ' IO Z1 4"10'2 41'104

INPUT fREQUENCY CfI- kHz Fig. 11 -Input current test circuit.
Fig. 10 - Typical power dissipation vs. frequency
(see Fig. 12 - dynamic power
dissipation test circuit). Fig. 12 - Dynamic power dissipation test circuit.
'NPUTOVOOOUTPUTS
V'H
=---
VIL ~:r
NOTE:
Vss TEST ANY COMBINATION
OF INPUTS
9ZCS-2744IRI
Fig. 13 - Input·voltage test circuit.
INPUTS
o
Vss
Dimension, and pad layout for CD4063BH.

DimBfJ,/on, in psrenths'tII.,. in millitrHlte" and.,. represent a chip when it is part of the wlfer. Whan the
derivad from the belie inch dimen,ions .. indiesr.tl. we fer ;s separated into individual chips, the angle of
Vss cleavage may vary with respect to the chip face for
.ZCS-2'4CIRI Grid graduation. artl in mil, (t 0-3 inch). different chips. The actual dimensions of the isolated
chip, therefore, may differ slightly from the nom;nal
Fig. 14 - Quiescent·device-current test circuit. of -3 mils to +16 mils applicable to the nominal
dimensions shown.
225
CD4066B Types
CMOS Quad Bilateral I~/OUT I
Switch SIG A
CONT
A
For Transmission or Multiplexing of Analog or
Digital Signals Features:
High-Voltage Types (20-Volt Rating) • 15-V digital or ±7.5-V peak-to-peak switching
The RCA·CD4066B is a quad bilateral switch • 125n typical on-state resistance for 15-V operation
intended for the transmission or multiplex· • Switch on·state resistance matched to within 5 n over
ing of analog or digital signals. It is pin-for· 15-V signal-input range
pin compatible with RCA·CD4016B. but • On-state resistance flat over full· peak-to-pea k signal
exhibits a much lower on-state resistance. In range
addition. the on·state resistance is relatively • High on/off output-voltage ratio: 80 dB typo @
constant over the full input·signal range. fis = 10 kHz. RL = 1 kn
• High degree of linearity: <0.5% distortion FUNCTIONAL DIAGRAM
The CD4066B consists of four independent typo @ fis = 1 kHz. Vis = 5 VP-P. VDD -
bilateral switches. A single control signal is VSS~10V.RL=10kn
required per switch. Both the p and the n • Extremely lOw off-state s,.,,;tch leakage
device in a given switch are biased on or resulting in very low offset current and high
off simJltaneously by the control signa I. effective off-state resistance: 10 pA typo @ Applications:
As shown in Fig.1. the well of the n·channel
VDD - VSS = 10 V. TA = 250 C • Analog signal switching/multiplexing
device on each switch is either tied to the
input when the switch is on or to VSS when • Extremely high control input impedan..-e Signal gating Modulator
the switch is off. This configuration elimi· (control circuit isolated from signal cir- Squelch control Demodulator
nates the variation of the switch·transistor cuit): 1012 n typo Chopper Commutating switch
threshold voltage with input signal. and thus • Low crosstalk between switches: -50 dB • Digital signal switching/Multiplexing
keeps the on-state resistance low over the full typo @fis = 8 MHz. RL = 1 kn • Transmission-gate logic implementation
operating-signal range. • Matched control-input to signal-output • Analog-to-digital & digital-to-analog
capacitance: Reduces output signal conversion
The advantages over single·channel switches transients
include peak input-signal voltage swings equal • Digital control of frequency. impedance.
• Frequency response. switch on = 40 MHz phase. and analog-signal gain
to the full supply voltage. and more constant (typ.)
on-state impedance over the input-signal
range. For sample·and-hold applications. • 100% tested for quiescent current at 20 V
however. the CD4016B is recommended. • 5-V. 10-V. and 15-V parametric ratings
The CD40668 is available in 14-lead ceramic Standard No.13A. "Standard Specifications
dual~in-line packages (0 and F suffixes).
for Description of "B" Series CMOS Devices"
14-lead plastic dual-in-line packages (E suf-
fix). 14-lead ceramic flat packages (K suffix).
SWITCH
CONTROL r-------~
MAXIMUM RATINGS. Absolute-Maximum Values: ~'N
DC SUPPLY·VOLTAGE RANGE. (VDD,
(Vollage. refer&need 10 VSS Terminall -0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS -0.5 t.o V DD +0.5 V
DC INPUT CURRENT: ANY ONE INPUT (except for TRANSMISSION GATE which is 25 rnA). ±10 mA
POWER DISSIPATION PiR PACKAGE (POi: .
For T A • -40 to +600 C (PACKAGE TYPE EI . . . .. 500 mW
For TA = +~ to +85 c:; (PACKAGE TYPE E I . Derate Linearly at 17 mW/oC to 200 mW
g
For T A = -55 to +l00°C (PACKAGE TYPES D. F. K) .. 500 mW
For T A ~ +100 to +125°C (PACKAGE TYPES D. F. K) Derale L .nearly al 12 mW/ C 10 200 mW
NORMAL OPERATION
FOR T A • FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl 100n.W CONTROL-LINE BIASING: OO
9 P_!;R.ATlillG-TE.M.PERATURE RANGE (TA': SWITCH ON,ytMt.Voo
SWITCH OFF, Vc ·o"·Yss
. PACKAGE TYPES D. F. K. H -55 to + 125°C
NOTE:
PACKAGE TYPE E -40 to +85°C ALL "P"SUBSTRATES
CONNECTED TO Vao
STORAGE TEMPERATURE RANGE (TS! I . . -65 to +1500 C
LEAD TEMPERATURE (DURING SOLD~RINGI:
AI distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from ea.e for 10. max. +265°C *ALL CONTROL 'N~TS AR~ Vss 92CS-29113
PROTECTED BY COS/MOS
PROTECTION NETWORK

For maxim!lm reliability. nominal operating conditions should be selected so that oper- Fig. 1 - Schematic diagram of 1 of 4 identical
ation is always within the following ranges: switches and its associated co,ntrol
LIMITS circuitry.
Min. Max.
226
CD4066B Types
ELECTRICAL CHARACTERISTICS d SUPPLY VOLTAGE CVDO-Yss)-DY
LIMITS AT. INDICATED TEM-

U
~600 AMBIENT TEMPERATURE;
PERATURES (OCI (T A'- +12a-c •
Values at -55, +25, +125 Apply N ~~
Characteristic Test Conditions o 0, F, K, H Packages I
Values at -40, +25, +85 Apply to T
E Package S
+25
VIN VDD
(VI (VI -55 -40 +85 125 Typ. Max.
0,5 5 0.25 0.25 7.5 7.5 0.01 0.25
-4-3-2-101234
Ouiescent Device 0,10 10 0.5 0.5 15 15 0.01 0.5 INPUT SIGNAL VOLTAGE (VI,I - v 9ZCS-21326RI
JlA
Current. I DD 0.15 15 1 1 30 30 0.01 1 Fig. 2- Typical on-state resistance vs. input signal
voltage (all types).
0.20 20 5 5 150 150 0.02 5
Signal Inputs (Visl and Output (Vosl
q SUPPLY VOLTAGE (Voo-VSS'-IDY ::: :::: ::::
Vc = VDD
~300 :::: :::: :::: ::::I::):::~:::: :::: ::::
~ 250 :::: ::i~bl~kU~~~lL~:?
On-State R L = 10 kSl returned
;;;; ;;;;
Resistance. ron to VDD -VSS
[, 800 850 200 1300 470 1050
;:::
<
4 .••• ::::!:;j!'~:lFrAI·+12~·C
Max. I-' . . . . . . . . V.::I~ .... ~ .......... ..
I~:: !!~jI0~~~~~b~~ !~~~ :::: :::: ::::

2 10 310 330 500 550 180 400 H
Vis = VSS to VDD 15 200 210 300 320 125 240
!'.On·State
Resistance
Between Any
2 Switches.!'.r on
RL=10kSl. VC=VDD
5
10
15
-
-
- -
_.
-
-
-
-
-
-
-
15
10
5
-
-
-
H
I-'
~z'
:::
~
100 ::::
....
::::~:-r:::
""k"':~"" .;~ ....... ,
:::: ~:i~~~~:
:::: :::: :::: I!:: :::: ....
5: ~iillHlhUHIiHjrmhiHllliHill:~lh
>. ,
-10 -7.5 -~ -2.15 0 2.5 5 7.5 10
INPUT SIGNAL VOLTAGE IVisl- V 92CS·21327RI
Total Harmonic VC=VDD =5V. VSS=-5V. Vis(p·pl
Distortion. = 5 V (Sine wave centered on 0 V) - - - - 0.4 - % Fig. 3- Typicalon·state VI. input signal voltage
RL =10 kn. fis=l kHz sine wave (al/ types).
THD
-3dB Cutoff VC=VDD=5V. VSS=-5V. Vis(p.pl
...I
Frequency
(Switch onl
=5 V (Sine wave centered on 0 V - - - - 40 - MHz
~3OC
SUPPLY VOLTAGE (Voo - Vss I -15 V
If illilill!;!;:: ,,.ii'!'
.t' "Hli:!
...
RL =1 kH.
-50dB Feed·
!!S
1
I
I!
lliil ruli :lli lnl ill! i Ii
II
through VC=VSS= -5V. Vis(p.p) = 5V

Sine wave centerd on 0 V MHz :2CO
250
r 11. I! fn Jlli I'" "'j ::1 '" rt
It! !
'!;I
- - - - 1 -
..II!
AMBIENT TEMPERATURE
Frequency
(Switch off) RL = 1 kH I!SO
(TAl- +125·C
ill lillI !
~ , . ,. I
Input/Output Vc = 0 \t ~. ICO flHtc I

Leakage Current Vis=18V;Vos=
(Switch off) o V. Vis = OV; 18 ±0.1 ±0.1 ±1 ±1 ±to-5 ±0.1 JlA
.
...
i !SO
tJltli
-55·C, t
lis Max. Vos=18V 15 - -7.5 to -5 - 2.5 0 2.5

ttmlllli
7.5 10
VC(A)=VDD= INPUT SIGNAL VOLTAGE (Vis) - V
92CS·2i:S29RI
-50dB +5 V. VC(B) = VSS
= -5V. Vis(A) = - - - - 8 - MHz
Crosstalk Fig. 4- Tvpical on-state resistance vs. input signal
Frequency 5 V p-p.' 50 n source voltage (all types).
RL = 1 kn
RL = 200 kH
Propagation Vc = VDD. VS~=
5 - - - - 20 40
Delay (Signal GND.CL=50p 10 - - - - 10 20 ns
I nput to Signal Vis = 10 V (Square
Outpull tpd wave centered on 5 V 15 - - - - 7 15
t r • tf = 20 ns
Capacitance:
Input. Cis VDD = +5V - - - - 8 -
Output. Cos VC= VSS =-5V - - - - 8 - pF
Feedthrough.
Cios - - - - 0.5 -
INPUT SIGNAL VOLTAGE (Visl- V 92CS-27330RI
Fig. 5- on-state resistance vs. input signal

227
CD4066B Types
ELECTRICAL CHARACTERISTICS (cont'd) KEITHLEY
LIMITS AT INDICATED •~VDD

10 KO.~:. r--
• ISO
I
DIGITAL
MULTIMETER
len
TEMPERATURES (OC) U RANGE Y
H.P.
Characteristic Test Conditions Valuesat-55,+25,+125 N ~s x-v MOSELEY
7030A
L....._ _......_ _-<o----lPLOTTER
Apply D, F, K, H, Packages
I
Vaiu~s -40, +25, +85 Apply to
T
~ E Package I +25 S
I (vt -55 1-40 1+85 1+125 Typ. Max.
Fig. 7 - Channel on-state resistance measurement
Control (VC) circuit.
Control Input lIisl <101lA

Low Voltage, Vis=VSS·VOS= VDD 5 1 1 1 1 - 1
VILC Max. and 10 2 2 2 2 2 V
Vis = VDD' VOS = VSS
l 25-C
2
i ' '.
2 2 2 2 - 2 ~::!E2~~ !~~E.R~~~:;(TA1.
: ·' "' 11 ~
5 3.5 (Min.)
Control Input
High Voltage. See Fig. 6 10 7 (Min.) V
VIHC 15 11 (Min.)
I nput Current, Vis';; V~D
liN Max. VDD- SS=18V 18 ~O. ±O. ± ±1 1±10-5 ±0.1 JlA
VCC';; VDD - VSS "',- IOF4
SWITCHES
Crosstalk (Can, Vc = 10 V (Sq. Wave)
trol I nput to t r • tf = 20 ns 10 - - - - 50 - ImV -
Signal Outp"t) RL = 10 kH
Turn-On and VIN-VDD 5 35 70 -3 -2 -I

Turn-Off t r • tf = 20 ns INPUT VOLTAGE (VI) -v 92CS' 30919
CL = 50 pF 10 20 40 ns
Propagation Fig. 8- Typical ON characteristics for 1 of
Delay RL = 1 kH 15 15 30
4 Channels.
~~ = VDD, VSS = GND.
L = 1 kH to gnd,
Maximum CL=50pF, 5 - - - - 6 -
Control Input Vc = 10 V(Square 10 - - - - 9 - MHz
Repetition Rate wave centered on 5 V)
t r , tf = 20 ns, 15 - - - - 9.5 -
Vos = Y,Vos@ 1 kHz
Input
Capacitance, - - - - 5 7.5 JlF
CIN
Switch Input Switch Output,

lis (mA) Vos (V)
VDD Vis
(V ) (VI -55°C -40°C +25o C +850 C +1250 C Min. Max. 10 2 4.. 8 102: 2 4 .. I 10'
SWITCHING FREQUENCY 1t1-kHr
5 0 0.64 0.61 0.51 0.42 0.36 0.4 92CS-30!t20
5 5 -0.64 -0.61 -0.51 -0.42 -0.36 4.6 Fig. 9 - Power dissipation per package vs. switching
10 0 1.6 1.5 1.3 1.1 0.9 0.5 frequency.
10 10 -1.6 -1.5 -1.3 -1.1 -0.9 9.5

15 0 4.2 4 3.4 2.8 2.4 1.5
15 15 -4.2 -4 -3.4 -2.8 -2.4 13.5
C~os
r----+-----, MEASURED ON BOONTON
CAPACITANCE BRIDGE
t Vc' -~v VOD '+5V : MOOEL 7SA IIMHII
TEST FIXTURE CAPACITANCE
I I NULLED OUT
- l is- CD4066B ~ I I
Vii --'-'--1,-_' _OF_4_S_W_'_TC.,."_E_S--,I· VOl
I
I
IVis-vo.1 C~,=4=
'on·~ 92CS-30966 I
~
Fig. 6- Determination of r qn as a test condition for control input

high voltage (V/HC' specification. Fig. 10 - Capacitance test circuit.
228
CD4066B Types
+10V~
I,"f
-20n$
200 kJl
ALL UNUSED TE~MINALS ALL UNUSED TERMINALS

ARE CONNECTED TO VSS ALL UNUSED INPUTS ARE CONNECTED TO VSS ARE CONNECTED TO VSS
Fig. 11 - Off-switch input or output leakage. Fig. 13 - Crosstalk-control input to signal output.
Fig. 12 - Propagation delay time signal input (Vi,!
to signal output (Vas)'
Vc
',",'20n5
"
1CK
[RATE
•
Voo 1NPUO
"DO S NOTE
+IO~ ~ ~:~~NRil~~~~~S
',"1,20n5 VSS TO BOTH VOO ANO VSS·
CONNECT ALL UNUSED
ALL UNUSED TERMINALS ARE CONNECTED TO VSS

... VSS
INPUTS TO EITHER
VOO OR VSS·
MEASURE CONTROL
INPUTS ONLY
92CS-27'"
Fig. 14 - Propagation delay tpLH. tpHL control- ALL UNUSED INPUTS ARE CONNECTED TO Vss
signa/ output. Delay is measured at

Vas level of +10% from ground (turn-ani Fig. 76 - Input leakage current test circuit.
Fig. 15 - Maximum allowable control input
or on-state output level (turn-off). repetition rate.
WJ~AL5
I/-4PUTS
CHANNEL I
CHANNEL 2
PACKAGE :OUNT
2 - C040018
1- C040498
=\=
:3 - C04(668 CLOCK f U l J U l ; V D D
2 - (04018B MAK ALLOWABLE 10
SIGNAL LEVEL ... -30"1.1\'00 -VsSl
"ss ~IOK
CHAN I CHAN 2 i CHAN31 CHAN 4 ~
92CM-30928
Fig. 11- 4-channel PAM multiplex system diagram.
229
CD4066B Types
INPUTS (±5V)
I
rrv
I~{
[,CONTROL
INPUTS
I
ANALOG OUTPUTS (i5 Vl
92CS-30927
Fig. 18 - 8idirectional signal transmission via digital control logic.
92CS-35105
CD4066BH
CHIP PHOTOGRAPH

Dimensions in parentheses are in millimeters and represent 8 chip when It Is part of the waf.r, When the
wafar Is sspar.fed Into Individual chips. the angl. of
are derived 'rom the basic inch dimensions as in- c1.8v8ge may vary with respect to the chip 'Ice for
dicated. Grid graduations are in mils (10- 3 inch). different chips. The actual dimensions of the I,o/.t.d
chip, therefore. may differ slightly trom the nomin.1
dimensions shown. The user should consider 8 tol.rance
of -3 mils to +16 mils applicable to the nom;n.'
dimensions shown.
SPECIAL CONSIDERATIONS - CD4066B 2. In certain applications, the external

load-resistor current may include
1. In applic:ations that employ separate both VOO and signal-line com-
power sources to drive VOO and the ponents. To avoid drawing VOO cur-
signal inputs, the VOO current rent when switch current flows into
capability should exceed VOO/RL (RL terminals 1,4,8, or 11, the voltage drop
= effective external load of the four across the bidirectional switch must
C04066B bilateral switches). This not exceed 0.8 volts (calculated from
provision avoids any permanent cur- RON values shown).
rent flow or clamp action on the VOO No VOO current will flow through RL
supply when power is applied or if the switch current flows into ter-
removed from the C04066B. minals 2,3,9, or 10.
230
CMOS Analog COMMON 1• 24 Voo
Multiplexers/Demultiplexers
OUT[":
~
2 ~::J
21 10
4 20 II
CD4067B - Single 16-Channel • Low ON resistance: 125 n (typ.) over 15 • 3 19 12 *
Multiplexer/Demultiplexer V p_p signal-input range for VDO-VSS=15 V 2 18 13
CD4097B - Differential 8-Channel • High OFF resistance: channel leakage of I 17 14
Multiplexer/Demultiplexer ±10 pA (typ.) @ VOD-VSS=10 V o 16 I~
• Matched switch characteristics: RON=5 n (typ.)

10 I~ INHIBIT
for VDO-VSS=15 V "

The RCA-CD40678 and CD40978 CMOS Vss 12 13
• Very low quiescent power dissipation under
analog multiplexers/demultiplexers' are digi- all digital-control input and supply conditions:
*CHANNEL TOP VIEW
INIOUT CD4067B
tally controlled analog switches having low 0.2 J.lW (typ_) @ VDO-VSS=10 V TERMINAL ASSIGNMENT
ON impedance, low OFF leakage current, and ~2CS-24~1a
internal address decoding. In addition, the • Binary address decoding on chip

~N resistance is relatively constant over the • 5-V, 10-V, and 15·V parametric ratings
full input-signal range. • 100% tested for quiescent current at 20 V
•
• Standardized symmetrical output
The CD4067B is a 16-channel multiplexer characteristics
with four binary control inputs, A,B,C,D, and • Maximum input current of 1 J.lA at 18 V
an inhibit input, arranged so that any com- over full package temperature range; COMMON
)( OUTIIN I. 2' VDD
bination of the inputs selects one switch. 100 nA at 18 V and 250 C 2'
[
The CD4097B is a differential B-channel multi- • Meets all requirements of JEDEC Tentative • 22 I
plexer having three binary control inputs A, Standard No. 13A, "Standard Specifications • 21 2 Y CHAN.
B, C, and an inhibit input. The inputs permit
selection of one of eight pairs of switches.
A logic "1" present at the inhibit input turns
all channels off.
App/ications:
• Analog and digital multiplexing and demultiplexing
CHAN.)(
INIDUT f
4 20
"I.
17
J
:
COMMON
Y OUTIIN
INIDUT
I.
~} Y CHAN.
The CD4067 and CD4097 are supplied in24- • A/O and 0/A conversion 10 7 INIOUT
"
lead dual-in-line welded-seal ceramic pack- • Signal gating I.
ages (D suffix), 24-lead dual-in-Iine frit-seal Vss 12 13 INHIBIT
ceramic packages (F suffix), 24-lead dual- TOP VIEW

C04097B
in-line plastic packages (E suffix), 24-lead TERMINAL ASSIGNMENT
ceramic flat packages (K suffix), and in chip 92CS-.!4919
form (H suffix).
*When these devices are used as demultiplexers,

the channel in/out terminals are the outputs and
o~ ~
the common Dutlin terminals are the inputs.
!
I~'" , iI Fa
J OUTIIN
Recommended Operating Conditions at INIOUT I '>1 ~ !

.. O........I----o-?'o-
TA = 25 0 C (Unless Otherwise Specified)
VOO-24 VSS.,2 92CS-24924~!
For maximum reliability. nominal operating Fig. 1 - CD4D67 functional diagram.
conditions should be selected so that opera·
tion is always within the following ranges.
Values shown apply to all types except as
noted
Characteristic Min. Max. Units
(T A=Full Package· 3 lB V CD4067 TRUTH TABLE
Temp. Range) Selected
Multiplexer Switch Input A .8 C D Inh Channel
- 25 mA Fig. 2-CD4097 functional diagram.
Current Capability X X X X 1 None
Output Load Resistance 100 - n 0
1
0
0
0
0
0
0
0
0
0
1
NOTE: 0 1 0 0 0 2
In certain applications, the external load·resistor CD4097 TRUTH TABLE
1 1 0 0 0 3
current may include both VOO and signal-line 0 0 1 0 0 4 Selected
components. To avoid drawing VOD current when 1 0 1 0 0 5 A B C Inh o....n.1
switch current flows into the transmission gate 0 1 1 0 0 6
. inputs, the voltage drop across the bidirectional X X X I None
switch rhust not exceed 0.8 volt (calculated from 1 1 I 0 0 7 0 0 0 0 OX,OY
RON values shown in ELECTRICAL CHARAC- 0 0 0 1 0 8 I 0 0 0 IX,tv
TERISTICS CHART!. No Vee current will flow 1 0 0 1 0 9
0 I 0 0 2X,2Y
through AL if the switch current flows into 0 1 0 1 0 10
terminal 1 on the CD4061; terminals 1 and 11 on 1 1 0 1 0 11 I 1 0 0 3X,3Y
the Ce4097. 0 0 1 1 0 12 0 0 1 0 4X,4Y
1 0 1 1 0 13 1 0 1 0 5X,5Y
0 1 1 1 0 14 0 I I 0 6X,BY
1 1 1 1 0 15 1 I 1 d lX,7Y
231
ELECTRICAL CHARACTERISTICS
LIMITS at Indicated Temperature (OC)
CHARAC· CONDITIONS Values at -55, +25, +125 Apply to 0, F, K, H pkg Units
TERISTIC Values at -40,+25, +85,apply to E pkg
Vis VSS VDD -55 -40 +85 +125 +25
(V) (V) (V) I Min.1 Typ. I Max.
SIGNAL INPUTS (Vis) AND OUTPUTS (VOS)
Quiescent 5 5 5 150 150 - 0.04 5
Device Cur· 10 10 10 300 300 - 0.04 10 I1A
rent,lDD 15 20 20 600 600 - 0.04 20
Max.
20 100 100 3000 3000 - 0.08 100
..9~:state He
sistance Fig. 3- Typical ON resistance vs. input signal
VSS";; 0 5 800 850 1200 1300 - 470 1050 voltage 18" types).
Viso;;;VDD 0 10 310 330 520 550 - 180 400 !!
ron Max. 0 15 200 210 320 - 125 240
300
Change in
on·state
Resistance
(8etween
Any Two 0 5 - - - - - 15 -
Channels) 0 10 - - - - - 10 - 11
6. r on 0 15 - - - - - 5 -
OFF Chan·
nel Leak·
age Cur·
rent: Any -10 -7.5 -5 -2.5 0 25 7.5 '0
Channel I NPUT SIGNAL VOLTAGE I v IS I - V
OFF Max. 92C5-27127
or
0 18 ±100' ±1000' - ±0.1 (±100' nA
Fig. 4- Typical ON resistance vs. input signal
All Chan·
voltage falf types).
nels OFF
(Common
OUT/IN)
Max. co
SUPPLY VOLTAGE (VDD - Vss ) -15 V
Capacitance: \300
Input, Cis - - - - - 5 -
Output,
Cos ~ 200 i I AMBIENT TEMPERATURE
:! :
CD4067
-5 5
- - - - - 55 - pF
!! t t (TA)·+12S-C.
CD4097 - - - - - 35 ~ '00 H!
Feed· ~ 100 :l!: .
through, - - - - - 0.2 ~
Cios
:i 50...
::::
I...... ':i! .1.1
:::':
",1 ill:-
::::-
..~.
... 1
lllHlllill1t
"x 0 :1: ':!.t Il~' , llIll
Propaga· -10 -7.5 -5 -2.5 0 2.5 7.5 10
tion Delay
RL = 200Kn 5 - - - - - 30 60 INPUT SIGNAl. VOLTAGE (Vi') - V
VDD CL =50 pF 10 - - _. - - 15 30 ns 92.C5-21329
Time (Sig'
nal Input It. t"tj=20 ns 15 - - - - - 10 20 Fig_ 5- Typical O~ resistance vs. input signal
to Output voltage la" types).
CONTROL (ADDRESS or INHIBIT) Vc
Input Low
RL=l Kll 5 1.5 - - 1.5
Voltage, to VSS 10 3 - - 3
=VDD IIS<2I1A
VIL Max.
thru on all OFF 15 4 - - 4
V
Input High 1 K!1 Channels 5 3.5 3.5 - -
Voltage, 10 7 7 - -.
VIH Min.
15 11 11 - -
* Determined by minimum feasible leakage measurement for automatic testing.
INPUT SIGNAL VOLTAGE IVI,) - V

92C5-27530
Fig. 6- Typical ON resistance vs. input signal

232
ELECTRICAL CHARACTERISTICS (Cont'd) TEST CIRCUITS
LIMITS at Indicated Temperature (OC)

CHARAC- CONDITIONS Values at -55, +25, +125 Apply to 0, F, K, H, pkg
TERISTIC Units
Values at -40,+25,+85,apply to E pkg Voo
Vis VSS VDD -55 -40 +85 +125 +25 V~D
2.
(V) (V) (V) Min_ Typ. Max. Vss
"
22
Input 21
Current, VIN=0,18V 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 iO.l MA 20
liN Max.
I.
"
I'ropagation
Delay Time:
Address Dr
RL "10 K£l,CL-
50 pF, tr,tf~20 ns
Voo
I.
17
Inhibit-to- O 5 - ... - - - 325 650

Signal OUT
(Channel
0 10 - - - - - 135 270 ns
turning ON) 0 15 - - - - - 95 190 92CS-21311
•
Address or R L =300 S!,CL =
Inhibit-to· 50 pF. t"tf~20 ns
Signal OUT _.
0 5 - - - - 220 440
(Channel
0 10 - - - - - 90 180 ns
turning
OFF) 0 15 - - - - - 65 130
Input
Capaci- Any Address or - - - - - 5 7.5 pF
tance, CIN Inhibit Input
92CS-215l2
MAXIMUM RATINGS, Absolute-Maximum Values: Fig. 7-0FF chsnnelleakage current-any channel OFF.
DC INPUT CURRENT, ANY ONE INPUT il0mA
For T A = -40 to +60o C (PACKAGE TYPE E) . . _ . . . . .. 500 mW
For T A = +60 to +850 C (PACKAGE TYPE E) Derate Linearly at 12 mW/oC to 200 mW Voo
For T A = -55 to +100'C (PACKAGE TYPES D, F, K) . . . _ _ . . . . . . . . . . . . . . 500 mW Voo
For T A = +100 to +125'C (PACKAGE TYPES 0, F, K) . . . . . Derate Linearly at 12 mW;oC to 200 mW
2'
DEVICE DISSIPATION PER OUTPUT TRANSISTOR VSS
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) 100mW "
22
OPERATING-TEMPERATURE RANGE (TA): 21

PACKAGE TYPES 0, F, K, H . _ _ _ _ _ . . _ . . . . . . . . . . . .
PACKAGE TYPE E _ . . . . . . . . . . . . .
STORAGE TEMPERATURE RANGE ITstg )
-55 to +125'C
-4010 +85'C
-65 to +150 0 C Voo
,.
20
"
17
At distance 1/16 ± 1/32 inch (1.59 ±0_79 mm) from case for IDs max. +265 0 C V55
Voo
I Kil
2.
23
I KIl
22
21
20 Voo-YIH
19
II
12
CD4097
V,L V,L
92CS-27337R2
Fig. 8-lnput voltage-measure <2 ~ on all OFF channels Fig. 9- OFF channel leakage current-all channels OFF.
(e.g., channel 12J.
233
ELECTRICAL CHARACTERISTICS (Cont'd) TEST CIRCUITS (Cont'd)
VDD
TEST CONDITIONS
TYPICAL
CHARAC- Vis VDD RL VALUES
TERISTIC UNITS
(V) (V) (KnI 2.
23
Cutoff 5- 10 1 22
(-3-dB) C04067 14 21
Vos at Common OUT/IN
I.
20
Frequency Vos C04097 20
Channel ON 20 log -=-3 dB MHz "
(Sine Wave Vis Vos at Any Channel 60 17
Input)
Total 2- 5 0.3
Harmonic 3- 10 10 0.2
Distortion, 5- 15 0.12 %
THO 92:CS-21338
fis = 1 kHz sine wave Voo

5- 10 1
-40-dB
Feedthrough C04067 20
Frequency Vos Vos at Common O}JT/IN 2.
C04097 12
(All Channels 20 log -=-40 dB MHz 23
OFF Vis Vos at Any Channel 8 22

21
I.
20
5- 10 1
"
Signal Cross· Between Any 2 Channels· 1
17
talk (Fre- Vos Between Measured on Common 10
quencyat 20 log -=-40 dB Sections MHz
-40 dB) Vis C04097 Measured on Any
18
Only Channel
- 10 10' 92C$-27339
Address·or- VSS=O, t"tf=20 ns, Fig. 10- Ouiescent deyice current.

Inhibit-to- VC=VOO-VSS 75 mV
Signal (Square Wave) (Peak)
Crosstalk
- Peak-to-peak voltage symmetrical about - - - -

Voo-Vss
2
• Worst case.
Both ends of channel.
22
4 21
5
I.I.
20
10
I.
17
vDD
...rt...: vss
C04067
92C5-21342'1I
'00 VDD VDD

Q
YgD
2.
23
I Vg~
2'
23
Ygo
2.
Vss Vss Vss
23
22 22 VDO
22
VDO VDO
• 21 4 21
5
7
20
I.
19
5
I.I.
20
• I.
17
I.
17
92CS-Zn4JR' 92CS-Z7343RI
92CS-H)_ORI
Fig. 12- Turn-on and rum-off propagation delav-

Fig. 11- Turn-on and turn-off propagation delay-address select input to signal output
inhibit input to signal output (e.g. measured
(e.g. measured on channel 0).
on channel 1).
234
92CS-27042Rl
Fig. 13- Channel ON resistance measurement circuit. Fig. 14- Propagation deiav waveform channel Fig. 15- Propagation delay waveform, channel
being' turned ON (RL = 10 K n. CL = 50 pF). being turned OFF (R L = 300 n,
C L =50pF).
-I r;: CHANNEL
IN/OUT Y
a\_ CHANNEL ~
IN/OUT X
•
Voo II ~@<W@) d{2t)(;2)(23~{2)(3)~(
15 14 13 12 II
CHANNEL IN/OUT
10 9 a 7 6 5 4 3 2 I 0
'iOO
2
76!5432 10765432
15)\1~~~ !OJ(zi)~ 2)(8 '2)(3)(4'~ 6 ..".
10
CY>CP'
(
'~01Le-
2
I~
Lf3-
~
~----l-B-
B- L------B-~IIN
COMMDN
-G-
~'O
=s- L----B-
-a-
>-
'9- iD
~ L-------------6-
*11
9- %
t:
~
-G- H5 DN
~-------~~
*I.
<?- &!
l!I
8 B-
OUT.>IN
L -_ _ _ _ _ _ _ _~~
.9- l!I.
*,.'~
!!!
l'i
- -B- L--.----~_B__
IN
~
~
4
Z
iD
G- ~
~
4
Z
'-----------1-B-
-B- iii
~~+_+_+--------------~-B-=Tr-G ~~:
-B- '----------------6--1 TG YOUT/IN
-G- L----------------------------l-B--
-B- '------------j@-
B- L---------B-
vDD '*ALL INPUTS PROTECTED BY
--
i3f"
'*ALL INPUTS PROTECTED BY
Vss" 12 COS/MOS PROTECTION NETWORK
Vss
Vss
VSS 92CM' 2733.
Fig. 16- CD4061logic diagram.
Fig. 1l-CD40911ogic diagram.
235
SPECIAL CONSIOERATIONS capacitor connected to the input or output
In applications where separate power sources of the channel will lose 3-4% of its voltage at
are used to drive VDD and the signal inputs, the moment the channel turns on or off.
the VDD current capability should exceed This loss of voltage is essentially independent
VDD/RL (RL=effective external load I. This of the address or inhibit signal transition
provision avoids permanent current flow or time, if the transition time is less than 1-2 /.IS.
clamp action on the VDD supply when power When the inhibit signal turns a channel off,
is applied or removed from the CD4067B or there is no charge dumping to VSS. Rather,
CD4097B. there is a slight rise in the channel voltage
level (65 mV typ.1 due to capacitive coupling
When switching from one address to another, from inhibit input to channel input or output.
some of the ON periods of the channels of Address inputs also couple some voltage
the multiplexers will overlap momentarily, steps onto the channel signal levels.
which may be objectionable in certain appl i-
cations. Also when a channel is turned on or In certain applications, the external "load-
off by an address input, there is a momen· resistor current may include both VDD and
tary conductive path from the channel to signal·line components. To avoid drawing
VSS, which will dump some charge from any VDD current when switch current flows into
capacitor connected to the input or output the transmission gate inputs, the voltage drop
of the channel. The inhibit input turning on across the bidirectional switch must not ex·
a channel will similarly dump some charge to ceed 0.8 volt (calculated from RON values
shown in ELECTRICAL CHARACTERIS-
VSS·
TICS CHART). No VDD current will flow
The amount of charge dumped is mostly a through R L if the switch current flows into
function of the signal level above VSS. terminal 1 on the CD4067B, terminals 1 and
Typically, at VDD-VSS=10 V, a 100-pF 17 on the CD4097 B.
92CM-~104
Dimensions and pad layout for CD4067BH. Dimensions and pad layout for CD4097BH.

represent. chip when it is pan o( the wafer. When the
waf., ;s separated into individual chips, the angle of
Dimensions in parentheses are in millimeters and are cleavage may vary with respect to the chip lace for
derived from the basic inch dimensions as indicated. different chips. The actuel dimenSions of the isolated
dimensions shown. The user shouldconsidera tolerance
dimensions shown.
236
CD4068B Types
Features:
CMOS a-Input • Medium·Speed Operation:
tpHL, tpLH = 75 ns (typ.) at VDD = 10 V
NAND/AND Gate • Buffered inputs and outputs
• 5·V, 10·V, and 15·V parametric ratings
High·Vo)tage Types (20·Volt Rating) • 100% tested for quiescent current at 20 V
• Maximum input current of 1 IlA at 18 V
over full package·temperature range;
100 nA at 18 V and 250 C
The RCA·CD4068B NAND/AND gate pro· • Noise margin (over full package·temperature
vides the system designer with direct imple· range): 1 Vat VDD = 5 V '0'00. 14
mentation of the positive·logic 8·input NAND 2VatVDD=10V 2.5VatVDD=15V "'55.7 6,a"NO CONNECTION
and AN D functions and supplements the • Meets all requirements of JEDEC Tentative 92CS-2,S]4R3
existing family of CMOS gates, Standard No. 13A, "Standard Specifications
FUNCTIONAL DIAGRAM
dual-in-line ceramic packages (0 and F suf-
•
fixes); 14-lead dual-in-line plastic packages
(E suffix), 14-lead ceramic flat packages (K
suffix), and in chip form (H suffix), RECOMMENDED
OPERATING CONDITIONS
K'A'B·C-Q·E·F-G-H I.
For maximum reliability, nominal operating C 4
conditions should be selected so that operation
A
,
2
12 is always within the following ranges: 0 •
"
'0
NC
vss NC CHARACTERISTIC 'Min. Max. Units
'l2CS'-24578k2
ITO~ VIEW)
Supply,Voltage Range
Nez,..O CONNECTION
(For T A = Full Package ~2CS 29093
TERMINAL ASSIGNMENT Temperature Range) 3 18 V

LIMITS AT INDICATED TEMPERATURES 10C)

CONDITIONS Values at -55, '25, '125 Apply to D, F, K, H Packages
ISTIC UNITS
Vo VIN VDD +25
IV) IV) IV) -55 -40 +85 +125 Min. Typ, Max,
Quiescent Device - a,s 5 0.25 0,25 7,5 7,5 - 0,01 0,25
Current, - 0,10 10 0,5 D,S 15 15 - 0,01 D,S
IJA
100 Max,
- 0,15 15 1 1 30 30 - 0,01 J
- 0,20 20 5 5 150 150 - 0,02 5
Output low 0.4 0,5 5 0,64 0,61 0.42 0,36 0.51 1 -
ISink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - ORAIN-TO-SOURCE VOLTAGE IVosl-V
IOl Min. 15 4.2 4 2.8 2.4 34 6.8
1.5 0,15
rnA Fig. 2 - Typical output low (sink) current
Output High 4.6 0,5 5 -0,64 -0.61 -0.42 -0.36 -0.51 -1 - characteristics.
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current,
IOH Min.
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - a 0,05
Low-Level,
VOL Max.
- 0,10 10 0.05 - 0 0.05
- 0,15 15 0.05 - a 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·level,
VOH Min.
- 0,10 10 9.95 9.95 10 -
- 0,15 15 14.95 14.95 15 -
Input low 0.5,4.5 - 5 1.5 - - 1.5
Voltage,
Vll Max.
1,9 - 10 3 - - 3
1.5,13,5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9. - 10 7 7 - -
VIH Min.
1.5,13.5 - 15 11 11 - - ORAIN-TO-SOURCE VOLTAGE (Vosl-V
Fig. 3 - Minimum output low (~;~t;731'R'

Input Current
liN Max.
0,18 18 ::0.1 :0.1 ::1 :1 - :10- 5 :to. 1 IJA current characteristics.
237
CD4068B Types
MAXIMUM RATINGS, Absolute-Maximum Valusa: DRAIN-TO-SOURCE VOLTAGE tVosl-V
1
bc SUPPLY-VOLTAGE RANGE, (VDD)
(Voltages referenced to VSS Terminal) ...•••.•.••••.•.•.•.•••.......••..•.••.•.•.•.••. -O.S to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -o.S to VDD +O.S V
For T A = -40 to +6OoC (PACKAGE TYPE E) ................................................. SOO mW
For T A = +60 to +8SoC (PACKAGE TYPE E) ... ................ Derate Linearly at 12 mW/oC to 200 mW
For T A = -55 to +IOO°C (PACKAGE TYPES D, F, K) .......................................... 500 mW
For T A = +100 to +125°C (PACKAGE TYPES D, F, K) .......... Derate Linearly at 12 mW/oC to 200 mW
PACKAGE TYPES D, F, K, H ........................................................ -55 to +12SoC
PACKAGE TYPE E .................................................................. -40 to +8SoC
92CS-24)20~)
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +IS0°C Fig. 4 - Typical output high (source)
LEAD TEMPERATURE (DURING SOLDERING): current characteristics.
At distance 1I16± 1/32 inch (I.S9 ±0.79 mm) from case for 10 s max.......................... +265°C
DRAIN-TO-SOURCE VOLTAGE {VOSI-V
At TA ~ 2!f'C; Input tr , tf~ 20ns, CL ~ 50pF, RL ~ 200kU
ALL TYPES
TEST CONDITIONS
LIMITS
V DD
TYP. MAX.
VOLTS
tpHL. tPLH 10 75 150 ns
15 55 110
5 100 200
ITHL, ITLH 15 40 80 Fig. 5 - Minimum output high (;~~~~,;ri
Input Capacitance, CI N Any Input 5 7.5 pF
VDO
"
12
10 *
•*

3
..
*
.
..
.2CS·1t0 . .
Vss
* ALLINPUTS PROTECTED BY 92eM-29094 Fig. 8 _ Typical propagation delay time
COSfMOS PROTECTION
Fig. 7 - Schematic di8gram. NETWORK as a function of load t;spac;tance.
238
CD40688 Types
AMCIENT TEMPERATVRE(TAI'2~'C: H~ HU Illl :~H "":, AMBIENT TEMPERATURE ITAI' 25-c
~~~~~tn~~t:~;:JH~~ ~;~ :::: fiH i@ , II .IV " VOO

~l~~~
>
~ 10"',
~":#F.lH :::: :::~ :::: :::: ::: :::: ::1 :g: 18 ,
6
: . ;~tt ~~~~ l~~~ :::: :::: ~~~~ ~~~~ I~~t ~~: ~~ , .f'~?-IL INPUTS r-~--'
~ 10 : :~g :fg :~~~ ~;~~ j~~~ ~~~~ ~~;~ :~g g

~~I01,
2:: ... (,
..Ii L"
-t-
o
Vss
138 "
Q~
~~
, LIL"
/"
j:t,:1:¢ ,'I ::: :::'W':: t:;:
...
- . . . '."
::::,,:;:'
•••• " d l t t i t •
. -+_ ......
~ '" ,I CL ,50 pF
• j' :H
10
iliWiU :i!HliH
INPUT VOLTAGE lVII-V
15 20
"
10
,
, , .. , .. , ..
10
,
102
INPUT FREQUENCY (111- kHI
,
CL'I5 pF ---
101
, , .
10'
Fig. 9 - Typical voltage transfer charac· Fig. 10 - Typical dynamic power dissi·
teristics (NAND outputl, pation as a function of frequency. Fig. 11 - Quiescent·device·current test circuit.
V~NPU(J' ::.;,.'"~ ... V,"

'--
INPUTOVDOOUTPUTS
~
•
o ~
Vss
SEQUENTIALLY,
TO 80TH VDD AND 'iss'
CONNECT ALL UNUSED
V~L :t CLOCK
INPUTS TO EITHER
NOTE:
VOD OR VSS'
VSS Vss TEST ANY COMBINATION
OF INPUTS
Vss =
92CS-27441RI 92cs-zt09'
Fig. 14 - Dynamic power dissipation

Fig. 12 - Input current test circuit. Fig. 13 - Input· voltage test circuit. test circuit.
The photographs and dimensions of each CMOS Chip

Dimensions in parentheses are in millimeters and are wafer is separated into individual chips. the angle 01
derived from the basic inch dimensions as indicated. cleavage may vary with respect to the chip face for
Grid graduations are in mils (10- 3 inch). different chips. The actual dimensions of the isolated
dimensions shown. The usar should consider a tolerance
dimensions shown.
239
CD4069UB Types
CMOS Hex Inverter

Features:
A~G"A
• Standardized symmetrical output el{>o-i-H =B
characteristics
The RCA-C04069UB types consist of six • Medium Speed Operation-tpHL,tpLH=30 ns (typ.1 c--L{>o-!- I =E
CMOS inverter circuits. These devices are at 10 V o..L.{>-!- J ~ 5
intended for all general·purpose inverter E.!L.{)ol2-I< ,. E
• Maximum input current of 1 J1A at 18 V
applications where the medium-power TTL·
drive and logic-level-conversion capabilities
100 nA at 18 V and 25 0 C F~L:F
of circuits such as the C04009 and CD4049 VOO=14
Hex Inverter/Buffers are not required. • Meets all requirements of JEDEC Tentative YSS=7 92CS-23737R2
The CD4069UB-Series types are supplied in for Description of 'B' Series .CMOS Devices"
14-lead hermetic dual-in-line ceramic pack- CD4069UB
ages (0 and F suffixes), 14-lead dual-in-line FUNCTIONAL DIAGRAM
Applications:
plastic package (E suffix), 14-lead ceramic
flat package~ (K suffix). and in chip form (H • Logic inversion
suffix).
• Pulse shaping
• Oscillators
• High-input-impedance amplifiers

operation is al .. ays within the following ranges:
Min. Max.
Supply·Voltage Range (For T A =Full Package· 3 18 V
Temperature Range)
I I
INPUT VOLTAGE 1Y11-V
Fig. 1 - Minimum and maximum voltage

MAXIMUM RATINGS, Absolute-Maximum Values: transfer characteristics.
DC SUPPLY-VOLTAGE RANGE. (Voo)

(Voltages referenced 10 VSS Terminal I -0.510+20 V
INPUT VOLTAGE RANGE, ALL INPUTS -0.510 VDo +0.5 V
o
For T A = -40 10 +60 C (PACKAGE TYPE E) . . . . . . • .. 500mW
For T A = +60 10 +85 0C (PACKAGE TYPE EI Derate Linearly at 12 mW/oC to 200 mW
For T A = -55 to +100·C (PACKAGE TYPES 0, F, K) . . . . . . . .. 500mW
For TA = +100 to +12S·C (PACKAGE TYPES 0, F, K) Derale Linearly al 12 mW/oC 10 200 mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) loomW
PACKAGE TYPES 0, F, K. H -55 10 +1250C 2.'
PACKAGE TYPE E . -4010 +850 C
STORAGE TEMPERATURE RANGE (Tslg ) -65 10 +1500 C 7.5 10 12.5 15
INPUT VOLTAGE 1VII-V
AI distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
Fig. 2 - Typical voltage transfer characteristics as a
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 250 C; Input y, 't = 20 ns, function of temperature.
CL a 50 pF, RL = 200 Kn
17.5 AMBIENT TEMPERATURE {TA'· 25" C =1+
CONDITIONS ALL TYPES TTTTlTTTlTTTTI rT r,r!~t
15 SUPPlY VOlTAGE {VooI"15Y
CHARACTERISTIC LIMITS
VDD UNITS
V Typ. Max.
5 55 110
10 30 60 ns
Propagation Delay Time, tpLH' tpHL
15 25 50
5 100 200
2.' + ... + , ••• 2.15
Transition Time;
tTHL' tTLH 10 50 100 ns 5V .. : :::: 0
2.5 5 7.5 10 12.5 15
15 40 80 INPUT VOlTAGE '''IJ-V
Input Capacitance; CIN Any Inpul 10 15 pF Fig. 3 - Typical current and voltage transfer
characteristics.
240
CD4069UB Types
fATIC ELECTRICAL CHARACTERISTICS
.
E
I
AMBIENT TEMPERATURE (TAI-25·C
CONDITIONS Values at -55, +25, +125 Apply to D,F,K,H Packages -"

,:!030
GATE-TO-SOURCE VOLTAGE (VGS,.15 V
CHARACTER· Values at -40, +25, +85 Apply to E Package ~
UNITS z
ISTIC +25 ~ 2~
Vo VIN VDD 3;:: 20
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
-
§ 10V·
uiescent Device - 0,5 5 0.25 0.25 7:5 7.5 0.01 0.25
Current, ~ "
- 0,10 10 0.5 0.5 15 15 - 0.01 0.5 ~ 10
100 Max. J-lA
- 0,15 15 1 1 30 30 - 0.01 1 § , 'v
- 0,20 20 5 5 150 150 - 0.02 5
0 ,
utput Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - '0
DRAIN-TO-SOURCE VOLtAGE (Vosl-V " ,),C' <4 ',e~'
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - Fig. 4 - Typical output low (sink)
IOL Min. current characteristics.
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.!>1 -1 - mA
utput High
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - "."~iir' ~'.'.'
A."'.'
$
Current,
IOH Min.
9.5
13.5
0,10
0,15
10
15
-1.6 -1.5
-4.2 -4
-1.1
-2.8
-0.9
-2.4
-1.3
-3.4
-
-2.6
-6.8
0
-
-
0.05 I~' ~ VOLTA
I
I~.
utput Voltage: - 5 5 0.05
Low·Level, 0.05 - 0 0.05
- 10 10
VOL Max.
- 15 15 0.05 - 0 0.05
V
I
'utput Voltage: - 0 5 4.95 4.95 5 - ~

High·Level, -
VOH Min.
-
-
0
0
10
15
9.95
14.95
9.95
14.95
10
15 - i"
,put Low 4.5 - 5 1 - - 1 DRAIN-TO-SOURCE VOLTAGE (Vasl-V
Voltage, 9 - 10 2 - - 2
nCS-2.31')~1
VIL Max. Fig. 5 _ Minimum output low (sink)

13.5 - 15 2.5 - - 2.5 current characteristics.
V
,put High 0.5 - 5 4 4 - -
Voltage, 1 - 10 8 8 - - DRAIN-TO-SOURCE VOLTAGE IVosl-V
.,
VIH Min.
1.5 - 15 12.5 12.5 - - AMBlE NT TEMPERATURE (TA,-25·C
." "0
ruE 0
,put Current
- ±10-5
k~.,;U~~-J.."-''''
~~-TO-SOURC£ VOLTAG~·t':G·s)~:~~
••
_+
~-5 f
liN Max.
0,18 18 ±0.1 ±0.1 ±1 ±1 ±0.1 J-lA .. :::t11I1H: E: . t:l!::: w.r-
.!.: 5
voo
Voo !"!-
+~
:l~m
• • ~
• • • • • • -i •
In!!
....• t·
HI t : . :1:: -IO~
., t
n
.... ..... ~~~~ -I~!
JL ~~---- -~~
nd G'A
A-~-VDO
G-i-2
B- 3
13~F
12-L-'F
",.....,
E ~
..
...
....
:::!~:
....
••••
...
.. t
~IOV
~~:: .....
IJ.:.H
t· .. 't:' ::::
.... ~-25~
:. . 3
;::~ -20~
:
LJ~'U'"
A~
H·jj- 4 ;-tj. •• .r!: ....
~ -!7: f~-:
c- • IO-K-E' -ISV .",<
1<3,5,9,'11,131
I'~- 6 ," +:
., : , ,
~
9,-0
Vss 7
• J -5 HI
(TOP VIEWI
92C5-24444 ~1'lH tHlf lili iii III 5
\Iss 92CS, 23736R2

Fig. 7 - CD4069UB terminal assignment. Fig. 8 - Typical output high (source)
Fig. 6 - Schematic diagram of one of six identical current characteristics.
inverters.
DRAIN-TO-SOURCE VOLTAGE tvDsl-V
AMBIENT TEMPERATURE (TAl- 25-C
-'
'"
.!'-IZO
~
:100
'"2
~ BO
15pF
10 15 20
. uCS·2·UIAl SUPPLY VOLTAGE (VCDI-V 92CS-24435RI
Fig. 9.- Minimum output high (source) Fig. 10 - Typical prppagation delay time vs. Fig. 11 - Typical propagation delay time vs.
current characteristics. load capacitance. supply voltage.
241
CD4069UB Types
':.
ffi
I~
. AMBIENT TEMPERATURE (TA)- 2f-C
.~ X
I¥'''~V
2
V
~~
~
!
ili
·
' -- I- ~~
~'r~y
,,'" ,0
'o~
,~ .,-
o:~•
~,No
i ,~ == ./. '"
~ V
ili ·, , , LOAD CAPACITANCE le,,)- 50pf
CI r pF FIXTUREt '9pF EXT.)
LOAO C"'''CITANCE ICI.,I-pF

~
° 10
.. ... , .. ., .. -~-CL -u,pF(IIpF
I IIII I IIII I III

INPUT FREQUENCY (f) kHz
10'
FIXTURE+ 4pFEXT.)
6810121416
SUPPLY VOLTAGE 1VOO)-VOLTS
9ZCS-211114RI
92C8-:5"12
Fig. 12 - Typical transition time VB. load Fig. 13 - Typical dynamic power dissipation Fig. 14 - Variation of normalized propagation
capacitance. VI. frequency. delay time (tpHL and tpLH) with
supply voltage.
VDD
VD~VDD INPUTS V,H INPUQTSUTPUTS.
v:s :--.
VIL
~
't" INPUTOVDD NOTE.
V'-<!>-DD MEASURE INPUTS SEQUENTIALLV,
TO BOTH Voo ANO vss.
I CONNECT ALL UNUSED INPUTS
VSS o TO EITHER Yoo OR Vss.
NOTE:
TEST ANY ONE INPUT, WITH OTHER V••
Vss INPUTS AT VOD OR Yss
v••
Fig. 15 - Ouiescen t device current test circuit. Fig. 16 - Noise immunity test circuit. Fig. 17 - Input leakage current test circuit.
APPLICATIONS
VDD
1/6 C04069
PULSE GEN.
tr·tf·20ft~
I.
"I>
FOR TYPICAL COMPONENT
VALUES AND CIRCUIT
IN
"
10 PERFORMANCE, SEE
• APPLICATION NOTES
ItAN 6086 AND
ICAN 6539
~------~----~T
200kO
92CM-2444!'Utl
92CS-24437RI
Fig. 18 - Dynamic electrical characteristics test circuit and waveforms. Fig. 19 - Typical crystal oscillator circuit.
113 CD4069
ffi~
1/6 CD4069
I N n OUT
92CS-24459Rl
FOR TYPICAL COMPONENT
VALUES ANO CIRCUIT PERFORMANCE,
SEE APPLICATION NOTE :ICAN-1466
Fig. 20 - High4nput impedance amplifier. 92(:5-24438112
Fig. 21 - Typical RC oscillator circuit.
113 C04069
IN~M
Voo
SOD,'
., 101tHI,
100 KH1, I MHI
Dimensions and pad layout for CD4069UBH.
UPPER SWITCHING POINT: I.
Dim.n$ions in parentheses are in millimeters and are
Vp. RS;'Rt . V~o
,
4CD4069UBII
"" derived from the basic inch dimensions a$ indicated.
LOWER SWITCHING POINT: Grid graduations arB in mils "0- 3 inch).
• .0
Rt - As Voo Th. photographs and dimensions of each CMOS chip
YN" - . - , - ' , - represent a chip when it Is part of the wafer. When the
wafer ;s separated into Individual chips, the angle of
Rt )0 RS cleavage may vary with respect to the chip face lor
92CS-24440RI CL INCLUOES dilierent Chips. The actual dimensions of the isolated
FIXTURE CAPACITANCE. chip. therefor., may differ slightly trom the nominal
Fig. 22 - Input pulse shaping cirCuit dimensions shown. The user should consider a tolerance
(Schmitt trigger). FIg. 23 - DynamIc powe, dissipation test cIrcuit. 01 -3 mils to +16 mils applicable to the nominal
dimensions shown.
242
Features:
CMOS • Medium-speed operation-tpHL, tpLH =
Quad Exclusive-OR and 65 ns (typ_) at VDD = 10 V, CL = 50 pF
Exclusive-NOR Gates
.5-V, 10-V, and 15-V parametric ratings
.'.2
c'
0'
'J
• K
E'
• Maximum input current of 1 J.lA at 18 V
CD4070B - Quad Exclusive-OR Gate
CD4077B - Quad Exclusive-NOR Gate
100 nA at 18 V and 25°C
• Noise margin (overfull package-temperature
."
F'
H"
J.A0B M'G(!)H
"M
KICeD L'E0 F
range):
The RCA-CD4070B contains four independ- "'55"
1 V at VDD = 5 V VOO'I4 'nCS'24~b&"2
ent Exclusive-OR gates. The RCA·CD4077B 2 Vat VDD = 10 V
contains four independent Exclusive-NOR 2.5 V at VDO = 15 V CD4070B
gates. • Meets all requirements of JEDEC Tentative FUNCTIONAL DIAGRAM
The CD4070B and CD4077B provide the Standard No. 13A, "Standard Specifications
system designer with a means for direct for Description of'S' Series CMOS Devices"
implementation of the Exciusive·OR and
Exclusive-NO R functions, respectively.
The CD4070S and CD4077S types are sup-
App/ications:
• Logical comparators • Adders/subtractors
• Parity generators and checkers
.'
AI
c'
I
plied in 14-lead hermetic dual-in-line ceramic o·
."
packages (0 and F suffixes), 14-lead dual- E
F •9
in-line plastic packages (E suffix), 14-lead
H "
ceramic flat packages (K suffix), and in chip
form (H suffix).
MAXIMUM RATINGS, Absolute-Maximum Values: 92CS-2449111'3
DC SUPPLY·VOL TAGE RANGE. (V Dol

(Voltages referenced to VSS Terminall -0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS -0.5 to VDD +0.5 V C04077B
DC INPUT CURRENT. ANY ONE INPUT ±10mA Functional Diagram
For T A = -40 to +60 0 C (PACKAGE TYPE E) . . . . . . . .. 500mW
For T A = +60 to +85 0 C (PACKAGE TYPE E) . Derate Linearly at 12 mW/oC to 200 mW
For TA = -5510 +100'C (PACKAGE TYPES D. F. K) . . • . . . . .. 500mW
For T A = +100 to +125'C (PACKAGE TYPES D. F. K) Derate Linearly at 12 mW/oC to 200 mW RECOMMENDED
OPERATING CONDITIONS
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) 100mW For maximum reliability, nominal operating
OPERATING-TEMPERATURE RANGE ITA): conditions should be selected so that opera-
PACKAGE TYPES 0, F, K, H ' -55 to +125 0 C tion is always within the following ranges:
STORAGE TEMPERATURE RANGE (Tstg ) -65 to +1500 C Characteristic Min. Max. Units
LEAD TEMPERATURE (DURING SOLDERING): Supply-Voltage Range
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max. (For T A = Full Package- 3 18 V
Temperature Range)
. I.
S
J4A@B
2
3
14
"
12
VOo
H
G
K·C$D II M-GG)H
C 10 L4E$F
TRUTH TABLE C04070B
• F
1 of 4 Gates Vss • E
A ITOP VIEW}
B J
e
92r.5-24498
0 0 0 TERMINAL ASSIGNM~NT
1 0 1 C04070B
0 1 1 I.
I".
Voo
Vss
oo
Vss 1 1 0 •
J-A$B
" H
G
* INPUTS KaC$D M.GijjH
PROTECTED
BY COS/Mas
PROTECTION NETWORK
- --
1 = HIGH LEVEL C "
10 L'~
0= LOW LEVEL F.
Vss E
J=A0B
Vss (TOP VIEW I
92CS-24499R2
Fig. 1 - Schematic diagram for CD4010B TERMINAL ASSIGNMENT

(1 of 4 identical gates) .•" CD4077B
243
'''~ ..p - - - - . - t - - - - H
9: 55 : TRUTH l'ABLE CD4077B

1 of 4 Gates
A B J
0 0 1
1 0 0
0 1 0 ,
~
oo vss DRAIN-lO-SOURCE VOLTAGE (VDSI-~
Vss
1 1 1
*rNPUTS PROTECTED --- 1 ~ HIGH LEVEL current characteristics.
BY COS/MOS
PROTECT ION NETWORK o ~ LOW LEVEL
J ~ A <Zl B
vss 92CS-30093RI
Fig. 2 - Schematic diagram for CD40778

(1 of 4 identical gates).
CHARAC-
Values at -55, +25, +125 Apply to D, F, K, H Pkgs. II ..
TERISTIC DRAIN-TO-SOURCE VOLTAGE lVosl-V
Vo VIN VDD +25 '2tS·2.~lt'"
(VI (VI (VI -55 -40 +85 +125 Min. Typ. Max. Fig. 4 - Minimum output low (sink)
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device
Current
-
-
0,10
0,15
10
15
2
4
2
4
60
120
60
120
-
-
0.02
0.02
2
4
p.A
DRAIN-lO-SOURCE VOLTAGE (VoSI-V
AMBlE NT TEMPERATURE (TA'-2S-C

-I' -10 -. 0
IDD Max. - 0,20 20 20 20 600 600 - 0.04 20 "

GATE-lO-SOURCE vOLTAGE {VGSI--5V
-5
c
f
~
Output Low -IOE!
(Sink) 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - is
-15 ~
Current, 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
-IOV
10L Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 - rnA
-20~
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1
r---=- -25~
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - -15V
-30 1
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - ~5
Output Volt-
age: - 0,5 5 0.05 - 0 0.05
<JltS-Z.3Z0R3
Low·Level, - 0,10 10 0.05 - 0 0.05 current characteristics.

VOL Max. - 0,15 15 0.05 - 0 0.05 oRAIN-TO-SOURCE VOL.TAGE (VosJ-V
Output Volt-
V
AMBlE NT TEMPERATURE ITA)" ZS"C
-!> -10 -. 0
age: - 0,5 5 4.95 4.95 5 -

GATE·TO·SOURCE VOLTAGE IVGsJ"·5 v
High· Level, - 0,10 10 9.95 9.95 10 - III
VOH Min. - 0,15 15 14.95 14.95 15 -
....
tm tlq !! . ., .
-,
Input Low
Voltage,
0.5,4.5
1,9
-
-
5
10
1.5
3
-
-
-
-
1.5
3 ~ :-lH
f'
-IOV
~ •• , I
..
HL .... ···t .rr:
-K)
:
- .. ...,. ...
VIL Max. 1.5,13.5 - 15 4 - 4 ·1:; .
~
..
Input High 0.5,4.5 - 5 3.5 3.5 - -
V
t:- 15\; •• iili n! .....,
. mII
-I>
Voltage, 1,9
1.5,13.5
-
-
10
15
7
11
7
11
-
-
-
-
. : ttl
: 1
VIH Min.
Input
~H rmill dl! tI
Current, - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 p.A
9lC5-Hlll~l

liN Max. current characteristics.
244
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =250 C; Input 1,. tt =20 ns.

CL = 50 pF. RL = 200 Kfl
CONDITIONS ALL TYPES

CHARACTERISTIC LIMITS
VDD UNITS
V Typ. Max.
5 140 280
10 65 130 ns
tpHL' tpLH
15 50 100
5 100 200 LOAD CAPaCITANCE IC L I-pf
,zn·,nn
Transition Time;
tTHL' tTLH 10 50 100 ns Fig. 7 - Typical transition time as a
15 40 80 function of load capacitance.
Input Capacitance; Any Input 5 7.5 pF
•
CIN
ZO <0 I
LOAO CAPACITANCE (eLI-pIC SUPPLY VOL.TAGE {Vool-V
INPUT FREQUENCY (111- kHz
Fig. 8 - Typical propagation delav time
Fig. 9 - Typical propagation delay time Fig. 10 - Typical dynamiC power dissipation
as a function of load capacitance.
as a function of supply voltage. as a function of input frequency.
Voo 1 N P UVeo
O S NOTE
~ MEASURE INPUTS
III ~ SEQUENTIAL.LV.
Vss TO BOTH Voo AND VSS
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS·
Vss
92CS-21""'IRI
Fig. 11 -Input current test circuit. Fig. 12 - Input-voltage test circuit.
92C5-35101
INPUTS
Dimensions and pad layout for CD4077BH. o
Dimensions and pad layout for Vss
CD4070BH are identical.
derived from the basic inch dimensions 83 indicated.
Grid graduations are in mils (10- 3 inchl.
The photographS and dimensions of Bach CMOS chip
represent a chip when it ;s part of the wafer. When the
Vss
cleavage may vary with respect to the chip faca lor
chip. therefore, may differ slightly Irom the nominal Fig. 13 - Quiescent-devlce-current Fig. 14 - Dynamic power dissipation
dimensions shown. The user should consider a tolerance test circuit. test circuit.
dimensions shown.
245
CMOS OR Gates Features:

• Medium-Speed Operation-tpLH,
High-Voltage Types (20-Volt Rating) tpHL = 60 ns (typ.) at VDD = 10 V
CD4071 B Quad 2-lnput OR Gate • 100% tested for quiescent current at 20 V •• 1
• J
• Maximum input current of 1 IJ,A at 18 V
CD4072B Dual 4-lnput OR Gate
over full package-temperature range; 100 nA at 0 •
CD4075B Triple 3-lnput OR Gate 18 V and 250 C C • • K
• Standardized, symmetrical output characteristics F •

10 L.
The RCA-CD4071 B, CD4072B, and • Noise margin (over full package tamperature E •
H 12
CD40758 OR gates provide the system ranga)
designer with direct implementation of the 1 VatVDD= 5 V " M
positive-logic OR function and supplement 2 V at VDD = 10 V

the existing family of CMOS gates. The 2.5 Vat VDD = 15 V Vss
CD4071, CD4072, and CD4075 types are • 5-V, 10-V, alld 15-V parametric ratings 92CS-27685
supplied in 14-lead dual-in-line ceramic CD4071B
packages (D and F suffixes), 14-lead dual- • Meets all requirements of JEDEC Tenta·
FUNCTIONAL DIAGRAM
In-line plastic packages (E suffix), 14-lead tive Standard No. 13 A, "Standard
ceramic flat packages (K suffix), and in chip Specifications for Description of '8' Series
form (H suffix). CMOS Devices"

MIN. I MAX.
Supply-Voltage Range (For TA = Full Package·Temperature
Range)
3
I 18 V
STATIC ELECTRICAL CHARACTERISTICS Vss

9ZCS-Z1886
LIMITS AT INDICATED TEMPERATURES (DC) CD4072B

CONDITIONS Values ai-55, +25, +125 Apply 10 D; F, K, H Packages FUNCTIONAL DIAGRAM
ISTIC UNITS
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Current, - 0,10 10 0.5 0.5 15 15 - 0.01 0.5
p.A
100 Max. - 0,15 15 1 30
1 30 0.01 1
- 0,20 20 5 5 150 ISO - 0.02 5
Output low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - F
IOlMin. 1.5 0,15 15 4.2 4 2.B 2.4 3.4 6.B - E •
5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA o •
.
Output High 4.6 0.5 I "
(Source) 10 L
2.5 0.5 5 -2 -1.B -1.3 -1.15 -1.6 -3.2, - H "
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - "
IOH Min.
13.5 0,15 15 -4.2 -4 -2.B -2.4 -3.4 -6.B -
Output Voltage: - 0,5 5 0.05 - 0 0.05 Vss
92CS-2T681
low·level, - 0 0.05
- 0.10 10 0.05 CD4075B
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
FUNCTIONAL DIAGRAM
Output Voltage: - 0.5 5 4.95 4.95 5 -

High·level. - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0.15 15 14.95 14.95 15 -
Input low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
Vil Max.
1.5,13.5 - 15 4 - - 4
V
Input High 4.5 - 5 3.5 3.5 - -
Voltage, 9 - 10 7 7 - -
VIH Min. 13.5 - 15 11 11 - -
Input Current
liN Max. O,IB lB to. 1 to.l tl tl - tl0- 5 to. I p.A
246
MAXIMUM RATINGS, Absolute~Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (VDD) 2°1 A"~ENT TEMPERATURE.' T~;;;~;~l"!ttljj t
(VoHagesre-rerenced to VSS Terminan ................................................ -0.5 to +20 v
INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -0.5 to VDD +0.5 V 1 supp, . ~O.L TAGE." . '"
For T A = -40 to +60'C (PACKAGE TYPE E) ................................................. 500 mW
For T A = +60 to +8S'C (PACKAGE TYPE E) ................... Derate Linearly at 12 mW/'C to 200 mW
For T A = -55 to +IOO'C (PACKAGE TYPES 0, F, K) .......................................... 500 mW
For T A = +100 to +12S'C (PACKAGE TYPES 0, F, K) .......•.. Derate Linearly at 12 mW/'C to 200 mW
It
For T A = FULL PACKAGE·TEMPERATURE RANGE (All Package Types) ...................... 100 mW
PACKAGE TYPES 0, F, K, H ........................................................ -55 to +12S'C , ,
INPUT ~)L.TAG£ (VIN)-V
PACKAGE TYPE E .................................................................. -40 to +8S'C
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +IS0'C Fig. 1 - Typical voltage transfer
At distance 1116 ± 1132 Inch (1.59 ± 0.79.mm) from case for 10 s max. ••....•..•••.•••.••.....• +26S'C
=25°C, Input t r , tf =20 ns,
•
DYNAMIC ELECTRICAL CHARACTERISTICS at T A
=
and CL 50 pF, RL 200 = kn
ALL TYPES
TEST CONDITIONS
LIMITS
VOO
TYP. MAX.
VOLTS
10 60 120 ns
tpHL. tpLH
15 45 90
Transition Time. 5 100 200

L.OAD CAPACITANCE {CL1-pF 92CS·2,1I1
10 50 100 ns
tTHL. tTLH Fig. 2 - Tvpical propagation delay time
15 40 80
-DO
* BY
NETWORK :a
COSI MOS PROTECTION - - -
Vss
DD
vss
92CS-29114
Fig. 3 - Schematic diagram for CD40778 (1 of 4 identical gata.l.

ORAIN-TD-SOURCE VOLTAGE (Vosl-V

characteristics.
1(6'8"3)~J 3(4,10,11)
2 (5,9,121
•
92C,-29139
,
DRAIN-TO-SDURCE VOlTAGE (Vosl-V

Fig. 5 - Logic diagram for CD40778 (1 of 4 identical gata.). characteristics.
247
Voo DRAIN-lO-SOURCE VOLTAGE ('0'05)-'0'
1 1
Vss
A - - --
DD
'* ALLINPUTS ARE PROTECTED

BY COS/Mas PROTECTION
Vss
NETWORK
characteristics.
Fig. 7 - Schematic diagram for CD40728 (1 of 2 identical gates).
2 (12)
3 (11)
1(13}
5(9)~
4 (10) 6-----{>---~
Fig. 9 - Logic diagram for CD40728 II of 2 identical gates). Fig. 10 - Minimum output high (source) current
characteristics.
8(5"3)~
2 (4,12) *0------1--;
1 (3,11) C*>----+---t-t
LOAD CAPACITANCE ICL)-pF
* BY
Vs:
COS/MOS PROTECTION
fi-- voo
.. ·,
Fig. 12 -
~"
Typical transition time as a function
AMBIENT TEftFERATURE (1,,)-25·C
NETWORK "ss
I
, II J .. v /
~ZCM'2911'5
~.'~ K "
-;eIO"a, &'fl "r:- -;C.
Fig. II - Schematic diagram for CD40758 II of 3 identical gates).
~
o
~ 10'
·, ..&:YV
.j'..j / '
z I
5 • ,/ /"
~ 2
S 102 V"
!
i 10
·, , . " 10 , , .. , ... , ...
CL·~ pF
CL-15 pF ---
102 103 10'

Fig. 13 - Logic diagram for CD40758 II of 3 identical gates). INPUT FREQUENCY (f1)- kHz
Fig. 14 - Typical dyanamic power dissipation

as a function of frequency.
248
TERMINAL ASSIGNMENTS (TOP VIEW)
INPUTS
o
Voo Vss
J"A+B+C+O I. VOO A I. Voo
J-A+B
"2 "13
12
H
G
2 "
13
12
K~E+F+G+H
• 2 "13
12
G
K-C+O M-G+H
10 L-E+F 10 F 10 L-Q+Ht-I
9 F NC
K-O+E+F J -A+B+C
VSS Vss NC
V.S c
CD4071B C040729
C040~
92CS-244'34 Ne· NO CONNECTION 92CS-2.... 9~
"00 1NPUOS
VOO NOTE'
~ ~:~~~::I~~~~~S
•
IISS TO BOTH liDO ANO Vss
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR "ss,
vss
62-70
(1.575-)·778)
Fig. 17 - Input-voltage test circuit.
DimensIOns in parentheses are in millimeters and

dicated. Grid graduatIons are in mils (10- 3 inch).
The photographs and dimensions of 8ach CMOS chip 92CS-35102

reprosent a chip when it is part of the waler, When the
chip. therefore, may differ slightly from the nominal Dimensions and pad layout for CD4071B.
dimensions shown.
Dimensions and pad layout for CD4072B. Dimensions and p.ad layout for CD4075B.
249
CD4073B, CD4081 B, CD4082B Types
Features:
CMOS AND Gates • Medium-Speed Operation - tpLH'
tpHL = 60 ns !typ.) at VDD = 10 V
CD4073B Triple 3-lnput AND ~ate • Maximum input current of lilA at 18 V over
CD4081B Quad 2-lnputAND Gate full package-temperature range; 100 nA at
CD4082B Dual4-lnput AND Gate 18 V and 250 C
range) =
The R::A-CD4073B, CD4081B and CD-
4082B AND gates,provide the system de- 1 VatVDD=5 V Vss
signer with direct implementation of the 2 VatVDD= 10 V
AND function and supplement the existing 2.5 V at VDD = 15 V
family of CMOS gates. • Standardized, symmetrical output
CD40818
The CD40738, CD40818 and CD40828 characteristics FUNCTIONAL DIAGRAM
types are supplied in 14-lead dual-in- • 5·V.l0·V, and 15·V parametric ratings
line ceramic packages (D and F suffixes), • Meets all requirements of JEDEC Tentetive
14-lead dual-in-line plastic packages (E
suffix), 14-lead ceramic flat packages (K Standard No. 13A, "Standard Specifications
suffix), and in chip form (H suffix). for Description of 'B' Series CMOS Devices"
MAXIMUM RATINGS. Absolute·Maximum Values:

DC SUPPLY.VOLTAGE,RANGE, IV DD )
(Voltages referenced to VSS Terminal) ~.5to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS. • ~.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT • . ±10mA
POWER DISSIPATION PER PACKAGE (PDI: 1 J
For T A = -40 to +60 C (PACKAGE TYPE E)
o •.••• , • .. 500mW B
For TA = +6() t9 ,+8SoGJPACKAGE TYPE Ii) " Derate Linearly at 12 mW{'C to 200 mW A
For TA = -5510 +loo°C (PACKAGE TYPES D, F, K) . . • . • . . •• 500mW
For TA = +100 10 +125°C (PACKAGE TYPES D, F, K) Derate Linearly at 12 mW/oC to 200 mW 13 K
"OPERATlNG·TEMPE_RATURE RANGE (TA):
PACKAGE TYPES D, F, K, H . • • • • • -55 to +1250 C
PACKAGE TYPE E • . . . . . • . . • • • • . . --40 to +85 0 C
STORAGE'TEMPERATURE RANGE (T stg ) . . . . . , . . -65 to +1500 C 92C5-Z7570
LEAD TEMPERATURE (DURING SOLDERING): CD40828

At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 105 ma •. FUNCTIONAL DIAGRAM

For maximum reliability, nominal operating conditions should be selacted so that
LIMITS
MIN. MAX.
Supply.Voltage Range (For T A = Full Package
3 18 V Voo
Temperature Range)
DYNAMIC ELECTRICAL CHARACTERISTICS at T A=25 0 C. Input t r .It=20 ns. .2

and CL =50 pF. RL=200 kQ
C •
ALL TYPES o '

E 4
CHARACTERISTIC UNITS F •
VDD
Volts TYP. MAX. 10
5 125 250
Propagation Delay Time.
10 60 120 ns
tpHL, tpLH
15 45 90 V5S
5 100 200
Transition Time, CD4073B
10 50 100 ns
tTHL' tTLH FUNCTIONAL DIAGRAM
15 40 80
250
CD4073B, CD4081 B, CD4082B Types
CONDITIONS Values at -55, +25, +125 Apply 10 D, F, K, H Packagel
UNITS
ISTIC +25
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Current. - 0,10 10 0.5 0.5 15 15 - 0.01 0.5
100 Max. IJA
- 0,15 15 1 1 30 30 0.01 1
- 0,20 20 5 5 150 150 - 0.02 5
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - INPUT VOLTAGE (VINI-V
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. Fig. 3 - Typical voltage transfer characteristics.
1.5 0,15 15 4.2 4 2.B 2.4 34 6.8 -
0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
Output High 4.6
•
(Source) 2.5 0,5 5 -2 -1.B -1.3 -1.15 -1.6 -3.2 -
Current, 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
9.5 0,10
IOH Min.
13.5 0.15 15 -4.2 -4 -2.B -2.4 -3.4 -6.B -
Output Voltage: - 0,5 5 0.05 - a 0.05
Lew·Level, - a 0.05
- 0,10 10 0.05
VOL Max.
- 0.15 15 0.05 - a 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level, - 0.10 10 9.95 9.95 10
VOH Min.
- 0.15 15 14.95 14.95 15 -
Input Low 0.5 - 5 1.5 - - 1.5
Voltage, - 10 3 - - 3 LOAD CAPACITANCE (eLI - pF
1
VIL Max.
1.5 - 15 4 - - 4
V Fig. 4 - Typical propagation delay time
Input High 0.5,4.5 - 5 3.5 3.5 - - as a function of load capacitance.
Voltage, 1,9 - 10 7 7 - -
VIH Min.
1.5,13.5 - 15 11 11 - -
liN Max.
O,lB lB ±0.1 ±0.1 ±1 ±1 - ±0.1 JJ.A
DRAIN-TO-SOURCE VOLTAGE (VosJ-Y

Fig. 7 - Schematic diagram for CD40878 f7 of 4 identical gatos).
I
Fig. 2 - Logic diagram for CD40878 (7 of 4 identical gates). DRAIN-lO-SOURCE VOLTAGE (V051-V

251
CD4073B,CD4081B, CD4082BTypes
VDD DRAIN-lO-SOURCE IJOLTAGE 1Vosl-V
I
.,,~
2UZlo---H
Vss
* ALL INPUTS ARE PROTECTED BY
riD
COS/MOS PROTECTION NETWORK Fig. 8- Typical output high (source)
ORAIN-TO-SOURCE VOLTAGl (Vaal-V
q vss
Fig. 7 - Schematic diagram for CD40828 (1 of 2 identical gates).

Fig. 9 - Logic diagram for CD40828 (1 of 2 identical gates).

VDD
*
B(S,m
*
1(4~.'21
2(3,13)
~~~~ Fig. 12 - Typical transition time as a

....
*ALL INPUTS ARE PROTECTED BY
Vss ,. ·
i .
;e
4
AMBIENT TEr.FERATURE (TA'- e-c
~•.t,J~
-~ "
5 ·
1;7- "Yo_ ~
10",
-
w
r ·
4
:P-L'IL
Fig. 11 - Schematic diagram for CD40738 (1 of 3 identical gates). 103: A iL"
I" · ""'I
4
VV"
lL:"
i cL-eo pF
·. ... .
4
CL-I!5 pF ---
10
4 •• , 4 •• , 4 "
10 102 10' 10 4
INPUT FREQUENCY "'11- kHz
Fig. 14 - Typical dynamic power dissi-

pation per gate as a function
Fig. 13 - Logic diagram for CD40738 (1 of 3 identical gates). of frequency.
252
CD4073B , CD4081B, CD4082B Types
INPUTS
o
Vss
56- 64
11.422-1.6261
Voe
~
o ~
INPUO
V S NOTE
DD
MEASURE IN~UTS
SEOUENTIALLY, Dimensions and pad layout 92CS-35100
1
VSS
V5S
TO BOTH Voe AND VSS'
CONNECT ALL UNUSEO
INPLIrS TO EITHER
VOO OR VSS'
for CD40818.
o 10 20 30 40 50 60
I
I
VDD
"
"2 13 Dimensions and pad layout
J:A-B 3 12
for CD40828.
K:C'O M:G-H
"
10 L= E F
0
Vss
TOP VIEW
CD4081B
J=A'B'C'O I. I. VDD
2 13 K=E·F·G·H
12 H
NC
"
10
9
Vss
TOP VIEW
• NC
NC=NO CONNECTION
92:CS-241137R2:
CD4082B Dimensions in parentheses are in

millimeters and are derived from
the basic inch dimensions as in'
dicated. Grid graduations are in
I.
mils (10-3 inch).
VDO
"
13 G
12
10 loG· H·I Dimensions and pad layout

K=O' E F 9 J=A· B-G for CD40738.
Vss C The photographs and dimensions of each CMOS chip
TOP VIEW
represent a chip when it is part of the wafer. When the chip, thorefore, may differ slightly from the nominal
ncs wafer is separated into individual chips, the angle of dimensions shown. The user should consider a tolerance
cleavage may vary with respect to the chip face for of -3 mils to +16 mils applicable to the nominal
CD4073B different chips. The actual dimensions of the isolated dimensions shown.
253
CD4076B Types
Features:
• Th ree-state outputs
• Input disabled without gating the clock
CMOS 4-Bit • Gated output control lines for
D-Type Registers enabling or disabling the outputs
High-Voltage Types (20-Volt Rating) characteristics
• Maximum input current of 1 J1A at 18 V over
The CD40768 types are four-bit registers
consisting of D·type flip-flops that feature
18 V and 25 0 C
three-state outputs. Data Disable inputs are "'$S'8
"'00'16
provided to control the entry of data into • Noise margin over full package temperature
the flip-flops. When both Data Disable in- range:
puts are low, data at the 0 inputs are loaded 1 VatVDD=5V
into their respective flip·flops on the next 2 V at VDD = 10 V FUNCTIONAL DIAGRAM
positive transition of the clock input. Out- 2.5 Vat VDD = 15 V
put Disable inputs are also provided. When • 5-V, 10-V, and 15-V parametric ratings
the Output Disable inputs are both low, the • Meets all requirements of JEDEC Tentative
normal logic states of the four outputs are Standard No. 13A, "Standard Specifications
available to the load. The outputs are disa- for Description of '8' Series CMOS Devices"
bled independently of the clock by a high
logic level at either Output Disable input,
and present a high impedance.
OUTPUT ~M I. IS VDD
The CD4076B types are supplied in 16-lead DISABLE ~N 2 15 RESET
ceramic dual-in-line packages (0 and F 01 I. DATA I
suffixes), 16-lead dual-in-line plastic pack-

ages (E suffix), 16-lead ceramic flat packages
02
03 "
12
DATA 2
DATA 3
DATA 4
(K suffix), and in chip form (H suffix).
O'
CLOCK 10 " G2(?~~~T
Vss G I DISABLE
TOP VIEW q,'CS

TERMINAL ASSIGNMENT
RECOMMENDED OPERATING CONDITIONS at T A = 25 0 C, Except as Noted.

CHARACTERISTIC VDD LIMITS UNITS

(VI Min. Max.
Supply·Voltage Range (For T A=FuJl Package·

5 200 -
DRAIN-lO-SOURCE VOL.TAGE
15 60 .-
Fig.2 - Minimum output low (sink)

5 200 -
Clock Pulse Width, tw 10 100 .- ns
DRAIN-lO-SOURCE VOLTAGE 1V051-V
15 80 - -IS -10 -5
AMBIENT TEMPE~ATURE (TA1'25-C
5 3
GATE-TO-SOURC£ VOLTAGE {VGSJo-5V
Clock Input Frequency, fCL 10 dc 6 MHz
15 8
5 - 15
Clock I nput Rise or Fall Time, trCL,tfCl 10 - 5 J1S
-IOV
15 - 5
5 120 -
Reset Pulse Width, tw 10 50 ns -15V
15 40 -
5 180 -
Data Input Disable Setup Time, ts 10 100 - ns
15 70 -
Fig.3 - Typical output high (source)
254
CD4076B Types
MAXIMUM RATINGS, Absolute-Maximum Values: DRAIN-lO-SOURCE VOLTAGE IVOSI-V
DC SUPPLY-VOLTAGE RANGE, (V DO) ."
(lJOlfages referenced 10 VSS-iermimil) "",........................................... -0.510 +20 V lAM."."'. '.'.~'.H.~'U.H.'. ....•.•.-
INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -0.510 VDD +0.5 V
For T A =-40 10 +60·C (PACKAGE TYPE E) ................................................. 500 mW
For T A =+60 10 +8S·C (PACKAGE TYPE E) ••••.••..•....•..•• Derale Linearly al12 mW/·C to 200 mW
For T A = -SSlo +l00·C (PACKAGE TYPES 0, F, K) .......................................... SOO mW
For T A = +100 to +12S·C (PACKAGE TYPES 0, F, K) .••.•••••• Derate Linearly at 12 mW/·C 10 200 mW
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW
PACKAGE TYPES 0, F, K, H ........................................................ -5510 +12S·C
PACKAGE TYPE E .................................................................. -4010 +8S·C
.!
STORAGE TEMPERATURE RANGE (T51g) ............................................. -6510 +lS0·C
LEAD TEMPERATURE (DURING SOLDERING): Fig.4 - Minimum output high (source)
At distance 1/16 ± 1/32 inch (1.S9 ± 0.79 mm) from case for 10 s max. • •••••••••••••.....•..••• +26S·C current characteri'tic,.
INPUT
DISABLE _ _
IS
-1____i-__.IJ
1~1Il1!!1~'JI!l11 •
t= :1': iiii" :.' ; =l[l!! v'::l
RESET
t~ldjltj:; : : i" :~: 'j:; :i11:i:i ;;;: i;:! ::wm::::::
o 20 40 60 80 100 120 140
LOAD CAPACITANCE (Cll- pF
92C5-27115
Q
OUTPUT Fig.6 -' Typic.1 propagation delay tim.
vs. load capacitance (clock to 0).
OUTPUT DISABLE
9<C ... ·HBBBRl
VDD
(a)
Q OUTPUT VOL
Q OUTPUT M I
VOH
OUTPUT {
DISABLE
N 2
TEST. VOLT.
CHAR.
AT 0 AT Q
'PHZ VDD ·Vss
t PLZ Vss VDD 12CS-2I2"
t pza, Vss VDD
VDD Vss (b)
• PZH
Fig.5 - Functional waveforms for CD4076B.
Truth Table
Ollollnput
Oilable Dill
.....
NI.I
Output
Reset tJ",k Gl G2 0 a
1 x X x x 0
0 0 x x x a NC
0 ....r- 1 x X 0 NC
0 ....r
....r-
x 1 X 0 NC
0 0 0 1 1 *
0 ....r- 0 0 0 0
RESET I'rl>------.l~-....:r
~VDO
0 1 X X X a NC *ALL INPUTS PROTECTED BY
COSINOS PROTECTION NETWORK

0
'- x x x a
When lithe, Oulpul Dluble M or N IS high, the outpuU Ife
NC
~VSS
dlsa~red (high Impedance stalel. however leQuenllill operation
of the fllp·flops IS nol affected. '2e5-241'111:2
Fig.7 - Typical transition time VI.
1;;; High level x • Don', ea.,.
load capacitance. 0= Low Level Ne· No Change Fig.S - CD40768 logic diagram.
255
CD4076B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input tr,tf = 20 ns,
Cl = 50 pF, Rl = 200 kSl (Unless otherwise noted)

VOO
V Min. Typ. Max.
Propagation Delay Til11e: 5 300 600
Clock to 0 Output. tpHl. tplH 10 125 250
15 90 180
5 230 460
Reset, tpHl 10 100 200
15 75 150
ns
5 150 300
3·State Output 1 or 0 to High
Rl =1 Hl 10 75 150
Impedance, tpHZ, tplZ
15 60 120
5 150 300
3·State High Impedance to 1 10 75 150
Rl=lkSl
or 0 Output, tpZH' tPZl 15 60 120
5 100 200
Transition Time, tTHl· tTlH 10 50 100 ns
15 40 80
5 3 6
Maximum Clock Inllut F,equency. fCl 10 6 12 .. MHz
.. 15 8 16
5 100 200
Minimum Clock Pulse Width, tw 10 50 100 ns
15 40 80
Maximum Clock Input Rise 5 15 - -

or Fall Time, 10 5 - - IJs
trel, tiel 15 5 - -
5 .. 60 120
Minimum Reset Pulse With, tw 10 25 50 ns
15 -- 20 40
5 100 200
Minimum Data Setup Time, ts 10 - 40 80 ns
15 30 60
Minimum Data Input Disable 5 - 90 180
Setup Time, ts 10 - 50 100 ns
15 - 35 70
Input Capacitance, CIN AllY Input - - 5 7.5 pF
INPUTS . - - - - ' - - ,
V~NPU(JS
Voo :~:~URE 'NPUTS
o
Vss
'NPUTOVCOOUTPUTS
V'H
'- ~
V~L 1 o~
Vss
SEQUENTIALLY,
TO BOTH Voo AND IIss'
CONNECT ALL UNUSED
NOTE: INPUTS TO EITHER
~srN",,~~~OM'INATICIN Yoo CIt vss'
Vss
vss
9lCS-27441RI
VSS
Fig. 1 1 - Quiescent device current test circuit. Fig. 12 - Input voltage test circuit. Fig. 13 - Input current test circuit.
256
CD40768 Types
STATIC ELECTRICAL CHARACTERISTICS. AMBIENT TEMPERATURE TA )-25-C
LOAD CAPACITANCE CCLI-50pF

ISTtC UNITS
Vo VIN VOO +25
~~I
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max. u~:
Quiescent Device - D,S 5 5 5 150 150 - 0.04 5

2-'
:>1 •
2'
Current, - 0,10 10 10 10 300 300 - 0.04 10
I1A
~i
100 Max.
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100 5 10 I' 20
SUPPLY VOLTAGE IVOO)-V
Output low 0.4 0,5 5 0.64 0.61 0.42 .0.36 0.51 1 - 9lCS-Z71IJRI
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOlMin.
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 - Fig.9 - Typical maximum clock input'
- rnA frequency VS. supply voltage.
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current,
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low·level, - 0,10 0.05 - a 0.05
10
VOL Max.
- 0,15 15 0.05 - a 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·level. - 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 15 -
Input low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
Vil Max.
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - - 92C5·27114
Input Current .. 0,18 18 iO.l ±0.1 ±1 ±1 - ±10- 5 iO.l I1A
liN Max. Fig. 10 - Typical dynamic power dissipation
VI, frequency.
3·State Output
Leakage Current 0,18 0,18 18 ±0.4 ±0.4 ±12 ±12 - il0-4 ±0.4 I1A
lOUT Max.
Dimensions and pad layout for CD4076BH

Grid graduations are in mils /10- 3 inch}.

waler is separated into individual chips. the angle of
dilferent chips. The actual dimenSIons 01 the isolated
dimensions shown.
257
CD40788 Types
Features:
• Medium-Speed Operation:
=
tpHL. tpLH 75 ns (typ.) at VDD 10 V =
CMOS a-Input • Buffered inputs and output
• 5-V. 10-V. and 15-V parametric ratings
NOR/OR Gate • Standardized symmetrical output characteristics
High-Voltage Types (20-Volt Rating) • Maximum input current of 1 p.A at 18 V
over full package-temperature range:
The RCA-CD4078B NOR/OR Gate provides 100 nA at 18 V and 25 0 C
the system designer with direct implementa- • Noise margin (over full package-temperature
VOO;14
tion of the positive·logic 8-input NOR and range): 1 Vat VDD = 5 V
Vss; 7
OR functions and supplements the existing 2 V at VDD = 10 V 2.5 V at VDD = 15 V
family of CMOS gates.
• Meets all requirements of JEOEC Tentative 'l2'CS-23S71R4
The CD407BB types are supplied in 14-lead Standard No. 13A. "Standard Specifications
dual-in-line ceramic packages (D and F suf- for Description of 'B' Series CMOS Devices"
fixes). 14-lead dual-in-line plastic packages FUNCTIONAL DIAGRAM
(E suffix). 14-lead ceramic flat packages (K
suffix). and in chip form (H suffix).

DC SUPPLY-VOLTAGE RANGE. (V DD )
(Voltages referenced to VSS Terminal) -0_5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS -0.5 to VDD +0.5 V
For T A = -40 to +60 oC (PACKAGE TYPE E) . . . . . . . .. 500mW
For T A = +60 to +850C (P""CKAGE TYPE E) Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +loo°C (PACKAGE TYPES D. F. K) . . . . . . . .. 500mW
For T A = +100 10 +125°C (PACKAGE TYPES D. F. K) Derate Linearly at 12 mW/oC to 200 mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) l00mW
DRAIN-TO-SDURCE VOLTAGE (Vos)-I/
PACKAGE TYPES D. F. K. H -55 to +1250C
PACKAGE TYPE E . -40 to+850C Fig. 2 - Typical output low (sink) current
STORAGE TEMPERATURE RANGE (Tstg ) -65 to +1500C characteristics.
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm) from case for lOs max.
RECOMMENDED
OPERATING CONDITIONS ••
conditions should be selected so that operation C 4
CHARACTERISTIC Min. Max_ Units

(For TA Full Package
Fig. 1 - Logic diagram. CRAIN-TO-SOURCE VOLTAGE (VDsl-V

At TA = 2fJC; Input t,. tf= 20ns. CL = 50pF. R L = 200kl2 DRAIN-TO-SOURCE VOLTAGE IVDS)-V
ALL TYPES
TEST CONDITIONS
LIMITS
V OD
TYP. MAX.
VOLTS
--
Propagation Delay Ti me. 5 150 300
tpHL, tPLH 10 75 150 ns
15 55 110
5 100 200
tTHL.ITLH 15 40 80
Input Capacitance. C I N Any Input 5 7.5 pF Fig. 4 _ Typical output high (source) current
characteristics.
258
CD4078B Types
DRAIN-TO-SOURCE VOLTAGE 1\105)-\1
LIMITS AT INDICATED TEMPERATURES 10C)

CHARACTER· Value. at -40, +25, +85 ApplV to E Package
ISTIC UNITS
Vo VIN VDD
+25
IV) IV) IV) -55 -40 +85 +125 Min, TVp. Max.

Current,
IDO Max.
- 0,10 10 0.5 0.5 15 15 - 0.01 0.5
J1A
- 0,15 15 1 1 30 30 - 0.01 1
- 0,20 20 5 5 150 150 - 0.02 5
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1
ISink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6
IOL Min. Fig. 5 - Minimum output high (source)
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8
rnA current characteristics.
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -I
ISource) -2 -1.8 -1.3 -1.15 -1.6 -3.2
•
2.5 0,5 5
Current,
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.ti
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8
Output Voltage: - 0,5 5 0.05 0 0.05
Lew-Level,
VOL Max.
- 0,10 10 0.05 0 0.05
- 0,15 15 0.05 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5
High·Level.
VOH Min.
- 0,10 10 9.95 9.95 10
- 0,15 15 14.95 14.95 15
Input Low 0.5.4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
VIL Max.
1.5,13.5 - 15 4 - - 4
V
Input High 0.5.4.5 - 5 3.5 3.5 - - Fig. 6 - Typical transition time as a
ncs .... 'n
Voltage, 1,9 - 10 7 7 - - function of load capacitance.
VIH Min.
1.5,13.5 - 15 11 11 - -
I nput Current
liN Max.
0,18 18 ±0.1 :to. 1 ±1 .:!:1 - :10- 5 ::D.l J1A
VDO
DETAIL OF INVERTERS
VDO

RVOO
Vss '0 . 20 ,.
Vss
Fig. 8 - Schematic diagram.

qvss * COSIMOS
NETWOft\(
PROTECTION
92CL-29098
INPUT VOL.TAGE (VI) - V
Fig. 9 - Typical voltage transfer charac-

teristics (NOR output).
259
CD4078B Types
IO~:
., ~."NT TE"PE."U~ 'llfl t~~ /
~ ,04 11
10
?~
6
"
. ..PV" ~p m~~
'?,-
V'
~9
t;i~IOS8
<1
.6 ]L/
Vss
o
INPUTS , - - ' - -
~
v./ V/v
90... 6
~5
Ow
" Veo 1NPUOS
Voo NOTE
:58
~ ~:::~:i,~~~~S
<1
//
~
•
102
., V"V
I 1=--:
i Cl "5QpF- Vss TO BOTH IIDD AND IISS'
, ... , ... , i 6~'~F~~i8

CONNECT ALL UNUSED
INPl/TS TO EITHER
'0 IIDD OR Vss'
10 J02 10' vSS
INPUT FRECUENC,," "11- kHt

as a function of frequency. Fig. 11 - Ouiescent·device-current test circuit. Fig. 12 - Input current test circuit.
Voo
AK
•
,.
2
,.
13
VDO
J.
'NPUTOVOO
OUTPUTS '2 H
V'H t
D " •
'-- ~
'0
Nt
Y~L :::t CLOCK Vss
9
Nt
TOP VIEW
NOTE:: • J-A+B+C+DtEtFiOtH
IISS ~N~~~~OMBINATiON .. K-A+B+C+D+E+F+G+H
NC- NO CONNECTION
92CS-0!1441AI 92CS-24!>93RZ
Fig. 13 -Input-voltage test circuit. Fig. 14 - Dynamic power dissipation test circuit. TERMINAL ASSIGNMENT

The photographs and dimensions of each eMuS chip
Dimensions in parentheses are in millimeters and are represent a chip when it Is part of the wafer. When the
wafer ;s separated into individual chips, the angle of
derived from the basic inch dimensions as indicated. cleavage may vary with respect to the chip 'ace for
Grid graduations are in mils (10- 3 inch). different chips. The actual dimensions of the isolated
chip, therefor., may differ slightly from the nominal
dimensions shown.
260
CD4085B Types
CMOS Dual 2-Wide

'NH'B':',~,O
2-lnput ANO-OR-INVERT Gate HI 2
CI 12
3 EI
01 13

INHIBI:~~~
82 6 4 E2
The RCA-CD4085 contains a pair of AND- Features: C2 •
OR-INVERT gates, each consisting of two 02 •
2-input AND gates driving a 3-input NOR • Medium-speed operation - tpH L = 90 ns; E·INHIHIT+AB+CD
gate. Individual inhibit controls are provided tpLH = 125 ns (typ.) at 10 V LOGIC I'HIGH
LOGIC 0 1 LOW
for both A-O-I gates. • Individual inhibit controls
92GS-231190R2
The CD4085B types are supplied in 14-lead • Standardized symmetrical output characteristics
dual-in-line ceramic packages (D and F • 100% tested for quiescent current at 20 V
FUNCTIONAL DIAGRAM
suffixes), 14-lead dual-in-line plastic pack- • Maximum input current of 1 p.A at 18 V over full package-
ages (E suffix), 14-lead ceramic flat packages temperature range; 100 nA at 18 V and 25°C
•
(K suffix), and in chip form (H suffix). • Noise margin (over full package-
temperature range):
1 Vat VDO= 5 V
2 V at VOO = 10 V "
2.5 Vat VOD = 15 V I
.5-V, 10-V, and 15-V parametric ratings ! 10
~g
I
.
INPUT VOLTAGEtV:II-V
"
DC INPUT CURRENT, ANY ONE INPUT ±10mA Fig. 1 - Typical voltage and current
POWER DISSIPATION PER PACKAGE (PD): transfer characteristics.
For TA = -40 to +60 0 C (PACKAGE TYPE E) . . . . . . • .. 500mW
For TA = +60 to +85 0 C (PACKAGE TYPE E) Derate Linearly at 12 mW/oC to 200 mW
. For T A = -55 to +100'C (PACKAGE TYPES D, F, K) . . . . . . . .. 500mW
For T A = +100 to +125'C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR > - - .AX
- __ MIN
FOR TA = FULL PACKAGE· TEMPERATURE RANGE (All Package Types) 100mW 112.!1
OPERATING·TEMPERATURE RANGE (T A): ~
PACKAGE TYPES D, F, K, H -55 to +125 0 C
PACKAGE TYPE E . -40 to +85"oC :>~ IOI+rnt:mmml-1
STORAGE TEMPERATURE RANGE (Tstg ) -65 to +1500 C 7.'I+I-I+FHfmtHHfHfl-l-lfl
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 5 max.
,·'mtttlftffitJijffijillitfurfffmTmTrrnm
operatIon is always within the following ranges:
Fig. 2 - Min. and max. voltage transfer
CHARACTERISTIC LIMITS UNITS characteristics.
Min. Max.
10 AMBIENT TEMPERATURE ITA ,. Z!I·C F
Supply·Voltage Range (For TA=Full Package·
V
Temperature Range) 3 18 10'
AI I. I. YoD
BI
EI- ~NHI+AIBI+CIDI
• 13
I.
DI
CI C el!lpF_
E2-INH2+A282+C2D2
A'
• "S 10
INHIBIT 2
INHIBIT I
B.
V5S
• D.
C2 10
TOPYI W
10° 10 1 10 1 10' 10'
92CS-Z38".' FREQUENCY It 1- IIH.
Terminal Assignment
Fig. 3 - Typical power dissipation vs. frequency.
261
CD4085B Types

Values al-55, +25, +125 Apply 10 D, F, K, H Pkgs.
CHARAC·
TERISTIC
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
jlA
Current - 0,15 15 4 4 120 120 - 0.02 4
100 Max. - 0,20 20 20 20 600 600 - 0.04 20
Output Low
(Sink) 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Current, 0.5 0,10 11) 1.6 1.5 1.1 0.9 1.3 2.6 -
1m Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 - mA
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 0.36 -0.51 -1
~
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Volt·
age: - 0,5 5 0.05 - 0 0.05
Low·Level, - 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output Volt·
age: - 0,5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 -
VIH Min. 1.5,13.5 - 15 11 11 - -
Input
Current, - 0,18 18 ±0.1 ±0.1 ±1 I ±1 - ±10-5 ±0.1 IJA
liN Max.
t.!! 7.e 10 12.15 15 11.5 20

SUPPLY VOLTAGE tVOOI-V
LOAD CAPACITANCE. 'ct.1-pF LOAD CAPACITANCE 1C1,.1-,F
Fig. 4 - Typical data high·to·low level propagation Fig. 5 - Typical data low-to·high level propagation Fig. 6 - Typical data propagation delay time vs.
delay time vs. load capacitance. delay time vs. load capacitance. supply voltage.
262
CD4085B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C; Input t r • it = 20 ns.
CL =·50 pF. RL = 200 Kr!
GATE-lO-SOURCE VOLTAGE (VG5,-15 V
CONDITIONS LIMITS ~
z
CHARACTERISTIC ~ 25
VD D UNITS
V Typ. Max. ~ 20
5 225 450 10V
Propagation Delay Time (Data):

High·to·Low Level, 10 90 180 ns
tpHL
15 65 130
5 310 620
10 15
Low·to·High Level, tpLH 10 125 250 ns DRAIN-lO-SOURCE VOLTAGE {Vos)-V
15 90 180 Fig. 7 - Typical output low (sink)

5 150 current characteristics.
300
Propagation Delay Time (Inhibit):
High·to·Low Level,
10 60 120 ns AMBIENT TEMPERATURE (TA)oZS"C
tpHL
15
I
40 80
5 250 500 ~ 15
~ GATE TO-SOURCE VOLTAGE (V65'-15V
Low·to·High Level, tpLH 10 100 200 ns ~ 12.5
15 70 140 a 10
5 100 200 10V
Transition Time,
tTHL' tTLH 10 50 100 ns
15 40 80
5 10 15
DRAIN-lO-SOURCE VOLTAGE ('105)-'1

DRAIN-lO-SOURCE VOLTAGE (Vos)-V ORAIN-TO-SOURCE VOLTAGE (Vosl-V
H+H+H+""!",=
GATE-la-SOURCE
-15
AMBIENT TEMPERATURE (TA)-Z5°C
-10
VOLTAGE {VGS)'-5V
-5
-5
.r -15
AMBIENT TEMPERATURE (TA)·25·C
ttttHtttHttttttH
-10
GATE-TO-SOURCE VOLTtiE (V.GSI' -5 V

, fljl ±! .
',H,
t
l
-10 ~ ~ , " i
-15 ~
.- ..
..
~ -IOV
-20~ ,
, ,.++.
't" ..... ;: ~ t!
,
r.-·-· I .,+ ,
+~. ~
-15V
;
: t"'-15 V .. 7
-15:1::
:-r n;[fff
d
HHH! jj' Ill, o
o
Fig.9 - Typical transition time vs. load Fig. 10 - Typical output high (source) Fig. 11 - Minimum output high (source)
capacitance. current characteristics. current characteristics.
INPUTS
o
vss
92CS-21441RI
Fig. 12 - Quiescent device current test circuit. Fig. 13 - Input voltage test circuit. Fig. 14 - Input current test circuit.
263
CD4085B Types
INHIBIT I
~~--------------------,
Voo
AI Qlr---------i-
81 2 ...
CI Q'!I--.....---j!""'
oIQI~-------'''''''
TERM 14· Voo "'DO
" , , - , , - - - - - - - - , T E R . "Vss ~
&.-
INHIBIT 2
* ALL INPUTS PROTECTED 8'1'
STANDARD COS/MOS PROTECTION
NETW(lFItI: 55
Fig. 15 - CD4085 schematic diagram.


represent B chip when it is part of the wafer. When the
wafer is sepsrated into individual chips, the angle of
cleavage may v8ry with respect to lI"Ie Chip face for
different chips. The Bcrual dimensions of the isolated
chip, therefore, may differ slightly 'rom the nominal
dimensions shown. The user should considers tolsrance
of -3 mils to +16 mils applicable to the nom;naf
d;mensions shown.
92CS-32204
Dimensions and Pad LByout for CD4085BH.
264
CD4086B Types
CMOS Expandable 4-Wide
2-lnput ANO-OR-INVERT Gate
The RCA·CD4086B contains one 4·wide Features:

2-input AND.QR·INVERT gate with an • Medium-speed operation - tpHL = 90 ns; LOG.C IS HIGH
LOGLC 0_ LOW
INHIBIT/EXP input and an ENABLEI tPLH = 140 ns (typ.) at 10 V VOO',4
EXP input. For a 4-wide A.Q-I function • INHIBIT and ENABLE inputs VSS·7
NC·4
INHIBIT/EXP is tied to VSS and ENABLE/ • Buffered outputs
• 100% tested for quiescent current at 20 V J -'NH + ENABLE + A8+CDt EF" GH
EXP to VDD' See Fig.l0 and its associated
• Maximum input leakage current of 18 V
ellplanation for applications where a cap· over full package-temperature range;
ability greater than 4-wide is required. FUNCTIONAL DIAGRAM
100 nA at 18 V and 250 C
• Noise margin (over full package
The CD4086B is supplied in 14-lead dual-in-
termperature range I:
II
line ceramic packages (0 and F suffixes).
1 VatVDD=5 V A I· I. VDD
14-lead dual-in-line plastic packages (E suf- 2 V at VDD = 10 V D
B 13
fix). 14-lead ceramic flat packages (K suffix). 2.5 VatVDD= 15V JaINH+ENABLE+ 12
AB+CD+EF+GH
and in chip form (H suffix), • Standardized, symmetrical output
characteristics
NC
E
•
5 "
10
ENABLE/EXP
INHIBIT/EXP
• 5-V, 10-V, and 15-V parametric ratings 6 9 H
VSS G
Standard No. 13A, "Standard Specifications '!J2CS-2:1B6'9AI
for Description of'S' Series CMOS Devices" Top View
TERMINAL ASSIGNMENT
MAXIMU,M RATINGS, Absolute-Maximum Values: AMBIENT TEMPERATURE ITAI*ZS-C

" SUPPLY VOLTAGE •
'm'
(Voltages referenced to VSS Terminal) , -41.5 to +20 V 1VOOI*IS v
I 1
INPUT VOLTAGE RANGE, ALL INPUTS
DC INPUT CURRENT, ANY ONE INPUT
-41.5 to VDD +0.5 V
±lOmA ~
~
m:t CIfa'l'l\HT
IO~.tJ:i
. ~
!:!
For TA • -40 to +60o C (PACKAGE TYPE E)

For T A -+60 to +850 C (PACKAGE TYPE E) •
.••.•••• , 500mW
Derate Linearly at 12 mW,aC to 200 mW
~
"'='
o •
I.
ForTA =-5510 +1OO·C (PACKAGE TYPES D. F. K)
For TA = +100 to +125·C (PACKAGE TYPES D. F. K)
•••••••• , 500mW
Derate Linearly at 12 mW/oC to 200 mW ~ 0
ov
- VDO
1 '1 ~D Z
!
DEVICE DISSIPATION PER OUtpUT TRANSISTOR I
FOR TA = FULL PACKAGE-TEMPER<!\TURE RANGE (All Package Types) l00mW
PA9KAGfO TIPES 1;l •• F••K. H '. • • • •• -55 to +1250C
0
• "'
INPUT VOLTAGE 1VXI-V "
PACKAGE TYPE E • • • • • • • • • • . • • • • -40 to +85 0 C
STORAGE TEMPERATURE RANGE (Tstg ) • • • • • -65 to +1 saoc Fig. 1 - Typical voltage and current transfer
LEAD TEMPERATURE (DURING SOLDERING): characteristlCl.
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10. max.
AMBIENT TEMPERATURE ITAI*ZS-C
"
LIMITS
MIN. MAX.
10 IS
Supply-Voltage Range (ForTA = Full Package-

Temperature Range)
3 18 V
INPUT VOLTAGE 1V:rI-V
...........
Fig. 2 - Minimum and maximum voltage tran,fer
characteri,tICl.
265
CD4086B Types

Values at -55, +25, +125 Apply 10 D, F, K, H Pkgs.
CHAAAC·
CONDITIONS Values at -40,+25,+85 Apply to E Plcgs. UNITS
TERISTIC
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
p.A
Current - 0,15 15 4 4 120 120 - 0.02 4
100 Max. - 0,20 20 20 20 600 600 - 0.04 20 1 1
DRAIN-lO-SOURCE VOLTAGE tVosl-V
Output Low
(Sink) 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - 7:1g. 3 - Typical output low 'sink!
Current, 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - curren t characteristics.
IOl Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.B - mA
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 . --=-...
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Volt·
age: - 0,5 5 0.05 - 0 0.05
Low-Level, - 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output Volt-
age: - 0,5 5 4.95 4.95 5 -
High- Level, - 0,10 10 9.95 9.95 10 - DRAIN-TO-SOURCE VOLTAGE
VOH Min. - 0,15 15 14.95 14.95 15 - Fig. 4 - Minimum output low (sink!
Input Low 0.5,4.5 - 5 1.5 - - 1.5 current characteristics.
Voltage, 1,9 - 10 3 - - 3
DRAIN-lO-SOURCE VOL.TAGE (\Iosl-V
VIL Max. 1.5,13.5 - 15 4 - - 4 1
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7
VIH Min. 1.5,13.5 - 15 11 11 - -
Input
Current, - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 p.A
liN Max.
92CS-Z4520R5
Fig_5 - Typicaloutputhigh (sourcei

DRAIN-lO-SOURCE VOL.TAGE tVosl-V

-15 -10 -,
AMBIENT TEMPERATURE {TAJ.25·C
10 AMBIENT TEMPERATURE tTA I. 25"( ~
GATE-TO-SOURCE VOLTAGE IVGS'- -, V
-IOV
'1::. ,"
:-15V
m .r
.
"
10
100 10' 10 2
FREQUENCV If 1- kHr
10' 10' imf! Ill! m "
o
LOAD CAPACITANCE ICL.I-pF

nC5· ~411'Al
Flg.8 - Minimum output-high (source)'

Fig.6 - Typical transition time vs:'oad capacitance.
C F;g.7 -' Typical power dissipation VI. frequency. current characteristics.
266
CD4086B Types
Voo
,
LOAD CAPACITANCE tell-pF
Fig. 11- Typical DATA or ENABLE high-to-low

COl:!}"+f4-----1i-' level propagation delay time VI. load
capacitance.
*
•
013
Vss
,
LOAD CAPACITANCE ICLi-pF
Fig. 12 - Typical DATA or ENABLE low-to-high

ENABLE/EXPQ.i)1.:.*-'V,,"'-_ _ _ _ _ _ _---'
level propagation delay time VI. load
INHIBIT/EXP(!Ig}*"'-----------_ _ _ _ _- - '
capacitance.
Vss
~2CM-23812RI
Fig. 9 - CD40868 schematic diagram.
ANalENT TEMPERATURE ITAI-Z5·C
..,, INHIBIT/EXP2 , - - - - - - - - - - ,
r
~.
!
_ 12!10
L.OAD CAPACITANCE tCLl " !lO pF
'000
01
IPlH
01 700
J2
"
F/
~
~
'00 tPHl
GI
HI
G2
HZ
I "0
2.' 7.' 10
Vo
ENAI:5LE/EXP,
'" "
SUPPLY VOLTAGE 1'0'001-'0'
J2~AIBltCI DHEI FltGI HltA2 82+C2D2+-E2 F2+G2 H2

Fig. 13- Typical DATA or ENABLE propagation
92cs-nS11 delay time VI. supply voltage.
Fig. 10 - Two CD4086B's connected a. an B·wide 2-input A-a-I gate.
Fig. 10 above shows two CD4086's utilized NAND gate output can be fed directly into
to obtain an 8-wide 2-input A-O-I function. the ENABLE/EXP input to obtain a 5-wide
The output (J1) of one CD4086 is fed di- A-O-I function. In addition, any AND gate
rectly to the ENABLE/EXP2 line of the output can be fed directly into the IN-
second CD4086. In a similar fashion, any HI BIT/EXP input with the same result.
267
CD4086B Types
DYNAMIC ELECTRICAL CHARACTERISTICS TEST CI RCUITS
At TA = 25'C; Input tr , tf= 20ns, CL = 50pF, RL = 200 kO
CONDITIONS LIMITS
V DD INPUTS r--L--,
TYP. MAX. o
(V) Vss
Propagation Delay Time 5 225 450

(Data): 10 90 180 ns
High·to·Low Level, tpHL 15 60 120
5 310 620
Low·to·High Level, tpLH 10 125 250 ns
15 90 180
Fig. 14 - Quiescent device current.
Propagation Delay Time 5 150 300
(Inhibit): High·to·Low 10 60 120 ns
Level, tpHL(lNH) 15 40 80
5 250 500
Low·to·High Level,
tpLH(lNH)
10 100 200 ns INPUTOVDOOUTPUTS
15 70 140 V,"
~
Transition Time,
10
5 100
50
200
100 ns
"'".....
V~l :r
tTHL' tTLH 40 80
NOTE:
15 'YSS
TEST ANY ONE INPUT,
WITH OTHER INPUTS AT
Voo DR YSS'
Input Capacitance CIN Any Input 5 7.5 pF
Fig. 15 - Input voltage.
V~NPU(J'
o~
'. :::~..~
SEQUENTIALLY,
Vss TO BOTH Voo AND YSS'
CONNECT ALL UNUSED
INPUTS TO EITHER
Yoo OR VSS'
56
1.422) Vss
Fig. 16 - Input leakage current.
92.CS-322.1l
Dimensions in parentheses are in millimeters and are The photographs and dimensions of each CMOS chip
derived from the basic inch dimensions as indicated. represent 8 chip when it is par, of the wafer. When the
wafer is separated into individual chips, the angle 01
Grid graduBtions are in mils (10- 3 inch). clsavage may vary with ,espect to the chip face for
different chips. The actual dimensions o( the isolated
chip, therefore. may differ sf{ghf/y from the nomina'
dimensions shown, The user should consider 8 tolerance
of -3 mils to +16 mils applicable to thfl nominal
dimensions shown.
Dimensions and Pad Layout for the CD4086BH
268
CD4089B Types
Features:
CMOS
• Cascadable in multiples of 4-bits BINARY RATE
Binary Rate Multiplier • Set to "15" input and "15" detect output
.100% tested for quiescent current at 20 V
The RCA-CD4089B is a low-power 4-bit digital • Maximum input current of 1 p.A at 18 V over
rate multiplier that provides an output pulse full package-temperature range; 100 nA at
rate that is the clock-input-pulse rate multi- 18 V and 25°C
plied by 1/16 times the binary input. For ". Noise margin (fui'l package-temperature
example, when the binary input number is range) =
liDO" 16
13, there will be 13 output pulses for every 1 Vat VOD = 5 V vss·a
16 input pulses. This device may be used in 2 V at VOD = 10 V 92CS-25004RI
conjunction wilh an upl down counter and 2.5 Vat VOO = 15 V
control logic used 10 perform arithmelic FUNCTIONAL DIAGRAM
operations (adds, subtract, divide, raise to a • Meets all requirements of JEOEC
•
power), solve algebraic and differential equa- Tentative Standard No. 13A, "Standard
AMBIENT TEMPERATURE ITAI'25·~rtHn:Hr
tions, generate natural logarithms and trigo- Specifications for Description of 'B'
metric functions, AID and DIA conversions, Series CMOS Oevices"
and frequency division.
GATE-TO-SOURCE VOLTAGE (VGS,"15 V
For words of more than 4 bits, CD4089B Applications:
devices may be cascaded in two different
• Numerical control
modes: an Add mode and a Multiply mode
• Instrumentation
(see Figs.14 and 151. In the Add mode some of ,ov
the gaps lett by the more significant unit at • Oigital filtering
the count of 15 are filled in by the less • Frequency synthesis
significant units. For example, when two
units are cascaded in the Add mode and
programmed to 11 and 13, respectively, the The CD4089B has an internal synchronous 10 15
OR.6,IN-TO-SQURCE VOLTAGE IVpSI-V
more significant unit will have 11 output 4-bit counter which, together with one of the
pulses for every 16 input pulses and the
Fig_ 1 - Typical output low (sink) current
four binary input bits, produces pulse trains characteristics.
other unit will have 13 output pulses for every' as shown in Fig. 2.
;,-111111
256 input pulses for a total of AMBIE.T TEM",RATURE, )-25"C
11 13 189 If more than one binary input bit is high, the
-+- =--
resulting pulse train is a combination of the
16 256 256
separate pulse trains as shown in Fig. 2.
r:,o:m~ffuifli-f.~IT~i:i-l:!f.tttl-ttmtm
In the Multiply mode the fraction pro-
grammed into the first rate multiplier is The CD4089B types are supplied in IS-lead
multiplied by the fraction programmed into ceramic dual-in-line packages (D and F suf-
the second multiplier. Thus the output rate
will be 11 13 143
fixes), IS-lead dual-in-line plastic packages
~"
~
(E suffix), 16-lead ceramic flat packages (K
x
16 16 256 suffix), and in chip form (H suffix).
,
DRAIN-TO-SOURCE VOL.TAGE lVOsl-V
Fig. 2 - Minimum output low (sink) currenr

characteristics.
MAXIMUM RATINGS, Absolute-Maximum Values: DRAIN-TO-SOURCE: VOL.TAGE (Vosl-V
DC SUPPLY-VOLTAGE RANGE, (VDDI -15 -10 -5
. -0.5 to +20 V AMBIENT TEMPERATURE (TAI-2S·C
(Voltages refer~need to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to V DO +0.5 V GATE-TO-SOURCE VOL.TAGE IVGSI--SV

POWER DISSIPATION P.ER PACKAGE (POl: -'0
For T A = -40 to +60. C (PACKAGE TYPE EI . . . . . . . .. 500mW
For:r A = +60 to +85 C (PACKAGE TYPE EI Derate Linearly at 12 mW/oC to 200 mW -"
ForTA = -55 to +100'C (PACKAGE TYPES 0, F, K) . . . . . . . .. 500mW -IOV -20
ForTA = +100 to +125'C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mWi"C to 200 mW

-25
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Type,l 100mW
OPERATING-TEMPERATURE RANGE (TAl:
-15V
-'"
PACKAGE TYPES 0, F, K, H . -55 to +1250 C
PACKAGE TYPE E -40 to +85°C
STORAGE TEMPERATURE RANGE (T SI I . . -65 to +150oC
LEAD TEMPERATURE (DURING SOLD~RINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml from case for 10, max. . +265 0 C Fig. 3 - Typical output high (source) current
characteristics.
269
CD4089B Types
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted. For maximum
reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
(VI Min. Max.
Supply·Voltage Range (For T A = Full Package·
3 18 V
Temperature Rangel
5 160 -
Set or Clear Pulse Width, tw 10 90 - ns
15 60 -
5 330 -
15 100 - Fig. 5 - Minimum output high (source) current
characteristics,
5 1.2
Clock Frequency, tCl 10 de 2.5 MHz
15 3.5
5,
Clock Rise or Fall Time, trCl or tfCl - 15 ps
10,15
5 100 -
Inhibit In Setup Time, tsu 10 40 - ns
15 20 -
5 240 -
fnhibit In Removal Time, tREM 10 130 - ns
15 110
5 150 - LOAD CAPACITANCE rCa)-pf'
Set Removal Time, tREM 10 80 - ns Fig. 6 - Typical propagation de/ay time as a

15 50 - function of load capacitance (Clock
5 60 - or Strobe to Out).
Clear Removal Time, tREM 10 40 - ns

15 30 -
STROBE CASCADE
LOAD CAPACITANCE CCL)- pF

'0:
-'"'-'~~r~
A
,
~
!
~
~
.
104
I :::
~11 ~ ~~••/
2
/' I • .j. ..
!!l •
.,
·AL.l INPUTS ARE PROTECTED E ,
~ i V C.... SOpF
NETWORK 00' Cl·"pF - - -
~
'::1
4
llll
92CS-2:5007R3 00 I ... 10
1
2 4., 102 24.' 10 3
INPUT FREQUENCY It'N)-~HI
... , ...
l,l i l l
104
t2CS-291S5
Io!!

Vss Fig. 4 - Logic diagram.
270
CD4089B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C; Voo
Input t r • tf = 20 ns. Cl = 50 pF. Rl =200 kH

TEST
r- LIMITS
VDD
V Min. Typ. Max.
Propagation Delay Time. tpHl' tplH

5 - 110 220
Clock to Out
10 - 55 110
15 - 45 90 ns 92CS-29157
5 - 150 300 Fig. 9 - Dynamic power dissipation test circuit.

Clock or Strobe to Out 10 - 75 150
15 - 60 120
Voo
Clock to Inhibit Out
5 - 360 720 INPUTS , - " - - - - ,
•
o
High level to low level
10 - 160 320 ns Vss
15 - 110 220
5 - 250 500
low level to High level 10 - 100 200 ns
15 - 75 150
5 - 380 760
Vss
Clear to Out 10 - 175 350 ns
15 - 130 260 Fig. 10 - Quiescent device current rest circuit.
5 - 300 600
C~ock to "9" or "15" Out 10 - 125 250 ns
V~NPU(J'
15 - 90 180
5 - 90 180
Cascade to Out 10 - 45 90 ns '. ;;:::c:::::'
15 - 35 70
Vss TO 80TH Voo ANO \Iss'
5 - 160 320 CONNECT ALL UNUSED
INPUTS TO EITHER
Inhibit In to Inhibit Out 10 - 75 150 VOD OR Vss'
15 - 55 110 Vss
ns
5 - 330 660
Set to Out 10 - 150 300
15 - 110 220
5 - 100 200
Transition Time. tTHl' tTlH 10 - 50 100 ns
15 - 40 80 INPUTOVOOOUTPUTS
V,H
5 1.2 2.4 -
'- ~
Maximum Clock Frequency. fCl 10
15
2.5
3.5
5
7
-
--
MHz V~L 1
NOTE:
5 - 165 330 Vss TEST ANY COMBINATION
OF INPUTS
92CS-21441RI
15 - 50 100
5 - - 15 Fig. 12 - Input-voltage test circuit.
Clock Rise or Fall Time. trCl. tlCl 10 - - 15 fJS
15 - - 15
5 - 80 160
"IS"OUT I. 16 voo
c 15 B
Minimum Set or Clear Pulse Width. tw 10 - 45 90 ns 0 14
15 - 30 60 SETTO"15" 4 13 CLEAR
OUT 5 12 CASCADE
5 - 50 100 INHIBIT IN
,Minimum Inhibit-In Setup Time. tsu 10 - 20 40 ns

OUT
INHIBIT OUT
(CARRY)
"
10
(CARRY)
STROBE
15 - 10 20 VS9 9 CLOCK
Minimum Inhibit In 5 - 120 240

92CS-2~OO!5RI
Removal Time.
10 - 65 130 ns
TOP VIEW
tREM
15 - 55 110
TERMINAL ASSIGNMENT
271
CD4089B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C (cont'd)
Input t r , tt = 20 ns, CL = 50 pF, RL = 200 kU
TEST
CHARACTERISTIC ... OND\TIO~ UNITS
LIMITS
VDD
V Min. Typ. Max.
5 - 75 150
Minimum Set Removal Time, tREM 10 - 40 80 ns
15 - 25 50
5 - 30 60
Minimum Clear Removal Time, tREM 10 - 20 40 ns
15 - 15 30
Input Capacitance, CIN Any Input - - 5 7.5 pF

CHARAC· N
CONDITIONS Values at -55, +25, +125 Apply to 0, F, K, H Packages I
+25 S
Vo VIN VOD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent
- 0,5 5 5 5 150 150 - 0.04 5
Device - 0,10 10 10 10 300 300 - 0.04 10
IJA
Current, - 0,15 15 20 20 600 600 - 0.04 20
100 Max.
- 0,20 20 100 100 3000 3000 - 0.08 100
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -

Output Low
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 6.8 -
3.4
Output High
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IQH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
- 0,5 5 0.05 - 0 0.05
Output Voltage:
Low·Level, 0,10 10 0.05 - 0 0.05
VOL Max. _. 0,15 15 0.05 - 0 0.05 V
Output - 0,5 5 4.95 4.95 5 -
Voltage: - 0,10 10 9.95 9.95 10 -
High·Level,
VOH Min. - 0,15 15 14.95 14.95 15 -
0.5,4.5 - 5 1.5 - - 1.5
Input Low
Voltage 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 - 15 4 - - 4 V
Input High 0.5,4.5 .- 5 3.5 3.5 - -

Voltage, 1,9 - 10 7 7 - -
VIHMin. 11 - -
1.5,13.5 - 15 11
Input Current ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 IJA

- 0,18 18
liN Max.
272
CD4089B Types
TRUTH TABLE MOST SIGNIFICANT
DIGIT
LEAST SIGNIFICANT
DIGIT
INPUTS OUTPUTS
Number of Pulses or Number of Pulses or 8 DRM®~
Input Logic Level Output Logic Level INHour
(0 = Low; 1 = High; X = Don't Care) (L = Low; H = High)
D C B A CLK INH STR CAS CLR SET OUT OUT INH "15"
IN OUT OUT
000 0 16 0 0 0 0 0 L H 1 1
o0 0 1 16 0 0 0 0 0 1 1 1 1 CLOCK
0 0 1 0 16 0 0 0 0 0 2 2 1 1 Fig. 13 - Two CD4089B's cascaded in the "Add'

mode with a preset number
0 0 1 1 16 0 0 0 0 0 3 3 1 1
11 13 189)
of189 ( - - + - = -
0 1 0 0 16 0 0 0 0 0 4 4 1 1 16 256 256 .
0 1 0 1 16 0 0 0 0 0 5 5 1 1
0 1 1 0 16 0 0 0 0 0 6 6 1 1
0 1 1 1 16 0 0 0 0 0 7 7 1 1
1 0 0 0 16 0 8
I
0 0 0 0 8 1 1
1 0 0 1 16 0 0 0 0 0 9 9 1 1
1 0 1 0 16 0 0 0 0 0 10 10 1 1
1 0 1 1 16 0 0 0 0 0 11 11 1 1 OUT
c ORM(i) OUT
1 1 0 0 16 0 0 0 0 0 12 12 1 1 c
1 1 0 1 16 0 0 0 0 0 13 13 1 1
1 1 1 0 16 0 0 0 0 0 14 14 1 1
1 1 1 1 16 0 0 0 0 0 15 15 1 1
X X X X 16 1 0 0 0 0 t t H t CLOCK
X X X X 16 0 1 0 0 0 L H 1 1 92CS·25009
Fig. 14 - Two CD4089B's cascaded in the "Multiply"

X X X X 16 0 0 1 0 0 H * 1 1
1 X X X 16 0 0 0 1 0 16 16 H L
11 13 143)
0 X X X 16 0 0 0 1 0 L H H L of143 ( - x - = - - - •
16 16 256
X X X X 16 0 0 0 X 1 L H L H
* Output same as the first 16 lines of this truth table (depending on values of A, B, C, DJ.
t Depends on internal state of counter.
CLOCK
caUNTER STATE a I 2 3 4 5 6 7 8 9 10 II 12 13 14 15 0 I
(LSB) IN PUT A- H
_____ n ~L _______ ~I~I
1*1 _
OUTPUT
I I WAVE
INPUT 8"H
______~n~______________~nL_____+:~:- TRAINS
ITERM.G)
INPUTC-H
L--_--I L_~nL_----JnL....-i_
(MSBIINPUT D"H
I I
*AN OUTPUT 81T MAY BE FILLED IN THIS COUNTER STATE
BY A LESS SIGNIFICANT C04089 CASCADED IN THE ADD MODE.

are derived from the basic inch dimensions as in·
dicared. Grid graduations are in mils 3 inch). "0-
represent a chip when it Is part of the wafer. When the
wafer is separated into individual chips, th. angle of
different chips. The actua' dimensions 01 the isolated
chip, therefore, may differ slJghtly from the nominal
Dimensions and Pad Layout for CD4089BH of -3 mils to +16 mils applicable to the nominal
dimensions shown.
273
CD4093B Types
CMOS Features:
• Schmitt-trigger action on each input with no
Quad 2-lnput NAND external components
• Hysteresis voltage typically 0.9 V at
Schmitt Triggers =
V DD 5 V and 2.3 V at VDD 10 V =
• Noise immunity greater than 50%
High-Voltage Types (20 Volt Rating) • No limit on input rise and fall times
The RCA-CD4093B consists of four Schmitt-
• Maxi mum input current of 1 /lA at 18 V
trigger circuits. Each circuit functions as a
over full package-temperature range,
two·input NAND gate with Schmitt·trigger
100 nA at 18 V and 25°C
action on both inputs. The gate switches at
• 5-V, 10-V. and 15·V parametric ratings
different points for positive- and negative-
going signals. The difference between the • Meets all requirements of JEDEC Tentative FUNCTIONAL DIAGRAM
Standard No. 13A. "Standard Specifications
positive voltage (Vp) and the negative volt·
age (VN) is defined as hysteresis voltage (VH)
(see Fig. 2). Applications: RECOMMENDED OPERATING CONDITIONS
The CD4093B types are supplied in 14-lead • Wave and pulse shapers For maximum reliability, nominal operating
hermetic dual-in-line ceramic packages (D • High-noise-environment systems conditions should be selected so that operation
and F suffixes). 14-lead dual-in-line plastic • Monostable multivibrators is always within the following ranges.
package (E suffix), 14-lead ceramic flat • Astable multivibrators
package (K suffix), and in chip form (H • NAND logic CHARACTERISTIC MIN. MAX. UNITS
suffix). Supply· Voltage Range
(T A = Full Package·
Temp. Range) 3 18 V
MAXIMUM RATiNGS, Absolute-Maximum Values:

(Vollages referenced 10 VSS Terminal) -0.510 +20 V 115,e.121~
* n 3(4,10,11}
2(6,9,13)
INPUT VOLTAGE RANGE. ALL INPUTS -0.510 VDD +0.5 V
* AL.L. INPUTS PROTECTED BY cosmos
PROTECTION NETWORK
For T A = -40 10 +60 oC (PACKAGE TYPE E) . . . . . . . .. 500mW
For TA = +60 10 +85 0C (PACKAGE TYPE E) , Derale linearly al12 mW/oC to 200 mW
For TA = -55 to +100·C (PACKAGE TYPES D, F. K) . . . . . . . .. 500mW
a
For TA = +100 to +125·C (PACKAGE TYPES D, F, K) Derale linearly at 12 mW/oC 10200 mW
FOR TA = FULL PACKAGE· TEMPERATURE RANGE (All Package Types) l00mW
PACKAG'E TYPES 0, F, K, H . . . . . . . . . . . . . . . . . . . . . . . -55 to +125 0C
PACKAGE TYPE E. . . . . . . . . . . . . . . • -40 10 +850C
STORAGE TEMPERATURE RANGE ITstgl -65 10 +150°C
LEAD TEMPERATURE (DURING SOLDERING): 92CS'238SIRI Vss
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. Fig. 1 - Logic diagram-1 of 4 Schmitt triggers.
JlVOH vr_
': Z_n---$J-
=iY-,::o.:-- ------'jJ0>-
YD~ Yo
ORIVER L.OAD
Yl~
OUTPUT INPUT
CHARACTERISTIC CHARACTERISTIC
cJ Test setup
~zu~~~~----VOO---------
L---~---t----~
LOOUG~;~';:/
T-------
:=1 ~ a) Definition of V p. VN' VH
bJ Transfer characteristic
of 1 of 4 gates.
Fig. 2 - Hvsteresis definition, characteristic, and test setup.

.,lCM-Zl8Ufill YOH
REG ION
-
_vp ____ _
VN ----...r;«-:~~~21
Fig. 3 - Input and output characteristics.

92CS-Z3883R3
274
CD4093B Types
CHARACTER- CONDITIONS Values al-55, +25, +125 Apply 10 D, F, K, H Packages
ISTIC Values at -40, +25, +85 Apply to E Packages UNITS
Vo VIN VDD +25

(VI (VI (VI -55 -40 +85 +125 MIN. TVP. MAX.
Quiescent Device - 0.5 5 I 1 30 30 - 0.02 1

Current, I DD - 0,10 10 2 2 60 60 - 0.02 2 Jl.A
Max. - 0,15 15 4 4 120 120 - 0.02 4
- 0,20 20 20 20 600 600 - 0.04 20
Positive Trigger - a 5 2.2 2.2 2.2 2.2 2.2 2.9 - Fig. 4 - Typical current and voltage
transfer characteristics,
Threshold Voltage - a 10 4.6 4.6 4.6 4.6 4.6 5.9 -
Vp Min. - a 15 6.8 6.8 6.8 6.8 6.8 .8.8 -
- b 5 2.6 2.6 2.6 2.6 2.6 3.3 - V
- b 10 5.6 5.6 5.6 5.6 5.6 7 -
Vp Max.
-
-
b
a
15
5
6.3
3.6
6.3
3.6
6.3
3.6
6.3
3.6 -
6.3 9.4
2.9
-
3.6
I
- a 10 7.1 7.1 7.1 7.1 - 5.9 7.1
- a 15 10.8 10.8 10.8 10.8 - B.B 1O.B V
- b 5 4 4 4 4 - 3.3 4
- b 10 B.2 B.2 B.2 B.2 - 7 B.2
- b 15 12.7 12.7 12.7 12.7 - 9.4 12.. 7 INPUT VOLTAGE !VI I-v
Negative Trigger - a 5 0.9 0.9 0.9 0.9 0.9 1.9 - Fig. 5 - Typical voltage transfer characteristics
Threshold Voltage - a 10 2.5 2.5 2.5 2.5 2.5 3.9 -
VN Min. - a 15 4 4 4 4 4 5.B -
V
- b 5 1.4 1.4 1.4 1.4 1.4 2.3 -
- b 10 3.4 3.4 3.4 3.4 3.4 5.1 -
- b 15 4.B 4.B 4.8 4.8 4.8 7.3 -
II
- a 5 2.8 2.8 2.8 2.8 - 1.9 2.8
VN Max.
- a 10 5.2 5.2 5.2 5.2 -- 3.9 5.2
- a 15 7.4 7.4 7.4 7.4 - 5.8 7.4 V
-
-
b
b
5
10
3.2
6.6
3.2
6.6
3.2
6.6
3.2
6.6
-
-
2.3
5.1
3.2
6.6 II ,
- b 15 9.6 9.6 9.6 9.6 - 7.3 9.6
DRAIN-Te-SOURCE VOLTAGE (vOSJ-V
- a 5 0.3 0.3 0.3 0.3 0.3 0.9 -
Hysteresis Voltage Fig. 6 - Typical output low (sink) current characteristics.
VH Min. - a 10 1.2 1.2 1.2 1.2 1.2 2.3 -
- a 15 1.6 1.6 1.6 1.6 1.6 3.5 -
V
- b 5 0.3 0.3 0.3 0.3 0.3 0.9 -
i'i
- b 10 1.2 1.2 1.2 1.2 1.2 2.3 - I~,
- b 15 1.6 1.6 1.6 1.6 1.6 3.5 -
VH Max. -
-
a
a
5
10
1.6
3.4
1.6
3.4
1.6
3.4
1.6
3.4
-
-
0.9
2.3
1.6
3.4
i'
- a 15 5 5 5 5 - 3.5 5 V
- b 5 1.6 1.6 1.6 1.6 - 0.9 1.6
- b 10 3.4 3.4 3.4 3.4 - 2.3 3.4
- b 15 5 5 5 5 - 3.5 5
,
OR.,"-·rO-,,,'UfICE VOLTAGE (VDSI-V
illnput on terminals 1,5,8,12 or 2.6.9,13; other inputs to V OD '

Fig. 7 - Minimum output low (s;nk) current
b, nput on terminals 1 and 2, 5 and 6,8 and 9, or 12 and 13; other inputs to V oo '
characteristics.
275
CD4093B Types
STATIC ELECTRICAL CHARACTERISTICS (CONT'DI DRAIN- TO-SOURCE VOLTAGE ('o'05)-V
~ ...:!Q.
LIMITS AT INDICATED TEMPERATURE (oCI
CHARACTER· CONDITIONS Values at-55, +25, +125 Apply to D, F, K, H Packages
ISTIC Values at -40, +25, +85 Apply to E Packages UNITS
Vo VIN VDD +25
(VI (VI (VI -55 -40 +85 +125 MIN. TYP. MAX.
Output Low (Sink) 0.4 D,S 5 0.64 0.61 0.42 0.36 0.51 1 -
Current, 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
mA
Output High 4.6 D,S 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 -
(Source) 2.5 D,S 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - Fig. 8 - Typical output high (source) current
IOH Min. characteristics.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage
- D,S 5 0.05 - 0 0.05
ORAIN-lO-SOURCE VOLTAGE (Vos)-V
Low-Level, - 0,10 10 0.05 - 0 0.05 -15 -10 -~
AMBIENT TEMPERATURE (TAI·25·C
VOL Max. - 0,15 15 0.05 - 0 0.05 V GATE -TO-SOURCE VOLTAGE ('iGS'· -~ 'i
Output Voltage
- 0,5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min. - 0,15 15 14.95 14.95 -
Input Current,
liN Max. - 0,18 18 ±0.1 ±0.1 ±1 ±, _. ±10- 5 ±0.1 fJ.A
DYNAMIC ELECTRiCAL CHARACTERISTICS

At TA = 25'C; Inputt" rf= 20ns, CL = 50pF, R L = 200kD.
characteristics.
VDO
TYP. MAX.
VOLTS
tpHL, 10 90 180 ns
tpLH 15 65 130
5 100 200
Transition Time, tTHL, 10 50 100 ns
tTLH 15 40 80
Input Capac'tance, CIN Any Input 5 7.5 pF

vs. supply voltage.
AMBIENT TEMPERATURE (TA"25·C -AMBIENT TEMPERATURE (TA1.25"C

INPUT ON TERMINALS I, ~,8. 12 OR Z. 6,9, 13;
I
OTHER INPUTS TIED TO "DO
"
'0
'"
10 15
'" "
SUPPLY VOLTAGE IVOOI-V
SUPPLY .... OLTAGE 1'I 00 1-V
Fig. 11 - Typical transition time vs. load Fig. 13 - Typical percent hysteresis vs.
Fig. 12 - Typical trigger threshold voltage vs. V DO'
capacitance. supply voltage.
276
CD40938 Types
APPLICATIONS
TO CONTROL
SIGNAL
OR VOO
~ n n-
VOO-T\--,- VOD
vss.L-~ __
114 C04093B
..J U Lvss
92CS·23885
2461 2461 2468 2 ""II 2 "'68 l '" 5110 ,2 '" .'IOlZ '" 1810 ",2 '" 6810~2 46'101 FREQUENCY RANGE OF WAVE SHAPE
10- 1 100 101 102 IOl 10'"
IS FROM DC TO I MHz
FREQUENCY III-kHz RISE AND FALL TlhtE Ilr.ltl-n.
Fig. 14 - Typical power dissipation vs. Fig. 15 - Typical power dissipation vs. rise and Fig. 16 - Wave shapero
frequency characteristics. fall times.
VOO
I
TO CONTROL SIGNAL
OR VOO
voo
vs.-J
1- " ....,
n
L-I
r INPUTS II
:oon
o
113CD4oo7A Z U 3 Vss
J~ 114C0409'. IA'Rct.[~)(~)l
50kQ:!;R:!;IMn
SS VSS 100 pF:!; C:!; I~F
FOR THE RANGE OF RAND C GIVEN

2~s < IA <0.41
FOR THE RANGE OF R AND C

GIVEN 5~, < 1M < Is
92CS-23886RI Fig_ 18 - Astable multivibrator.

Fig. 17 - Monostable multivibrator. Fig. 19 - Quiescent device current test
circuit.
Veo
?@-
I h l P UVoo
OS NOTE
~::~~:il~~~~~S
I. 14
13
12
voo
Vss TO BOTH VOO ANDVSS·

CONNECT ALL UNUSED
10 L~""["7"F
INPUT"S 10 EITHER
VSS
Voo OR VSS·
Vss
•
(TOP VIEW)
9ZCS-24835
Fig. 20 - Input current test circuit. TERMINAL ASSIGNMENT


wafer is separated into individual Chip$, the angle of
dimenSions shown. The user should consider a tolerance
dimensions shown.
92CS-35099
277
CD4094B Types
CMOS
a-Stage Shift-and-Store
Bus Register Features:
• 3-state parallel outputs for connection to common bus
High-Voltage Types (20-Volt Rating) • Separate serial outputs synchronous to both positive
and negative clock edges for cascading
The RCA-CD4094B is an 8-stage serial shift • Medium speed operation - 5 MHz at 10 V (typ.)
register having a storage latch associated
with each stage for strobing data from the • Maximum input current of 1p.A at 18 V over full package-
PARALLEL OUTPUTS al-C8
serial input to parallel buffered 3-state out- temperature range; 100 nA at 18 V and 25°C
ITERMINAl.S 4,'.6,7,14,13.12,11.
puts. The parallel outputs may be connected • Noise margin (full package temperature range): RESPECTIVELY)
directly to common bus lines. Data is shifted 1VatVOD=5V 2VatVOO=10V

on positive clock transitions. The data in 2.5 Vat VOO = 15 V
• 5-V, 10-V, and 15-V parametric ratings FUNCTIONAL DIAGRAM
each shift register stage is transferred to the
storage register when the STROBE input is Standard No. 13A, "Standard Specifications
high. Data in the storage register appears at for Description of'S' Series CMOS Devices" STROBE I. I. VOD
the outputs whenever the OUTPUT -ENABLE DATA 2 15 OUTPUT ENABLE
CLOCK I. O'
signal is high. 01 13 O.
02 12 07
Two serial outputs are available for cascad- Applications: 08
ing a number of CD4094B devices. Data is
0'
"
10 O's
• Serial-to-parallel data conversion Vss Os
available at the Os serial output terminal on • Remote control holding register TOP VIEW
positive clock edges to allow for high-speed • Dual-rank shift, hold, and bus applications
Fig. 1 - Terminal assignment.
operation in cascaded systems in which the
clock rise time is fast. The same serial infor-
mation, available at the Q'S terminal on the MAXIMUM RATINGS, AbSOlute-Maximum Values:
next negative clock edge, provides a means DC SUPPLY-VOLTAGE RANGE, (VDD)
for cascading C04094B devices when the (Voltages referenced to VSS Terminal) ..•...•......••................................... -0.5 to +20 V
clock rise time is slow. INPUT VOLTAGE RANGE, ALL INPUTS ..•.•........•.....•.•.•.•................•.• -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT •.....•...............................•...•••.•..•...•• ±10 mA
The CD4094B types are supplied in l6-lead POWER DISSIPATION PER PACKAGE (PD):
hermetic dual-in-line ceramic packages (D For TA ~ -40 to +60·C (PACKAGE TYPE E) ....•...•.............•.•................•........ 500 mW
and F suffixes), l6-lead dual-in-line plastiC For TA ~ +60 to +85·C (PACKAGE TYPE E) ..........•...•.•... Derate Linearly at 12 mW/·C to 200 mW
package (E suffix), l6-lead ceramic flat ForTA ~-55 to +l00·C (PACKAGE TYPES D, F, K) ...•......•..............•.......•........•. 500 mW
package (K suffix), and in chip form (H For TA ~ +100 to +125·C (PACKAGE TYPES D, F, K) ..•.•.....•. Derate Linearly at 12 mW/·C to 200 mW
suffix).
DEVICE DISSIPATION PER OUTPUT TRANSISTOR: .
ForTA ~ FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ....•.........•.....••. 100 mW
PACKAGE TYPES D, F, K, H .......................................................... -55 to +125·C
PACKAGE TYPE E .................................................................... -40 to +85·C
STORAGE TEMPERATURE RANGE (Tstg) ............................................... -65 to +150·C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max............................ +265·C
CLOCK
SERIAL
OUT 9 DATA IN
STAGES Os
'-7
£t
TR
VDD
OUTPUT ,\I.,!.'--~-++-r"---'
SERIAL.:Q~_ _ _t+T1_-"""~
3-
~~:~~~
OS
OUTPUT..:li.-----t+-l+-++-T-I-'
STATE
8 *ALL INPUTS PROTECTED
BY COS/MOS
PROTECTION NETWORK Fif/- 3 - Timing diagram.
08
Fig. 2 - C040948 Logic diagram.
278
CD4094B Types
RECOMMENDED OPERATING CONDITIONS at TA = 25"C, Except as Noted. TRUTH TABLE
For maximum reliability, nominal operating conditions should be selected so that Par.llel Serial
operation is always within the following ranges: CL'

Output
Enable Strobe D,,, Outputs Outputs
01 ON OS· O·S
.r 0 X X OC OC 07 NC
VDD
LIMITS \... 0 X X OC OC NC 07
CHARACTERISTIC UNITS J 1 0 X NC NC 07 NC
(V) J 1 1 0 0 Q7 NC
MIN. MAX. °N·1
J 1 1 r 1 ON·' Q7 NC
Supply·Voltage Range (For T A=Full '- 1 1 1 NC NC NC Q7
3 18 V • :; Level Change Logic' == Hign

Package·Temperature Range) X '" Don'1 Care Logie a == Low
NC '" No Change
ac " Open Circuil,
5 125 - • At the positive clock edge information in the 7tn snift register,
Data Setup Time, ts 10 55 - ns stage 1$ transferred to tne Btn register stage and tne aS output.
15 35 -
5 200 -
15 83 -
5 1.25
Clock Input Frequency, tCl 10 dc 2.5 MHz
15 3
Clock Input Rise or Fall time, 5 15
trCl, ttCl:*
10
15
- 5
5
Ils
I
5 200 - ORAIN-TO-SOURCE VOLTAGE lVosl-V
Strobe Pulse Width, tw 10 80 - ns Fig. 4 - Typical output low (sink) current

15 70 - characteristics.
·U more than one unit is cascaded tfel (for as only) should be made less than or equal
to the sum of the fixed propagation delay at 50 pF and the transition time of the output
driving stage for the estimated capacitive load.
DRAIN-TO-SOURCE: VOI..TAGf.: IVesl-V
DRAIN- TO- SOURCE VOLTAGE lVosl-V
AMBIENT TEMPERATURE ITA,-2!!i·C I I
.,
•,
~15
GATE-lO-SOURCE VOLTAGE (VGS'-I!5V
ffi12.5
~
a 10
'OV
5V
,. 92CS-24319R1
Fig. 5 - Minimum output low (sink) current Fig. 6 - Typical output high (source) ·current Fig. 1 - Minimum output high (source) current
I
LOAD CAPACITANCE IC .. I- (IF LOAO CAPACITANCE IC .. I- " LOAD CAPACITANCE ICLI-" 92CI-25e"
'2CS-2"" .2C,-Z'5n4
Fig. 8 - Clock-ta-serial output aS propagation Fig. 9 - Clock-to-serial output D'S propagation Fig. 10 - Clock-to-Parallel output propagation
delay vs CL. delay vs CL. delay vs CL.
279
CD4094B Types
UNITS
ISTIC +25
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Current, - 0,10 10 10 10 300 300 - 0.04 10
100 Max. /lA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
ucs-nne
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - LOAD CAPACITANCE ICLI- pF
IOL Min. Fig. 11 - Strobe-fa-parallel output propagation

1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 - delay vs CL-
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
Output High
(Source) 2.5 D,S 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current,
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.B -2.4 -3.4 -6.B -
Output Voltage: - D,S 5 0.05 - 0 0.05
Low·Level,
VOL Max.
- 0,10 10 0.05 - 0 0.05
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0.5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage,
VIL Max.
1,9 - 10 3 - - 3
1.5,13.5 - 15 4 - - 4 LOAD CAPACITANCE ICI.I- pf SZCS-2,e17
V
Input High 0.5,4.5 - 5 3.5 3.5 - - Fig. 12 - Output enable·to·parallel output propa·
gation delay vs CL-
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1,5,13,5 - 15 11 11 - -
Input Current ±lQ-5
liN Max.
- O,lB 18 ±D. 1 ±0.1 ±1 ±1 - ±0.1 /lA
3·State Output
Leakage Current 0,18 0,18 18 ±0.4 ±0.4 ±12 ±12 t10- 4 ±0.4 /lA
lOUT Max.
Fig. 13 - Typical transition time vs./oadcapacitance.
AMBIENT TEMPERATURE (fA )-25-C

i 15 LOAD CAPACITANCE (ell a 5011f'
t
r
CONTROL >
a
SYNC
CIRCUITRY
92C5 <'!>643
I
~
FROM REMOTE 10 15 20
CONTROL PANEL SUPPLY YOLTAGE (Yoal-V
Fig. 14 - Remote control holding register. Fig. 15 - Typical maximum-clock-frequency liS.

supply voltage.
280
CD4094B Types
AMBIENT TEMPERATURE (T A )02'5'C
DYNAMIC ELECTRICAL CHARACTERISTICS ALTERNATING 0 AND I PATTERN
At TA;25°C; Input tr, tf; 20 ns, CL ; 50pF, RL ; 200 krl ~~:g~l HfGNHA~~fR~I~HCLOCK PULSES ----jf-----j
LIMITS g IO~
CHARACTERISTIC UNITS ~
VDD ~ 1041::----t--
(VI MIN. TYP. MAX.' ;:
~ 10 3
tpH l. tPlH
5 - 300 600
."
~102~~~f---+---~---r--~
Clock to Serial Output Os 10 - 125 250 ns

15 - 95 190
INPUT CLOCK FREQUENCY "CL)-kH:
5 - 230 460 Fig. 16 - Dynamic power dissipation vs

Clock to Serial Output Os 10 - 110 220 ns input clock frequency.
15 - 75 150
5 - 420 840
Clock to Parallel Output 10 - 195 390 ns
15
5
-
-
135
290
270
580
°
Vss
INPUTS
II
Strobe to Parallel Output 10 - 145 290 ns
15 - 100 200
Output Enable to Parallel 5 - 140 280
Output: 10 - 60 120 ns
tpHZ' tpZH 15 - 45 90
5 - 100 200 Fig. 17 - Quiescent device current
tpLZ. tpZL 10 - 50 100 ns test circuit.
15 - 40 80
Minimum Strobe Pulse

5 - 100 200
10 - 40 80 ns
Width. tw
15 - 35 70
5 - 100 200
Minimum Clock Pulse
10 - 50 100 ns
Width. tw
15 - 40 83
5 - 60 125 Fig. 18 - Input voltage test circuit.
Minimum Data Setup
10 - 30 55 ns
Time. ts
15 - 20 35
Transition Time;
5 - 100 200
tTHL. tTlH
10 - 50 100 ns
15 - 40 80
Maximum Clock Input Rise 5 15 - -
or Fall Time. trCl, tfCl
10 5 - - I1 s
15 5 - -
Maximum Clock Input
5 1.25 2.5 - Fig. 19 - Input current test circuit.
Frequency. fCl
10 2.5 5 - MHz
15 3 6 -
Input Capacitance CI N
(Any Input)
- - 5 7.5 pF
The photographs and dimensions of each CMOS· chip

wafer is saparatud into individual chips, the angle of
cleavage may vary with respect to the chip facB for
dimensions shown. The USBr should considar 8 tolerance
dimensions shown.
Dimensions in parenrheses are in millimeters and arel

Grid graduations are in mils (10- 3 inch). Dimensions and Pad Layout for CD40948 Chip.
281
CMOS Gated J-K SET----_
Master-Slave Flip-Flops
With Set-Reset Capability
CD4095B Non-Inverting J and K Inputs
CD4096B Inverting and Non-Inverting J and K Inputs RESET----.....J
92CS-2'1427RI
Features:
The RCA·CD4095B and CD4096B are J·K
• 16 MHz toggle rate (typ.) at VOD - VSS = 10 V
Master·Slave Flip·Flops featuring separate
• Gated inputs
AND gating of multiple J and K inputs. The • 100% tested for quiescent current at 20 V CD4095B
g&ted J·K inputs control transfer of informa· • Maximum input current of 1 I1A at 18 V over full package· Functional Diagram
tion into the master section during clocked temperature range; 100 nA at 18 V and 25°C
operation. Information on the J·K inputs is • Noise margin over full package-temperature
transferred to the aand a
outputs on the
range: 1 Vat VDD = 5 V, 2 V at VOO =
10 V, 2.5 Vat VOD = 15 V
positive edge of the clock pulse. SET and
RESET inputs (active high) are provided for • Standardized, symmetrical output TRUTH TABLES
asynchronous operation. characteristics SYNCHRONOUS OPERATION (S=O R=O)
The CD4095B and CD4096B types are sup- • Meets all requirements of JEDEC Tentative Inputs Before Outputs After
Standard No. 13A, "Standard Specifications Positive Clock Positive Clock
plied in 14-lead hermetic dual-in-line cer-
amic packages (D and F suffixes). 14-lead Transition Transition
Applications:
dual-in-line plastic package (E suffix). 14-
lead ceramic flat package (K suffix). and in • Registers • Counters - Control circuits
J* K* ala
chip form (H suffix). 0 0 No Change
0 1 0 1

1
1
0
1
1
Toggles
I 0

INPUT VOLTAGE RANGE. ALL INPUTS ........................................... -0.5 to VDD +0.5 V * For CD4095B For CD4096B
DC INPUT CURRENT. ANY ONE INPUT ..................................................... ±10 mA J = J1 . J2' J3 J = J1 . J2' J3
POWER DISSIPATION PER PACKAGE (PD): K = K1 . K2' K3 K= K1' K2' K3
For TA = -40 to +60"C (PACKAGE TYPE E) ................................................. 500 mW ASYNCHRONOUS OPERATION
For TA = +60 to +85"C (PACKAGE TYPE E) ................... Derate Linearly at 12 mW;oC to 200 mW (J and K· DON'T CARE)
For TA = -55 to +100" C (PACKAGE TYPES D, F. K) .......................................... 500 mW
For TA =+100 to +125"C (PACKAGE TYPES D. F. K) .......... Derate Linearly at 12 mW;oC to 200 mW S R a a
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW 0 0 No Change
OPERATING-TEMPERATURE RANGE (TA): 0 1 0 1
PACKAGE TYPES D. F. K. H ........................................................ -55 to +125"C 1 0 1 0
PACKAGE TYPE E .................................................................. -40 to +85"C
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +150"C 1 1 0 0
LEAD TEMPERATURE (DURING SOLDERING): 0= VSS, 1 = VDO
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.......................... +265"C
AMBIENT TEMPERATUR( CTAI.~·C
SET-------, GATE-lO-SOURCE VOLTAGE lVGs).I~ \I
10V
RESET----.....J
92CS - 24430AI
5 10 15
DRAIN-lO-SOURCE VOLtAGE (V051-V DRAIN-TO-SOURCE VOLTAGE (VoSl-V
Fig. 1 - CD40968 Functional Diagram. Fig.2 - Typical output low (sink) Fig.3 - Minimum output low (sink)
282
RECOMMENDED OPERATING CONDITIONS at TA =25' C. Except as Noted, DRAIN-lO-SOURCE VOLTAGE IV05)-1/

CHARACTERISTIC VDD liMITS UNITS

(VI MIN, MAX,
Supply-Voltage Range (For TA = Full

3 18 V
Package-Temperature Rangel
5 400 -
15 100 -
5 140 -
10 60 - ns Fig.4 - Typical output high (source)
Clock Pulse Width, tw
15 40 -
5 3,5 CRAIN-lO-SOURCE VOlTAGE IV051-v
Clock Rise and Fall Time, trCl, tfCl:

15
5
10 --
12
15
5 f.1S
II
15 5
5 200 -
Set or Reset Pulse Width, tw 10 100 - ns
15 50 -

Fig.5 - Minimum output high (source)
LIMITS AT INDICATED TEMPERATURES (DC) current characteristics.
CONDITIONS Value. at -55, +25, +125 App!y: Ie? D, F, K, H Packages
ISTIC UNITS
Vo +25
VIN VDD
(VI (V) (V) -55 -40 +85 +125 Min, Typ, Max,
Current, - 0,10 10 2 2 60 60 - 0.02 2
100 Max. pA
- 0,15 15 4 4 120 120 - 0.02 4
- 0,20 20 20 20 600 600 - 0.04 20
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOlMin.
1.5 0,15 15 4.2 4 2.8 2.4 34 6,8 -
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - LOAD CAPACITANCE (CLI-pf
Current,
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - Fig.6 - Typical propagation delay time VI.
IOH Min. load capacitance.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low·Level, - 0,10 10 0.05 - 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level,
VOH Min.
- 0,10 10 9.95 9.95 10 -
- 0,15 15 14.95 14.95 15 -
Input low 0.5,4.5 - 5 1.5 - - 1.5
Voltage,
Vil Max.
1,9 - 10 3 - - 3
1.5.13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min.
1.5,13.5 - 15 11 11 - -
I nput Current
0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 pA Fig.7 - Typical transition time vs.
liN Max.
load c;apacitance.
283
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25' C; Input t r• tf = 20 ns, "_lENT TEMPERATURE (TA 1-2S·C
CL = 50pF, RL = 200 KQ ' t'l ',.'n.

3C CL -&OpF
iI 2.
CHARACTERISTIC TESTCONDI~ LIMITS UNITS
VDD
~
(VI MIN. TYP. MAX. ~
Propagation Delay Time: tpHL, tpLH 5 - 250 500
2~ 15
10
j
.
~
,:n 1I
Clock 10 - 100 200
~ • !i III ·1'
-
15
5 -
75
150
150
300
ns . I
5
~:i! 10
ill il Ii
15 20
SUPPLY VOLTAGE [VoOI-V
Set or Reset Hi - 75 150
15 - 50 100
Fig.8 - Typical clock frequency lIS. supply
5 - 100 200 voltage (toggle mode-see Fig. 16).
Transition Time, tTHL, tTLH 10 - 50 100 ns
15 - 40 80
5 3.5 7 -
Maximum Clock Input Frequency, (fCLI * 10 8 16 - MHz
15 12 24 -
5 - 70 140
Minimum Clock Pulse Width, tw 10 - 30 60 ns
15 - 20 40
5 - - 15
Clock Input Rise or Fall Time. 10 - - 5 I1S
- 2 4 6 10 2 46 10 2 2 4 6'0' 2 46 104 2
trcl' tref 15 - 5
INPUT CLOCK FREQUENCY (fCL)-kHZ
5 - 100 200
Fig. 9 - Typical power dissipation vs.
Minimum Set or Reset Pulse Width, tw 10 - 50 100 ns input clock frequency.
15 - 25 ' 50
5 - 200 400
Minimum Data Setup Time, ts 10 - 80 160 ns
15 - 50 100
Input Capacitance, CIN Any Input - - 5 7.5 pF
Fig. to - Propagation delay, transition, and

FOR CD409~B J3@!-----. ... setup' time waveforms.
fORCD"I096BJ3~'"
fORCD4095B K3(!)!-------. ...
rORCD4096BK1~'"
RESET. '00
Fig. 12 - Clock pulse rise and fall time
waveforms.
~
CLOCIC
I·
"Ei.
INPUT TO OUTPUT IS·
0\" BIDIRECTIONAL LOW .MPEDANCE -All INPUTS PROTECTED 8Y
WHEN C~TROL INPUT I IS "LOW·
r--~--'
STANDARD COS/MOS
AND CONTROL INPUT 2 IS "HIGH" PflOT[CTION NETWORI! INPUTS
DIAN OPEN CIRCUIT WHEN CONTAOL o
INPUT I IS "HIGH"ANO CONTROL INPUT V55
:2 IS "LOW·
Fig.ll - CD40958 and CD40968 logic diagram.
Fig. 13 - Quiescent device current test

circuit.
284
CD4095B, CD4096B Typ~s
Vss
INPUTOVOO
OUTPUTS '100 1NPUOS
Voo NOT[
"5
V,H
~ MUSURE INPUTS
'-- ~ o ~ SEQUENTIALLoY,
V~L :t 'Iss TO BOTH 'IDe AHD VS5
CONN[CT ALL UNUSED
INPUTS TO [ITNEA
CLOCIC0--t----''-j
NOTE: 'loa OR 'Iss

VSS ~~srN-'p~~~ONBINATION Vss
R
•Vss
Fig. 14 - Input voltage test circuit. Fig. 15 - Input leakage current test
circuit.
Fig. 16 - CD40958 connected in toggle
mode.
'. 't
"
C0409&6
5 ~~g~~ - .....-------n-------I~------h
v" I
CLOCK
Vss
Fig. 17 - CD40968 connected as a "D" oI I I ' I ' I• I• I, I ' I , I' I 0 I I

STATE QA Os OC DO
type flip-flop_
~
o 0
, ,,
0 0 0
c. ~ ,
NOTE PIN$:r.'lAESE'.
's ~ sn.GOTOVssON
ALL-UNITS
't
'0 -------------~
Fig. 18 - Synchronous binary divide·by·ten counter.
DIMENSIONS AND PAD LAYOUT FOR CD4095B AND CD4096B

NO I. voo
RESET 2 " SET
JI "
" .,CLOCI(
J'
J'
il
10
9 .,••
Vss 0
1.7781 TOP \lIEW

NC'NOCONNECTION 92C~ il4'UIJ
CD4095B
NO I. I. 1IQ0
RESET
• " SET
92CS-32213 J>
JI 12
"
.,
Cl.OCK
J!
CD4095BH
CD4096BH
10
9 "i1J
Vss
represent a chip when it is par' of the wafer, When the Dimensions in parentheses are in millimeters and are
wafer is separated into individual chIps. the angle of lOP \l1E¥"
derived from the basic inch dimensions as indicated. NC"NQCONNECTION 9'r.~ l!44"'.,
clsavage may vary with respect to the chip face for Grid graduations are in mils (10-3 inch).
different chips. The actual dimensions of the iso/a red
dimensions shown. Ths ussr should consider a to/srance CD4096B
dimensions shown.
285
CD4098B Types
CMOS Dual Monostable .-I1_..J>v'V'v-VDD
Multivibrator Features:
High·Voltage Types (20·Volt Rating) • Retriggerablefresettable capability
• Trigger and reset propagation delays
independent of RX, Cx
The RCA·CD409BB dual monostable multi- • Triggering from leading or trailing edge
vibrator provides stable retriggerable/reset- • Q and Q buffered outputs available
table one-shot operation for any fixed-volt- • Separate resets
age timing application. • Wide range of output· pulse widths
An external resistor (RX) and an external • 100% tested for maximum quiescent
capacitor (CX) control the timing for the current at 20 V
circuit. Adjustment of RX and Cx provides • Maximum input current of 1 J.lA at
a wide ra.Dge of output pulse widths from the 18 V over full package·temperature
ex. RX'
o and 0 terminals. The time delay from range; 100 nA at 18 V and 25°C
CD4098B
92CS-24253
trigger input to output transition (trigger • Noise margin (full package·temperature

range): 1 Vat VOO= 5 V Functional Diagram
propagation delay) and the time delay from
reset input to output transition (reset pro- 2 V at VOO=10 V
pagation delay) are independent of RX and 2.5 V at VOO=15 V
CX·
Leading-edge-triggering (+TR) and trailing-
characteristics
CXI
R X C)(1I1
I. ,.I. VDD
CX'
RESET (I) R)(C)(12)
edge-triggering (-TR) inputs are provided
for triggering from either edge of an input
• Meets all requirements of JEOEC
Tentative Standard No. 13A, "Stand·
+TR (II
-TR (I) I. "
13 RESET (2)
+TR (2)
pulse. An unused +TR input should be tied
to VSS. An unused - TR input should be tied
to VDD. A RESET (on low level) is provided
ard Specifications for Oescription of '8'
Series CMOS Oevices."
01
OT
vss
I." -TR 121
O.
ii2
for immediate termination of the output Applications: TOP VIEW
pulse or to prevent output pulses when power • Pulse delay and timing TERMINALS 1,8,15 ARE
is turned on. An unused RESET input should • Pulse shaping ELECTRICALLY CONNECTED
be tied to VDD- However, if an entire section • Astable multivibrator INTERNALLY
92CS-24848AI
of the CD409BB is not used, its RESET
should be tied to VSS. See Table I. TERMINAL ASSIGNMENT
In normal operation the circuit triggers (ex-
tends the output pulse one period) on the MAXIMUM RATINGS, Absolute-Maximum Values;
application of each new trigger pulse. For
DC SUPPLY·VOLTAGE RANGE.IVOO'
operation in the non-retriggerable mode, Q is (Voltages referenced to VSS Terminal) 0.5 to +20 V
connected to - TR when leading-edge trig- INPUT VOLTAGE RANGE. ALL INPUTS ·0.5 to VDD +0.5 V
gering (+TR) is used or 0 is connected to +TR DC INPUT CURRENT. ANY ONE INPUT ±10mA
when trailing-edge triggering (-TR) is used_ POWER DISSIPATION PER PACKAGE IPD):
The time period (T) for this multivibrator can For TA ~ -40 to +60 0 C IPACKAGE TYPE E) . . . . . . . .. 500mW
be approximated by: TX=%RXCX for Cx ;;. For T A ~ +6010 +85 0 C IPACKAGE TYPE EI Derate Lmearly at 12 mW/oC to 200 mW
0.01 J.lF. Time periods as a function of RX =
For T A -55 to +100'C (PACKAGE TYPES D, F, K) . . . . . . . .. 500mW
for values of Cx and VDD are given in Fig_ 8. =
For T A +100 to +125'C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mW/oC to 200 mW
Values of T vary from unit to unit and as a FOR TA ~ FULL PACKAGE·TEMPERATURE RANGE IAII Package TV~"'s) 100 rnW
function of voltage, temperature, and RXCX. OPERATING·TEMPERATURE RANGE IT A):
PACKAGE TYPES D, F, K, H 55 to .,25 0 C
The minimum value of external resistance,
PACKAGE TYPE E 40 to +85 DC
RX, is 5 kn. The maximum value of external
STORAGE TEMPERATURE RANGE ITstgl 65 to +150o C
capacitance, CX, is 100 J.lF- Fig. 9 shows time
LEAD TEMPERATURE lOURING SOLDERING):
periods as a function of Cx for values of RX At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max.
and VDD.
The 'output pulse width has variations of
±2.5% typically, over the temperature range RECOMMENDED OPERATING CONDITIONS
of _55°C to 125°C for CX=1000 pF and For maximum reliability, nominal operating conditions should be selected
RX=100 kn. so that operation is always within the following ranges:
For power supply variations of ±5%, the out- LIMITS
put pulse width has variations of ±0.5% VDO
typically, for VDD=10 V and 15 V and ±1% V MIN. MAX.
typically, for VDD=5 Vat CX=1000 pF and Supply·Voltage Range (For TA =
RX=5 kn. Full Package-Temperature - 3 lB V
These types are supplied in 16-lead hermetic Range)
dual-in-line ceramic packages (D and F 5 140
suffixes). 16-lead dual-in-line plastic pack- Trigger Pulse Width tW(TR) 10 60 - ns
age (E suffix). 16-lead ceramic flat packages 15 40 -
See
The CD4098B is similar to type MC1452B_ Reset Pulse Width tW(R) Dynamic Char.
(This is a function of CX) - Chart and
-
Fig. 10
Trigger Rise or Fall Time
5·15 - 100 J.ls
tr(TR), tf(TR)
286
CD4098B Types
TABLE I
CD4098B FUNCTIONAL TEFIMINAL CONNECTIONS
V DD TO VSS TO INPUT PULSE OTHER

FUNCTION TERM. NO. TERM. NO. TO TERM. NO. CONNECTIONS
MONO, MON0 2 MONO, MON0 2 MONO, MON0 2 MONO, MON0 2 7it 'I
IDV---It
Leading·Edge
10 t t
, r:r; 1
Trigger/ 3,5 11,13 4 12
Retriggerable f , til
Leading·Edge
rm U
, '0
Trigger/ 3 13 4 12 5·7 11·9 DRAIN-TO-SOURCE VOLTAGE (VDS)-V
Non·retriggerable Fig. 1 - Typical output low (sink)

Trailing·Edge current characteristics.
Trigger/ 3 13 4 12 5 11
Retriggerable
Trailing·Edge ,
Trigger/
Non·retriggerable
3 13 5 11 4·6 12·10
I
~15
~12.5
If
1.
GATE-TO-SOURCE VOLTAGE (VGS)'15 V
II
Unused Section 5 11 3,4 12,13 3 10
NOTES: III 7.5
1. A RETRIGGERABLE ONE-SHOT MUL TI-

VIBRATOR HAS AN OUTPUT PULSE
2. A NON-RETRIGGERABLE ONE.SHOT g 5
MUL TIVIBRATOR HAS A TIME PERIOD
WIDTH WHICH IS EXTENDED ONE FULL TX REFERENCED FROM THE APPLI·
"
~ 2.5
TIME PERIOD (T xl AFTER APPLICATION CATION OF THE FIRST TRIGGER PULSE.
OF THE LAST TRIGGER PULSE.
S 10 IS
The minimum time between INPUT PULSE TRAIN DRAIN-TO-SOURCE VOLTAGE (VDS)-V
retriggering edges (or trigger
and ret rigger edges) is 40 AETRIGGERABLE MODE PULSE WIDTH --'r---FI-:--....,T,..x-~..., Fig. 2 - Minimum output low (sink)
per cent of (T x). (+TR MODE)
curren t characteristics.
NDN·RETAIGGERABLE MODE PULSE ~
WIDTH i--Tx--.j DRAIN-TD-SOURCE VOLTAGE (VDS)-V
(+TR MODE) -IS -10
AMBIENT TEMPERATURE (TA)-2S"C
·10
'(1
·20
3( 13) * -ISV .",

RESET

'''5'~ current characteristics.
so---l-vss
DRAIN-TO-SOURCE VOLTAGE (VOs)-V
-o::'~~)eV:D-
ISO---VOO
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _
NOTE: SCHEMATIC SHOWN IS 1/2 OF TOTAL
~~~~~GREs' TA~ ~~~~~~ ;::::~:~s *:~TI~~~g A:;

1,6,15 ARE ELECTRICALLY CONNECTED COS/MOS PROTECTION
INTERNALLY. NETWORK
9ZCM-27628RI Vss
Fig. 4 - CD40988 logic diagram.

287
CD40988 Types
Values at -55, +25, +125 Apply to D, F, K, H, pkgs.
CHARAC·
TERISTIC
Vo VIN VDD +25
Quiescellt - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
IlA
Current - 0,15 15 4 4 120 120 - 0.02 4
IDD Max. 0,20 20 20 20 600 600 - 0.04 20
Output L.ow
(Sink) 0.4 0.5 5 0.64 0.61 0.42 0.36 0.51 1 - LOAD CAPACITANCE (CLI-pF
92C5-28735
Current. 0.5 0.10 10 1.6 1.5 1.1 0.9 1.3 2.6 - Fig. 6 - Typical propagation delay time vs.
IOL Min. 1.5 0.15 15 4.2 4 2.8 2.4 3.4 6.8 - load capacitance, trigger into Q
mA out. (All values of CXand R X')
Output High 4.6 0.5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -
-1 . -
(Source I 2.5 0.5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current. 9.5 0.10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min. 13.5 0.15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Volt·
age: - 0.5 5 0.05 - 0 0.05
Low·Level. - 0.10 10 0.05 - 0 0.05
VOL Max. 0.15 15 0.05 - 0 0.05
V
Output Volt·
age: - 0.5 5 4.95 4.95 5 -
High·Level. - 0.10 10 9.95 9.95 10 -
VOH Min. - 0.15 15 14.95 14.95 15 -
Input Low 0.5.4.5 - 5 1.5 1.5
Voltage. 1.9 - 10 3 - - 3
VIL Max. 1.5.13.5 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage. 1.9 10 7 7
VIH Min. 1.5.13.5 - 15 11 11 - - Fig. 7 - Transition time vs. load capacitance
for RX = 5 kll·10000 knand
Input CX = 15pF·10000pF.
Current. - 0.18 18 ±0.1 ±0.1 ±1 ±1 .- ±10-5 ±0.1 IlA
liN Max.
Output
Leakage 0.18 0.18 18 ±0.4 ±0.4 ±12 ±12 - ±10-4 ±0.4 IlA
lOUT Max.
! lorl:--+---+-+'DT~--:...--l--,.;~h..
:
;;;
.
2
~'~2·t--+--~~6¥~~.6~~~~-
in •
~ 2
;1~!.t--+-~~-'~~~~~--~--1
:eI04!C'----.M'i---cA---J4-H'--
2
PULSE WIDTH IPWI-,...

10 103
PUL.SE WIDTH I PW) -,.,
I. 10 2: .. 68102 2: 4 r. '10' 2
EXTERNAL. CAPACITANCE (Cxl- pF
.. 68 104 2: .. 6 BId'
,2e$-28nS
Fig. 8 - Tvpical external resistance vs. Fig. 9 - Tvpical external capacitance vs. Fig. 10 - Tvpical minimum reset pulse width
pulse width. pulse width. vs. external capacitance.
288
CD40988 Types
TEST CIRCUITS
At TA ; 25°C; InputtrJf;20ns, CL;50pF, R L;200kQ
RX (km Cx (pFI VDD(V) Typ. Max. INPUTS
Trigger Propagation Delay Time 5 250 500 °

V55
5 to
+TR, -TR to 0, 0: >15 10 125 250 ns
10,000
tpHL' tpLH 15 100 200
Minimum Trigger Pulse Width, 5 70 140
5 to
>15 10 30 60 ns '00
tWH,tWL 10,000
15 20 40
Transition Time, 5 100 200
5 to
tTLH >15 10 50 100 Fig. 12 - Quiescent·device·current
10,000
15 40 80 test circuits.
5 to 15 to 5 100 200
10,000 10,000 10 50 100
15 40 80
ns
tTHL
5 to
10,000
O.Ol/lF
to
O.l/lF
5
10
15
150
75
65
300
150
130 INPUTQV/lO
OUTPUTS
I
O.l/lF 5 250 500 V,H
5 to
10,000
to
l/lF
10
15
150
80
300
160
'--
V~L
~
~
Reset Propagation Delay Time, 5 225 450
5 to
>15 10 125 250 ns NOTE: V's
TpHL, TpLH 10,000 TEST ANY COMBINATION
92CS-27441Al
15 75 150 OF INPUTS
5 100 200
15 10 40 80
15 30 60
ns
5 600 1200
Minimum Reset Pulse Width,
100 1000 10 300 600
twR
15 250 500
5 25 50
O.l/lF 10 15 30 /lS
15 10 20
Yeo 1NPUO'
Voo NOTE
Trigger Rise or Fall Time 5 to
tr(TR)' tf(TR)
- -
15
- 100 /lS ~
o ~--
MEASURE INPUTS
SEQUENTIALLY,
Vss TO 80TH Yoo ANO Vss
Pulse Width Match 5 5 10 CONNECT ALL UNUSED
INPUTS TO EITHER
Between Circuits in 10 10,000 10 7.5 15 % Yoo OR VSS'
~U':i 21402 Vss
Same Package 15 7.5 15
Input Capacitance, elN Any Input 5 7.5 pF Fig. 14 - Input leakage current test circuit.
TOQICU.... I_... po_dl~tton IP,

lor ... tlMn 10CJ'11, duty cydl;
r---j TT
',OO"'....... pa_for l~dl,ltrcyde;
P"(~)Pl00Wher' 'm'"oM·.t.Itpul• •idth rr 1'1

'T'"t"'I111"""'J*iOd -.J L--..J L
'.,. FOf 'I'll .. eoo $II, 'T" 1000 ,.. •. ex .. 0.01 pF.
VOo'"SV
---
Yoo ·SV----
p' .. (,:),03 /lW .. 600 IlW 1_ clonIC!
lin.on •• phl
-IOV---
-,!Sv--
24'-.024611022 4'\p' ....to,,2 "68~
ONE-SHOT PULSE WIDTH 1,..,-__ ,
Fig. 11 - Average power dissipation vs. one·shot pulse width.
289
CD4098B Types
APPLICATIONS
Voo
.J"""\.. +TR
Voo
INPUT PULSE ~ TI~RXI eX!
~TI~T2~ T2~RX~CX2
OUTPUT PULSE
-.-
ex!. 0.01 ~F
92CS-24256R2
Fig. 15 - Pulse delav.
'DO. TX Y1. RX
TX
RX '00 (Avg.l IT1 +T21 Voo
10kn 1mA 3.8j.1l
+ + 5V
I
0.05 rnA O.Ss
2.SmA 3.2~
10V
VDD~ +
O.SmA
+
0.5.
~~~'to.....J 5mA 3.,
RESET* ~
RESET
*10 ENSURE RESTART,APPL.'t RESET ~

1QMO
NOli.
+
1mA ot 15V
(NEGATIVE PUL$E) AFTER Vao Q2 ~ ------l -- All yaluesar.typieal.

SUPPLY VOLTAGE HAS REACHED ~ LTX L l eXr.n,.: O.OO()1. ",F to 0.1 j.lF. 92C"-28140
ITS VOOLEVEL. I DO _ --
Fig. 16 - Astable multivibrator with restart after reset capabilitv.
1 (1.905-2·108)

Dimensions in parentheses are in millimeters and represent a chip when it is part of the wafer. When th9
wafer ill separated into individual chips. the angle of
are derived from the basic inch dimensions as cleavage may vary with fflspect to the chip face for
indicated. Grid graduations are in mils (10- 3 inch). diffe/enr chlp:l. The actual dimensions at the isolated
chip. theretols, may differ slightly from the nominal
dimensions shown. The user should consider B tolerance
of -3 mils to +16 mils applicable to the nomina'
dimensions :lhown.
290
CD4099B Types
CMOS
a-Bit Addressable Latch
High-Voltage Types (20-Volt Ratin~)
WRITE DISABLE • 00
10 QI
DATA-----'-j
The RCA-CD4099B B-bit addressable latch Features: II 02
12 0:5
is a serial-input, parallel-output storage regis· - Serial data input - Active parallel output
13 04
14 05
ter that can perform a variety of functions. - Storage register capability - Master clear I~ 06
RESET , 07
Data are inputted to a particular bit in the - Can function as demultiplexer voo'I6
vss'8
latch when that bit is addressed (by means _ Standardized, symmetrical output characteristics
of inputs AO, Al, A2) and when WRITE _ 100% tested for quiescent current at 20 V
DISABLE is at a low level. When WRITE _ Maximum input current of 1 pA at 18 V
(full package-temperature range), 100 nA
DISABLE is high, data entry is inhibited;
at 18 V and 25°C
however, all B outputs can be continuously Functional Diagram
read independent of WRITE DISABLE and - Noise margin (full package-temperature
range) =1 Vat VDD =5 V,2 V at VDD
•
address inputs.
= 10 V, 2.5 V at VDD = 15 V
A master RESET input is available, which - 5-V, lON, and 15-V parametric ratings
Applications:
resets all bits to a logic "0" level when RESET - Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications - Multi-line decoders
and WRITE DISABLE are at a high level.
When RESET is at a high level, and WRITE for Description of 'B' Series CMOS Devices" - AID converters
DISABLE is at a low level, the latch acts as
a 1·of-8 demultiplexer; the bit that is ad- MAXIMUM RATI NGS, Absolute·Maximum Values:
DCSUPPLY·VOLTAGE RANGE,IV DD )
dressed has an active output which follows (Voltages referenced to VSS TerminaH -0.5 to +20 V
the data input, while all unaddressed bits INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to VDD +0.5 V
are held to a logic "0" level. DC INPUT CURRENT, ANY ONE INPUT ±lOmA
The CD4099B types are supplied in l6-lead
For TA = -40 to +60 0 C (PACKAGE TYPE E) . . . . . . . .. 500mW
hermetic ceramic dual-in-line packages (D For T A = +60 to +BSoC (PACKAGE TYPE E) . . Derate Linearly at 12 mW/oC to 200 mW
and F suffixes), 16-lead plastic dual-in-line ForTA = -55 to +100°C (PACKAGE TYPES 0, F, K) . . . . • . . • • • . . . , . . 500mW
For T A = +100 to +125°C (PACKAGE TYPES 0, F, K) , . , " Derate linearly at 12 mW/oC to 200 mW
packages (K suffix), and in chip form (H FOR TA = FULL PACKAGE· TEMPERATURE RANGE (All Package Types) 100mW
suffix). OPERATING·TEMPERATURE RANGE (TAl:
PACKAGE TYPES 0, F, K, H . • • . . , • . . • . , . • . . , • . . • • -55 to +125°C
PACKAGE TYPE E . . . . , . • • • • . • , . -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) -65 to +lS00C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.
QO
Q7 I. 16 Yeo
RESET
•
..""
Q&
DATA 3 Q5
WRITE 4 04
DISABLE
AD I. QS
Q. AI II QZ
A2 7 10 QI
IISS • TCP VIEW
9 QO
wacs-24428
TERMINAL ASSIGNMENT
AMBIENT TEMPERATURE CTA1-U-C
WRrTE
.* "'-_ _
A_ ~ AI
DISABLf~WD Q7 GATE-lO-SOURCE VOLTAGE 'VQS).I!5 v
2*
RESET~R
.....
8-
ADDftESS 10V
WD
"00'" Q
DATA---++I
*PROTECTED
AU. INPUTS ARE
BY ".COy"
COS/MOS PROTECTION 5 10 15
NETWORK DRArN-TO-SOURCE VOLtAGE (Vosl-V
Fig. 2 - Tvpical output low (sink)

Fig. 1 - Logic diagram of CD40998 and detail of 1 of B/atches.
291
CD40998 Types
RECOMMENDED OPERATING CONDITIONS at TA = 2ft' C (Unless otherwise specified)
MODE SELECTION
ADDRESSED UNADDRESSED
is always within the following ranges. WD R
LATCH LATCH
SEE VDD LIMITS
CHARACTERISTIC UNITS 0 0 Follows Data Holds Previous
FIG. 15- (V) MIN. MAX. State
Supply Voltage Range: 0 1 Follows Data Reset to "0"
(Active High 8·Channel Demulti·
(At T A = Full Package
Temperature Range)
3 18 V
I
plexer)
1 0 Holds Previous State
Minimum Pulse Width, tw 5 200 - 1 1 Reset to "0" 1
Reset to "0"
Data
0 10
15
100
80
- WD = WRITE DISABLE R=RESET:
5 400 - ns
Address
CD 10
15
200
125
-
- AD
5 150 - A'
Reset
0 10
15
75
50
-
-
A2·
WD
__+--J
Setup Time, ts 5 100 -

Data to WRITE DISA8LE
0 10
15
50
35
-
- ns Fig. 3 - Definition of WRITE DISABLE ON timtl.
Hoid Time, tH 5 150 -

Data to WRITE DISA8LE (2) 10 75 - ns
15 50 -
III Circled numbers refer to times indicated on master timing diagram. ~
e
I
Note: In addition to the above characteristics, a WRITE DISABLE ON time !the time that WRITE ~ 15
DISABLE is at a high level) must be observed during an address change for the total time that the ~
ffi12.5 GATE-TO-SOURCE VOLTAGE (Vc;SI-15V
external address lines AO, At. and A2 are settling to a stable level. to prevent a wrong cell from
being addressed (see Fig. 3). ~
B 10
,ov
• 10 to
DRAIN-TO-SOURCE VOLTAGE (Vos)-V

Itlct2'
"
~
START
CONVERSION
ORAIN-TO- SOURCE VOLTAGE IVosI-V
LS.
t-t-t-t--+-+ CD40"
+-+-+-+-+--+.... OUTPUTS
+--+-+-+-+-+--+.... TD DISPLAY
+--+-+-+-+-+-+-+--+.........
* CD4001
t ~~Cf:&I:f~~~~LD~2R
.N1~~r--------------- ________________ J
Fig. 6- - Typical output high (source)

Fig. 5 -. AID converter current characteristics.
292
CD40998 Types
DRAIN-TO-SOURCE VOLTAGE IVDSi-V
CONDITIONS Valuelst -55, +25, +125 Apply 10 D,F,K,H Package.
ISTIC UNITS
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Current, - 0,10 10 10 10 300 300 - 0.04 10
100 Max. IlA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOLMin. 4 2.8 2.4 34 6.8 -
1.5 0,15 15 4.2 Fig. 7 - Minimum output high (source)
4.6 D,S 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
Output High current characteristics.
(Source) 2.5 D,S 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
•
Current, 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
9.5 0,10
IOHMin.
13.5 0.15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.B -
Low-Level,
VOL Max.
- 0,10 10 0.05 - 0 0.05
- 0,15 15 0.05 - 0 0.05
V
High-Level, - 0,10 10 9.95 9.95 10 -
VOH Min. 14.95 15 -
- 0,15 15 14.95
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, -
VIL Max.
1,9' - 10 3 - 3
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - - Fig. 8 - Typical propagation delay time
Voltage, 1,9 - 10 7 7 - - (data to On! lIS. load capacitance.
VIH Min. 1.5,13.5 - 15 11 11 - -
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±0.1 IlA
Fig. 9 - Typical transition time lIS. I~d

capacitance.
'0' io---t---t-'
~~
CD4099SI:1 represent Ii chip when it ;s part of the waler. When the la} L
2469 469 2468 2 "69 ",.

DIMENSIONS AND PAD LAYOUT wafer ;s separated into individual cMps. the angle of 100 101 102 I 1 10" 10'
Cleavage may vary with respect to the chip lace for ADDRESS CYCLE TIM[-,..
different chips. The actusl dimensions of the isolated 92CS-27610
Dimemions in parentheses are in millimeters and chip, therefore, may differ slightly from the nominal
are derived from the basic inch dimensions as
dimensions shown. The user should consider 8 tolerance Fig. to - Typical dynamic power dissipation vs.
of -3 mils 10 +16 mils applicable to the nominal address cycle time.
indicatBd. Gridgraduationsarein mils (70-3 inch!. dimensions shown.
293
CD4099B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25" C, CL = 50pF,
Input t T, tf= 20ns, RL = 200 KG
INPUTS , - - ' - - - - ,
o
LIMITS Yss
CONDITIONS
ALL PACKAGE TYPES
CHARACTERISTIC SEE VDD UNITS
FIG.1S" (VI TYP. MAX.
Propagation Delay: tpLH· 5 200 400
tpHL CD 10 75 150
"so
Data to Output. 15 50 100
Fig. 11 - Ou/elCllnt device current
WRITE DISABLE 5 200 400 ttlStcircuit.
to Output, tpLH·
0 lO 80 160 ns
tpHL 15 60 120
5 175 350
Reset to Output, @) 10 80 160
tPHL 15 65 130
Address to Output. 5 225 450
tpLH· @ 10 100 200
tpHL 15 75 150 92CS-2744UU
Fig. 12 - Input YOltagS t1Jst cirCuit;

Transition Time, tTHL' 5 100 200
(Any Outputl tTLH 10 50 100 ns
15 40 80
Veo 1NPUOS
Yeo NOT£,
Minimum Pulse 5 100 200 "'----1':\.__ MEASURE INPUTS
~
Width,tw 0 10 50 100 ns o
Vss
. SEQUENTIALLY,
TO BOTH Voo AND Vss'
CONNECT ALL UNUSED
Data 15 40 80 INPUTS 10 EITHER
Voo OR Yss'
5 200 400
VSS .zt:5-27.02
Address ® 10 100 200 ns
Fig. 13 -Input current t1Jstcircuir.
15 65 125
AD AO DO 9 DO I
5 75 150 AI AI 01 10 002
Reset @ 10 40 75 ns
A>
A. A.
IrD
02 II DO.
QS 12 00.
15 25 50 OATA IN DATA 04 13 00.
CD4099 Q' 14 000
Minimum Setup 5 50 100 Q6 ., 007
I
Time,ts @ 10 25 50 ns R
07 008
Data to WRITE DISABLE 15 20 35 •

"00
Minimum Hold 5 75 150
Time,tH G) 10 40 75 ns
AD
AI
00
01
10
00'
0010
15 25 O. II DOli
Data to WRITE DISABLE 50 A'
IrD O. I. 0012
DATA DO 13 DO 13
Input Capacitance, CIN Any Input 5 7.5 pF * C04099 DO I. DOl.
..
116 e04069
Q6 0015
DT
" 0016
Circled numbers refer to times indicated on master timing diagram. R
2
92C5-27675
VDD
AO.At,A2 'w' 4'-_ _ __ Fig. 14 - 1 of 16 decoder/demultiplexer.

® 114 CD4016 trubuT
o I •
DATA
WRITE DISABLE
/
/
/
RESET
'-_____--'F2L
G>
/
/
/
IN
/
00 /
/
O, _ _ _ _ _..J
Fig. 16 - Multiple selection decoding - 4 x 4

Fig. 15 - Mast1Jr timing diagram. crosspoint switch.
294
CD4502B Types
Features:
CMOS Strobed Hex
• 2 TTL-load output drive capability
InverterIBuffer • 3-state outputs
THREE-STATE
OUTPUT
DISABLE
•
High-Voltage Types (20-Volt Rating) • Common output-disable control
INHIBIT
01
,
" 01
• Inhibit control 02 0 02
• '00% tested for quiescent current at 20 V I 0'

The RCA-CD4502B consists of six inverter/ 0'
buffers with 3-state outputs. A logic "'" on • 5-V, 10-V, and 15-V parametric ratings 04 10 04
the OUTPUT DISABLE input produces a • Maximum input current of 1 /lA at 18 V over
high-impedance state in all six outputs. This 05 13 O.
full package-temperature range; 100 nA at
feature permits common busing of the out- 18 V and 25°,,- 14 06
D6 15
puts, thus simplifying system design. A
• Meets all requirements of JEDEC Tentative VOO'16
Logic "'" on the I NHIBIT input switches vss'S
all six outputs to logic "0" if the OUTPUT Standard No. 13A, "Standard Specifications
DISABLE input is a logic "0". This device for Oescription of'S' Series CMOS Devices" 92C5 ~2921AI
is capable of driving two standard TTL loads, • Noise margin (full package-temperature FUNCTIONAL DIAGRAM
which is equivalent to six times the JEDEC rangel =
"B"-series IOL standard. 1 VatVOO=5 V
The CD4502B types are supplied in 16-lead 2 V at VOO = 10 V
hermetic dual-in-line ceramic packages (0
package (E suffix), 16-lead ceramic flat
package (K suffix), and in chip form (H
2.5 Vat VOO = 15 V
Applications:
• 30state hex inverter for interfacing IC's
I
suffix). Thisdevice is similar to the MC14502. with data buses
• COS/MaS to TTL hex buffer
MAXIMUM RATINGS,Absolute-Maximum Values:

DC SUPPLY-VOLTAGE RANGE, (VOO)
,Voltages referenced to VSS Terminal) -0.5 to +20 V
INPUT VOLTAGE RANGE_ ALL INPUTS -0.5 to VDD +0.5 V
DRAIN-TO-SOURCE VOLTAGE IVosl-V
DC INPUT CURRENT, ANY ONE INPUT ±IOmA 9aCS-291"
POWER DISSIPATION PER PACKAGE ,PO):

For T A = -40 to +60oC (PACKAGE TYPE E) _ . . . . . . . .. 500mW Fig.2 - Typical output low (sink)
For TA = +60 to +850 C ,PACKAGE TYPE E) _ Derate Linearly at 12 mW/oC to 200 mW current characteristics_
For TA = -55 to +100'C (PACKAGE TYPES 0, F, K) . . . . . . . .. 500mW
For T A = +100.10 +125'C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mW/oC to 200 mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE 'All Package Types) 100mW
OPERATING-TEMPERATURE RANGE 'TA):
PACKAGE TYPES 0, F, K, H -55 to +1 25°C
P-ACKA-GE TYPE E_ . -40 to +850 C
STORAGE TEMPERATURE RANGE 'Tstg ) -65 to +1 50°C
LEAD TEMPERATURE 'DURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm) from case for 10 s max.
r.N~RTE~!WF;ER N;I- - - - - -I TRUTH TABLE
~:::;'5± I:t~H"
DISABLE INHIBIT On an I
DRAIN-TO-SOURCE YOlTAGE '
0 0 0 1
0 0 1 0
0 Fig.3 - Minimum output low (sink)
1 X 0
1 X X Z
rt ~TVDD ~,-l
,.
___________ TO 50THI;.R
INHRlER/BUFFERS
~~J Logic 0 = Low
Z = High Impedance
X = Don't Care
DRAIN-TO-SOURCE VOLTAGE lVos}-V
I
Logic 1 = High
* ALL I"<PUTS A~E PROTECT~O
. Vss ~~TC~~~~OS PAOTtCTION 92CM-?9145
Fig. 1 - Logic diagram of 1 of 6 identical inverterlbuffers.
I.•, vDO
I.
0' 10
0' to DO
01 00
3-STATE
OUTPUT DISABLE
01
D.
"" O.
INHIBIT
O.
02 "
10 D'
Vss
TOP VIEW
• O.
Fig.4 - Typical output high (source)

92C5-25128
TERMINAL ASSIGNMENT
295
CD4502B Types
RECOMMENDED OPERATING CONDITIONS DRAIN-TO-SOURCE VOLTAGE (VosJ-V
For maximum reliability, nominal operating conditions should be selected so that oper·
ation is always within the following ranges:
LIMITS
Min. Max.
Supply·Voltage Range (For T A = Full Package-
LIMITS AT'INDICATED TEMPERATURES (OC)

CONDITIONS Values al-55, +25, +125 Apply 10 D, F, K, H Package.
ISTIC UNITS
+25 Fig.5 - Minimum output high (source)
Vo VIN VOO current characteristics.
(V) (V) (VI -55 -40 +85 +125 Min. TVp. Max.
Current, - 0,10 10 2 2 60 60 - 0,02 2
100 Max, IlA
- 0,15 15 4 4 120 120 - 0.02 4
- 0,20 20 20 20 600 600 - 0.04 20
Output Low 0,4 0,5 5 3,84 3,66 2,52 2,16 3,06 6 -
(Sink) Current 0.5 0,10 10 9,6 9 6,6 5,4 7,8 15.6 -
IOL Min,
1.5 0,15 15 25,2 24 16,8 14.4 20.4 40,8 -
Output High 4.6 0.5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
(Source) 2,5 0.5 5 -2 -1.8 -1.3 -",5 -1.6 -3.2 -
Current,
9.5 0,10 10 -1.6 -1.5 -u -0.9 _1.3 -2.6 -
IOH Min.
13.5 0.15 15 -4,2 -4 -2.8 -2.4 -3.4 -6.8 - ,
INPUT YOLTAGE (Vtl-V
Output Voltage: - 0,5 5 0,05 - 0 0.05
Low-Level.
- 0.10 10 0.05 - 0 0.05
VOL Max. Fig_6 - Typical voltage transfer
- 0.15 15 0,05 - 0 0,05 characteristics.
V
Output Voltage: - 0,5 5 4,95 4,95 5 -
High-Level. - 0.10 10 9.95 9,95 10 - ... wi AMalENT TEMPERATURE CTA I- Z"C
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0,5.4,5 - 5 1.5 - - 1.5
Voltage. 1.9 - 10 3 - - 3
VIL Max.
1.5.13,5 - 15 4 - - 4
V
Input High 4,5 - 5 3,5 3.5 - -
Voltage. 9 - 10 7 7 - -
VIH Min. 13.5 - 15 11 11 - -
0.18 18 ±0.1 ±0.1 ±1 ±1 - ±0.1 IlA
liN Max.
2 .... Z .... Z .... , .... 1 4 ••
3-State Output 100 10' 102 10" lei 10'
Leakage Current 0.18 0.18 18 ±0.4 ±0.4 ±12 ±12 - ±10-4 ±0.4 J1.A INPUT FREQUENCYCfZI-utl _eel-Z_I ••
lOUT Max,
Fig.7 - Typical power dilSipstion as a
LOAD CAPACITANCE (CL,-,F
92C$-29141
Fig.8 - Typical transition time as a function Fig.9 - Typical propagation-delay time as a
of load capacitance. function of load capacitance. Fig_ 10 - Power-dissipation test circuit.
296
CD45028 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input t r , tf =20 ns,
CL = 50 pF, RL = 200 KU Unless otherwise specified.
INPUTS
TEST CONDITIONS LIMITS o
CHARACTERISTIC V55
UNITS
VDD
(VI TYP MAX
5 135 270
Data or Inhibit Delay Times:
10 60 120
High to Low. tpHL
15 40 80
ns
5 190 380
Low to High, tpLH 10 90 180
Fig. 11 - Quiescent-dev;ce-current
15 65 130 test circuit.
Disable Delay Times: RL=1 Kn 5 60 120
Output High to High 10 40 80
Impedance, tPHZ 15 30 60
•
5 110 220
H igh·1 mpedance to Output 10 50 100
High, tPZH 15 40 80
See Fig.14 ns
5 125 250
Output Low to High
10 65 130
Impedance, tPLZ
15 55 110
9ZCS-Z7441Rl
5 125 250
High Impedance to Output Fig. 12 - Inpur-voltage test circuit.
10 55 110
Low, tPZL
15 40 80
Transition Times: 5 100 200
DD
Low to High, tTLH 10 50 100
Voo INP(JV
U S NOTE'
15 40 80
ns
5 60 120 ~ ~i~j~:;I~~~~~S
High to Low, tTHL 10 30 60 CONNECT All UNUSED
INPUTS TO EITHER
15 20 40 Voo OR VSS'
Vss
Input Capacitance, GIN Any Input 5 7.5 pF
Fig. 13 -Input leakage current test circuit.
D'
Q'
01
PULSE DISABLE
GENERATOR
QI INHIBIT
02
02
Vss
TEST CONDITIONS
TEST PIN 15 POINT A
'PHZ V55 V55
IPLl VOD VDO
IPZl VOD VDD
IPZH V55 Vss
Fig. 14 - Oisable delay times test circuit and waveforms.

are derived from the basic inch dimensions as
indicated. Grid graduations are in mils (10- 3 inch.)

represent I chip when it is part of the wl'er. When the
cleavage may vary with respect to the chip faca for
different chip,. The actua' dimensions of the isolated
chip, ther.fore. may dlffe, slightly from the nominal
dimensions shown. The user should consld., a tolerance Dimensions and Pad Layout for CD4502BH
of -3 mila to +16 mil. applicable to the nom;nal
dimension, shown.
297
CD4503B Types
CMOS Hex Buffer

Features:
High·Voltage Types (20-Volt Rating) • 1 TTL-Ioad output drive capability
DISAILE I
01 '01
3·State Non·lnverting Type • 2 output·dlsable controls
• 3-state outputs 02 S 02
• Pin compatible with industry types MM80C97,
MC14S03, and 340097 O. 7",
• S·Y, 10·Y, and 15·Y parametric ratings 04 '0 '0'

The RCA-C04503B is a hex noninverting • Maximum input current of 1 fLA at 18 Y over full
os
package-temperature range; 100 nA at 18 Y and 2S·C
..
12
buffer with 3-state outputs having high sink-
and source-current capability. Two disable • Meets all requirements of JEDEC
Tentative Standard No. 13A, "Standard
06 '4 "
controls are provided, one of which controls
DIS\8LE '5
four buffers and the other controls the Specifications for Description of 'B'
IEi-Voo a-vss
remaining two buffers. The C04503B types Series CMOS Devices."
are supplied in 16-lead hermetic dual-in- FUNCTIONAL DIAGRAM
line ceramic packages (0 and F suffixes), Applications:
16-lead dual-in-Ilne plastic packages (E suf- • 3-state hex buffer for Interfacing IC's
fix), ~6-lead ceramic flat packages (K suffix). with data buses
and 10, chip form (H suffix). • CMOS to TTL hex buffer
VDD
214,8,10,12,14) ..-"---l-l J
... QN DN
TRUTH TABLE
DISAIB) QN
~7'9'1I'13) 0
I
0
0
0
I
I
DIsABLE TO OTHER
BUFFERS
I
vDD
iVss
X I
X. DONIT CARE
HIGH Z
Fig. 2-Typlcal n-channal output low (sink)
a
NETWORK
vss
Fig. 1-Logic diagram of 1 to 6 identical buffers.
OR"N-T(~SO'"RC' VOLTAGE (Vos)-V

92CS-321:S~
MAXIMUM RATINGS, Absolute-Maximum Values: -FIg. 3-Minimum n·channel output low (sink)
DC SUPPLY·VOLTAGE RANGE, (VDD) current characteristics.
(Voltages referenced to VSS Terminal) ....... , , ........... ' , .. , ... , . ' ... , ...... -0.5 to + 20 V _
INPUT VOLTAGE RANGE, ALLIN PUTS ................. , , . , , ... , ......... -0.5 to VDD + 0.5 V
DC INPUT C.uRRENT, ANY ONE INPUT ................ , ..... , . , , ....... , .... , ...... ± 10 mA
POWER DISSIPATION PER PACKAGE (PO): DIS A 1& Voo
ForTA = -40to +60'C(PACKAGETYPEE) ....... " ............................... 500mW 01 IS DIS B
ForTA = +6010 + 85'C (PACKAGE TYPE E) ............. Derate Linearly al12 mW/'Clo 200mW 01 I. D&
For T A =-5510 +100' C (PACKAGE TYPES D, F, K) ......................................... SOD mW O' 13 Q&
ForTA = +100 to +125'C (PACKAGE TYPES 0, F, K) .......... Derate Linearly at 12 mwrc 10 200 mW Q2 OS
DS " QS
For TA = FULL PACKAGE·TERMPERATURE RANGE (All Package Types) ...... , , .. , .... 100 mW QO 10 O.
OPERATING·TEMPERATURE RANGE (T A): Vss

TOP VI W
• Q•
PACKAGETYPESD.F,K,H ........................................................ -55to+125'C '2el-SlItI

PACKAGE TYPE E .................................................................. -40 to +85' C
STORAGE TEMPERATURE RANGE (TSlg)' ........ '. , ........ , , ... , .. , ... , ' , . , , , -6510 + 150'C
LEAD TEMPERATURE (DURING SOLDERING): TERMINAL ASSIGNMENT
At dislance 1116 ± 1132 inch (1.59 ± 0.79mm) from case for 10 s max, .. , .. ',' , .... , ...... + 265'C
298
CD4503B Types
DRAIN-TO - SOURCE VOLTAGE (Vos)-"
STATIC ELECTRICAL CHARACTERISTICS -9 -8 -7 -6 -5 -4 -3 -2
LIMITS AT INDICATED TEMPERATURES ('C) U

CHARAC· CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H Packages N
TERISTIC Values at -40, + 25, + 85 Apply to E Package I
T
Vo VIN VDD +25 S
(V) (V) (V) -55 -40 +85 + 125 Min. Typ. Max.
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2
flA
Current, - 0,15 15 4 4 120 120 - 0.02 4
IDD Max. - 0,20 20 20 20 600 600 - 0.04 20
AMBIENT TEMPERATURE (T,,'-25-C
Output
low 0.4 0 5 2.6 2.5 1.4 1.3 2.1 2.3 -
Fig. 4- Typical p-channel output high (source)
(Sink) 0.5 0 10 6.5 6.4 3.9 3.8 5.5 6.2 - current characteristics.
Current 1.5 0 15 19.2 18.9 11.4 11.2 16.1 23 -
IOl Min.
DRAIN - TO- SOURCE VOL. TAGE {Vos 1- II
Output
II
_ • 4 4 4 4 4 1
-
~
4.6 5 5 -1.2 -1.16 -0.7 -0.7 H.02 -1.9 mA

High
(Source)
2.5 5 5 -5.8 -5.7 -3.4 -3 -4.8 -6.1 -
Current,
9.5 10 10 -3.1 3 -1.9 -1.8 -2.6 -3.7 -
IOH Min.
13.5 15 15 -8.2 -8 -4.9 -4.8 -6.8 -14.1 -
_\0'1
Output
Voltage: - 0,5 5 0.05 - 0 0.05
low·
level, - 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output
Voltage: - 0,5 5 4.95 4.95 5 - AMBIENT TEMPERATURE (T A )- 25-C
92C$- ~2737
High·
Fig. 5-Minimum p·channel output high (source)
level, - 0,10 10 9.95 9.95 10 - current characteristics.
VOH Min. - 0,15 15 14.95 14.95 15 -
Input low 0.5,4.5 5 1.5 - - 1.5 AMBIENT TEMPERATURE (TAl- 2~·C
Voltage, 1,9 - 10 3 - - 3 r 175 _ tt:~:

Vil Max. 1.5,13.5 - 15 4 - - 4 -::.
~150
Input
V
High 0.5,4.5 - 5 3.5 3.5 - - !"125
Voltage, 1,9 - 10 7 7 - - w
~ 10
VIH Min. 1.5,13.5 - 15 11 11 - - ~ 75
Input z
Current - 0,18 18 ±O.1 ±0.1 ±1 ±1 - ± 10-5 ±0.1 ~ 50
liN Max.
~ l5
3-State flA VOO"15\1
Output 10 20 30 40 50 60 70 eo 90 100
LOAD CAPACITANCE (el)- pF
leakage 0,18 0,18 18 ±0.4 ±0.4 ±12 ±12 - ± 10.4 ±0.4
Current,
lunction 01 load capacitance.
lOUT
Max.
eo AMBIENT TEMPERATURE IT AI-25*C
70
f 60
~
~ 50
RECOMMENDED OPERATING CONDITIONS -= 40

~
For maximum reliability, nominal operating conditions should be selected so Ow
z
o
~20
LIMITS :=
CHARACTERISTIC UNITS 10
Min. Max.
10 20 30 40 50 60 70 50 90 100
Supply-Voltage Range (For LOAD CAPACITANCE (CL1-pF
TA = Full Package·
3 18 V Fig. 7- Typical transition time as a function
Temperature Range) 01 load capacitance.
299
CD45038 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A 2SDC; Input 'r, 'I = 2Ons,
CL = 50 pF, RL = 200 kQ unless otherwise specified.
INPUTS
VDD LIMITS o
CHARACTERISTIC UNITS Vss
(V) Typ. Max.
Low-to-High, tpLH 10 35 70 ns
15 25 50
Hlgh-to-Low, tpHL 5 55 110
10 25 50 ns
15 17 35
Transition Time: 5 50 90 Vss
92CS~!740IAI
Low-to-High, tTLH 10 30 45 ns
15 25 35 Fig. 10-Qulescent-devlce-current test circuit.
High-to-Low, tTHL 5 35 70
10 20 40 ns
15 13 25
3-State Propagation Delay Time: RL = 1 kO 5 70 140
tpHZ, tpZH 10 30 60 ns
15 25 50 INPUTQVDO
OUTPUTS
tpZL' tpLZ 5 90 180 V,H

10 40 80 ns '-- ~
15 35 70 v~ ~
·
:~B!~NT TEMPERATURE ITA)·2~·C
, _ -- I- V
Voo
VSS
NOTE:
TESTIllfYC_'NATlCIII
OF INPUTS
I,,~·V 500l&F
·,
9ZCS-2744IRI
~IOK8
.'.
.p
·11
~.,o. ~.
- .!i/ Fig. 11-lnput-voltage test circuit.
."..
16 •
z V· V I
:~~
15
CL-15pF----
~ V V ~4-"""-I 4
.· CUSOpF--
2
:5 1008
1(/ V 6
~ 10
~
V i'I'I"'jO''!t 12
.
r- ---- NO~E'
IOi!V , , , II I I_I 14 MEASURE INPUTS
• • 010 .oo102 6 8103 2 • 6 8 10 • 8 SEQUENTIALLY,
FREQUENCY (f I-KHz W2CS.3!740 TO 80TH Voo AND IIss'
CONNECT ALL UNUSED
Fig. 8- Typical power dissipation as a function 92CS-:S2741
L_,-_....l INPUTS TO EITHER
of frequency. Fig. 9-Dynamic power dissipation test circuit. Voo DRVss'
V55
92C5-2741)2
Fig. 12-lnput current test circuit.
81
D,mensIons In pdrentheses are In millimeters and

are dertved from the basIc Inch dimenSIons in-as
dIcated. Grid 9rddudrlons .Ire In mils (10-- 3 mch}:
The photographs and dimensions of .ach CMOS chip

represent a chip when it is part of the waf.r. When the
wafar is separated Into Individual chips. the 8ng/e of
e/ea'lage may vary with respect to the chip f.ee for
chip. therefore. may differ slightly from the nomln.'
dimensions shown. The user should consider 8 tolerance
of -3 mils to +16 mils applicable to the nomln.'
dimensions shown.
300
CD4508B Types
Features:
CMOS Dual 4-Bit • Two independent 4·bit latches
OUWUT
Latch • Individual master reset for each 4-bit latch
• 3'state outputs with high·impedance state for bus
DISABLE
DO. OOA
DIA OIA
4- BIT 3-STATE
line applications D.A
LATCH OUTPUTS
O'A
High·Voltage Types (20·Volt Rating) • Medium·speed operation: tpHL = tpLH = 70 ns D'A O'A
STROBE
(typ.) at VDD = 10 V and CL = 50 pF RESET
OUTPUT
The RCA·CD4508B dual 4·bit latch contains • 100% tested for quiescent current at 20 V DlSAIll.
two identical 4·bit latches with separate 00. OD.
STROBE. RESET. and OUTPUT DISABLE • 5·V, 1a-V, and 15·V parametric ratings DI. 01.
D•• 0'.
controls: With the STROBE line in the high • Standardized, symmetrical output characteristics
D•• 0 ••
state. the data on the "D" inputs appear at • Maximum input current of 1 /lA at 18 V STROBE
the corresponding "0" outputs provided the over full package·temperature range; RESET
DISABLE line is in the low state. Changing 100 nA at 18 V and 25 0 C
tile STROBE line to the low state locks the • Noise margin (full package· temperature
data into the latch. A high on the reset line FUNCTIONAL DIAGRAM
range) =
forces the outputs to a low level regardless of 1 VatVDD = 5 V
•
the state of the STROBE input. The outputs
are forced to the high·impedance state for 2VatVDD=10V (
bus line applications by a high level on the 2.5 V at VDD = 15 V
DISABLE input. • Meets all requirements of JEDEC Tenta·
tive Standard No.13A, "Standard Speci·
The CD4508B types are supplied in the 24- fications for Description of'S' Series
lead dual-in-line ceramic packages (D and F CMOS Devices"
suffixes). 24-lead dual-in-line plastic pack-
ages (E suffix). 24-lead ceramic flat pack-
ages (K suffix). and in chip form (H suffix). Applications:
• Buffer storage
The CD4508S is similar to industry type • Holding registers
MC14508.
• Data storage and multiplexing
DC SUPPLY·VOLTAGE RANGE. (V DO)
(Voltages referenced to VSS Terminal! -0.5 to +20 V Fig.2 - Typical output low (sink) current
INPUT VOLTAGE RANGE. ALL INPUTS -0.5 to VDD +0.5 V characteristics.
For T A = -40 to +60o C (PACKAGE TYPE E) . . . . • . • .. 500mW
For T A = +60 to +85 0 C (PACKAGE TYPE E) Derate Linearlv at 12 mW/oC to 200 mW
For T A = -55 to +100·C (PACKAGE TYPES D. F. K) . . . . • . . .. 500mW
For T A = +100 to +125·C (PACKAGE TYPES D. F. K) Derate Linearly at 12 mW/oC to 200 mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE IAII Package Types) 100mW
OPERATlNG·TEMPERATURE RANGE ITA):
PACKAGE TYPES D. F. K. H -55 to +1250 C
PACKAGE TYPE E . -40 to +850 C
STORAGE TEMPERATURE RANGE (T"g) -65 to +1500 C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case. for 105 max.
RECOMMENDED OPERATING CONDITIONS at TA = 25 0 C, Except as Noted. For maximum

reliability, nominal operating' conditions should be selected so that operation is always within the I I
ORAIN-TO-SOURCE VOLTAGE !VDS)-V
following ranges:
Fig.3 - Minimum output low (sink) current
VDD LIMITS characteristics.
(V) Min. Max.
Supply· Voltage Range (For T A = Full Package·
3 18 V ORAIN-TO-SOURCE VOLTAGE !VoSI-V
TelTlperature Range)
5 200 -
Reset Pulse Width, tWIRl 10 140 -
15 100 -
5 140 -
Strobe Pulse Width. tWIst) 10 80 -
15 70 -
ns
5 50 -
Setup Time, tsu 10 30 -
15 20 -
5 0 -
Hold Time, tH 10 0 -
15 0 - Fig.4 - Typical output high (source) current
characteristics.
301
CD4508B Types
DRAIN-lO-SOURCE VOLTAGE (Vosl-v
STATIC ELECTRICAL CHARACTERISTICS -15 -10 -5
AMBIENT TEMPERATURE (TA)'25°C
Values ai-55, +25, +125 Apply to D, F, K, H Packages ftt1H-tt+ttGttATtlE-H_TtfWuJtitjot~tltt!1r_ 5 v
CHARACTER·
CONDITIONS
Value. at -40, +25, +85 Apply to E Package , 'i iN W
UNITS
ISTIC
Vo VIN VDD
-55 -40 +85 +125 Min.
+25
Typ. Max.
: Hi! J ,J;
(V)
(V) (V) ti ~~ ~ r
- 0,5 5 5 5 150 150 - 0.04 5

:~
Quiescent Device
Current, - 0,10 10 10 10 300 300 - 0.04 10
•• 4, :ei
IDD Max.
- 0,15 15 20 20 600 600 - 0.04 20
IlA :: ~l/\,:i:~f:
,. _ -+--15
- 0,20 20 100 100 3000 3000 - 0.08 100 II f::~
Output Low
(Sink) Current
0.4
0.5
0,5
0,10
5
10
0.64
1.6
0.61
1.5
0.42
1.1
0.36
0.9
0.51
1.3 2.6
1 -
-
-!i llilllJ Ji 11.
IOLMin.
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 - Fig. 4 - Minimum output high (source) current
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
Output High characteristics.
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 0,10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
9.5 10
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low·Level.
VOL Max.
- 0,10 10 0.05 - 0 0.05
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
VIL Max.
1.5,13.5 - 15 4 - - 4
Input High 0.5,4.5 - 5 3.5 3.5 - -
V ,
LOAD CAPACITANCE (CL)-pF
Voltage, 1,9 - 10 7 7 - -
VIH Min. Fig. 5 - Typical transition time as a function of
1.5,13.5 - 15 11 11 - - load capacitance.
Input Current
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 IlA
liN Max.
3·State Output ~175f'.:';;"+=J..;.:.~=.j..:.:.'-+=-l-'· c:.j..:..:.:-'-l~~=-'-l

Leakage Current 0,18 0,18 ±0.4 ±0.4 ±12 ±12 - ±10-4 ±O.4
,
18 IlA
~150f'.:';;"+=J..;.:.~=.j..:.:.,-+c:.c:.i
lOUT Max.
iI2S"'.':':::c:.:f-'-'-+=+'cc~'""
j..:::.:c...:.:==+-_-
__-__-_-_ __-__-,TVPICAL LArcH - ""1 ~ 100"':':':'+~=+-"-+
Yoo I
§ ...
d l ~ 75r·~~~.c:t-=~~~~~~~~
RESET·A
* 'b~I7,9,'"
J ~ OUTPUT
* 9:
risr
4{6,e,IO}
Dn-A
Fig. 6- Typical propagation delay time as a func-

¥_ YSS: tion of load capacitance (strobe to data out).
,,:~~'~;A;'~-~-------J dO ~'AMBiEN-T TEMPERATU"RE
, ! 'r .\~A:2~2n~OC 1/
'ALL'N~SS ..
" , 1/
RL 'fo,o,~n 1 1 .'1
RESET DISABLE STROBE DINPUT QOUTPUT 210:, a~'''~~~ jL- -
0 0 1 1 1 PROTECTED BY
COS/MOS PROTECTION
~
, ~';L
0" ,0.
7~
0 0 1 0 0
NETWORK
z
f-Jo-:->/
10: 1-...
0 0 0 X LATCHED
92CM-2929~
~,!6 "' ,v
~.!. 4 ~~/ V
~~2
.,
1 0 X X 0 0- ,
1/ CL ~50 pF _ _
ffi IOe CL' 15 pF
X 1 X X Z
'
1 = HIGH LEVEL
0= LOW LEVEL
X = DON'T CARE
Z = HIGH IMPEDANCE
~
'0
'/
10 2.
, S8101 2 4 6Bl(f 2. 4 6610~ 2.
INPUT FREQUENCY (fINJ- kHz
1m
4661042.
+t 4 6e10~
92CS- 29295
Fig. 7 - Logic diagram (A-Section), 1 of 4 identical/atches with
common output disable, reset and strobe.
I Fig. 8 - Typical power dissipation \9$ a function
of frequency.
302
CD4508B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25 0 C; Input t r , tf = 20 ns, CL = 50 pF, Voo
RL = 200 kn, unless otherwise specified.
TEST LIMITS
CONDITIONS VDD Typ. Max.
5 100 200
Transition Time, tTHL, tTLH 10 50 100
15 40 80
5 100 200
Minimum Reset Pulse Width, tWIRl 10 70 140
15 50 100
5 70 140
Minimum Strobe Pulse Width, tWIst) 10 40 80 9ZCS-292:96
15 35 70
5 25 50 Fig.9 - Power dissipation test circuit.
Minimum Setup Time, tsu 10 15 30
15 10 20
5 0 0
Minimum Hold Time, tH 10 0 0
15 0 0
5 130 260 VDO
Propagation Delay Times: tpH L, tPLH
Strobe to Data Out 10
15
5
70
50
105
140
100
210
ns
.
VDO
Vss
INPUTS
Data I n to Data Out 10 60 120

15 45 90
5 90 180
Reset to Data Out 10 50 100
15 40 80
Fig. to - Quiescent device
5 90 180 current test circuit.
3·State Propagation Delay Times:
10 50 100
Output High to High Impedance,tpHZ
15 35 70
5 90 180
High Impedance to Output High, tpZH 10 50 100
15 35 70
5 90 180
Output Low to High Impedance, tpLZ 10 50 100
15 35 70 'NPUTOVDO
OUTPUTS
5 90 180 V'H
High Impedance to Output Low, tpZL 10 50 100 ""'-- ~
15 35 70 V~L J
Input Capacitance, CIN Any Input - 5 7.5 pF NOTE:
Vss ~srN~r:,~~OMBINATION
tWist) f..-- ~2.CS-Z7"'4IRI
STROBE
INPUT Fig. 11 - Input voltage test circuit.
·SU --j
I 'H--1 f--
~~PUT ---{ r-----+--_...J/
---i L.-
V~NPU(J' ::;::.::~
t W(R I
RESET ----+---------ir-------------~
1 I ~.- - - -
'.
OUTPUT I I
D'SABLE ~'----i-------_:_---------I:--...Jlf__---- Vss TO BOTH Voo AND Vss·

CONNECT ALL UNUSED
INPUTS TO EITHER
• PLH ---+i '-- 'PHL ---+I l+- • PHL --: L.- I Voo OR VSS·
I--J Vss
1'1)--------1.. 1 I
Do OUTPUT _ _ _ _-11 I I ),_ _ _ _ _ _../
tTLHI f.- tTHL~ 1- Fig. 73 -Input current tesrcircuit.

92.CM-Z9297
Fig. 12 - Test waveforms.
303
CD4508B Types
OUTPUT DISABLE
Q OUTPUT
TEST ANY
OUTPUT I Ul
Q OUTPUT
~o
leaPF
CHAR.
tiW~
tpHZ VIJo V.S
tpLZ Vss VDD
t PZL Vss VDD
f PZH VDD Vss
Fig. 14 - Output disable test circuit and waveforms.
c-'-----'_~L~CD4S0BB
CLOCK>
RESET »====;::::==+===::;:===+==::::
VCD4015B
S ERIAL OAT A >--I.....L,.~~~~ I

-.J
STROBE >--~--+-+--j--jl-~-+-+-++ __-+
DISABLE >----t~L,..--,---.__._
FUNC.TION
SELECT
Fig. 15 - Bus register.

92CM-29301
Fig. 16 - Dual multiplexed bus register with

function select.
91-99
(2.311-2.515)
RESET A I· 2. Voo
STROBE A 2 23 038
OUTPUT
DISABLE A 22 D38
DOA 21 028
ODA 20 D28
DI A I. 018
OIA 18 018
D2A 17 008
020 IS DOB
D3A 15 OUTPUT
10 ISABLES
0" I' STROBE 8
93-101 92CM-29302 Vss 12 I> [SETB
2.362-2.565
TOP VIEW
wafer is separated into individual chips, the angle of TERMINAL ASSIGNMENT
DmJef1S/ons in parentheses are in millimeters and cleavage may v..ary with respect to the chip face for
are derived from the baSIC inch dimensions as in- different chips. The actual dimensions of the isolated
dicated. Grid graduations are in mils (1(J3 inch). chip, therefore, may differ slightly from the nominal
dimensions shown. Ths ussr should considers tolerance
of -3 mils to +16 mils applicable to ths nominal
dimensions shown.
Dimensions and pad layout for CD450BB.
304
CMOS Presettable
Up/Down Counters • Features:
PRESET
High-Voltage Types (20-Volt Rating) • Medium-speed operation -- ENABLE
f Cl = 8 MHz typo at 10 V 0'

CD451 OB - - - BCD Type .2 0'
• Synchronous internal carry propagation P3
I. 0'
CD4516B - - - Binary Type 0'
• Reset and Preset capability VOO'IS

CLOCK
" Vss·a
The RCA-CD4510B Presettable BCD Up!Down UP/DOWN
CARRY IN ~
Counter and the CD4516 Presettable Binary • 5-V, 10-V, and 15-V parametric ratings
RESET
Up/Down Counter consist of four synchron- • Standardized symmetrical output characteristics
ously clocked D-type flip-flops (with a gating
• Maximum input current of 1 /J.A at 111 V CD4510B, CD4516B
structure to provide T-type flip-flop capa- over full package temperature range; FUNCTIONAL DIAGRAM
bility) connected as counters. These counters 100 nA at 18 V and 25°C 92CS-24824
can be cleared by a high level on the RESET
line, and can be preset to any binary number • Noise margin (full package-temperature
range): 1 Vat VDD = 5 V Applications:
I
present on the jam inputs by a high level on
the PRESET ENABLE line. The CD4510B 2 V at VDD = 10 V • Up/Down difference counting
will count out of non-BCD counter states in a 2.5 Vat VDD = 15 V • Multistage synchronous counting
maximum of two clock pulses in the up • Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications • Multistage ripple counting
mode, and a maximum of four clock pulses
for Description of 'B' Series CMOS Devices" • Synchronous frequency dividers
in the down mode.
If the CARRY-IN input is held low, the
counter advances up or down on each
positive-going clock transition. Synchronous
cascading is accomplished by connecting all OPERATING CONDITIONS AT TA = 25°C, Unless Otherwise Specified
clock inputs in parallel and connecting the
CARRY-OUT of a less significant stage to For maximum reliability, nominal operating conditions should be selected so that operation
the CARRY-IN of a more significant stage. is always within the following ranges.
The CD451 OB and CD4516B can be cascaded Characteristic VDD Min. Max. Units
in the ripple mode by connecting the CAR RY-
OUT to the clock of the next stage .. 11 the Supply Voltage Range (At T A = Full Package-Temperature Range) 3 18 V
UP/DOWN input changes during a terminal 5 150 -
count, the CARRY-OUT must be gated with Clock Pulse Width, tw 10 75 - ns
the clock, and the UP/DOWN inpu~ must 15 60 -
change while the clock is high. This method
5 - 2
provides a clean clock signal to the subse-
quent counting stage. (See Fig. 15).
15 - 5.5
These devices are similar to types MC14510
5 150 -
and MC14516. Preset Enable or Reset Removal Time- 10 80 - ns
The CD4510B and CD4516B Series types 15 60 -
are supplied in 16-lead hermetic dual-in-
5 - 15
line ceramic packages (D and F suffixes), Clock Rise and Fall Time, trCl, tfCl • 10 - 5 f,Ls
16-lead dual-in-line plastic packages (E suf- 15 - 5
fix), 16-lead ceramic flat packages (K suffix), 5 130 -
and in chip form (H suffix). Carry-In Setup Time, ts 10 60 - ns
15 45- -
5 360 -
PRESET
ENABLE I. I. Voo Up-Down Setup Time, ts 10 160 - ns
O.
P'
2
3
I. CLOCK
03
15 110 -
PI "13 P3
CARRY IN 12 5 220 -
.
P2
01
CARRY OUT 10
02
UP/DOWN
Preset Enable or Reset Pulse Width, tw 10 100 - ns
Vss
(TOP VIEW)
9 RESET
15 75 -
CD4510B, CD4516B -Time required after the falling edge of the reset or preset enable inputs before the rising edge
TERMINAL ASSIGNMENT of the clock will trigger the counter (similar to setup time).
"'If more than one unit is cascaded in the parallel clocked application, trCl should be made less
than or equal to the sum of the fixed propagation delay at 15 pF and the transition time ofthe
carry output driving stage for the estimated capacitive load.
305
MAXIMUM RATINGS, Absolute-Maximum Values; AMBIENT TEMPERATURE (T41.25"C
GATE-TO-SOURCE VOLTAGE (VG5'015 V
For TA = -40 to +SO°C (PACKAGE TYPE E) ................................................. 500 mW
For T A =+60 to +85°C (PACKAGE TYPE E) ••• ••••• ••• ••••• ••• Derate Linearly at 12 mW/oC to 200 mW
ForTA = -55 to +100°C (PACKAGE TYPES D, F, K) .......................................... 500 mW 10V
For TA =+100 to +125°C (PACKAGE TYPES D, F, K) .•••.•..•• Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR: ~ 10
ForTA =FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW
il ,
PACKAGE TYPES D, F. K, H ............ , ........................................... -55 to +125°C
5 10 15
PACKAGE TYPE E .................................................................. -40 to +85°C DRAIN-TO-SOURCE VOLtAGE (IIOS)-II
STORAGE TEMPERATURE RANGE (Tstg) ••• ! ......................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING)l. Fig.l - Typical output low (sin/<) current
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.••..•.••.•••••.....•.•... +265°C characteristics.
PI* QI P2* 02 P'5* Q3 P4* Q.4

• 6 12 II 13 14 3 2
PRESET-I
ENABLEv-crr,-~
~g7~----------'
VDD
."'-.~
I
Q4 Q4
OOAIIN-'·O·"OO'''' VOLTAGE (Vos)-V
Fig.2 - Minimum output low (sink) current

characteristics.
PROTECTED BY
COSIMOS
""'s
.;) DRAIN-TO-SOURCE VOLTAGE (IIOS)-V
PROTECTION NETWORK. -15 -10 -5
AMBIENT TEMPERATURE CTA).25·C
CARRY IN" 5 GATE-TO-SOURCE VOLTAGE (IIGSJ~-5V
-IOV
-15V
Fig.3 - Logic Diagram for CD4510B.

Fig.4 - Typical output high (source) current
characteristics.
DRAIN-lO-SOURCE VOLTAGE (VOSI-V
-l~ -10 -5 AM"'NT TEMPERATURE {T
AMBIENT TEMPERATURE ITAlo2S"C
GATE -TO-SOURCE VOL.TAGE lvt;sJo -5 v
-10'.1
-:: ~ :F.~
::iO~.
.:.,:
i: iii .,::
'1::, ,.•
"P'~ iii:.'
"'-·15 V
.'.:
,I,,:iiiiiliiii iH ',.,
:I
1111111 LOAD CAPACITANCE (ell-pF
Fig.5 - Minimum output high (source) current Fig.6 - Typical transition time vs. load
characteristics. capacitance.
306

liMITS AT INDICATED TEMPERATURES laC}
CHARACTER· Value. at -40, +25, +85 Apply to E Package
ISTIC UNITS
+25
Vo VIN VDD ::
IV} IV} IV} -55 -40 +85 +125 Min. Typ. Max. :: ::
Quiescen t Device - 0,5 5 5 5 150 150 - 0.04 5 :

Current, - 0,10 10 10 10 300 300 - 0.04 10 : : : :: :
100 Max. J1.A : : :: : : : : : :
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
10 15 20
Output low 0.4 D,S 5 0.64 0.61 0.42 0.36 0.51 1 - SUPPLY VOLTS-VOO
ISink} Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - Fig.8 - Typical maximum clock input frequency
IOlMin. vs. supply voltage.
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
4.6 D,S 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
Output High
ISource} 2.5 D,S 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current,
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
II
10, AMBIENT TEMPERATURE (TAl- 2S"C
IOH Min. 6 'r,tt· 2On5
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - ~
-CL;50pF
- 5 - 0 0.05
i 4
---CL"15pF II I ,I
Output Voltage:
low·level,
D,S 0.05 g 2
.. I II J 1/
- 0,10 10 0.05 - 0 0.05 w 10'
- =~~.~r.
VOL Max. 'I I '
~.p
~
,.
- 0,15 15 0.05 - 0 0.05
V
6
4 'rl-- ~~ .p
Output Voltage: - D,S 5 4.95 4.95 5 - '--~ ~
Q 2 .P:
High·Level, - 0,10 10 9.95 9.95 10 - ~ ~
,
== tt,;;
10'
VOH Min.
- 0,15 15 14.95 14.95 15 - 2i 6
- -
"'" 4 •
Input Low
Voltage,
0.5,4.5 - 5 1.5 1.5
~. 2
r1X
Vil Max.
1,9 - 10 3 - - 3 10 J.rX
1.5,13.5 - 15 4 - - 4 0,1
I 2 468 10 2 46~cf-2 468 103 2 46~04
V CLOCK INPUT FREQUENCY ifCLi- kHz
Input High 0.5,4.5 - 5 3.5 3.5 - - Fig.9 - Typical dynamic power dissipation
92CS-21001
Voltage, 1,9 - 10 7 7 - - vs. frequency.

VIH Min. 1.5,13.5 - 15 11 - -
11
Input Current
- 0,18 18 ±0.1 ±O.'j ±1 ±1 - ±10- 5 ±0.1 J1.A
liN Max.
PI* QI pz+ Q2 P3* 03 P4* 04 VDD

, 2 INPUTS
• 6 12 II 13 14
o
vss
PRESET* I
ENABLE v--1r?"""L.-/
Vss
'Ci'RiW"OuT 0---------,
7
Fig. 11 - Quiescent-device-cur-
.,,~~
rent test circuit.
~~g;~g~ED BY Vss
PROTECTION NETWORK.
CARRY IN- 5
INPUOS
Von
Voo NOTE:
~ ~:~~~:;I!~~~~S
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS'
vss
Fig. 12 - Input-current
Fig. to - Logic Diagram for CD45t6B. test circuit.
307
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, CL = 50 pF;
Input t r , tf = 20 ns, RL = 200 kQ
Condit- Limits INOPUTQVDOOUTPUTS

ions
Characteristic All Packages ., Units V,H
~_
VDD o
(VI Min_ Typ_ Max_ '--
VIL _
Propagation Delay Time (tPH L, tPLHI: NOTE:

TEST ANY ONE INPUT.
5 - 200 400 VSS WITH OTHER INPUTS AT
Yoo ORYss'
Clock-to-Q Output (See Fig. 101 10 - 100 200 ns
tzCI-ZUOOIU
15 - 75 150
5 - 210 420
Preset or Reset·to-O Output 10 - 105 210 ns Fig. 13 - Input-vo/rage
15 - 80 160 telt circuit
'5 - 240 480

Clock-to-Carry Out 10 - 120 240 ns
15 - 90 180
Carry·ln-to·Carry Out
5
10
-
-
125
60
250
120 ns
15 - 50 100
5 - 320 640
Preset or Reset-to-Carry Out 10 - 160 320 ns
15 - 125 250
5 - 100 200
Transition Time (tTHL. tTLHI (See Fig. 91 10 - 50 100 ns
15 - 40 80
5 2 4 -
Max. Clock I nput Frequency (fcLl 10 4 8 - MHz
150 5.5 11 -
Input Capacitance (CIN) - 5 7.5 pF
Set-up Time. ts 5 25 12 -
Preset Enable to J n 10 10 6 -
Hold times. tH
15
5
10
60
5
30
-
- l
~
1cFi20",
.0 ...
...
20Ol
voo
Clock to Carry-In 10 30 4 -
~VARIABLE ~
'O ... V
15 30 1 - ns WIDTH
ss
5 30 10 -
Clock to Up/Down 10 30 4 -
15 30 5 -
5 70 35 -
Preset Enable to J n 10 40 20 - Fig.. '4 - Power-dissipation telt circuit and
15 40 20 - input walleform.
308
CD451 DB, CD4516B Types
Cl.OCK
Ci'RiiY iii
rt- rth. h- rt- h- t"t-t"t-t"t-t"t- rt-rt-rt- h- r- h.r- h- rr: r-r-r-r CL
'X
CJ UfO PE
1 X 0
R ACTION
0 NO COUNT
UP/DOWN I-t- .I 0 1 0 0 COUNT UP
RESE T I- .r 0 0 0 0 COUNT DOWN

X X X 1 0 PRESET
Eh ht- X X X X 1 RESET
, x - DONTCARE
I-t-r-
•3 r- t-r-
TRUTH TABLE
4 10 2:0 30 40 60 70 80 90
l- I- l- t- t-
I- t-I- l-
'I- 1-1- I-
l-
I-
1= I- l- 1= I- t-I= I- I-t- 1= t-r-
'1- 1-1- l- I- t- t-I- l- t- I-t-
Q3 r- t-r-
1= != 1= t-;
. ..,
4
I-- t-t-
Ciiiiii au T IU I~
COUN T 0 , 3 4 .5 6 7 o • o 7 6 • 4 3 o 0 • 6 7 0
Fig. 15 - Timing Diagram for CD4510B. 92 100

(,.,,7-'.540J II
CLOCK
CAiiiiiiH
LP/OOWN
RESET
E'
,
"'l. tL tL h- rL h. "'l. "'l. rt-rt- h- h. rt-rt-rt- n.. rL rL n.. n.. rL
rL
"'l. rL
r "'L.. -
Voo
J 92CS-21037RI
•• Vss
3
•4 Dimensions and Pad Layout for CD4510BH.
,f- f- I- ,....- f- l - I-- I- r- r- I- ......
~ l-
~ l- ~ r- ,....- ~ r- f- ~ r-r- I-
'-
2f- f-
I-- r- ' - f- I-- - r-r- r-r-r- -
Q 3f- f- f- l-
I-- l-
41- l- I- t-
CAiiiiVOiiT
f- ~ lL- l-
COUNT o • 7
•• 10 II 12 13 14 15
•• T • • 4 3 • 1 o 0 I.
Fig. 16 - Timing diagram for CD4516B. gO

2.489)
PARALLEL
DATA
OUTPUTS
~"4J I 92CS-27036RI
I-----;;;o~~=r'~
CLOCK PRESET Dimensions and Pad Layout for CD4516BH.
ENABLE
This acquisition system can be operated in represent a chip when it is part of the wafer. When the
the random access mode by jamming in wafer IS separated into individual chips, the angle of
the channel number at the present inputs, or different Chips. The actual dimensions of the isolsled
in the sequential mode by clocking the chip, therefore, may differ slighrly tram the nominal
dimensions shown. The user should consider a lolerance
CD4516B. of -3 mils to +16 mils applicable to the nominal
dimensions shown.
Fig. 17 - Typical16-channel, IO-bitdataacquisition system.
309
"PARALLEL CLOCKING"
UWDOWN >--------.--------------------------~------------------------~._------------------_.
~~~~t~ >--------+--~----------------------~--~----------------------~~~---------------.
UWD
C.l. CD4510/16 C.O. o - - - - { ] C . I. CD4510/16 C.O. [)------(JI c. I . CD4510/16 C.O. *"
R R R
CLOCK >--------t--~----------------------_r--~------~--------------t_~~---------------.
RESET
• CARRY OUT line. at the 2nd, 3rd, etc., stages may have a negative-going glitch
pulse resulting from dillerential delays 01 dillerent CD4510/16 IC',. These negative-
~0ln1l!Vlltche,do not allect proper CD4510/16 operation. However, II the
AR OOT signals are used to tr~ger other edge-sensitive logic devices, such
as FF'. or counters, tl\e CARRY 00 signal. should be gated with the clock signal
u.lng a 2-lnput OR gate such as CD4071 B•
• RIPPLE CLOCKING".
UP/DOWN
PRESET
ENABLE
C I.
CLOCK
RESET>-----J~~================::::====:t==================~---~L_----------.
RIPPLE CLOCKING MODE'
THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY RESTRICTION ON CHANGING
THE UP/DOWN CONTROL IS THAT THE CLOCK INPUT TO THE FIRST COUNTING STAGE MUST BE 'HIGH".
For cascading counters operating in a IIxed.!!l1.-count or down-count mode,the OR

gates are not required between stages, and CO Is connected dlreclly to the CL Input
01 the next stage with lrr grounded. 92CL-17194R5
Fig. 1B - Cascading counter packages.
310
CD4511B Types
CMOS B.CD-to-7-Segment
Latch Decoder Drivers BCD
l:
High-Voltage Types (20-Volt Rating) 'T"
:·.
.S ,
DISPLAY
IDI/liJI311.flSlbll1Sfli
4 5 1 8
0'
LE/S'i'iiOe'£ 5
ifL
The CD4511 B types are BCD-to-7-segment Features:
latch decoder drivers constructed with
CMOS logic and n-p-n bipolar transistor out- • High-output-sourcing capability •••••••• up to 25 rnA
put devices on a single monolithic structure. • Input latches for BCD Code storage
These devices combine the low quiescent • Lamp Test and Blanking capability FUNCTIONAL DIAGRAM
power dissipation and high noise Immunity • 7-segment outputs blanked for BCD input codes> 1001
features of RCA CMOS with n-p-n bipolar
output transistors capable of sourcing up to .100% tested for quiescent current at 20 V
25 rnA. This capability allows the CD4511 B Applications:
• Max. input current of 1 p.A at 18 V, over
types to drive LED's and other displays
full package-temperature range, 100 nA • Driving common-cathode LED displays
directly.
at 18 V and 25·C . • Multiplexing with common·cathode LED
.5-V, 10N, and 15-V parametric ratings displays
Lamp Test (IT), Blanking (Eit), and Latch
Enable or Strobe inputs are provided to test • Driving incandescent displays
the display, shut off or intensity-modulate it, • Driving low-voltage fluorescent displays
and store or strobe a BCD code, respectively.
Several different signals may be multiplexed
and displayed when external multiplexing
circuitry is used. The CD4511 B is supplied
in 16-lead hermetic dual-in-line ceramic
packages (D and F suffixes), 16-lead dual- (Voltages referenced to VSS Terminal) ~.6to+20V
in-line plastic packages (E Suffix), 16-lead INPUT VOLTAGE RANGE, ALL INPUTS. • ~.5 to VDD +0.6 V
ceramic flat packages (K suffix), and in chip DC INPUT CURRENT, ANY ONE INPUT • • ±IOmA
form (H suffix). POWER DISSIPATION PER PACKAGE (PDI:
These devices are similar to the type o
For TA - -40 to +60 C (PACKAGE TYPE El . . • . • • • • . 500mW
MC14511. For TA - +60 to +8So C (PACKAGE TYPE E) . Derate Linearly at 12 mWfJC to 200 mW
For TA = -55 to +100·C (PACKAGE TYPES D, F, Kl • • • • • • • •. 500mW
ForTA = +100 to +12S·C (PACKAGE TYPES D, F, K) Derate Linearly at 12 mW/oC to 200 mW
FOR TA ~ FULL PACKAGE-TEMPERATURE RANGE (All Package Types) l00mW
. OPERATING-TEMPERATURE RANGE (TAl:
I. I. Voo PACKAGE TYPES 0, F, K, H • • • • • • • •• • -55 to +1250 C
C 2 I~ PACKAGE TYPE E • • • • • • • • • . • • • • • -40 to +860 C
LT I. STORAGE TEMPERATURE RANGE ITstgl • • • • • • • . -65 to +1500C
iil
LE/STROiiE
•
5
13
12
At distanca 1/16 ± 1/32 inch 11.59 ±0.79 mml from case for 105 max.
0
A "
10
Vss 9
OPERATING CONDITIONS AT TA = 25·C Unless Otherwise Specified
TOP VIEW
92CS-2,084RI For maximum reliability, nominal operating conditions should be selected
so that operation is a/ways within the following ranges
CD4511B
TERMINAL ASSIGNMENT Characteristic VDD Min. Max. Units
Supply·Voltage Range (T A):
- 3 18 V
(Full Package-Temperature Rangel
5 150 - ns
Set-Up Time ItS) 10 70 - ns
15 40 - ns
5 0 - ns
Hold Time (tHI 10 0 - ns
15 0 - ns
5 400 - ns
Strobe Pulse Width (twl 10 160 - ns
15 100 - ns
311
CD4511B Types
..
Conditions Limit. at Indicated Temperature. (OC)
Values at -55, +25, +125 for D, F, K, H, Packages
Values at -40, +25, +85 for E Packages
,...
Characteristic IOH Va VIN VDO +25 Units
(rnA) (V) (V) (V)
-55 -40 +85 +125 Min. Typ. Max.
Quiescent Device - - - 5 5 5 150 150 - 0.04 5
Current: IDD - - - 10 10 10 300 300 - 0.04 10
Max. - -
-
-
-
15
20
20
100
20
100
600
3000
600
3000
-
-
0.04
0.08
20
100
IlA
I:
I~
Output Voltage:
- - 0,5 5 0.05 - 0 0.05 DRAIN-TO-SOURCE VOLTAGE (Vosl-Y 'lCS·Z.,II'"
-
Low· Level VOL - 0,10 10 0.05 - 0 0.05 V Fig. 7 - Typical output low (.ink) current
Max. - .. 0,15 15 0.05 - 0 0.05 characteristics.
.. - 0,5 5 4 4 4.2 4.2 4.1 4.55 -
High·level VOH
Min. - -
0,10
0.15
10
15
9
14
I 9
14
9.2
14.2
9.2
14.2
9.1
14.1
9.55
14.55
-
-
V
..
7<X :q! . :: . . :::su~y VOLTAG~p~OD)·5~3:
-oj t
!:5 :':::
:fH +. :J ;:p Jii: I::: :;~: ;W.! :: :., ;-.
! ~ r :~ t;~ "!tit ~~ •. ~: .•
Input Low
- 0.5,3.8 5 1.5 - - 1.5
.
t+-t-t-
Voltage, V IL
- 1,8.8 . 10 3 - - 3 V !r
t- +!1 dli'., T'
Pi UH~r
Max. .. 15 4 - - • _4
~
1.5,13.8 4
Input High 0.5,3.8 5 3.5 3.5 - - + 10V
Voltage, V IH - 1,8.8 10 7 7 - - V i'5 ,. ;-
~
,"V
Min. - 1.5,13.8 15 11 11 - -
flCx)
i
0 .. 4.0 4.0 4.20 4.20 4.10 4.55 -
5 · - - - 4.25 - AMBIENT T£MPERATURE (T A )-25·C
10 5 3.80 3.80 3.90 3.90 3.90 4.10 - 0 2. 00
15 3.50 3.50 - 3.95 -
V
LOAD CAPACI!ANCE(CL)-pF '"
100
UCS-27077
20 3.55 3.55 3.39. - 3.40 3.75 - Fig, 2 - Typical data·tooQutput, low-to-high-level

25 3.40 3.40 - - 3.10 3.55 - propagation delay time a. a function of
load capaCitance.
0 9.0 9.0 9.20 9.20 9.10 9.55 -
Output Drive 5 .. . . - - 9.25 -
Voltage: 10 · .. 8.85 8.85 9.00 9.00 9.00 9.15 - ~MBIENT TEMPERA~~TA~.~~i'"
V I
High Level VOH 15 · 10 - - - - - 9.05 - f SUPPL'" VOl-TAGE t VOD)- 5 "I
Min. 20
25
- -
-
8.70
8.60
8.70
8.60
8.40
-
8.40
-
8.60
8.30
8.90
8.75
-
- !
~
,
0 - - 14.0 14.0 14.20 14.20 14.10 14.55 - ;:
5
10
-
-
-
-
15 13.90 13.90 14.0 14.0
-
14.0
14.30
14.20
-
-
V
; +
io'¥
15 .. _. - - - - - 14.10 - is
20
25
-
-
-
- 1 13.75
13.65
13.75
13.65
13.50
-
13.50
-
13.70
13.50
13.95
13.80 - ~
0
,"v
f
Output Low
(Sink) Current, - 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
0 .. 00 ..
LOAD CAPACITANCE eeL )-pF
75 100
UCS-270711
rnA
IOL - 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - Fig. 3 - Typical data'!QoQutput, high-to-low-Ievel
Min. - 1.5 0,15 15 4.2 2.8 2.4 3.4 6.8 - propagation delay time a. a function of
4
load capacitance,
Input
Current, lIN
- 0,18 0,18 18 ±o.l ±o.l ±1 ±1 - ±10-5 ±o.l Il A
Max. AMBIENT TEMPERATURE (TA )"2S·C

.-
.~'~~THTH-H~~MTMT~~~Tn~Tnu
.
13~1
6 ~
~
ii30
5
10
25 50 75 100
LO~!» CAPACITANCECCL.t-pF 92CS-27019
Fig. 4 - Typicallow-to-high-levBl tran.ition time a.

B function of load capacitance.
312
CD4511B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , t f = 20 ns,

CL =50 pF, RL =200 kn
Test LIMITS
CHARACTERISTIC Conditions All Packages UNITS
VDD
Volts Min. Typ. Max.
(Data) 10 - 210 420 ns
High·to·Low Level, tpHL 15 - 150 300
5 - 660 1320 LOAD CAPACITANCEICL1-pF 92.CS-2TOao

Low·to·High Level, tpLH 10 - 260 520 ns
Fig_ 5 - Typical high·to-low transition time as a
15 - 180 360 function of load capacitance.
(BL) 10 - 175 350 ns
High·to·Low Level, tpHL 15 - 125 250
Low-to-High Level, tpLH

5
10
-
-
400
175
800
350 ns
AMBIENT lEMPERATURE (TA )a25-C
t
II
15 - 150 300
- 10 - 125 250 ns
(L T)
High-to-Low Level, tpHL 15 - 85 170 ~ 1:5
!!i
Low-to-High Level, tpLH

5
10
-
-
150
75
300
150 ns
."
Ii!
"-
10
-
5 5
15 50 100 o
Transition Time: 5 - 40 80 o 0.5 1.5

SUPPLY VOLTAGE -OUTPUT DRIVE VOLTAGE (VOO-YOH)-V
10 - 30 60 ns 92CS-210&1
Law-to-High Level, tTLH 15 - 25 50 Fig_ 6 - Typical voltage drop IVDO to output) ...
output soutee current BS 8 function of
5 - 125 310 supply.
10 - 75 185 ns
High-to-Low Level, tTHL 15 - 65 160
5 150 75 -
Minimum Set-Up Time, ts 10 70 35 - ns
15 40 20 -
5 0 -75 -
Minimum Hold Time, tH 10 0 -35 - ns
15 0 -20 -
5 400 200 -
Strobe Pulse Width, tw 10 160 80 - ns
15 100 50
'" ~O'I FREQUaoC: If41~:lg~ '" 8'02 2. '" 101
Input Capacitance, CI N • - 5 7_5 pF 92CS-2.7082

Fig. 7 - Typical dynamic power dissipation characteristics.
313
CD4511B Types
LE 81 LT D C
TRUTH TABLE
8 A . b c d . f 9 Display
X X 0 X X X X 1 1 1 1 1 1 1
B
X 0 1 X X X X o 0 o 0 0 0 0 Blank
0 1 1 0 0 0 0 11 1 1 1 1 0
a
0 1 1 0 0 0 1 o 1 1 o 0 0 0
I
0 1 1 0 0 1 0 11 0 1 1 0 1
r
0 1 1 0 0 1 1 11 1 1 0 0 1
3
0 I 1 0 1 0 0 o 1 1 o 0 1 1
"I
0 I 1 0 I 0 1 I 0 I I 0 I I
5
0 I 1 0 I I 0 o 0 I I I 1 1
b
0 I 1 0 I I 1 1 I I o 0 o 0
7
0 I 1 I 0 0 0 I I I I I 1 1
B
0 I 1 I 0 0 I 1 I I 0 0 1 I
II
0 I 1 I 0 I 0 o 0 o 0 0 0 0 Blank
0 I 1 I 0 I I o 0 o 0 o 0 0 Blank
0 I 1 I I 0 0 o 0 o 0 0 0 0 Blank
0 I 1 I 1 0 I o 0 o 0 o 0 0 Blank
0 I I 1 1 I 0 o 0 o 0 0 0 0 Blank
0 I I I 1 I I o 0 o 0 0 0 0 Blan~
Vss
92(;L-2707~RI 1 I 1 X X X X
* *
Fig. 8 - Logic diagram. X;::; Don't Care * Depends on BCD code previously
·applied when LE = 0
TEST CIRCUITS QVCO

INPUTS OUTPUTS
Note: Display is blank for all illegal input codes (BCD> 1001).
INPUTS
o V,H
Vss
~ ~
VIL 1
NOTE:
OF INPUTS
92CS-27404IRI
Vss Fig. 10 - Input voltage.
Fig. 9 - Quiescent device current.

Voo
(JVCO
INPUTS NOTE:
92C5-25085
~ ~:~~~~I~~~~~S
I, ,If ~ 20"1
Vss TO 80TH Voo ANO Vss

CONNECT ALL UNUSED
INPUTS TO EITHER
. Voo OR VSS'
Vss
20" n i r : ; , : ; - ; ; - - - - - - V O O
Fig. I I - Input current.
10%W~%
,oa
, - - - - - - , Voo LE
o
Voo ----"'t-'""","'su""---t- t HOLD
VOO
DATA 10%
l/.
__ _ _ _ - " r_50%
90% _ _ __
INPUTS
20 ns FOR SETUP
VOO - - - , - -
,,-
L~O!!..H~l~_,
Vss
:~:::: ---2:-~-~-~"7"""7C---1-:Jf:-:-j--2-0-"-'
Vss
T 50PF
50,..1
10%~,W~
Vss
MEASURE OUTPUT d FOR t PLH
MEASU~E OUTPUT g FOR tpHL 9ZCS-27088RI Vss 92CS-27086RI 92CS- 25086RI
Ir ,tf -20 n1
Fig. 12 - Data propagation delay. Fig. 13 - Dynamic power dissipation. Fig. 14 - Dynamic waveforms.
314
CD4511 B Types
APPLICATIONS LrIlVOO
Interfacing with Various Displays A -:- - -l:-,.,-_~_____---,

~ I~b__________---,
VOO
c.J
0-1
I
I
':"E -, I'"'.-----J
aLn I
·-------l VD~~IIJ
iitl
I 92CS-27091RI -=-
iss
TO DO I I A medium-brightness intensity display can be
I obtainad with 10w-volt8ge fluorescent displays
I I such as the Tung-5ol Digivac S/G-- SerieS.
I I ··Trademark Tung-Sol Division Wagner Electric Co.
I I Fig. 16 - Driving low-voltage fluorescent displays.
I
I I
•
I I
I CD4511 I
I I
I __ J
I ______ _
L LED 7-SEGMENT
DISPLAY
R.4QDA
92CS-27089RI
Duty Cycle = 100%

ISEG = IDIODEAVG. = 20 rnA at Luminous Intensity/Segment = 250 microcandles
92CS-27090RI
R=VOH-V DF
2 of 7 Segments Shown Connected
'SEG Resistors R from VOO to each 7-5egment driver
Fig. 15 - Driving cammon-cathade 7-segment LED displays (example Hewlet-Packard 5082·7740). output are chosen to keep all Numitron segments
slightly on and warm.
-Fig. fi - Driving incandescent displays (RCA
Numitran DR2000 series display.).
,--- ---,
I
LL I SEG I I I
Ie II I
r;- + II I
Ie II I
I I I
I I
I
I
Vss
Multiplexing Scheme Showing 2 of 7 Segments Connected 92ChI-Z7087RI
92CM- 32873
Transistors T 1 - T4 (RCA·2N3053 or 2N2102) have IC Max.rating >7xISEG Dimensions and pad layout for CD4511 8 chip.
Duty Cycle = 25% The photographs and dimensions of each CMOS chip
represent a chip when it is part of the wafer, When the
ISEG = (lDIODEAVGJ x 4 waf.r is separated inlo individual chips. the angle of
R = (V OH - V DF - VCE ) different chips. The actual dimensions of the isolated
ISEG dimensions shown, The user should consider a tolerance
All unused inputs on C04555 of -3 mils to + 16 mils applicable 10 Ihe nominal
dimensions shown.
are connected to VOO or VSS'
Fig. 7B - Multiplexing with common·cathode 7·segment LED displays (example Hewlet·Packard 5082·7404 derived from the basic inch dimensions as indicated.
. 4 character display or 4 discrete Monosanto Man 3 displays). Grid graduations are in mils (70- 3 inch).
315
CD4512B Types
CMOS 8-Channel Features:

• 3-state output
Data Selector • Standardized, symmetrical output characteristics
High-Voltage Types (20-Volt Rating) •
•
100% tested for quiescent current et 20 V
S-V, 10-V, and lS-V parametric ratings
'·STATE DII'ILIE
I..... IT---~
DD_'
,.
• Maximum input current of 1 jlA at 18 V over full package- 01'"
The RCA-C04512B is an B-channel data 01-1
temperature range; 100 nA at 18 Vand25"C CNANNEL 01-4
selector featuring a three-state output that. INItUTI 04 ...
• Noise margin lover full package·temperatura range): 01-. 1• •LECr
..,..,7
can interface directly with, and drive, data 00-7
. 1 VatVDD= 5V ' 07-.
lines of bus-oriented systems.
2 Vat VDD = 10 V ....... {,-n
_. TIIDL ... 11
The C04Sl2B-series types are supplied in 2.5 V at VDD= 15 V e-' C04111.
lS-lead hermetic dual-in-line ceramic pack-
ages (0 and F suffixes). lS-lead dual-in-line • Meets all requirements of JEDEC Tentative
plastic packages (E suffix), lS-lead ceramic StBndard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices" FUNCTIONAL DIAGRAM
flat packages (K suffix), and in chip form (H
suffix). Applications:
• Digital multiplexing
• Number-sequence generation
• Signal gating 00 ,.
01 2 :: ;!lTATE _ .
01 a 14 ..... OUTPUT
DI 4 II C
RECOMMENDED OP~RATING CONDITIONS D4 • 12 •
DI • II A
operation is always within the fol/owing ranges' V.. •
01 7
TOP VIEW
10
• . D7
,.H,.,T
.2-.:. ..... 17
LlIIo'ITS
CHARACTERISTIC UNITS TERMINAL ASSIGNMENT
MIN. MAX.
Supply-Voltage Range (For TA = Full Package
3 18 V
Temperature Rangel
TRUTH TABLE
SEL.CONT. 3-STATE SEL
c ..~.~----------~----------__~ INH
A B C DISABLE OUTPUT
0 0 0 0 0 DO
1 0 0 0 0 01
0 1 0 0 0 D~
1 1 0 0 0 D3
0 0 1 0 0 04
1 0 1 0 0 OS
Vao 0 1 1 0 0 DB
d 1
X
1
X
1
X
0
1
0
0
07
0
r
X X X X 1 HlghZ
1 - High LIV8I 0- Low LIV8I
X-Don'tea ..
1VIS
. gWDD
* ALL INPUTS ARE PROTECTED
LOAD
NETWORK Vss Fig. 2 - Tllpical t",,,.itio,, ti"", ... function
Fig. 1 - LogiC diagram. of load "aplJt:ltlllIC/I.
316
CD4512B Types
INPUT VOLTAGE RANGE. ALL INPUTS ........................................... -0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ..................................................... ±10 mA
For TA = -40 to +60'C (PACKAGE TYPE E) ................................................. 500 mW
For TA =+60 to +85'C (PACKAGE TYPE E) ......•............ Derate Linearly at 12 mW/'C to 200 mW
For TA = -55 to +100'C (PACKAGE TYPES D. F. K) .......................................... 500 mW
For TA = +100 to +125'C (PACKAGE TYPES O. F. K) ....•.•... Derate Linearly at 12 mW/'C to 200 mW
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .........•............ 100 mW
PACKAGE TYPES D. F. K. H ........................................................ -55 to +125'C
PACKAGE TYPE E .................................................................. -40 to +85'C DRAIN-lO-SOURCE VOLTAGE (Vosl-V
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +150'C Fig. 3 - Typical output low (sinkl
LEAD TEMPERATURE (DURING SOLDERING): current characteristics.
At distance 1/16 ± 1132 inch (1.59 ± 0.79 mm) from case for 10 s max. .. ....................... +265'C
AMBIENT TEMPERATURE IT.o,'.Z5·C
CHARAC· CONDITIONS
Values at -55, +25, +125Applyto 0, F, K, H, Packages
U
N
I GATE-lO-SOURCE VOlTAGE p'GS'".!!Y
II
Vo
(V)
VIN VOO
(V) (VI -55 -40 +85 +125 Min.
+25
Typ. Max.
S
·•
~ 7.5
3 ,
- -
·,
0.5 5 5 5 150 150 0.04 5
Quiescent
Device - 0,10 10 10 10 300 300 - 0.04 10
IJ.A
~ 25 ,V
Current, - 0,15 15 20 20 600 600 - 0.04 20 5 10 '5

100 Max. DRAIN-lO-SOURCE VOlTAG~ IVD~I:-V
- 0,20 20 100 100 3000 3000 - 0.08 100 Fig. 4 - Minimum ou.tput low (sink)
Output Low
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0.10 10 1.6 1.5 1.1 0.9 1.3 2.6 - DRAIN-lO-SOURCE VOLTAGE IVoSJ-V
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -

4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - m,o
Output High
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current. 9.5 0,10 10 . -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage:
- 0,5 5 0.05 - 0 0.05
Low·Level, - 0,10 10 0.05 - 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05 V
Output - 0,5 5 4.95 4.95 5 -
Voltage: - 0,10 10 9.95 10 - Fig. 5 - Typical output high (sourcel
9.95
High·Level,
~u"ent characteristicS.
VOH Min. - 0,15 15 14.95 14.95 15 -
0.5,4.5 - 5 1.5 - - 1.5 DRAIN-lO-SOURCE VOLTAGE (11051-11
Input Low -" -10 -5
I
Voltage 1,9 - 10 3 - - 3 AMBIENT TEIrllPERATURE .(TAJ" 25"C
v
VIL Max. .5,13.5 - 15 4 - - 4 V
GAT(~TO-SOURCE VOLTAGE (VGsJ" -5
0.5,4.5 - 5 3.5 3.5 - -

.,
Input High
Voltage; 1,9 - 10 7 7 - -
-IOV
VIHMin.
1.5,13.5 - 15 11 11 - - .K)
Input Current
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 IJ.A
3·State
Output
Leakage 0,18 0,18 18 ±0.4 ±0.4 ±12 ±12 - ±10-4 ±0.4 IJ.A
Current
IOUTMax. Fig. 6 - Minimum .output high (source)
current characteri$tic$~
317
CD4512B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r,t1 = 20 ns, IO"~ AMBIENT TEMPERATURE {TA)o25 ec ::::t::t:t t=
Cl = 50 pF, Rl = 200 kQ
~ 104 8
·, IlL 1.,1)1
JJI /' .,:L:
'fl- 7.:'~~
·,
CHARACTERISTIC UNITS I ,
~ ~r:Y"'"" ,0 C--
':14 -
VDD
(V) Typ. Max. is
~ 103 ~ 0Jl'~ IL
Propagation Delay Time, tpHl, tpLH
Inhibit to Output
5
10
140
70
280
140
~
"
~
W
·, -
IL
,,-
IL
I02~
~
·, ." . ==~~:~::: ~
15 50 100
5 200 400 II
"A" Select to Output 10 85 170 ns 10
,/, ... , .10
, "
J lJ
"
15 60 120 INPUT fREQUENCY UINl-kHz
5 180 360 Fig. 7 - Typical dyanamic power dissipation

Data to Output 10 75 150 as a function of frequency.
15 55 110
5 60 120
3·State Disable Delay Time: AMBIENT TEMPERATURE (TA)_25 8 C
10 30 60 ns
tpZL' tpLZ' tpHZ' tpZH 15 20 40
5 100 200
Transition Time, tTH L, tTLH 10 50 100 ns
15 40 80
(Any Input) 5 7.5 pF
20 40 GO 100
500 pF Voo LOAD CAPACITANCE (CL}-pF
INPUTS
I. o Fig. 8 - Typical propagation delay time as a function

V55
15 of load capacitance rUA" select to output).
14
13 CL
12
"
10
9
Vss
Fig. 9 - Dynamic power dissipation test circuit. Fig. 10 - Quiescent device current test circuit.
Voo INPu(Js
"00 NOTE.
T.
I
~ MEASURE INPUTS
o ~ SEOOENTIALLY,
Vss TO 80TH Voo AND Vss'
CONNECT ALL UNUSED
INPUTS 10 EITHER
Voo OR VSS'
imenSions in parentheses are in millimeters and
"$5 are derived from the basic inch dimensions as in·
dlcated. Grid graduations are in mils (10- 3 inch).
Fig. 11 - Input current test circuit. 72-80

wafer is separated into individual chips, the ang18 of
Chip, therefore, may differ slightly from the nominal
dimensions shown. The user should considera tolerance
dimensions shown.
92CS-2744IRI 75-83
(1.905-2.108)
Fig. 12 - Input voltage test circuit. Dimensions and pad layout for CD4512BH
318
CMOS 4-Bit Latch/4-to-16 VOO·24 II so

VSS·12 9 51
Line Decoders Features: 10 52
•7 54
53
High-Voltage Types (20-Volt Rating) • Strobed input latch 6 5'
OATA I 2 : S6
• Inhibit control
CD4514B Output "High" on Select OATA 2 3 18 57
• 100% tested for quiescent current at 20 V OATA 3 21 ~:
CD4515B Output "Low" on Select 17
• Maximum input current of 1 IlA at 18 V DATA'" 22 20 SID
19 SIl
over full package-temperature range; STROBE I 14 SI2
The RCA-CD4514B and -CD4515B consist 100 nA at 11.1 V and 25 0 C 13 513

16 514
15 515
of a 4-bit strobed latch and a 4-to-16-line • Noise margin (over full package temper-
ature range):
decoder. The latches hold the last input data
presented prior to the strobe transition from 1 Vat VDD = 5 V
INHIBIT -'.''''-'t====_.J
1 to O. Inhibit control allows all outputs to 2VatVDD=10V CD4514B, CD4515B
be placed at O(CD4514B) or 1(CD4515B) 2_5VatVDD=15V FUNCTIONAL DIAGRAM
regardless of the state of the data or strobe • 5-V, 10-V, and 15-V parametric ratings
inputs_
The decode truth table indicates all combi- characteristics_
nations of data inputs and appropriate se-
II
lected outputs. Standard No_ 13A, "Standard Specifications
These devices are similar to industry types for Description of 'B' Series CMOS Devices"
MC14514 and MC14515_
The CD45148 and CD45158 types are Applications:
supplied in 24-lead hermetic dual-in-line • Digital multiplexing
ceramic packages (0 and F suffixes). 24- II Address decoding
lead dual-in-line plastic packages (E suffix). • HexadecimallBCD decoding
24-lead ceramic flat packages (K suffix). • Program-counter decoding
and in chip form (H suffix). II Control decoder
MAXIMUM RATINGS, Absolute-Maximum Values: DRAIN-lO-SOURCE VOLTAGE (VOSI-V

DC SUPPLY-VOLTAGE RANGE. (V DO)
(Voltages referenced to VSS'Terminall -0.5 to +20 V Fig_ 1 - Typical output low (sink)
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to VDD +0.5 V current characteristics.
DC INPUT CURRENT. ANY ONE INPUT ±lOmA
POWER DISSIPATION PER PACKAGE (PO); AM'"'' "."H.,UH•..1'''-'
For TA = -40 to +60 0 C (PACKAGE TYPE EI . . . . . . . .. 500mW
For TA = +60 to +85 0 C (PACKAGE TYPE EI Derate linearly at 12mW/oC to 200 mW
For T A = -55 to +tOO'C (PACKAGE TYPES D. F. K)
For TA = +100 to +125'C (PACKAGE TYPES D. F. K)
. . . . . . . .. 500 mW
Derate Linearly at 12 mW/oC to 200 mW 1;I>fH:ltltH-lttftHtttH-l-tfH-!ttftHtttItHtlmHHE
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Typesl 100mW
OPERATING-TEMPERATURE RANGE (TAl; ",lo!!illllllllmtl!mUllllllllll!Wlllllllll!W
I~
PACKAGE TYPES D. F. K. H -55 to +1250 C
PACKAGE TYPE E . . -40 to +85 0 C I
STORAGE TEMPERATURE RANGE (Tstgl -65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERINGI;
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max.
II" DRAIN-lO-SOORCE VOLTAGE (Vosl-V
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted. Fig. 2 - Minimum output/ow (sink)
For maximu~ reliability, nominal operating conditions should be selected so that current characteristics.
operation is always within the following ranges: CRAIN-lO-SOURCE VOLTAGE (Vosl-V
VDO LIMITS
(V) Min_ Max.

3 18 V
Temperature Range)
5 150 -
15 40 -
5 250 -
Strobe Pulse Width, tw 10 100 - !,!S
15 75 -
Fig_ 3 - Typical output high (source)

. current characteristics.
319
STATIC ELECTRICAL CHARACTERISTICS CRAIN-TQ-SOURCE VOLTAGE IVOS)-V
-j~ -10 .~

CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H Packages ,
CHARACTER· Vllues It -40, +25, +85 Apply to E Pocklge
UNITS
ISTIC +25
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Mox.
.. tt:- ..
Quiescent Device
Current,
-
-
0,5
0,10
5
10
5
10
5
10
150
300
150
300
-
-
0,04
0,04
5
10
.. 11 ,.. , :d
"I
~!d
:i: I:i
I
P
IDD Max, IJA t!;
eUi..
!'"
- 0,15 15 20 20 600 600 - 0,04 20 '-I~'';' •
- 0,20 20 100 100 3000 3000 0,08 100 m:

0.4 0,5 5 0,64 0,61 0.42 0.36
-
0,51 1 -
J
:i
Output low
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2,6 - JIm 'il
IOl Min. 2,8 6,8 -
1.5 0,15 15 4.2 4 2.4 34
5 -0.64 -0.61 -0.42 -0.36 -0,51 -1 mA Fig. 4 - Minimum output high (source)
Output High 4.6 0.5 -
(Source) 2.5 0.5 5 -2 -1.8 -1.3 -115 -1.6 -3,2 -
Current, -1,6 -1.5 -1.1 -0.9 -1.3 -2,6 -

9.5 0.10 10
IOH Min,
13.5 0.15 15 -4,2 -4 -2,8 -2.4 -3.4 -6,8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
low-Level, - 0.05 - 0 0,05
0.10 10
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0.5 5 4.95 4.95 5 -
High·level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0.15 15 14,95 14.95 15 -
Input low 0.5,4.5 - 5 1,5 - - 1.5
Voltage, -
1,9 - 10 3 - 3
Vil Max.
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
Fig. 5 - Typical strobe or data propagation delay
VIH Min. 1.5,13.5 - 15 11 11 - - time vs. load capacitance.
Input Current il0- 5
- 0,18 18 iO.l iO.l il il - iO.l IJA
liN Max.
LOAD CAPACITANCE {CL.I-pF
Fig. 6 - Typical inhibit propagation delay time

CL'50 pf
--Cv 15 pf f--
LOAD CAPACITANCE ICLI-pF 2 468 102 2 4 68 103 2 4 6 ~04

'0
fREQUENCY (f)-kHz
Fig. 7 - Typicallow-to-high transition time vs. Fig. 8 -, Typical strobe Of data propagation delay
load capacitance. time vs. supply voltage. Fig. 9 - Typ;cal power dissipation vs. frequency.
320
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input tr,lt = 20 ns,

CL=50pF,RL = 200 Kil
INPUTS
o
TEST CONDITIONS LIMITS Vss
VDD
V Typ. Max.
Propagation Delay Time: tpH L, tpLH 5 485 970

10 185 370
Strobe or Data
15 135 270
5 250 500
Inhibit 10 110 220 ns
15 85 170 Fig. 10 - Quiescent device current test circuit.
5 100 200
Transition Time, tTLH. tTH L 10 50 100
15 40 80
Minimum Strobe Pulse Width, tw

5
10
15
125
50
40
250
100
75
ns II
5 75 150
Minimum Data Setup Time, ts 10 35 70 ns
15 20 40
Input Capacitance. CIN Any Input - 5 7.5 pF
9<:CS-2144IRI
Fig. 11 - Input voltage test circuit.
Yoo 1NPUOS
VDO NOTE'
~ ~::~~:;I~~~~~S lin
\Iss TO BOTH "00 ANO \Iss' ... Iff!

CONNECT ALL UNUSED
INPUTS TO EITHER
i ICD
"DO OR "ss'
Vss A BCD
llell
... ieD
•"
DATA i? ]o-i/~tr--:H---f I Bel!
A II cD
i ico
DATA] 2Io-i/~tr~H __-f
AicD
i BCD
A B ~o
i ie 0
STROBE Io-~")~~---<LJ ABC['\
i B CD
THESE INVERTERS
USED OHLYON
CD4~'~1I
*
g '55
ALL INPuTS PROTECTED B'I'
COSIMOS
PROTECTION NETWORK
Fig. 13 - Logic diagram for CD45148 and CD45158.
321
DECODE TRUTH TABLE (Strobe = 1)

DECODER SELECTED OUTPUT
INPUTS
INHIBIT CD4514B a Logic 1 (Hight STROBE I. 2. VDD
D C B A CD4515B = Logic 0 (Low) DATA I 2 23 INHIBIT
OATA 2 3 22 DATA 4
0 0 0 0 0 SO 57 21 DATA 3
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
51
S2
53
5.
55
54
I.I.
20 SID
511
s.
0 0 1 0 0 54 ~,~ 50%
DATA 1,,1, ·20M
---- 53
51 I.
17 5.
Sl4
0
0
0
0
1
1
0
1
1
0
55
56 _ _ _ _ .oJ ~'5 1 52
SO
10 15
14
515
Sl2
0 0 1 1 1 57 V55 12 13 Sl3
TOPYIEW
~
ROBE 92C$-245!14
0 1 0 0 0 58 50%
0 1 0 0 1 59
0 1 0 1 0 S10 'W
92CS-2t!l91"2 CD4514B
0 1 0 1 1 Sll CD4515B
0 1 1 0 0 512 Fig. 14 - Waveforms for setup time and
0 1 1 strobe pulse width. TERMINAL ASSIGNMENT
0 1 S13
0 1 1 1 0 514
0 1 1 1 1 515
1 X X X X
All Outputs = 0, CD4514B
All Outputs = 1, CD4515B
X = Don't Care Logic 1 = high Logic 0 = low
....]-
71-79
92CS-29457
Dimensions and Pad Layout for CD45158 Chip

(Dimensions and pad layout for the CD45148 are identical)
Dimensions in parentheses are in millimeters and are The photographs and dimensions of sBch CMOS chip
derived from the basic inch dimensions as indicated. represent 8 chip when It ;s part of the wafer. When the
Grid graduations are in mils (to- 3 inch). wafer Is separated Into individual chips, the angle of
cleavage may vsry with respect to the chip 'ace for
diflerent chips. The actual dimensions of the isolated
chip, therefore. may dif/er sUghtly from the nominal
dimensions shown.
322
CD4517B Types
CMOS DuafS4-Stage
Static Shift Register
ClDCK~~r----------'
TERMINAL ASSIGNMENT
High-Voltage Types (20-Volt Rating) DAT4(01)
WRITE
alsA 16 VOD ENABLEU"'--'-,-__, -__--,--.J
Q48 A 15 016a
WE A 14 0488
WE· 0-- QI6---032- --o48---Q64
The RCA-CD45178 dual 64-stage static shift CL A 4 13 WEB WE- t~-··DI7---D33---D49-·-HiZ
register consists of two independent registers Q64 A 5 12 CLB r OF 2 SHIFT REGISTERS- TERM. Nos
Q32 A - 064 8 IN PARENTHESES ARE FOR 2ND HALF.
each having a clock, data, and write enable
10 032B VOO -16 VSS· 8
input and outputs accessible at taps following °A
the 16th, 32nd, 48th, and 64th stages. These Vss 9 DB
taps also serve as input points allowing data TOP VIEW 92C$- 31097
to be inputted at the 17th, 33rd, and 49th

stages when the write enable input is a logic TERMINAL ASSIGNMENT
1 and the clock goes through a low-to-high
transition. The truth table indicates how the
clock and write enable inputs control the
operation of the CD45178. Inputs at the MAXIMUM RATINGS, Absolute·Maximum Values:
intermediate taps allow entry of 64 bits into
DC SUPpLY-VOLTAGE RANGE, IVDDI
the register with 16 clock pulses. The 3-state (Voltages referenced to VSS Terminal) -0.5 to +20 V
outputs permit connection of this device to INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to V DD +0.5 V
an external bus. DC INPUT CURRENT. ANY ONE INPUT ±lOmA
The CD45178 is supplied in 16-lead hermetic POWER DISSIPATION PoER PACKAGE IPDI:
dual-in-line ceramic packages (0 and F For T A = -40 to +60 C IPACKAGE TYPE EI . . . . . . . .. 500mW
suffixes). 16-lead dual-in-line plastic pack- For T A = +60 to +85°C IPACKAGE TYPE EI Derate Linearly at 12 mwtC to 200 mW
ages (E suffix), 16-lead ceramic flat pack- For T A = -55 to +100'C (PACKAGE TYPES D, F, K) . . . . . . . . 0 500 mW
ages (K suffix). and in chip form (H suffix). For T A = +100 to +125'C (PACKAGE TYPES D, F, K) Derate Linearly at 12 mW/ C to 200 mW
FOR T A = FULL PACKAGE·TEMPERATURE RANGE IAII Package Typesl 100mW
OPERATING·TEMPERATURE RANGE IT AI'
Features: PACKAGE TYPES D, F, K, H -55to+125 °C
• low quiescent current - 10 nA/pkg (typ.) PACKAGE TYPE E ~40 to t85:C
atVOO=5V STORAGE TEMPERATURE RANGE ITstgl -65 to +t50 C
LEAD TEMPERATURE IDURING SOLDERINGI:
• Clock frequency 12'MHz (typ.) at At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mmJ from case for 10 s max. +265°C
VOO= 10 V
• Schmitt trigger clock inputs allow operation
with very slow clock rise and fall times
• Capable of driving two low-power TTL loads,
one low- power Schottky TTL load, or two RECOMMENDED OPERATING CONDITIONS
HTL loads For maximum reliability, nominal operating conditions should be selected so that
• Three·state outputs
• 100% tested for quiescent current at 20 V operation is always within the fol/owing ranges:
• Standardized, symmetrical output LIMITS
characteristics CHARACTERISTIC UNITS
• 5·V, 10-V and 15-V parametric ratings MIN. MAX.
Standard No.13A, "Standard Specifications Supply-Voltage Range (For T A = Full Package
3 18 V
for Description of 'B' Series CMOS Devices" Temperature Range)
Applications: TRUTH TABLE
Clock Write Data Stage 16 Stage 32 Stage 48 Stage 64

• Time-delay circuits Enable Tap Tap Tap Tap
• Scratch·pad memories 0 0 X 016 032 048 064
• General-purpose serial shift-register 0 1 X Z Z Z Z
applications 1 0 X 016 032 048 064
1 1 X Z Z Z Z
--
~ 0 Olin 016 032 048 064
----
X = Don't Care
1
0
1
Olin
X
X
D171n
016
Z
Z = High Impedance
033 In
032
Z
049 In
048
Z
Z
064
Z
323
CD4517B Types
CL--~------'---~------~~--~------~----'------,
CL
QI6 Q~2 Q48
01
049
16 STAGES 16 STAGES
STAGE 16 STAGE 32 STAGE 48

•
STAGE 64
OUTIIN TAP OUTIIN TAP OUllIN TAP ourllN TAP
92CM-31098RI
Fig. 1-CD45178 functfonal block diagram (one half).
Vss
A. PROTECTED BY COS/MOS
PROTECTION NETWORK
8 Vss
"* PROTEe]ED 9'1' COSIMOS
PROTECTION NETWORK
SAME AS
STAGES
16,32,48
EXCEPT
~O~ Q.
92CL-3274i5
Fig. 2-CD45178 logic block diagram (one half).
CLK
WE
\\...-_-.J(
Q64
------------------
HIGH Z
92CM-32763
Fig. 3-Dynamic test waveforms.
324
CD4517B Types
N
CHARAC· CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H Packages I
+25 S
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
- 0,5 5 5 5 150 150 - 0.04 5
Quiescent
Device - 0,10 10 10 10 300 300 - 0.04 10 p.A
Current, - 0,15 15 20 20 600 600 - 0.04 20
100 Max.
- 0,20 20 100 100 3000 3000 - 0.08 100
DRAIN-lO-SOURCE VOLTAGE {VOSI-V
0.4 0,5 5 0,64 0.61 0.42 0.36 0.51 1 -

Output Low Fig. 4-Typical n·channel output low (sink)
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mJl
Output High
(Source)
Current,
2.5
9.5
0,5
0,10
5
10
-2
-1.6
-1.8
-1.5
-1.3 -1.15
-1.1 -0.9
-1.6
-1.3
-3.2
-2.6
-
-
·
E
\
~15
jll
I
IOH Min. ~12.5
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
a 10
- 0,5 5 0.05 - 0 0.05 ~ t
Output Voltage: iii 7.5
Low·Level, - 0,10 10 0.05 - 0 0.05 ~
VOL Max. g 5
- 0,15 15 0.05 - 0 0.05 ,
Output - 0,5 5 4.95 4.95 5 -
V
·
§ 2.5
Voltage: - 0,10 10 9.95 10 - 5 10 15
9.95 DRAIN-lO-SOURCE VOLTAGE (Vosl-V
High·Level,
VOH Min. - 0,15 15 14.95 14.95 15 -
Fig. 5-Minimum n·channel output low (Sink)
Input Low
Voltage 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 .- 15 4 - - 4 -15 -10 -5
V AMBIENT TEMPERATURE (TA1=2S-C
-!-+·.......U-!IWltUllli-!
Input High 0.5,4.5 - 5 3.5 3.5 - - GATE-TO-SO~1rnmrE "'GSI=-5V
Voltage, 1,9 - 10 7 7 - -
VIH Min.
1.5,13.5 - - - HjlWI
Input Current
- 0,18
15
18 ±0.1 ±0.1
11
±1 ±1 -
11
±10- 5 ±0.1 p.A

-, t.!:I :.p m:
-IOV
.
liN Max. .\ -,~
~
;±( t:::
.. II
3·State
-15V
Output t·
Leakage 0,18 0,18 18 ±O.4 ±0.4 ±12 ±12 - ±10-4 ±0.4 p.A
Current
lOUT Max.
Fig. 6- Typical p-channel output high (source)

-15 -10 -5 f AMBIENT TEMPERATURE n~ 1.25·~
AMBIENT TEMPERATURE (TA,·2S·C
1I ~
-5~
j~ £
-iov
;
-IO~
~ 200
S
SUPPL't VOLljlt,GE t\lDO)~ 5 ·t·~
.
\OV
20 40 60 .0
LOAD CAPACITANCE (Cll-pF
Fig: 7-Minimum p·channel output high Fig. 8-Typical propagation delay time as a · Fig. 9- Typical transition time a a function
(source) current characteristics. function of load capacitance. of load capacitance.
325
CD4517B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input tr , t,=20ns,
CL =
50pF, RL 200kQ = ··• AMBIENT TEMPERATUREITA'-2!5-c
Il~X
;,IOK. J." ~ y,..
,," ~~
CHARACTERISTIC TEST
CONDITIONS VDD (V)
Min.
-IMITI
Typ. Max.
UNITS ~ .. :
eo • ~ ",,,Ov
,,~ .p"
K"
Propagation Delay Time: 5 - 200 400 ~ 1Ka =~.l·~
CLto Bit 16 Tap 10 - 110 220 ns
if
iiii •
•
Vi CL-SOIIF - -
tpHL, tpLH
3·State. Output, WE to Bit
15
5
10
-
-
-
90
75
40
180
150
80 ns
~Ioo,;
;
~
.· A
i
CL·"pF - - - -
16 Tap tpHZ, tpLZ; tpZH' •

tpZL (See Note) 15 - 30 60 10
It. & 8'0 2 4 e ',02 2 4 6 8,01 2 4 . "04
Output Transition Time 5 - 100 200 FREQUENCY If) KHz
tTHL, tTLH
10 - 50 100 ns Fig. to-Typical power dlss;pation as a
15 - 40 80 function of frequency.
Write Enable·to·Clock
5 0 -SO -
Setup Time
10 0 -25 - ns
15 0 -15 -
Data·to-Clock
5 20 0 -
Setup Time, ts
10 10 0 - ns
15 10 0 - D
C
Minimum Write 5 - 50 100
Enable-to-Clock 10 - 25 SO ns
Release Time 15 - 20 40
Minimum 5 - 100 200
Data-to-Clock 10 - 50 100 ns
Hold Time. tH 15 - 25 SO
Minimum Clock Pulse 5 - 90 180
Width, tw
10 - 40 80 ns
15 - 25 SO
REPETITIVE WAVEFORM
Maximum Clock Input 5 3 6 -
Frequency, tCL
10 6 12 - MHz fa
C-J
r-\. r-\.
\.......I
r - - \ , - VOO
\.......I ' - - VSS
15 8 15 - ~VDD
5 D --VSS
Maximum Clock Input Rise (1-112 '01
10 UNLIMITED I'S
or Fall Time, ttCL trCL 92CS-32766
15 Fig. tt-Dynamic power dissipation test
Input Capacitance CIN Any Input - 5 7.5 pF circuit and waveforms.
NOTE: Measured at the point of 10% change in output with an output load of 50 pF. RL = 1 kQ to
VOO for tpZL. tpLZ and RL = 1 kQ to VSS for tpZH. tpHZ'
INPUTS
}~.Q'.'~~
o
V55
VDO NOTE'
~ MEASURE INPUTS
SEQUENTIALLY.
vss TO BOTH VDO AND VSS'
CONNECT ALL UNUSED
' - - _ , . - - - - ' INPUTS TO EITHER
NOTE' Voo ORVSS •
V55 ~srNApNu~~OMaINATION VSS
Vss
92CS-2740IRI
92CS-2744IRI 92CS-27402
Fig. t2-Qulescent-device-current test circuit. Fig. t3-lnput-voltage test circuit. Fig. 14-lnput current test circuit.
326
CD4517B Types
III
2.8191
I
1 - - - - - - - - - -1'"',-154°
56 :134~5·~971--------------I 92CM-3276Z
Dimensions and pad layout for CD4517B. The photographs and dimensions of each CMOS chip
represent 8 chip when it is part of the wefer. When the
Dimensions in parentheses are in millimeters cleavage may vary with respect to tho chip fecB for
and are derived from the basic inch dimen- different chips. The actual dimensions of the isolated
sions as indicated. Grid graduations are in chip, therefors. may differ slightly from the nominal
dimensions shown. The user should consider 8 tolerance
mils (I (J3 inch).
of -3 mils to +16 mils applicable to the nominaf
dimensions shown.
327
CMOS Dual Up-Counters

• Medium-speed operatiCln -
CD4518B Dual BCD Up-Counter 6-MHz typical clock frequency at 10 V
CD4520B Dual Binary Up-Counter • Positive- or negative-edge triggering
• Synchronous internal carry propagation
The RCA·CD4518 Dual BCD Up-Counter • 100% tested for quiescent current at 20 V
and CD4520 Dual Binary Up·Counter each
consist of two identical, internally synchro· • Maximum input current of 1 /lA at 18 V
nous 4·stage counters. The counter stages are over full package-temperature range;
D·type flip·flops having interchangeable 100 nA at 18 V and 25°C
CLOCK and ENABLE lines for incrementing CD4518B, CD4520B
on either the positive-going or negative·going • Noise margin(over full package-temperature
FUNCTIONAL CIAGRAM
transition. For single·unit operation the range): 1 Vat VDC = 5 V
ENABLE input is maintained high and the 2 V at VCC = 10 V
counter advances on each positive-going 2.5VatVCC=15V
transition of the CLOCK. The counters are Applications:
cleared by high levels on their RESET lines. • 5-V, 10-V, and 15-V parametric ratings
• Multistage synchronous counting
The counter can be cascaded in the ripple • Standardized, symmetrical output
mode by connecting Q4 to the enable input characteristics • Multistage ripple counting
of the subsequent counter while the CLOCK • Meets all requirements of JECEC Tentative • Frequency dividers
input of the latter is held low. Standard No. 13A, "Standard Specifications
The CD4518B and CD4520B types are sup- for Description of 'B' Series CMOS Devices" TRUTH TABLE
plied in 16-lead hermetic dual-in-line cer- CLOCK ENABLE RESET ACTION
amic packages (D and F suffixes), 16-lead
dual-in-line plastic packages (E suffix), 16-
lead ceramic flat packages (K suffix), and in
.r 1 0 I ncrement Counter
chip form (H suffix).

0
'- 0 Increment Counter
'- X .r
X 0
0
No Change
No Change
..r 0 0 No Change
1 ""'\... 0 No Change
MAXIMUM RATINGS, Absolute-Maximum Values: X X 1 01 thr" 04= 0
DC SUPPLY·VOLTAGE RANGE, (VDD)
(Voltages referenced to VSS Terminan -0.5 to +20 V x - Don't Car. 1 '" High S.... 0= Low State
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to VDO +0.5 V
For T A = -40 to +6Oo C (PACKAGE TYPE E) . . . • . . • .• 500mW CLOCK A I. 16 VDO
For T A = +60 to +85 0 C (PACKAGE TYPE E) Derate Linearlv at 12 mW/oC to 200 mW ENABLE A 2 15 RESET B
For TA = -55 to +100'C (PACKAGE TYPES 0, F, K) • • • . • . . .. 500mW QIA 3 14 Q4B
Q2A 4 13 Q3B
For TA = +100 to +125'C (PACKAGE TYPES D, F, K) Derate Lin.arlv et 12 mW/oC to 200 mW
Q3A 5 12 Q2B
Q4A 6
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package TVpe,)
OPERATlNG·TEMPERATURE RANGE (TA):
loomW
RESET A "
10
9
QIB
ENABLE B
CLOCK B
PACKAGE TYPES D, F, K, H VSS
-55 to + 1250 C
ITOP VIEW)
PACKAGE TYPE E . . . • • . -40 to +85 0 C
92C5-24515
STORAGE TEMPERATURE RANGE (Tstg ) -65 to + 1500 C
LEAD TEMPERATURE (DURING SOLDERING): CD4518B, CD4520B
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from ca,e for 10, max. TERMINAL ASSIGNMENT
DRAIN-YO-SOURCE VOLTAGE (Vosl-V

I
DRAIN-YO-SOURCE VOLTAGE CVoIJ-V

DRAIN~TO-SOURCE VOLTAGE (VDS)-V
Fig. 1 - Typical output low (sink) current Fig. 2 - Minimum output low (sinkJ current Fig. 3 - Typical output high (source) current
328
STATIC ELECTRICAL CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE {Vosl-V

CONDITIONS Value. ai-55, +25, +125 Apply 10 0, F, K, H Packages
CHARACTER- V.lul. It -40, +25, +85 Apply to E Pockoge
ISTIC UNITS
Vo VIN VDO +25
(VI (VI (V) -55 -40 +85 +125 Min. Typ. Mox.
Quieseent Deviee - 0,5 5 5 5 150 150 - 0.04 5
Current. - 0,10 10 10 10 300 300 - 0.04 10
100 Max.
- "A
- 0,15 15 20 20 500 600 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 D,S 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 ,0.9 1.3 2.6
IOlMin. 4 2,8 2.4 34 6.8
1.5 0,15 15 4.2
rnA Fig. 4 - Minimum output high (source) current
Output High 4.6 D,S 5 -0.64 -0.61 -0.42 -0,36 -0.51 -1 - characteristics.
(Source) 2.5 D,S 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 ~
IOHMin, Ij j~: I i ! : :
I
350 AMBIENT TEMPERATURE ITAI· 2!)OC :::: :: ••
13.5 0,15 15 -4.2 -4 -2.8 2.4 -3.4 6.8 f IIIIIIIIIIIII"'':\~;'" :::~~
Output Voltage: - 0,5 5 0.05 - 0 0.05 ~
~
300
''0 ;
lill
I.).
SUf'P\"'f~~mrr !!.: :::! ::;:
!-itt 11; 11:: ,: I ::::::::::::
low·level,
VOL Max.
- 0,10 10 0.05 - 0 0.05
t~ ' 111'!!li! j!!1i i :::! ,:;! :::;,
200 I'" ... .. "
- 0,15 15 0.05 0 0.05 ,j. ,
Output Voltage: - 0,5 5 4.95 4.95 5 -

V ;:
~ 150 I! -! I !!IIi!i;:.. ;:It ;,'! I!!
! If .... . 1: :,' .. ..
;~ 'OUf~tlt~~~'~!~~i*:~,0~V1¥"~'¥'~MtHI1
High·level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 l I~(,'i ;;;; ' ... , ..
Input low 0,5,4.5 - 5 1.5 - - 1.5 ~ 50HtHtHtH~~HtHtHt~lIth!l~iiHtr.tHt~·'~'~'
Voltage, 1,9 - 10 3 - - 3 -#lI l 1 i H ij!! ....
Vil Max.
1.5,13.5 - 15 4 - - 4
V
'0
10 20 40 50
60 70 80 90 100
Input High 0,5,4.5 - 5 3.5 3.5 - - Fig. 5 - Typical propagation delay vs. load
Voltage, 1,9 - 10 7 7 - - capacitance, clock or enable
VIH Min. 1.5,13.5 - 15 11 11 - to output.
Input Current
lIN Max.
- 0,18 18 ±0.1 ±0.1 ±1 tl - ±10- 5 to,1 IlA
LOAD CAPACITANCE fCLJ-pF

load capacitance, reset to output.
: :: : ::
: ::
~ . .1 L[
..
:::
~.~
,/
~ 105
:: : : :: : ffi ~ ...'-I: ti: ,0
~
!P','
< ,,-
,0'
... , ~
s• ...... !
~
-Cs" "so pF
-CL""pF
I; " '0
illJ 11 l 111 lUllPII!!i iPi !ill
10 I~ 20
SUPPLY 'I(ILlM[ IVDDI-Y 0.1 2 .. "1 2 .. "10 2 • "1021 • "1052 ... '10.
FREQUENCY If) - kHr '2a.-~~09
Fig. 7 - Typical transition time vs. load Fig. 8- Typical maximum-clock-frequency Fig. 9 - Typical power dissipation
capacitance. vs. supply voltage. characteristics.
329
RECOMMENDED OPERATING CONDITIONS at TA = 25 o C, Except as Noted.
TEST CIRCUITS
For maximum reliability, nominal operating conditions should be selected 50 that VDD

(V) Min. Max.
Supply·Voltage Range (For T A=Full Package·
3 18 V
Temperature Rangel
5 400
Enable Pulse Width, tw 10 200 - ns
15 140 -
5 200 -
15 70 - Fig. 10 - Dynamic power dissipation.
5 1.5
15 4
5 15
10
- 5 fJ.s
Clock Rise or Fall Time, trCL or tfeL:
15 - 5
5 250 -
Reset Pulse Width, tw 10 110 - ns
15 80 -
DYNAMIC ELECTRICAL CHARACTERISTICS at TA-moc; 92CS~2744UU
Input t r.tjo-20 nl. CL-SO pF, RL-200 Kfl Fig. 11 - Input voltage.

I VDD
V Min. Typ. Max.
Propagation Delay Time, tPHl' tplH: 5 - 280 560 VDD
Clock or Enable to Output

10 - 115 230
15 - 80 160 VDO
ns INPUTS
5 - 330 650 o
Reset to Output 10 - 130 225 Vss
15 - 90 170
5 - 100 200
Transition Time. tTHl. tTlH 10 - 50 100 ns
15 - 40 80
5 1.5 3 -
Maximum Clock Input Frequency.' fCL 10 3 6 - MHz
15 4 8 - Vss
5 lOa 200
Minimum Clock Pulse Width, tw 10 50 lOa ns Fig. 12 - Quiescentdevicecurrenttesrcircuir.
15 35 70
5 - - 15
Clock Rise or Fall Time. tr or tf: fJ.S
10, 15 - - 5
5 - 125 250
Minimum Reset Pulse Width. tw 10 55 110 ns
15 - 40 80 Yeo 1NPUO'
VDO NOT"
'-~
5 - 200 400 o~
MEASURE INPUTS
SEQUENTIALLY.
Minimum Enable Pulse Width. tw 10 100 200 ns Yss TO BOTH liDO AND Vss'
15 70 140 CONNECT ALL UNUSED
INPUTS TO EITHER
Input Capacitance, C(N Any Input - 5 7.5 pF Yeo OR V'S'
Vss
Fig. 13 - Input leakage-current test

oircuit.
330
01 Ql 03 04
Fig. 14 - Decade CQunter (CD45188J logic diagram

for one of two identical counters.
I
* ALL INPUTS PROTECTED BY Vss
COS/MOS PROTECTION
NETWORK
Fig. 15 - Binary counter (CD4520BJ logic diagram

for one of two identical counters.
NtM~~M~h
II 12 13 14 IS 16 17 18
CLOCK -
~* ~* ~LI ~~ I - -
ENABLE
RESET
I l 3 4 • 6 7 • 9 0 I Z • 4 • 6 7 • 9 0
QI
- .1- n-
CD4518 { Q2 - i-
I--
03 t--
04
1 Z
• • •• 7 • 9 10 II 12 13 14 15 a I l
iL-
••
Fig. 16 - Timing diagrams for CD4518B and CD4520B.
01 - l- i-
I-
r-t-
C04520 {
OZ -
l-
I-
l- IL
O. f-
Q4
331
CLDCK
INPUT
r
I
I
I ~o-=b-:~
I
Ic..:;r-~;r--";ir
IL ___ -.:04518/20 _ _ _ _ _ J
Fig. 17 - Ripple cascading of four counters with positive edge triggering.
*NOTE:
FOR SYNCHRONOUS CASCADING,THE CLOCK TRANSITION
TIME SHOUL.D BE MADE LESS THAN OR EQUAL TO THE
SUM OF THE FI)cEO PROPAGATION DELAY AT 15pF AND
THE TRA.NSITION TIME OF THE OUTPUT DRIVER STAGE
FOR THE ESTIMATED CAPACITATIVE LOAD.
Fig.t8 - Synchronous cascading of four binary counters with negative edge triggering.
Dimensions and pad layout for CD4518BH chip. Dimensions and pad layout for CD4520BH chip.

wafsr ;s separated into individual chips, the angle of
cleavage may vary with rflspect to the chip face for
Dimensions in parentheses are in millimeters and are different chips. The actual dimensions of the isolated
derived from the basic inch dimensions as in dicated. chip, therefore, may differ slightly from the nominal
Grid graduations are in mils 00-3 inch). dimensions shown. The user should consider a tolerance
dimensions shown.
332
CD4527B Types
CMOS BCD Rate Features:

• Oascadable in multiples of 4-bits
Multiplier • Set to "9" input and "9" detect output
• 100% test for quiescent current at 20 V
The RCA-CD4527B is a low-power 4-bit digi- • Standardized, symmetrical output
tal rate multiplier that provides an output- characteristics
pulse rate which is the c1ock-input-pulse rate • Maximum input current of l/JA at 18 V over
multiplied by 1/10 times the BCD input. For full package-temperature range; 100 nA at
example, when the BCD input is B, there will 18 V and 250 C
be 8 output pulses for every 10 input pulses. • Noise margin (full package-temperature
This device may be used to perform arith- range) = Voo" 16
metic operations (add, subtract, divide, raise 1 VatVDO= 5V vss·a
to a power), solve algebraic and differential 2 V at VDD = 10 V
equations, generate natural logarithms and FUNCTIONAL DIAGRAM
trigonometric functions, AID and DIA con- 2_5 Vat VDD = 15 V
version, and frequency division. • Meets all requirements of JEDEC Tentative
•
Standard No.13A, "Standard Specifications
For fractional multipliers with more than one
digit, CD4527B devices may be cascaded in
two different modes: the Add mode and the MAXIMUM RATINGS, Absolute-Maximum Values:
Multiply mode. (See Figs.12 and 15).ln the OC SUPPLY·VOLTAGE RANGE. (VODI
Add mode, (Voltages referenced to VSS Terminal) -0.5 to +20 V
Output Rate = INPUT VOLTAGE RANGE. ALL INPUTS -0.5 to VDD +0.5 V
+
(CI k R ) [ 0.1 BCDI 0.01 BCD2
oc ate 0.001 BCD3 + . . . .
+] DC INPUT CURRENT. ANY ONE INPUT
±10mA
o
For T A = -40 to +60 C WACKAGE TYPE E) . . . . . . . .. 500mW
In the Multiply mode, the fraction program- For T A = +60 to +85 0 C (PACKAGE TYPE E) . Derate Linearly at 12 mW/oC to 200 mW
med into the first rate multiplier is multiplied For TA= -55 to +1OO'C (PACKAGE TYPES 0, F. K) . . . . . . . .. 500mW
For TA= +100 to +125'C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mW/oC to 200 mW
by the fraction programmed into the second
one, FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl 100mW
e.g. ~ x .i. = ~ or 36 output OPERATING· TEMPERATURE RANGE (TA):
10 10 100 PACKAGE TYPES 0, F. K, H -55 to +125°C
pulses for every 100 clock input pulses. STORAGE TEMPERATURE RANGE (Tstg ) -65 to +1500 C
The CD4527B types are supplied in 16-lead At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from ca,e for 10 , max.
ceramic dual-in-line packages (D and F
RECOMMENDEO OPERATING CONDITIONS AT TA = 250 C, Except as Noted.
ages (E suffix), 16-lead ceramic flat pack-
ages (K suffix), and in chip form (H suffix). For maximum reliability, nominal operating conditions should be selected so that operation is
VOD LIMITS
Applications: (V) Min. Max.
• Numerical control Supply· Voltage Range (For TA = Full Package·
• Instrumentation 3 18 V
Temperature Range)
• Digital filtering 5 160 -
• Frequency synthesis 10 90 - ns
Set or Clear Pulse Width. tw
15 60 -
5 330 -
Clock Pulse Width. tw 10 170 - ns
15 100 -
5 1.2
"9~ OUT I. I. Voo
C IS Clock Frequency. fCl 10 dc 2.5 MHz
" 15 3.5
CLEAR
SET TO"9"
OUT "
12 CASCADE
INHIBIT IN
Clock Rise or Fall Time. t rCl or tlCl 5,10,15 - 15 IlS
OUT
INHIBIT OUT
(CARRY)
"
10
!CARRYI
STROBE 5 100 -
CLOCK
Vss Inhibit In Setup Time, tsu 10 40 - ns
TOP VIEW 15 20 -
5 240 -
Inhibit In Removal Time, tREM 10 130 - ns
15 110 -
TERMINAL ASSIGNMENT 5 150 -
Sel Removal Time. tREM 10 80 - ns
15 50 -
5 60 -
Clear Removal Time, tREM 10 40 - ns
15 30 -
333
CD4527B Types
LIMITS AT INDICATED TEMPERATURES (Oct

Values at -55, +25, +125 Apply to 0, F, K, H Packages
.
E
CONDITIONS
CHARACTER· Value. at -40, +25, +85 Apply to E Package GATE-TO-SOURCE VOLTAGE ('o'G5)-15 V
ISTIC UNITS
+25
Vo VIN VDD
(vt (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent Device - 0,5 5 5 5 150 150 - 0.04 5 10V
Current, - 0,10 10 10 10 300 300 - 0.04 10 3
100 Max. _. /lA ~
0,15 15 20 20 600 600 - 0.04 20 10
- 0,20 20 100 100 3000 3000 - 0.08 100 6 ,
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - 5 10 15

(Sinkt Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - ORAIN-TO-SOURCE VOLTAGE (V05)-V
IOL Min. -
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8
rnA Fig. 1 - Typical output low (sink)
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - current characteristics.
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
9.5 0,10 10
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low-Level, -
.- 0,10 10 0.05 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min. -
- 0,15 15 14.95 14.95 15
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
VIL Max.
1.5,13.5 - 15 4 - - 4 I
V
Input High 0.5,4.5 - 5 3.5 3.5 - - ORAIN-TO-5OURCE VOLTAGE IVos)-V
Voltage, 1,9 - 10 7 7 - -
VIH Min. Fig.2 - Minimum output low (sink)
1.5,13.5 - 15 11 11 - - current characteristics.
Input Current
0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 /lA
HfH '"m .
liN Max.
DRAIN-lO-SOURCE VOLTAGE (V051-'o' ORAIN-TO-SOURCE VOLTAGE ('0'05)-'0'

-15 -10
Id'! AM"ENT TEMPERATURE 'T A -
AMBIENT TEMPERATURE (TA'-25-C
, -~~ " /
~ ..... I I , 0""
.
GATE-TO-SOURCE VOLTAGE (VGS" -5 V
1
104
! - ~~ 'I
. , ~ ~. t~t,io\"V' .•'
~ , ,Ov
.
2
/
~ 1039
,v
~ ~!
~
~ 10:
.,
CL-~pF
~ ! CL- )!5pF --
10
, ... , ... , ... , ... , ...
10
INPUT FREQUENCY If IN '-kHz
IIII
10' 10'
92CS-29155
Fig.3 - Typical output high (source) FigA - Minimum output high (source) Fig.5 - Typical dynamic power dissipation as a
current characteristics. current characteristics. function of input frequency.
V~NP(JU' :~;;,,:c,::,
Vss
'.
TO 80TH Voo AND VSS·
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS·
Vss
LOAD CAPACITANCE (CLI- pF
LOAD CAPACITANCE (CLI-pr 9?CS-24l22
Fig. 6 - Typical propagation delay time as a Fig.7 - Typical transition time as a function of Fig.B - Input current test circuit.
function of load capacitance (Clock load capacitance.
or Strobe to Out).
334
CD45278 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C:

Input tr.q = 20 ns. CL = 50 pF. RL = 200 kn

(V) Min. Typ. Max.
5 - 110 220
Propagation Delay Time. tpHL. tplH -
10 55 110
Clock to out 92CS-27044IRI
15 - 45 90
ns
5 - 150 300 Fig.9 - Input voltage test circuit.
Clock or Strobe to Out 10 - 75 150
15 - 60 120
Clock to Inhibit Out 5 - 320 640

10 - 145 290
High level to low level INPUTS
15 - 100 200 o
ns Vss
-
•
5 250 500
(
low level to High level 10 - 100 200
15 - 75 150
5 - 380 760
Clear to Out 10 - 175 350
15 - 130 260
ns
5 - 300 600
Clock to "9" or "15" Out 10 - 125 250
15 - 90 180 Fig. to - Quiescent device current test circuit.
5 - 90 180
Cascade to Out 10 - 45 90 VDD
15 - 35 70 ns
5 - 130 260
Inhibit In to Inhibit Out 10 - 60 120
15 - 45 90
5 - 330 660
Set to Out 10 - 150 300
15 - 110 220
ns
5 - 100 200
Transition Time. tTH l' tTlH 10 - 50 100
15 - 40 80 92C5-29157
5 1.2 2.4 -
Maximum Clock Frequency, fCl 10 2.5 5 - MHz Fig.tt - Dynamic power dissipation test circuit.
15 3.5 7 -
5 - 165 330 APPLICATIONS
15 - 50 100
MOST SIGNIFICANT L.EAST SIGNIFICANT
5 - - 15 DIGIT DIGIT
Clock Rise or Fall Time. trCl' tlCl 10 - - 15 IlS DRM([) A ORM®
15 - - 15 OUT
5 - 80 160 OUr
- INH.
Minimum Set or Clear Pulse Width, tw 10 45 90 OUT
15 - 30 60
ns
5 - 50 100
Minimum Inhibit In Setup Time, tsu 10 - 20 40
15 - 10 20
5 - 120 240
_ _ _ _ _ _ _ _-.J
Minimum Inhibit In Removal Time, CLOCK<>~
10 - 65 130
tREM 15 - 55 110
ns
5 - 75 150
Minimum Set Removal Time, tREM 10 - 40 80
15 - 25 50 TIMING DIAGRAM SHOWING ONE OF FOUR OUTPUT
PULSES CONTRIBUTED BY DRM (5) TO OUTPUT FOR
I
5 - 30 60 EVERY 100 CLOCK PULSES IN FOR PRESET No.94.
92CS-24911RI
Minimum Clear Removal Time, T REM 10 - 20 40 ns
15 - 15 30 Fig. 12 - Two CD4527B's cascaded in the "Add"
Input Capacitance, CIN Any Input - 5 7.5 pF
335
CD45278 Types
*
STROBE *
CASCADE 0123456789012]4
to 12 CLOCI< flIlJUUU11lJlIl
O. .J1.fLJlJU1J1..
Ob~
O'~
·"O--..C-~f>---......~r'\
INHIBIT IN
O'~
RI~
R'~
R'~
R4~
OUTPUT (PIN 61 n n
A ENABLED ----1 L - - - - . . . . . J L
B ENABLED
C ENABLED
D ENABLED
INH. OUT U
OUPUT!PIN61
(PRESET No. OF 11
n! n
----l~L
(PRESET No. OF 21
(PRESET No. OF 31
IPRESET No· OF 41 ~
*13 I
CLEAR IPRESETNQ.OF51 ~
I
Fig. 13 - Logic diagram. (PRESET No. Of 61
I
(PRESET No· Of 11
(PRESET No. OF 81 JUlflILJlJlJlJU

IPRESETN.·O'., ~
I 92CM-<'4915
Fig. 14 - Timing diagram (See Logic Diagram).
DRM I DRM 2
o
OUT OUT
OUT !roT
INH. INH·
OUT OUT
"g"
ClOCKO..... --------.J
Dimensions and Pad Lavout for CD4527BH

Fig. 15 - Two CD4527S's cascaded in the
The photographs and dimensions of each CMOS chip nMultiply" mode with a preset number
represent 8 chip when it ;8 part of the wafsr. When the

wafer Is separated into individual chips, the angle of
cleavage may vafy with respect to th" chip fBce for of 36 (!!....x.!...=
10 10 100 •
~)
are derived from the basic inch dimensions as in- different chips. The actua' dimensions of the isolated
chip, therefore. may diller slightly from the nominal
dimensions shown.
336
CD4527B Types
TRUTH TABLE
INPUTS OUTPUTS
Number of Pulses or Number of Pulses or
Input Logic Level Output Logic Level
(0 = Low; 1 = High; X = Don't Care) IL = Low; H = High)
o C B A CLK INH STR CAS CLR SET OUT OUT INH "9"
IN # # OUT OUT
0 0 0 0 10 0 0 0 0 0 L H 1 1
0 0 0 1 10 0 0 0 0 0 1 1 1 1
0 0 1 0 10 0 0 0 0 0 2 2 1 1
0 0 1 1 10 0 0 0 0 0 J J 1 1
0 1 0 0 10 0 0 0 0 0 4 4 1 1
0 1 0 1 10 0 0 0 0 0 5 5 1 1
0 1 1 0 10 0 0 0 0 0 6 6 1 1
0 1 1 1 10 0 0 0 0 0 7 7 1 1
1 0 0 0 10 0 0 0 0 0 8 8 1 1
1
1
1
0
0
0
0
1
1
1
0
1
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
8
9
9
8
9
1
1
1
1
1
1
I
1 1 0 0 10 0 0 0 0 0 8 8 1 1
1 1 0 1 10 0 0 0 0 0 9 9 1 1
1 1 1 0 10 0 0 0 0 0 8 8 1 1
1 1 1 1 10 0 0 0 0 0 9 9 1 1
X X X X 10 1 0 0 0 0 t t H t
X X X X 10 0 1 0 0 0 L H 1 1
X X X X 10 0 0 1 0 0 H • 1 1
1 X X X 10 0 0 0 1 0 10 10 H L
o X X X 10 0 0 0 1 0 L H H L
X X X X 10 0 0 0 0 1 L H L H
* Output same as the first16 lines of this truth table (depending on values of A, B, C, OJ.
tDepends on internal state of counter.
#Clear and Set Inputs should not be high at the same time; device draws increased quies-
cent current when in this non-valid state.
337
CD4532B Types
CMOS 8-Bit Priority

Encoder Features:
• Converts from 1 of 8 to binary
High·Voltage Types (20·Volt Rating) • Provides cascading feature to handle any number of inputs
• Group select indicates one or more priority inputs
The RCA·CD4532B consists of combination· • Standardized, symmetrical output characteristics
a) logic that encodes the highest priority • 100% tested for quiescent current at 20 V '0
input (D7·DO) to a 3-bit binary code. The • Maximum input current of 1 f.!.A at 18 V
eight inputs, D7 through DO, each have an over full package temperature range;
assigned priority; D7 is the highest priority
and DO is the lowest. The priority encoder is 100 nA at 18 Vand 25°C
inhibited when the chip·enable input E I is • Noise margin (full package· temperature
low. When EI is high, the binary representa· range):
tion of the highest· priority input appears on 1 VatVDD= 5V FUNCTIONAL DIAGRAM
output lines 02·00, and the group select 2VatVDD=10V
line GS is high to indicate that priority inputs 2.5VatVDD=15V
are present. The enable·out (EO) is high
• 5-V, 10·V, and 15-V parametric ratings
when no priority inputs are present. If any
one input is high, EO is low and all cascaded • Meets all requirements of JEDEC Tentative
lower·order stages are disabled. Standard No. 13A, "Standard Specifications
for Description of 'B' Series CMOS Devices" RECOMMENDED OPERATING CONDITIONS
The CD4532B types are supplied in IS-lead For maximum reliability, nominal operating condi-
Applications: tions should be selected so that operation is always
• Priority encoder within the fol/owing ranges.
and F suffixes), IS-lead dua(-in-line plastic
packages (E suffix), IS-lead ceramic flal • Binary or BCD encoder (keyboard encoding) Characteristic Min. Max. Units
packages (K suffix), and in chip form (H • Floating point arithmetic Supply Voltage
suffix). Range (for T A- 3 18 V
Full Package
Temp. Range)
MAXIMUM RATINGS,Absolute·Maximum Values:

DC SUPPLY·VOLTAGE RANGE, (V DD )
(Voltages referenced to VSS Terminal) -{l.S to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS -{l.S to VDD +0.5 V
POWER DISSIPATION PER PACKAGE (PO): 04 I. 16 VOO
For T A = -40 to +60 oC (PACKAGE TYPE E) . • • . • . • .. 500mW 05 2 15 EO
For T A = +60 to +8S oC (PACKAGE TYPE E) Derate Linearly at 12 mW/oC to 200 mW 06 14 GS
For T A = -5510 +loo·C (PACKAGE TYPES 0, F, K) . . • . • . • .. 500mW 07 03
Derate Linearly at 12 mW/oC to 200 mW 13)
For TA= +100 10 +125·C (PACKAGE TYPES 0, F, K) EI 12 02
DEVICE DISSIPATION PER OUTPUT TRANSISTOR 02 II 01
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl 100mW 01 IP 00
OPERATING·TEMPERATURE RANGE (TAl: VSS 9 - 00
PACKAGE TYPES 0, F, K, H -55 to +125°C
PACKAGE TYPE E . -40 to +85 0 C (lOP VIEW)
STORAGE TEMPERATURE RANGE (T stg ) -65 to +1500 C 92CS·24596RI
LEAD TEMPERATURE (DURING SOLDI'RING): TERMINAL ASSIGNMENT
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mml from case for lOs max.
ORAIN-lO-SOURCE VOLTAGE (Vosl-V

AMBIENT TEMPERATURE (TAI-e·c A"BIE.N~ c~"':"R~c~i 1I i:~
, -15 -10 -5
AMBIENT TEMPERATURE ITAI~25°C
lli:I:±±±±P.:G':!AT±'E--':T~O-~SOURCE
I~I
VOLTAGE (VGSlo-5V
IIIlit.
I i
I m :
: -IOV
H •
10V
+-. h
~ I~
S 10
-15V
I~
~
5 ,
5 10 15
DRAIN-lO-SOURCE VOLtAGE (VosJ-V
DRA~N-TO-SOURCE voLTAGE
I
:VosJ-V
Fig. 1 - Tvpical output low (sink) current Fig. 2 - M;nimum output low (sink) current Fig. 3 - Typical output high (source) current
338
CD4532B Types
D"AIN-TO-SOURCE VOLTAGE IVDSI-V
ISTIC UNITS
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent Device - a,s 5 5 5 150 150 - 0.04 5
Current, - 0,10 10 10 10 300 300 - 0.04 10
jJ.A
IDD Max.
- 0,15 15 20 20 600 600 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6
IOLMin.
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 Fig. 4 - Minimum output high (source) current
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA characteristics.
Output High
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 1.6 3.2
Current, -1.6 -1.5 -1.1 -0.9 2.6
9.5 0,10 10 1.3
IOH Min.
Output Voltage:
Low·Level.
13.5
-
0,15
0,5
15
5
-4.2 -4
0.05
2.8 2.4 3.4
-
6.8
a 0.05
• AMBIENT TEMPERATURE (TA'-
: LOAD CAPAC~TAMC~ (Cll- 50 pF
e-c
.
I
- 0,10 10 0.05 - 0 0.05
VOL Max.
- 0,15 15 0.05 0 0.05
V
Output Voltage: - 0.5 5 4.95 4.95 5 -
High·Level, - 0.10 10 9.95 9.95 10
VOH Min.
- 0.15 15 14.95 14.95 15
Input Low 0.5,4.5 - 5 1.5 - 1.5
Voltage. 1.9 - 10 3 3
VIL Max.
1.5,13.5 - 15 4 4 5 7.5 10 12.5 15 11.' 20
V SUPPLY VOLTAGE (11001- V
Input High 0.5,4.5 - 5 3.5 3.5 - - Fig. 5 - Typical propagation delay (Dn to Om)
Voltage,
VIH Min.
1.9 - 10 7 7 - - VI. supplV voltage.
1.5,13.5 - 15 11 11 -
I nput Current
0.18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 jJ.A AMBIENT ~E"PERATURE 1T,,}-25·C
liN Max.
DYNAMIC ELECTRICAL CHARACTERISTICS at T A=25 0 C; CL =50 pF,

Kn
Input tr,tf= 20 ns, R L =200
CHARACTERISTIC
TEST CONDITIONS
VDD
LIMITS
ALL TYPES UNITS
,0'
.
,
30 40 50 60 70 90 100
VOLTS TYP. MAX. 92CS-Z65&S
Fig. 6 - Typical propagation delay (E, to GS, E, to EoJ

Propagation Delay Time tpHL' tpLH 5 110 220 vs, load capacitance.
EI to EO, EI to GS 10 55 110
15 45 85
5 170 340
EI to Om, Dn to GS 10 85 170 ns
15 65 125
5 220 440
Dn to OM
10 110 220
15
'0'
85 160
'"
5 100 200
Transition Time tTH L, tTLH 10 50 100 ns
'0
15 40 80 ~ ~ ~ ~ ~ ro 90 90 00
LOAD CAPACITANCE (CLJ- pF 92CS-26S1i4
Input Capacitance CI N Any Input 5 7.5 pF Fig. 7 - Typical propagation delay (Dn to Om)
339
CD4532B Types
1..0AO (;APA(;ITANCE (CL1-pF
Fig.9 - Typical transition time VI.

load capacitance.
. IO~
I' 10:
,
AMBIENT TEMPERATURE (TAl' 2S·C
~ 'l- I -
'r- r---
SUPPLY VOLTAGE 1100'" II
~ 1036
LOAD CAPACITANCE {CLI·50pF
~ ,
~
" 'r- r---
i
10'
.. 10V
50pF
7
IYr V
r:K"
~
OV
"~ 7
'v
,,
10
OOp'
~
,
I
10:2 468'OZ2 468 10 , 2 46a lO4
fREQUENCY ltl-kHz
Fig. to - Typical dynamic power dissipation

Voo 92CL-26:56IRI VS. frequency.
£\-
Fig.
Vss
*ALL
8 - CD4532 logic diagram.

INPUTS PROTECTED BY
TRUTH TABLE
Input Output Fig.11 - Dynamic power dissipation
EI 07 06 05 04 03 02 01 00 GS 02 01 00 EO test circuit.
0 X X X X X X X X 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 1
1 1 X X X X X X X 1 1 1 1 0
1 0 1 X X X X X X 1 1 1 0 0 INPUTS
o
1 0 0 1 X X X X X 1 1 0 1 0 Vss
1 0 0 0 1 X X X X 1 1 0 0 0
1 0 0 0 0 1 X X X 1 0 1 1 0
1 0 0 0 0 0 1 X X 1 0 1 0 0
1 0 0 0 0 0 0 1 X 1 0 0 1 0
1 0 0 0 0 0 0 0 1 1 0 0 0 0
X = Oon't Care Logic 1 '= High Logic 0'= Low
340
CD4532B Types
APPLICATIONS
G51-'1.::......----,
INPUT(JVOO
OUTPUTS 015 ---+I
V,H I 02 6
:-- .~
I
I
Vil. J I
NOTE: I .....- - - - - - - - - 03'
TEST ANY ONE INPUT, 08--........J"'-jC
Vss WITH e:[~~~~TS AT
)-"-+---G5'
Fig. 13 - Input voltage test circuit. 07---~

I
I
I
I '-----r-L _____ )-"''-'----01·
I
00-----"'-1
)-'-'-"---00'
92C5- 26369R I L-_ _ _ _ _ _ _ _ _ _ _ EO'

Yeo 1NPUOS
Veo NOTE
~ MEASURE INPUTS
Fig. 15 - 16-/evel priority encoder.
o ~ SEOUENTlA.'Y.
Vss TO BOTH "DO AND Vss·
CCNNECT ALL UNusm
INPUTS TO EITHER
Veo CRYss·
VSS
1/4 CD4071
09----.--\
)--.....- - - - - - - 0 3 ·
Fig. 14 - Input current test circuit. 08----+-1
07
69-77
r----ir------ 02'
1--+=--=-- 01'
J"" DO
Input
TRUTH TABLE
92CS-26370RI
00'
Output
.1
92CS-26337RI
09 08 07 06 05 04 03 02 01 DO GS 03' 02' 01' 00'
1 X X X X X X X X X 0 1 0 0 1
0 1 X X X X X X X X 0 1 0 0 0
Dimensions in parentheses are in millimeters. and are 1 X X X X X X X 1 0 1 1 1
0 0
derived (rom the basic inch dimensions as indicated. 0 0 0 1 X X X X X X 1 0 1 1 0
Grid graduations arB in mils (10- 3 inch}. 0 0 0 0 1 X X X X X 1 0 1 0 1
The photographs and dimenSions 01 each CMOS chip 0 0 0 0 0 ) X X X X 1 0 1 0 0
reprftsent a chip when it is part of the wafer. When the
wafer is separaled into individual chips, the angle of 0 0 0 0 0 0 1 X X X 1 0 0 1 1
cleavage may vary with respect to the chip face for 0 0 0 0 0 0 0 1 X X 1 0 0 1 0
different chips. The actual dimenSions of the Isolated 0 0 0 0 0 0 0 0 1 X 1 0 0 0 1
chip, therefore, may differ slightly from the nomina' 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
dimensions shown. The user should consider. tolerance
of -3 mils to +16 mils applicable to the nomlnaf X::; Don't Care logic 1 := High logic Os low
dimensions shown.
Dimensions and pad layout for CD4532BH. Fig. 16 - 0-to-9 keyboard encoder.
341
CD45368 Types
CMOS Programmable Timer CLOCK
INHIBIT

1
.a-BYPA:Srl;.;4..L..=_3:.L ,'L:r ~
The RCA-CD4536B is a programmable timer Features: ~~{:ell ,: OUT I RT
J
consisting of 24 ripple-binary counter stages_ .24 flip-flop stages -- counts from 2° to 224
~d 5 ___
The salient feature of this device is its men 012 OUT 2
• last 16 stages selectable by BCD select code
flexibility. The device can count from 1 to SET I 13 DECODE
• Bypass input allows bypassing first 8 stages R£SET 2 OUT
224 or the first a stages can be bypassed to
allow an output, selectable by a 4-bit code,
• On-chip RC oscillator provision
• Clock inhibit input VOo -16
"
MONO J:N '--_ _---'
92CS-31718
from anyone of the remaining 16 stages. It
• Schmitt-trigger in clock Iine permits operation with very vSs,s
can be driven by an external clock or an RC long rise and fall times
oscillator that can be constructed using on- FUNCTIONAL DIAGRAM
• On-chip monostable output provision
chip components. Input INI serves as either • Typical fCl = 3 MHz at VDD = 10 V
the external clock input or the input to the • Test mode allows.fast test sequence
on-chip RC oscillator. OUTI and OUT2 are • Set and reset inputs
connection terminals for the external RC
• Capable of driving two low power TTL
components. In addition, an on-chip mono- loads, one lower-power Schottky load, or
stable circuit is provided to allow a vari- two HTl loads over the rated temperature RECOMMENDED OPERATING CONDITIONS
able pulse width output. Various timing range
functions can be achieved using combi- For maximum reliability, nominal operating
• Standardized, symmetrical output charac-
nations of these capabilities. teristics conditions should be selected so that operation
A logic 1 on the a-BYPASS input enables a is always within the following ranges:
bypass of the first a stages and makes stage 9 • 5-V, 10-V, and 15-V parametric ratings CHARACTERISTIC liMITS UNITS
the first counter stage of the last 16 stages. • Meets all requirements (If JEDEC Tentative Min. Max.
Selection of 1 of 16 outputs is accomplished Standard No. 13A, "Standard Specifi-
by the decoder and the BCD inputs A, B, C cations for Description of 'B' Series Supply-Voltage Range
and D. MONO IN is the timing input for the CMOS Devices" (For TA = Full
on-chip monostable oscillator.· Grounding of Package Temperature
the MONO IN terminal through a resistor of Range) 3 18 V
10K ohms or nigher, disables the one-shot divides the 24-stage counter into three a-stage
circuit and connects the decoder directly to sections to facilitate a fast test sequence.
the DECODE OUT terminal. A resistor to
V DD and a capacitor to ground from the
hermetiG..dual-in-line ceramic packages (0
MONO IN terminal enables the one-shot cir-
cuit and controls its pulse width.
A fast test mode is enabled by a logic 1 on packages (K suffix), and in chip form (H DECODE OUT SELECTION TABLE
a-BYPASS, SET, and RESET. This mode suffix). NUMBER OF STAGES IN
DIVIDER CHAIN
DC B A
8-BVPASS=O 8-BYPASS=l
o0 o 0 9 1
000 1 10 2
001 0 11 3
o0 1 1 12 4
0 1 o 0 13 5
DC SUPPLY·VOL TAGE RANGE, (VDDI
IVoltages referenced to VSS Terminal) -0.5 to +20 V 0 1 o 1 14 6
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to VDD +0.5 V 0 1 1 0 15 7
DC INPUT CURRENT, ANY ONE INPUT ±10 mA 0 1 1 1 16 8
POWER DISSIPATION PER PACKAGE (POl:
For TA = -40 to +60 0 C IPACKAGE TYPE EI . . • . . . . .. 500 mW 1 0 o 0 17 9
For T A = +60 to +850 C (PACKAGE TYPE EI . . Derate Linearly at 12 mWloC to 200 mW 1 0 o 1 18 10
For T A = -55 to +100'C (PACKAGE TYPES 0, F, K) . . . • • • . . • • • • • • • . 500 mW
ForTA = +100 to +125'C (PACKAGE TYPES 0, F, K) • • • • • Derate Linearly at 12 mWI"C to 200 mW
1 o 1 0 19 11
DEVICE DISSIPATION PER OUTPUT TRANSISTOR 1 o 1 1 20 12
FOR TA = FULL PACKAGE·TEMPERATURE RANGE IAII Package Typesl 100 mW 13
1 1 0 0 21
OPERATING·TEMPERATURE RANGE IT AI:
PACKAGE TYPES 0, F, K, H . . . . . . . . . . • . . . . . . . . . . . -55 to +125'C 1 1 0 1 22 14
PACKAGE TYPE E • . • • . . • • . . . . . . • • • • • • • • . • • -40 to +85' C 1 1 1 0 23 15
STORAGE TEMPERATURE RANGE ITstgl -65 to +IS00 C 1 1 1 1 24 16
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 105 max. +26S0C 0= low level 1 = High level
342
CD4536B Types
CHARAC· CONDITIONS
LIMITS AT INDICATED TEMPERATURES lOCI
Values at -55, +25, +125Applyto D, F, K, H Packages I
~
+25 S
Vo VIN VDO
IVI IV) IVI -55 -40 +85 +125 Min. Typ. Max.
Quiescent
- 0,5 5 5 5 150 150 - 0.04 5
Device - 0,10 10 10 10 300 300 - 0.04 10
IJA
Current, - 0,15 15 20 20 600 600 - 0.04 20
100 Max.
- 0,20 20 100 100 3000 3000 - 0.08 100
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Output Low Fig. 2- Typical output low (sink) current
(Sink) Current 0.5
IOL Min.
0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - characteristics.
1.5 0,15 15 4.2 4 2.8 .2.4 3.4 6.8 -
Output High
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - m,tl
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -

Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -·2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05

Low·Level, - 0,10 10 0.05 - 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05 V
Output - 0,5 5 4.95 4.95 5 -
Voltage: - 0,10 10 9.95 9.95 10 - DRAIN-TO-SOURCE VOL.TAGE (VOs)-Y
High·Level,
VOH Min. - 0,15 15 14.95 14.95 15 - Fig. 3-Minimum output low (sink) CUfl1lnt
Input Low
0.5,4.5 - 5 1.5 - 1.5 characteristics.
Voltage 1,9 - 10 3 - - 3 DRAI~-TO-SOURCE VOLTAGE IVosI-Y

VIL Max. 1.5,13.5 - 15 4 - - 4 V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIHMin.
1.5,13.5 - 15 11 11 - -
Input Current ±10- 5 ±0.1 IJA
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 -
Fig. 4- Typical output high (source) current

B-BYPASS characteristics.
DRAiN-TO-SOURCE VOLTAGE (Vos)-Y
92CS-!O!73
Fig. 1 - Functional block diagram. Fig. 5-Minimum output high (source) current
characteristics.
343
CD4536B Types
SET
CLOCKINH 7
"*"INPUTS PROlECTEO BY COSIMOS

PROTECTION NETWORK
EfVOO
~VSS
"S
"T
cc;_~=~u~NII 4 }--t-----------<><.,
- OUT 2 5 }--t-------------,
92CL-31725
L-_________________________________________ ,G
Fig.6 - Logic diagram for CD45368 [continued on next page].
344
CD4536B Types
DETAil FOR I CLEN(CL DlS FOR FF9 AtlOFF251 OETAll FOR

FF3-S, 11-16,17-24 Voo ~. HI, FF2. FFIO,FF9, FF25
r------------------R~i~J~ ~I
l-p ,
I
I
~~=J:::==I-"~I
- - - - - - +-------'-
- - - ~ fi FF2,I0
iCLii
CL
FF9
FF25
A------------------~~ -·FFI :AS SHOWN EXCEPTQ NOT BROUGHT OUT
I FF9:SAME AS FFI EXCEPTQ .15 BROUGHT OUT AND Q,"Q' GO TO

TGf AND TGe RESP.
i
FF2;FF10: DELETE TGe,TGf,AND INVfiFEEO-n TO Di
DELETE ClEN ,CLOIS
FF2':lWa AND INVd BECOME 2-INPUT NAND GATES, WITH
~~~~~O~N:~T~N~~JiE~~ L~JEOJ~u~U~~ TGe
--------- ----
92CL-31725RI
G--~--~~--~--------------------------------------~
Fig,6 - Logic diagram for CD45368 [continued from previous page),
345
CD4536B Types
DYNAMIC ELECTRICAL CHARACTERISTICS, at TA =25°C, Input t,. tf =20 ns,
CL = 50pF, RL= 200kQ
CHARACTERISTIC VDD LIMITS

UNITS
(V) Min. Typ. Max.
Propagation Delay Times: 5 - 1 2
Clock to a1, 8-Sypass High 10 - 0.5 1 jAS
tpHL, tpLH 15 - 0.35 0.7
Clock to a1, 8-Bypass Low 5 - 2.5 5
tpHL, tpLH 10 - 0.8 1.6 ,..s
15 - 0.6 1.2
Clock to a16; TpHLtpLH 5 - 4 8
LOAD CAPACITANCE CCL)-IIF taCS-U"",
10 - 1.5 3 jAS Fig. 7- Typical propagation delay time as B function

15 - 1 2 of load capacitance (CLOCK to a"
8·8YPASS high).
an to Cn+ 1, tpHL, tpLH 5 - 150 300
10 - 75 150 ns
15 - 50 100
Set to an' tpLH 5 - 300 600
10 - 125 250 ns
15 - 80 160
Reset to an, tpHL 5 - 3 6
10 - 1 2 ,..s
15 - 0.75 1.5
Transition Time, tTHL, tTLH 5 - 100 200
10 - 50 100 ns
15 - 40 80
Minimum Pulse Widths: 5 - 200 400
Clock 10 - 75 150 ns
15 - 50 100
Set 5 - 200 400
10 - 100 200 ns
15 - 60 120
Reset 5 - 3 6
10 - 1 2 jAS LOAD CAPACITANCE (CLJ-pF 92CS-3211S9
15 - 0.75 1.5 Fig. 8- Typical propagation delay time as 8 function

of. load capacitance (CLOCK to a"
Minimum Set Recovery Time, 5 - 2.5 5 8·BYPASS low).
10 .- 1 :2 ,..s
15 - 0.6 1.6
Minimum Reset Recovery Time, 5 - 3.5 7
10 - 1.5 3 ,..s
15 - 1 2
Maximum Clock Pulse Input 5 0.5 1· -
Frequency, fCL 10 1.5 3 - MHz
15 2.5 5 -
Maximum Clock Pulse Input 5,10,15
Rise or Fall Time, t r , tf Unlimited ,..s
SET 18 VDD
RESET 2 IS MONO IN
J:N I 3 14 DSC INHIBIT
OUT I 4 13 DECODE DUT
OUT 2
B -BYPASS
CLOCK INHIBIT
5
•
7
12
II'
10
g}
B
BINARY
SELECT LOAO CAPACITANCE leLI - pF
.,es-uno
VSS 8 9 A Fig. 9-Typlcal propagation delay time as a
TOP VIEW S2CS':S1716 function of load capacitance (CLOCK
Terminal Assignm,nt ; to QlI,. 8·BYPASS high).
346
CD4536B Types
102 2 4 G8103 '2. .. 6~O" 2 .. GBIOS

LOAD CAPACITANCE (CLI-pF 9ZC'-32171 SUPPLY 'IOLTAGE I 'IDol - v 92CS~32772
EXTERNAL CAPACITANCE ICx)- pF
Fig. 10-Typicai propagation delay time as a Fig. II-Typical RCoscillator Irequency de·
function of load capacitance IQN to viation as a lunction of supply
EXTERNAL RESISTANCE eRte,--lItl 92CS-32773
QN+ll. voltage.
Fig. 12- Typical RC oscillator frequency devia·
lao Rte • 5611a
tion as a function of time constant
RE -120 lin. resistance and capacitance.
7.5 Cx -1000 pF
e'loOI -!5V
• .0 4 SUPPLY 'IOLTAGE 1VOO)-5 V
'2. RS· 2Rlc
2 .•
I
15V
'0 v
10V
I5V ...
•
10 2 8
s
b 2~~1+~r-l-H~r-~~~hl~'H-~~~
-2.5
j 10! R'IC~I mn
-'0 .V
~ .
-7.5 ~ 2~-+1+~~-H~f-~R-+-t+H-~~~
-10.0
-.0 .0 ~:50 50 100 1150
AMBIENT TEMPERATUREITA)-·C AMBIENT TEMPERATURE eTA) _·c 92CS.3211~ 2
0.1
Fig. 13-Typical RCoscillator frequencydevia· Fig. 14-Typical RC oscillator frequency devia-
2 4 .810 2 .. '~02 2 468103 2 .. 6810" '2. 4 .~o!S
tion as a function of ambient temper' tion as a function of ambient
EXTERNAL CAPACITANCE lex)~pF 92CS~3277.
ature IRS = 0). temperature IRS = 120 k!J.I.
Fig. 15- Typical pulse width as a function of
.. SUPPLY VOLTAGE ('100)-10 'I
external capacitance (VDD 5 VI. =
2 RS - Ztc
Functional Test Sequence
Inputs Outputs Comments

Decode Out
1n1 Set Reset 8-Bypass Q1thru Q24 All 24 steps are In Reset mode
1 0 1 , 0
1 1 1 1 0 Counter is in three 8-stage section In
D.' 10114
,
0 1 , , 0
parallel mode
First "'" to "0" transition of clock
2 .. "10 2 .. "02 2 .. '~03 '2. .. '~o" 2 .. "OS
EXTERNAL CAPACITANCE (Cxl-pF
FIg. 16- Typical pulse width as a function of
92CS-32777
-
0
, , , 255 "'" to "0" transitions are clocked in
external capacitance (VDD = 10 VI. the counter
-
00>: , , , ,
·
AMBIENT TEMPERATURE (TAl - 2S-C
SUPPLY VOLTAGE (Vool -15 v 0 Th.e 255 "'" to "0" transition
, As· 2R te Counter converted back to 24 stages In
, series mode
·,
102,
0 0 0 0 Set and Reset must be connected
t together and simultaneously go from "'"
I
, ,
.,
~ to "0"
i 10. ,Rtc -lmO 0 0 0 In, Switches to a"'"
"'~ 0 0 0 0 0 Counter Ripples from an all '" state to
,. ,
iI an all "0" state
,0\"
D.'
·, , .. , ... , ..
S
'a.
~o ~O'
, 'S
'0" 00>
FUNCTIONAL TEST SEQUENCE
Test Function (Figure 23) has been in-
loaded in each of the 8-stage sections in
parallel. All flip-flops are now at a "1".
The counter is now returned to the normal
,0'
ElCTERNAL. CAPACITANCE (C){}~pF
cluded for the reduction of test time re- 24-steps in series configuration. One
92es-S2771 quired to exercise all 24 counter stages. more pulse is entered Into In1 Which will
Fig. 17-Typlcal pulse width as a function of This test function divides the counter Into cause the counter to ripple from an all "1"
external capacitance (VDD = 15 VI. three 8-stage sections and 255 counts are state to an all "0" state.
347
CD4536B Types
92CS-32782
FIg. 22-lnput waveforms for switching-time
test circuit.
Fig. 18- Typical transition time as a function

8 V55
92CS-3278S
Fig. 20-Dynamic power dissipation test cir-

cuit and waveform.
,..,..----'--......0·00
Fig. 23-Functlonal test circuit.
NOTE:
MEASURE INPUTS
0.12 46B 1 2 4 6 8 10 Z 46°1022468103
SEQUENTIALLY,
PULSE INPUT FREQUENCY (kHz) 9ZCS- 32779 TO BOTH Voo AND Vss'
V55
19 - Typical dynamIc power dissipation as a CONNECT ALL UNUSED
Fig. 21-Switching tIme test circuit. L-_...,-_--' INPUTS TO EITHER
function of input pulse frequency.
Voo OR VSS'
Vss 92CS-27402
Fig. 24-lnput-current test circuit.
TRUTH TABLE
INl SET RESET CLOCK OSC oun OUT2 DECODE

INH INH OUT
J J ~
0 0 0 0 No
Change
Advance
~ 0 0 0 0
~ J to Next
State 92CS-21441RI
1 0 0 0 0 1 1 Fig. 25-lnput-voltage test circuit.

X
X 0 1 0 0 0 1 0
No
X 0 0 1 0 INPUTS
Change o
V55
No
0 0 0 0 X 0 1
Change
Advance
1 0 0 0 J ~ J to Next
State
DO
V55
0= Low Level 1 = High Level X = Don't Care
Fig. 26-Quiescent-device current test cIrcuIt.
348
CD4536B Types
APPLICATIONS
VDD . -_ _ _ _-+Voo VDD
OUT I RS
A A OUT I
A C
B B B OUT I
C lite
SET D
SET
RESET OUT 2 SET
RESET OUT2
RESET OUT 2
8-BYPASS a-BYPASS START B-BYPASS
C INH
-1' r-
C INH
MONO-IN
DECODE
OUT DE811¥E ...fL DECODE
OUT
Lt+---lXNI
92CS-3I726 LL~===+'''s~S;---'92CS-31727RI
'-------~ VSS "'tRICC
Fig. 27- Time interval configuration using Fig. 28- Time Interval configuration using ex- RS2:2Rtc
external clock; set and clock inhibit ternal clock; reset and output mono- '--_ _ _ _ _ _ _ _ _- ' flNHz t
functions. stable to achieve a pulse output. ~1~~~:6s
"no
92CS-31728RI
Fig. 29- Time interval configuration using on-

chip RC oscillator and reset input to initiate
II
Voo time Interval.
16
9A
10 B OUTI
"C
12 0 C04536B
I SET
1.. 2 RESET OUT 2
6 a-BYPASS
DCBA
OOOOC+21
OOOU+41-+--...JA'-
OOIO(.81-+-----~''-
Jl NOTE,
SHADED PULSE REPRESENTS DECODE OUTPUT
IN MONOSTABLE MODE. IF AN OUTPUT PULSE
IS REQUIRED I FULL-CQUNT-DOWN AFTER
REMOVAL OF RESET PULSE, SEE FIG, 31 FOR
USE OF CD4098B.
92CS-32783
Fig.31 -CD45368 Timing Diagram.
Fig.3D - Application showing use of

CD40988 and CD45368 to get
decode pulse 8 clock pulses
after Reset pulse.
Dimensions in parentheses are in millimeters

and are derived from the basic inch dimen-
sions as !i'dicated. Grid graduations are in
mils (10- inch).
The photographs and dimensions a/elch CMOS chip
reprlsent a chip when it is part of the wafer. When the
wafer Is separated into Individual chips, the angle of
cleavage may vary with ,espect to the chip face for
chip, therefore. may dilfer slightly from the nominal
92CM-32787
dimensions shown.
349
CD4538B Types
CMOS Dual Precision eXI
Monostable Multivibrator
Features:
.. Retriggerable/resettable capability
.. Trigger and reset propagation delays
independent of Rx, Cx
.. Triggering from leading or trailing edge
.. Q and Q buffered outputs available 4I--O-'lNIr-_ Voo
.. Separate resets
.. Wide range of output-pulse widths
CD45388
.. Schmitt trigger input allows unlimited
Functional Diagram
rise and fall times on +TR and - TR inputs
The RCA-CD45388 dual preCision monostable multivibrator .. 100% tested for maximum quiescent
provides stable retriggerable/reseUable one-shot operation current at 20 V
for any fixed-voltage timing application. .. Maximum input current of 1 pA at
An external resistor (Rx) and an external capacitor (Cx) 18 V over full package-temperature
control the timing and accuracy for the circuit. Adjustment range; 100 nA at 18 V and 25°C
of Rx and Cx provides a wide range of output pulse widths • Noise margin (full package-temperature
from the Q and Qterminals. The time delay from trigger range): 1 Vat Voo=5 V
input to output transition (trigger propagation delay) and
2 Vat Voo=10 V
the time delay from reset input to output transition (reset
2.5 Vat Voo=15 V
propagation delay) are independent of Rx and Cx. Precision
control of output pulse widths is achieved through linear • 5-V, 10-V, and 15-V parametric ratings
CMOS techniques. • Standardized, symmetrical output
characteristics
Leading-edge-triggering (+ TR) and trailing-edge-triggering
II Meets all requirements of JEDEC
(-TR) inputs are provided for triggering from either edge of
an input pulse. An unused +TR input should be tied to Vss. Tentative Standard No. 13B, "Standard
An unused - TR input should be tied to Voo. A RESET (on SpeCifications for Description of
low level) is provided for immediate termination of the 'B'Series CMOS Devices."
output pulse or to prevent output pulses when power is
turned on. An unused RESET input should be tied to Voo.
However, if an entire section of the CD45388 is not used, its Applications:
inputs must be tied to either Voo or Vss. See Table I. • Pulse delay and timing
In normal operation the circuit retriggers (extends the • Pulse shaping
output pulse one period) on the application of each new
trigger pulse. For operation in the non-retriggerable mode,
a is connected to - TR when leading-edge triggering (+TR) C XI I. 16 Voo
is used or Q is connected to +TR when trailing-edge RXCX(I) 15 Cx.
triggering (-TR) is used. The time period (T) for this RESET (I) RxCxt21
multivibrator can be calculated by: T=RxC x. +TA til "
13 RESET (2)
-TR (I) 12 +TR (2)
The minimum value of external resistance, Rx, is 4 Kn. The 01 -TR (21
maximum and minimum values of external capacitance, Cx, CiT "
10 02
V55 9 02
are 100 pF and 5000 pF, respectively.
TOP V lEW
The CD4538B types are supplied in 16-lead hermetic dual-
in-line ceramic packages (D and F suffixes), 16-lead dual- TERMINALS 1,8,15 ARE
ELECTRICALLY CONNECTED
in-line plastic packages (E suffix), 16-lead ceramic flat INTERNALLY
92CS-24848Rl
packages (K suffix). and in chip form (H suffix).
The CD4538B is similar to type MC14538 and is pin-for-pin
compatible with the CD40988. Terminal Assignment
350
CD4538B Types

DC SUPPLY-VOLTAGE RANGE, (Vee)
(Voltages referenced to V•• Terminal) .............................................•............ , , ..........•......... -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS .......................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................... ±10 mA
For T,=-40 to +60° C (PACKAGE TYPE E) .............................................•......•......................•.... 500 mW
For T,=+60 to +85°C (PACKAGE TYPE E) .................................................. Derate Linearly at 12 mW/oC to 200 mW
For T,=-55 to +100° C (PACKAGE TYPES D,F,K) ........................................................................ 500 mW
For T,=+1 00 to +125°C (PACKAGE TYPES D,F,K) .......................................... Derate Linearly at12 mW/oC to 200 mW
FOR T.=FULL PAqKAGE-TEMPERATURE RANGE (All Package Types) ..................................................... 100 mW
OPERATING-TEMPERATURE RANGE (T,):
PACKAGE TYPES D,F,K,H ........................................................................................ -55 to +125°C
PACKAGE TYPE E ................................................................................................ -40 to +85°C
STORAGE TEMPERATURE RANGE (T••• ) ............................................................................ -65 to +150°C
•
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. . .................................................... +265°C

For maximum reliability, nominal operating conditions should be selected
so that operating Is always within the following ranges:
Voo LIMITS
(V) Min. Max.
Supply-Voltage Range (For TA=Fuli Package-Temperature Range) - 3 18 V
Input Pulse Width tWH, tWL 5 140 -

+TR, - TR, or RESET 10 80 - ns
15 60 -
TABLE I
CD4538B FUNCTIONAL TERMINAL CONNECTIONS
VooTO VssTO INPUT PULSE OTHER

FUNCTIION TERM. NO. TERM. NO, TO TERM. NO. CONNECTIONS
MONO, MONO. MONO, MONO. MONO, MONO. MONO, MONO.
Leading-Edge Trigger/
3,5 11, 13 4 12
Retriggerable
Leading-Edge Trigger/
3 13 4 12 5-7 11-9
Non-Retriggerable
Trailing-Edge Trigger/
3 13 4 12 5 11
Retriggerable
Trailing-Edge Trigger/
3 13 5 11 4-6 12-10
Non-Retriggerable
INPUT PULSE TRAIN

NOTES:
1. A RETRIGGERABLE ONE-SHOT MUL TIVIBRATOR HAS AN
OUTPUT PULSE WIDTH WHICH IS EXTENDED ONE FULL RETRIGGERABLE MODE PULSE
TIME PERIOD (T) AFTER APPLICATION OF THE LAST WIDTH (+TR MODE)
TRIGGER PULSE.
NON-RETRIGGERABLE MODE
2. A NON-RETRIGGERABLE ONE-SHOT MULTIVIBRATOR PULSE WIDTH
HAS A TIME PERIOD (T) REFERENCED FROM THE APPLI- (+TR MODE)
CATION OF THE FIRST TRIGGER PULSE. 92CS-32816
351
CD4538B Types

CHARACTERISTIC CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H Pkgs. UNITS
Values at -40, +25, +85 Apply to E Pkgs.
Va VIN Voo +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
- 0,5 5 5 5 150 150 - 0.04 5
IIA
Current, 100 Max. - 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low (Sink)
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Current, 10L Min.
0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
Output High (Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 10H Min. 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage:
- 0,5 5 0.05 - 0 0.05
Low-Level, VOL Max.
- 0,10 10 0.05 - 0 0.05
- 0,15 15 0.05 - 0 0.05
Output Voltage:
- 0,5 5 4.95 4.95 5 - V
High-Level, VOH Min.
- 0,10 10 9.95 9.95 10 -
- 0,15 15 14.95 14.95 15 -
Input Low Voltage,
0.5,4.5 ~
5 1.5 - - 1.5
VIL Max.
1,9 - 10 3 - - 3
1.5,13.5 - 15 4 - 4
V
Input High Voltage,
0.5,4.5 - 5 3.5 3.5 - -
VIH Min.
1,9 - 10 7 7 - -
1.5,13.5 - 15 11 11 - -
Input Current,
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 IIA
6(10)
RESET LATCH
92CM-32815
3(13)
RESET ( ) - - - - - - - - - - - - '
Fig. 1 - Logic diagram ('12 of device shown).
352
CD4538B Types
DYNAMIC ELECTRICAL CHARACTERISTICS, At TA=25°C; Input t"t,=20 n8, CL=50 pF

VDD (V) Min. Typ. Max.
Transition Time tTLH. trHL 5 - 100 200
10 - 50 100
15 - 40 80
Propagation Delay Time: tPLH. tPHL 5 - 300 600
+TR or-TR to Q ora 10 - 150 300
15 - 100 220 ns
Reset to Q or Q 5 - 250 500
10 - 125 250
15 - 95 190
•
Minimum Input Pulse Width: tWH. tWL 5 - 80 140
+TR. - TR or Reset 10 - 40 80
15 - 30 60
Output Pulse Width - Q or Q: T 5 57 60.6 64.5
Cx=0.005 f./F. Rx=10 Kn" 10 55 58.9 63.0 fJS
15 55 59.1 63.5
Cx-0.1 f./F. Rx-100 Kn 5 9.4 9.97 10.5
10 9.4 9.95 10.6 ms
15 9.5 10.00 10.6
Cx-10 f./F. Rx-100 Kn 5 0.95 1.00 1.06
10 0.95 1.00 1.06 s
15 0.96 1.01 1.07
Pulse Width Match between 100 (T,-T2) 5 - ±1 -
circuits in same package:
T,
10 - ±1 - %
Cx=0.1 f./F. Rx=100 Kn 15 - ±1 -
Minimum Retrigger Time trr 5 0 - -
10 0 - - ns
15 0 - -
Input Capacitance C,N Any Input - 5.0 7.5 pF
"Note: Minimum Rx value=4 KQ, minimum ex value=5000 pF.
AMBIENT TEMPERATURE (TA)-2e-C
i!
-I...
!30 GATE-lO-SOURCE VOlTAGE(VGS).I~V.
ffi25
~
~ 20
10V
'V
!5 10 1!5
DRAIN-Ta-SOURCE VOLTAGE (VDsl-V DRAIN-TQ-SOURCE VOLTAGE (YDS)-V
Fig. 2 - Typical output low (sink) current characteristics. Fig. 3 - Minimum output low (sink) current characteristics.
353
CD4538B Types
DRAIN-TO-SOURCE VOLTAGE (Vosl-V DRAIN-TO-SOURCE VOLTAGE (Vos)-V
-15 -10 -5 -15 -10 -5
AMBIENT TEMPERATURE (TAl-25'C AMBIENT TEMPERATURE (TAI-25'C
GATE-TO-SOURCE VOLTAGE (VGS}--5V
i!
I
'i
5~
z
~
-IOV -IOV a
-lOw
~
-15 V
-15V
92CS-2432IAZ
Fig. 4 - Typical output high (source) current characteristics. Fig. 5 - Minimum output high (source) current characteristics.
i [AMBIENT .<Me<KA'UK. I.TA'·25·C
1-
~
I 40 60 80 100
LOAD CAPACITANCE (ell pF LOAD CAPACITANCE ICL)pF
92CS-35936 92C5-35938
Fig. 6 - Typical propagation delay time as a function of load Fig. 7 - Typical propagation delay time as a function of load
capacitance (+ TR or - TR to Q or m. capacitance (RESET to Q or OJ.
6 9 12 15 18
Veo SUPPLY VOLTAGE (VOLTS)
92CS-3'939
Fig. 8 - Typical transition time as a function of load capacitance. Fig. 9 - Typical pUlse-width variation as a function of supply
voltage.
_-~ _ 0 w ~ ~ 00 ~ ~ ~ -60 -40 -20 0 20

AMBIENT TEMPERATURE ('C)
40 60 80 100 120 140
AMBIENT TEMPERATURE (-C)
92CS-3S941
92CS-3"40
Fig. 10 - Typical pulse-width variation as a function of temp6ra- Fig. 11 - Typical pUlse-width variation as a function of tempera-
ture (Rx=l00 KCl. Cx=O.1 /IF). ture (Rx=l00 KCl. Cx=5000 pF).
354
CL -so pF. RL -200 Kn
CD4538B Types
Voo .
RX -IOOKa
1000 ~::I~~~O~~~:C;Ari~~~~J:~·25.C - - - \ - - - 1
INPUTS
o
Vss
9ZCS-27401RI
92CS-55137
Fig. 12 - Typical total supply cummt as a function of output duty Fig. 13 - Quiescent device curren! test circuit.
cycle. voo
NOTE'
MEASURE INPUTS
SEQUENTIALLY.
VSS TO BOTH voo AND vSS'
CONNECT ALL UNUSED
' - _ , - _ . . . J INPUTS TO EITHER
voo OR VSS'
II
VSS
Vss 92CS-2744fRI
9ZCS-17402
Test any combination of inputs.
Fig. 14 - Input-val/age test circuit. Fig. 15 - Input-leakage-current test circuit.
Power-Down Mode
During a rapid power-down condition, as would occur with
a power-supply short circuit or with a poorly filtered power
supply, the energy stored in ex could discharge into Pin 20r
14. To avoid possible device damage in this mode, when ex
is ~ 0.5 microfarad, a protection diode with a 1-ampere or
higher rating (1 N5395 orequivalent) and a separate ground
return for ex should be provided as shown in Fig. 16.
voo
IN~3:5 ~
89-97
(2.261-2.464)
EQUIVALENTL .....-=2.:..{I:..:4.:..1 ~ 16
+
cxT
~O.5I'fd-.l
1(151 8
vss= = vss
92CS- 36707
Fig. 16 - Rapid power-down protection circuit.
An alternate protection method is shown in Fig. 17, where a

51-ohm current-limiting resistor is inserted in series with
ex. Note that a small pulse width decrease will occur
however, and Rx must be appropriately increased to obtain 92CM-35091
the originally desired pulse width.
voo
Dimensions in parentheses are in millimeters and are derived

from the basic inch dimension as indicated. Grid graduations are
2 (141 in mils (10-3 inch).
16
51 OHMS The photographs and dimensions of each CMOS chip represent e

chip when It Is part of the wafer. When the wafer Is separated Into
8 individual chips, the angle of cleavage may vary with respect to
Cx I tl51
the chip face for different chips. The actual dimensions of the
~0.5I'fd
= vss isolated chip, therefore, may differ slightly from the nominal
92CS-36706 dimensions shown. Tha user should consider a tolerance of -3
mils to +16 mils applicable to the nominal dimensions shown.
Fig. 17 - Alternete rapid power-down protection circuit.
355
CD45418 Types
CMOS Programmable Timer

.Jl.
High-Voltage Types (20-Volt Rating) 8...!1.
RTC .-!...
-1...
eTC
Features: .2.
RS ~Q
• Low symmetrical output resistance, typically 100n at 'R~
MR .....§..
Vee = 15 V
• Built-in low-power RC oscillator MODE ..1£.
• Oscillator frequency range: DC to 100 kHz QJQ ...2..
SELECT
• External clock (applied to pin 3) can be used instead Voe" PIN 14
of oscillator Vss " PIN 7
• Operates as 2N frequency divider or as a single- 92CS~3501!6
transition timer
• o/a select provides output logic level flexibility CD4541B
• AUTO or MASTER RESET disables oscillator during FUNCTIONAL DIAGRAM
reset to reduce power dissipation
• Operates with very slow clock rise and fall times
The RCA-CD45418 programmable timer consists of a 16- • Capable of driving six low power TTL loads, three
stage binary counter, an oscillator that is controlled by low-power Schottky loads, or six HTL loads over the
external R-C components (2 resistors and a capacitor), an rated temperature range
automatic power-on reset circuit, and output control logic. • Symmetrical output characteristics
The counter increments on positive-edge clock transitions • 100% tested for quiescent current at 20 V
and can also be reset via the MASTER RESET input. • 5-V, 10-V, and 15-V parametric ratings
The output from this timer is the a or Q output from the 8th, • Meets all requirements of JEDEC Tentative Standard
No. 13A, "Standard Specifications for Description of
10th, 13th, or 16th counter stage. The desired stage' is
'B'Series CMOS Devices"
chosen using time-select inputs A and 8 (see frequency
select table). The output is available in either of two modes
selectable via the MODE input, pin 10 (see truth table). sumes an appreciable amount of power and should not be
When this MODE input is a logic "1", the output will be a used if low-power operation is desired.
continuous square wave having a frequency equal to the
The RC oscillator, shown in Fig. 2, oscillates with a fre-
oscillator frequency divided by 2N. With the MODE input set quency determined by the R-C network and is calculated
to logic "a" and after a MASTER RESET is initiated, the
using:
output (assuming a output has been selected) changes
from a low to a high state after 2N- 1 counts and remains in where f is between 1 kHz
that state until another MASTER RESET pulse is applied or f= and 100 kHz
the MODE input is set to a logic "1". 2.3 RTcCTc and Rs2': 10 kn and = 2R Tc
Timing is initialized by setting the AUTO RESET input (pin
5) to logic "a" and turning power on. If pin 5 is set to logic The CD4541 8 types are supplied in 14-lead hermetic dual-
"1", the AUTO RESET circuit is disabled and counting will in-line ceramic packages (D and F suffixes), 14-lead dual-
not start until after a positive MASTER RESET pulse is in-line plastic packages (E suffix), and in chip form (H
applied and returns to a low level. The AUTO RESET con- suffix).
TRUTH TABLE
FREQUENCY SELECTION TABLE STATE
PIN
No. of Stages Count 0 1
A B N 2N 5 Auto Reset On Auto Reset Disable
a a 13 8192 6 Master Reset Off Master Reset On
a 1 10 1024 9
Output Initially Low Output Initially High
1 a 8 256 After Reset (a) After Reset (0)
1 1 16 65536 10 Single Transition Mode' Recycle Mode
356
CD4541B Types
MAXIMUM RATINGS. Absolute-Maximum Valtles:
DC SUPPLY-VOLTAGE RANGE, (Vee)
(Voltages referenced to Vss Terminal) ............................................................................. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS .........................................................................-0.5 to Vee +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ..................................................................................± 10 rnA
POWER DISSIPATION PER PACKAGE (Pe):
For TA = -40 to +60°C (PACKAGE TYPE E) ............................................................................ 500 mW
For TA = + 60 to + 85° C (PACKAGE TYPE E) ............................................. Derate Linearly at 12 mW/o C to 200 mW
For TA = -55 to + 100°C (pACKAGE TYPES 0, F) ....................................................................... 500 mW
For TA = + 100 to + 125°C (PACKAGE TYPES 0, F) ...................................... Derate Linearly at 12 mWI" C to 200 mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................. 100 mW
PACKAGE TYPES 0, F, H ....................................................................................... -55 to + 125°C
PACKAGE TYPE E ............................................................................................... -40 to + 85° C
STORAGE TEMPERATURE RANGE (Tsto ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150°C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max..................................................... +265°C I
For maximum reliability, nominal operating conditions should be selected so that operation is always within the fol/owing
ranges:
LIMITS
CHARACTERISTIC Vee UNITS
(Vl MIN. TYP.
Supply-Voltage Range (For TA = Full Package-Temperature Range) - 3 18 V
12 13
A 8
,-------1 I OF 3
,------1 MUX
MOOE Q III SELECT
VOO·,4
VSS' 7 NC'4,1I
5
AUTO 92CM-34975
RESET
MANUAL RESET
Fig. 1 - CD4541B functional diagram.
357
CD4541B Types

CHARAC- CONDITIONS Values at -55, +25, +125 Apply to D, F, H Packages UNITS
TERISTIC Values at -40, +25, +85 Apply to E Package
Vo V ,N Voo +25
(V) (V) (V) -55 -40 +85 +125 MIN. TYP. MAX.
Quiescent - 0,5 5 5 5 150 150 - 0.04 5
Device - 0,10 10 10 10 300 300 - 0.04 10
/JA
Current, - 0,15 15 20 20 600 600 - 0.04 20
100 Max. - 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 1.9 1.85 1.26 1.08 1.55 3.1 -
(Sink) Current 0.5 0,10 10 5 4.8 3.3 2.8 4 8 -
IOL Min. 1.5 0,15 15 12.6 12 8.4 7.2 10 20 -
Output High 4.6 0,5 5 -1.9 -1.85 -1.26 -1.08 -1.55 -3.1 - rnA
(Source) 2.5 0,5 5 --e.2 -6 -4.1 -3 -5 10 -
Current, 9.5 0,10 10 -5 -4.8 -3.3 -2.8 -4 -8 -
IOH Min. 13.5 0,15 15 -12.6 -12 -8.4 -7.2 -10 -20 -
Output Voltage: - 0,5 5 - 0.05 - 0 0.05
Low-Level, - 0,10' 10 - 0.05 - 0 0.05
VOL Max. - 0,15 15 - 0.05 - 0 0.05
V
Output
Voltage:
- 0,5 5 - 4.95 4.95 5 -
High-Level,
- 0,10 10 - 9.95 9.95 10 -
VOH Min.
- 0,15 15 - 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 - 1.5 - - 1.5
Voltage 1,9 - 10 - 3 - - 3
V,L Max. 1.5,13.5 - 15 - 4 - - 4
V
Input High 0.5,4.5 - 5 - 3.5 3.5 - -
Voltage, 1,9 - 10 - 7 7 - -
V,H Min. 1.5,13.5 - 15 - 11 11 - -
Input Current
hN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-s ±0.1 /J A
,----------- - - - -
I
14
INTERNAL
Ric Voo RESET
.etc 13 B
Rs 12 A
NC 4 II NC
AUTO RESET 10 MOOE
MASTER RESET Q/Q SELECT
Vss OUTPUT
92CS-34976 92CS-34977
TERMINAL ASSIGNMENT Fig. 2 - RC oscillator circuit.
358
CD4541 B Types
DYNAMIC ELECTRICAL CHARACTERISTICS, at TA = 25° C, Input tr, tt = 20 ns, CL = 50 pF, RL = 200 kQ
Voo LIMITS
(V) MIN. TYP. MAX.
Propagation Delay Times: 5 - 3.5 10.5
Clock to Q 10 - 1.25 3.8 /.IS
(2 8 ) tPHL, tpLH 15 - 0.9 2.9
5 - 6 18
(2 '6 ) tPHL, tPLH, 10 - 3.5 10 /.Is
15 - 2.5 7.5
Transition Time, IrHL 5 - 100 200
10 - 50 100 ns
15 - 40 80
tTLH 5 - 180 360
10 - 90 180 ns
15 - 65 130
MASTER RESET, CLOCK 5 900 300 -
Pulse Width 10
15
300
225
100
85
-
-
ns
I
Maximum Clock Pulse Input 5 - 1.5 -
Frequency, fCL 10 - 4 - MHz
15 - 6 -
Maximum Clock Pulse Input
Rise or Fall Time, tt, tt 5,10,15 Unlimited /.IS
79-87
(2.007-2.210)
DIGITAL TIMER APPLICATION
A positive pulse on MASTER RESET resets the counters
and latch. The output goes high and remains high until the
number of pulses, selected by A and B, are counted. This
circuit is retriggerable and is as accurate as the input fre-
quency. If additional accuracy is desired, an external clock
can be used on pin 3. A set-up time equal to the width of the
one-shot output is required immediately following initial
power up, during which time the output will be high.
voo 92CS-35090
R,c
14 Dimensions and pad layout for CD4541 B.
2 13 B
12 A Dimensions in parentheses are in millimeters
4 II and are derived from the basic inch dimensions
5 10 as indicated. Grid graduations are in mils (10- 3
IL 6 9 inch).
INPUT
7 8 OUTPUT -...r-L
~ I f-- The photographs and dimensions of each CMOS
chip represent a chip when it is part of the wafer.
92CS- 34978 When the wafer is separated into individual
chips, the angle of cleavage may vary with
respect to the chip face for different chips. The
actual dimensions of the isolated chip, therefore,
may differ slightly from the nominal dimensions
Fig. 3 - Digital timer application circuit. shown. The user should consider a tolerance of
-3 mils to +16 mils applicable to the nominal
dimensions shown.
359
CD4543B Types
CMOS BCD-to-Seven-Segment
Latch/Decoder/Driver
For Liquid-Crystal Displays LATCH
r
DISABLE 22
16 vDD
2 15
21
High-Voltage Types (20-Volt Rating) BCD B
25
3 14
INPUTS ~ 4 13 J!!
2° :::>
Features: 5 12
...:::>
Q.
• Display blanking of all illegal input combinations

• Latch storage of code
PHASE
BLAN~ING
VSS
6
7
8
II
10
9
I} 0
• Capability of driving two low power TTL loads,

two HTL loads, or one low power Schottky load
9lCS-S4511
over the full rated-temperature range
• Pin-far-pin replacement for the CD4056B
(with pin 7 tied to VSS) CD4543B
• Direct LED driving capability TERMINAL ASSIGNMENT
The RCA-CD4543B is a BCD-to-seven segment latch/de- • 100% tested for quiescent current at 20 V
coder/driver designed primarily for liquid-crystal display • MaKimum input current of 1 pA at 18 V
(LCD) applications. It is also capable of driving light over full package-temperature range;
emitting diode (LED), incandescent, gas-discharge, and 100 nA at 18 V and 25°C
fluorescent displays. This device is functionally similar to
and serves as direct replacement for the CD4056B when pin
7 is connected to Vss. It differs from the CD4056B in that it
range)= 1 Vat VDD=5 V
has a display blanking capability instead of a level-shifting 2 Vat VDD=10 V
function and requires only one power supply. When the 2.5 Vat VDD=15 V
CD4056B is used in the level shifting mode, two power • 5-V, 10-V, and 15-V parametric ratings
supplies are required. When the CD4543B is used for LCD • Meets all requirements of JEDEC Tentative
applications, a square wave must be applied to the PHASE Standard No. 13B, "Standard Specifications
input and the backplane of the LCD device. For LED for Description of 'B' Series CMOS Devices"
applications a logic 1 is required at the PHASE input for
Applications:
common-cathode devices; a logic 0 is required for common-
anode devices (see truth table). • Instrument display driver
• Dashboard display driver
The C04543B is supplied in hermetic dual-in-lineceramic • Computerlca/cuitJ.tor display d,-iver
packages (0 and F suffixes), l6-lead dual-in-line plastic • Timing device driver (clocks, watches, timers)
packages (E suffix), l6-lead ceramic flat packages (K
suffix), and in chip form (H suffix).
MAXIMUM RATINGS, Absolute-MaKimum Values:

OC SUPPLY-VOLTAGE RANGE, (VOO)
(Voltages referenced to VSS Terminal) .............................................................................. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ......................................................................... -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................... ±10 mA
For T A = -40 to +60°C (PACKAGE TYPE E) .............................................................................. 500 mW
For T A = +60 to +85°C (PACKAGE TYPE E) ................................................ Derate Linearly at 12 mW/oC to 200 mW
For T A =-55 to +100°C (PACKAGE TYPES 0, F, K) ........................................................................ 500 mW
For T A = +100 to +125°C (PACKAGE TYPES 0, F, K) ........................................ Derate Linearly at 12 mW/oC to 200 mW
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................... 100 mW
PACKAGE TYPES 0, F. K. H ...................................................................................... -55 to +125°C
PACKAGE TYPE E ................................................................................................ -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) ........................................................................... ~5 to +150°C
At distance 1/16± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max........................................................ +265°C
360
CD4543B Types
-:m·8= tl~
PH
~
* BY
ALL INPUTS PROTECTED
CMOS PROTECTION
V$
~~~s
NETWORK 92CL-34512R1
LD~A
Fig. 1 - BCD-to-seven-segment latch/decoder/drivar CD4543B logic circuit diagram.
RECOMMENDED OPERATING CONDITIONS at TA=25°C, Unless Otherwise Specified

For maximum reliability. nominal operating conditions should be selected so that operation II always within the following
ranges:
LIMITS
_cn MIN. TYP.
Supply-Voltage Range (For T A=Fuli Package-Temperature Range) - 3 18 V
5 250 125
Latch Disable Pulse Width tWH 10 100 50
15 80 40
5 60 15
Minimum Data Setup Time tsu 10 20 -5 ns
15 10 -5
5 25 -5
Minimum Data Hold Time tH 10 20 10
15 20 10
361
CD4543B Types
LIMITS AT INDICATED TEMPERATURES (0 C)

CHARAC- Values ai -40, +25, +85 Apply to E. Package
UNITS
TERISTIC Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent - 0, 5 5 5 5 150 150 - 0.04 5
Device - 0,10 10 10 10 300 300 - 0.04 10
pA
Current 100 - 0,15 15 20 20 600 600 - 0.04 20
Max. - 0,20 20 100 100 3000 3000 - 0.08 100
Output Low
(Sink)
0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 -
Current
0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL
Min.
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
rnA
Output High 4.6 0, 5 5 -0.46 -0.44 -0.30 -0.26 -0.37 -0.75 -
(Source) 2.5 0,5 5 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
Current IOH' 9.5 0,10 10 -0.98 -0.92 -0.68 -0.55 -0.8 -1.6 -
Min. 13.5 0,15 15 -3.33 -3.18 -2.2 -1.9 -2.7 -5.4 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low-Level VOL - 0,10 10 0.05 - 0 0.05
Max. - 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0, 5 5 4.95 4.95 5 -
High-Level VOH - 0,10 10 9.95 9.95 10 -
Min. - 0,15 15 14~95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage VIL 1,9 - 10 3 - - 3
.,Max .. 1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage VIH 1,9 - 10 7 7 - -
Min. 1.5,13.5 - 15 11 11 - -
Input Current liN
Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 pA
DRAIN-lO-SOURCE VqLTAGE (VOSI-V

DRAIN-lO-SOURCE VOL,TAGE (Vosl-V
-15 -10-5 -15 -10 -5
AMBIENT TEMPERATURE (1: I- 2S-C
GATE-lO-SOURCE VOLTAGE (VGSI=-5 II . E

I
AMBIENT TEMPERATURE (TA)-25°C
GATE-TO-SO R VOL: AGE V, 5.- II
-IO~
;::
-16 V' !
92CS-34513
Fig. 2 - Typical output high (source) current characteristics. Fig. 3 - Minimum output high (source) current characteristics.
362
CD4543B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=25° C; CL =50 pF, Input t r ,tf=20 n., RL=200 kn
TEST LIMITS
CHARACTERISTIC CONDITIONS All Packaa•• UNITS
VDD (V) MIN. TYP. MAX.
Propagation Delay Time tPHL 5 - 600 1200
10 - 200 400
15 - 150 300
5 - 500 1000
tpLH 10 - 200 400
15 - 150 300
5 - 180 360
Transition Time tTHL 10 - 90 180
15 - 65 130
ns
5 - 180 360
•
tTLH 10 - 90 180
15 - 65 130
5 250 125 -
Latch Disable Pulse Width twH 10 100 50 -
15 80 40 -
5 60 15 -
Address Setup Time tsu 10 20 -5 -
15 10 -5 -
5 25 -5 -
Address Hold Time tH 10 20 10 -
15 20 10 -
Input Capacitance CIN Any Input - 5 7.5 pF
LATCH BDC DISPLAY

TO DRIVER
7-SEGMENT
DECODER
d 7 SEGMENT
OUTPUTS
Fig. 4 - BCD-to-s9ven-segment latch/decoder/driver functional diagram.
..
E
I
AMBIENT TEMPERATURE (TA)-25°C
.E
AMBIENT TEMPERATURE (TAl-25°C
-~ I
J'30 GATE-TO-SOURCE VOLTAGE (YGs).I~ V
--.,J
.g
16
...z
~ 25 ffi 12.5 GATE-TO-SOURCE VOLTAGE (VGSI-Iev
a:
a:
~ a
. 20 10
z
§"
10V
z 10V
- IS 7.5
~
E '9" •
6
10
5 'V .....
:>
~ 2.5 ,v
0
5 10 15 5 10 15
DRAIN-TO-SOURCE VOLTAGE (Vos)-V DRAIN-TO-SOURCE VOLTAGE IVos)-V
Fig. 5 - Typical output low (sink) current characteristics. Fig. 6 - Minimum output low (sink) current characteristics.
363
CD4543B Types
TRUTH TABLE FOR CD4543B
INPUT CODE OUTPUT STATE

LD BI Ph- D C B A a b c d • r g DISPLAY
CHAR-
X 1 0 X X X X 0 0 0 0 0 0 0 ACTER
1 0 0 0 0 0 0 1 1 1 1 1 1 0
'--I
LaJ
1 0 0 0 0 0 1 0 1 1 0 0 0 0 I
1 0 0 0 0 1 0 1 1 0 1 1 0 1 C~
1 0 0 0 0 1 1 1 1 1 1 0 0 1 :::1J
__
1 0 0 0 1 0 0 0 1 1 0 0 1 1 q
1 0 0 0 1 0 1 1 0 1 1 0 1 1 5
1 0 0 0 1 1 0 1 0 1 1 1 1 1 l=J
-,
1 0 0 0 1 1 1 1 1 1 0 0 0 0 I
1 0 0 1 0 0 0 1 1 1 1 1 1 1
c-,
~::l
1 0 0 1 0 0 1 1 1 1 1 0 1 1 t:1
I
1 0 0 1 0 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 0 1 1 0 0 0 0 0 0 0 Blank
1 0 0 1 1 0 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 0 1 0 0 0 0 0 0 0 Blank
1 , 0 0 1 1 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 1 0 0 0 0 0 0 0 Blank
0 0 0 X X X X ** **
t t 1 t Inverse of Output Display

Combinations as above
Above
X=Don't care.
t=Above combinations.
*=For liquid-crystal readouts, apply a square wave to Ph.
For common cathode LED readouts, select Ph=O.
For common anode LED readouts, select Ph=1.
**=Depends upon the BCD code previously applied when LD=1.
AMBIENT TEMPERATURE (TA}a25°C AMBIENT TEMPERATURE (TAl=25°C
10' 10'
15V
15
20 40 60 80 100 20 40 60 80 100
LOAD CAPACITANCE (CL)-pF 92CS-34~19
92CS-34!518
Fig. 7 - Typical transition time as a function of load capacitance. Fig. 8 - Typical propagation delay time as a function of
load capacitanca.
364
10": AMBIENT TEMPERATURE (1 A )-25·C
CD4543B Types
-
4
CL"'O pr ..L!.:..!.. 1111 ]I
.,4• CL ." pF
~~:I 1/
;0 •
11I.~"''L~~
< •
~ • .pL~
4
z lo~ 11/
0
• .V~
~ •4
:~
fJ
...2ri'
15 1
.
2
4
1/
2
10
0.1 2 468. 2 468'02 468'022 468'0,2 468'04
FREQUENCY (II-II H:c 92CS-34!!120
Fig. 9 - Typical dynamic power dissipation as a function of frequency.
INPUTS
o NOTE:
Vss MEASURE INPUTS
SEQUENTIALLY,
CONNECT ALL UNUSED
INPUTS TO EITHER
NOTE: Voo OR VSS' .
OF INPUTS Vss
92CS-27441RI 92CS-27402
Vss
92CS-27401RI
Fig. 10 - Quiescent device current Fig. 11 - Input voltage test circuit. Fig. 12 - Input current test circuit.
test circuit.
76-84
( 1.930-2.134)
92CS -350B9RI
Dimensions in parentheses are in millimeters The photographs and dimensions of each CMOS
and are derived from the basic inch dimensions chip represent a chip when it is part of the wafer.
as indicated. Grid graduations are in mils (10-3 When the wafer is separated into individual
inch). chips, the angle of cleavage may vary with
respect to the chip face for different chips. The
actual dimensions of the isolated chip, therefore,
may differ slightly from the nominal dimensions
shown. The user should consider a tolerance of
-3 mils to +16 mils applicable to the nominal
dimensions shown.
365
CMOS
Dual Binary to 1 of 4
Decoder/Demultiplexers
Features:
CD4555B: Outputs HIgh on Select
CD4556B: Outputs Low on Select - Expandable with multiple packages
- Standard, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
The RCA·CD4555B and CD4556B are dual
- Maximum input current of 1IJ.A at 18 V over full
one-of-four decoders/demultiplexers. Each 92CS-229t8RL
package temperature range; 100 nA at 18 V and 25°C
decoder has two select inputs (A and Bl. an
Enable input (E), and four mutually exclu· - Noise margin (full package-temperature
sive outputs. On the CD4555B the outputs range): 1 Vat VDD = 5 V CD45558
are high on select; on the CD4556B the out- 2VatVDD=10V FUNCTIONAL DIAGRAM
2.5 V at VDD = 15 V
puts are Iowan select.
- 5-V, 1D-V, and 15-V parametric ratings
When the Enable input is high, the outputs - 'Meets all requirements of JEDEC Tentative
of the C04555B remain low and the outputs Standard No. 13A, "Standard Specifications
of the CD4556B remain high regardless of
the state of the select inputs A and B. The
Applications:
CD4555B and CD4556B are similar to types - Decoding - Code conversion
MC14555 and MC14556, respectively. - Demultiplexing (using Enable input as a E I
data inputl
The C04555B and CD4556B types are sup- - Memory chip-enable selection
plied in 16-lead hermetic dual-in-line cer- - Function selection
amic packages (0 and F suffixes), 16-lead
dual-in-line plastic packages (E suffix), 16" •
vss '32CS-22919~1
lead ceramic flat packages (K suffix), and in CD45568

chip form (H suffix). FUNCTIONAL DIAGRAM

For maximum reliability. nominal operating conditions should be selected
so that operation is always within the following ranges.
CHARACTERISTIC VOO MIN. MAX. UNITS
Supply Voltage Range - 3 18 V TERMINAL ASSIGNMENTS

(For T A = Full Package
Temp. Range) I. I. VDD
}-
I.
"'{1
2
or
•
4
14
13
DuAL
1!2
• 12
II
1m
or
DuAL
Q3 10 1!2
Vss iI!
MAXIMUM RATlNGS,Absolute-Maximum Values: TOP VIEW
92CS-249"'3RI
DC SUPPLY·VOLTAGE RANGE. IV DD }
(Voltages referenced to VSS Terminal) ~.5to+2OV CD4656B
INPUT VOLTAGE RANGE. ALL INPUTS ~.5 to VDD '+0.5 V
POWER DISSIPATION PER PACKAGE IPD}:
I. I.
'!}"'
For T A = -40 to +60 oC IPACKAGE TYPE E} . . . • . . • •. 500mW
,·"t:
For T A = +60 to +850 C IPACKAGE TYPE E} . , Derate Linearly at 12 mW,oC to 200 mW 2
For T A = -55 to +100·C (PACKAGE TYPES 0, F, K) • . . • • . . ., 500mW DUAL QO
• "
14
13
For T A = +100 to +125·C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mW,oC to 200 mW 01 00
OF
DUAL
FOR TA = FULL PACKAGE·TEMPERAT'JRE RANGE IAII Package Types} l00mW
O'
O.
•
7
"II
10
01
O.
OPERATING·TEMPERATURE RANGE ITA}: "ss Q'
PACKAGE TYPES D, F, K, H -55 to +1250 C TOP VIEW
PACKAGE TYPE E • '. - -40 to +85 0 C 92CS-2"1942RI
STORAGE TEMPERATURE RANGE ITstgl -65 to +1500 C
CD4655B
LEAD TEMPERATURE lOURING SOLDERING}:
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm} from case for 10 s max,
366
STATIC ELECTRICAL CHARACTERISTICS AMBIENT TEMPERATURE (TA1.2~·C

CONDITIONS Values at -55, +25, +125 Apply to 0, F, K, H Packages GATE-TQ-SOORCE VOLTAGE (IJGS)·I~ V
CHARACTER- Values al -40, +25, +85 Apply 10 E Package

UNITS
ISTIC +25
Vo VIN VDD
(VI (VI (VI -55 -40 +85 +125 Min. Typ_ Max.
10V
Current, - 0,10 10 10 10 300 300 - 0.04 10
100 Max. _. J1A
0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
10 15
Output Low 0.4 0,5 5 0,64 0.61 0.42 0.36 0.51 1 - DRAIN-TO-SOURCE VOLTAGE (VOS1-V
(Sinkl Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 --
IOL Min. Fig. 1 - Typical output low (sink) current
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 - characteristics.
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
Output High
(Sourcel 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current,
III
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4. -3.4 -6.8 -
~15
. !!ttl! iIltttH
Output Voltage: - 0,5 5 0.05 - 0 0.05
~12,5
ttl.1A!JM1Uj!~E VOLTAGE (VOS,-1511
Low-Level,
VOL Max.
-
-
0,10
0,15
10
15
0.05
0.05
-
-
0
0
0.05
0.05 a 10
ttl
,
Hi
V
Output Voltage: - 0,5 5 4.95 4.95 5 - ~ 7,5
10V t
High·Level, - 0,10 10 9.95 9.95 10 - •
3 ,
VOH Min.
- 0,15 15 14.95 14.95 15 - o
"g 2.5 5V
Input Low 0,5,4.5 - 5 1.5 - - 1.5
Voltage,
VIL Max.
1,9 - 10 3 - - 3 5
DRAIN- TO-SOURCE VOLTAGE
10 15
{Vosl-v
1.5,13.5 - 15 4 - - 4
Input High 0.5,4.5 - 5 3.5 3.5 - - characteristics.
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1,5,13,5 - 15 11 - -
11 DRAIN-lO-SOURCE VOLTAGE (VDS)-V
Input Current
liN Max.
0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 J1A
-I~
AMBIENT TEMPERATURE (TA)'2~"C

-10 -~
-5
.
~
~
-10 ~
-15 ~
......c.
-IOV
-20~
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 2tJC; Input t,. tf= 20ns,
CL =50pF, RL = 200 KP. -15V
o
ALL TYPES o
TEST CONDITIONS o
LIMITS
V DD
Volts TYP, MAX, Fig. 3 - Typical ou tput high (source) current
characteristics.
Propagation Delay Time, tpH L, 5 220 440
A or B Input to tpLH 10 95 190 ns DRAIN-TO-SOURCE VOLTAGE (VDSI-V
-I!> -10 -!>
AMBIENT TEMPERATURE (TA)o2!>"C
Any Output 15 70 140 l±±±±l±llitHHtHttt+ttHt It
GATE -TO-SOURCE VOLTAGE (VGS)O -!> v
5 200 400 j
E Input to Any 10 85 170 ns nil I
Output 15 65 130 ,I ~t~~·
5 100 200
• 1:1
!d ;:1. ..
t·
;
t .
Transition Time t THL , tTLH 10 50 100 ns '-I!> v
15 40 80 ,
Input G~pacitance GIN Any Input 5 7.5 pF o
o

characteristics.
367
'" "'. "''''4

* ALL INPUTS PROTECTED BY COSIMOS
Vss 'J2CS'~4222RI
Fig. 5 - CD45568 logic dlBflrem

II of 2 identical circuiu). Fig. 6 - CD45558 logic diagram
(1 of 2 identical circuitsl.
TRUTH TABLE
INPUTS OUTPUTS OUTPUTS

ENABLE SELECT CD4555B CD4556B
E B A a3 a2 a1 ao a3 a2 a1 ao
0 0 0 0 0 0 1 1 1 1 0
0 0 1 0 0 1 0 1 1 0 1
0 1 0 0 1 0 0 1 0 1 1
0 1 1 1 0 0 0 0 1 1 1
1 X X 0 0 0 0 1 1 1 1
X = DON'T CARE LOGIC 1 == HIGH Fig. 7 - Typical proPBf/8tion delay time vs. load
LOGIC 0== LOW capacitance IA or 8 input to any output).
I ....IIENTTlMP'U..'UREIT .. I.2S·C
1",,300
~
z150
i
i 200
ANY INPUT
"
.• . .
LOAD CAPACITANCE ICLI- pF
F;g. 8 - Typical proPBf/8tion delay time vs. load Fig. 9 - ,Typical proPBf/8tion delay time vs. Fig. 10 - Typical transition time w. load
capacitance (E input to any output). supply voltBf/B. capacitance.
.
Vss
INPUTS ,-_L--,
INPUTOVOIlOUTPUTS
V'H
'--
V~L
~
J
i 10
!c, NOTE;
1
2 ••1.2
10
.. , .
10 2
2"'"
10 3
l .. , .
10" Vss Vss ~SJN~"u~~OMaINATlON
INPU,T FREQUENCY III-~Hr 9ZCS-Z 7401RI
92C'S-2744IRI
Fig. I 1 - Typical dynamic power dissipation Fig. 12 - Quiescent device current test
vs. fraquency. circuit Fig. 13 - Input voltage test circuit.
368
V~NPU(J'
o ~
.. :::~._ SEQUENTIALLY,
90 ... --l--.,Ic=~:--t---
50'" --t--,lL---~~
.0 ..
50 ..
10 ..
--+--*,==>\,
--+-~ ___ ~_
Vss TO 90TH VOO AND YSs 10·4 ==lyl-----t-:Ib:=-__ vss

CONNECT ALL UNUSEO
INPUTS TO EITHER
VOO OR VSS'
V55
Fig. 14 - Input current test circuit

.0 % ----+-,""'="!.'=r-- '0" ======~'+ ____~c voo
50..,. 50 .. ----~~---_I~
0'
10 '1. ===,!L-I-+-+-~- VSS
tI ; I MHz, 50 -to DUTY CYCLE 'I ~ I MHz, 50 0/. DUTY CYCLE
Fig. 15 - CD45558 8 input to 03 output dynamic Fig. 16 - CD45568 8 input to 03 output dynamic
•
signal waveforms. signal waveforms.
VDD
90%
90"1.
50%
10% --7f--+----+-"t-. . APPLICATIONS
Vss 10'"
~~
"2CD45"~0 o~
INPUTS [ SELECT B 01 QI
B _ Q2 Q2 OUTPUTS
'0'. ====~I--------+--¥=
'0% ----+-''1<------:>1'-1
voo
OUTPUT
""
50%
. DATA E
116 C040698
TRUTH TABLE
3 03
92CS- 242<'9
0' 0; SELECT
OUTPUTS
to% ----t--~==~~-~- vSS IOOY. INPUTS
v"
B A CO 01 Q2 03
0 0 DATA 0 0 0
0 1 0 DATA 0 0
tI; F MHz, 50 '"I. DUTY CVCLE 'I"' MHz.50"!. DUTY CYCLE
1 0 0 0 DATA 0
1 1 0 0 0 DATA
Fig. 17 - CD45558 E input to 03 output dYnamic Fig. 18 - CD45568 E input to 03 output dYnamic Fig. 19 - l-of-4lme data demultiplexer usmg
signal waveforms. signal waveforms. CD45558.
TRUTH TABLE
INPUTS o OUTPUTS
C B A 0 1 2 3 456 7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
DECODER OUTPUTS
INPUTS 0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
92CS-2H17
Fig. 20 - l-of-8 decoder using CD45558.
369
T""THTAIkI
·, ,, .., •••, .. •• •••• •• •••• ,.•• • •• •••

'''''"" • • ,.
OQU1I'Uft
E DC.
o 0 0 0
, 2 3
• •• 7 •• n '2 '3
o 0 0 0
, 0 0
·...
o 0 • 00 o , • o 0 • o • 0 0 0
• •• o • , o 0 0 0 0 0 0
D£eODER
INPUTS , ,
0
0 •, 0
o
o
•
• 0 ,
0 0 o
0 0
0 0
, 0 o• 00 •
0
• 0
••
,,
•0 0 , • 0 o • 0 o
0 0 0 0
••
, 0 , 0 0 0
•• •
• 0 •
0 1 • o • 0 1 0 0 0 0
•
o 1 o 0 0 o •• 00 o 1 0 0 0 0
•o 00 •1 00 o • 0 • 0 0 0
•o 11
•• o • 0 o 0 • • 0 1
0 0 1 0 0 0
•
•
• 1
11 1• 01
1 •
••
o
o
• 0 o
•• •
• 0 •o 00 00
0 0
o 0 0 0
• 1
0
0
1
•
0
o 1 1 0 1 • o •• o 0 0 0 0 0 1
1 1 o 0 0 o
• 0 0
0 0 o 0 • 0
• 0
• 1
• 1
o 1 1 1
1 X X X
•1 00
o 0
•• 0 o
o 0 0 o
0 •
• 0
o
o
0 •
0 •
•
0
0
0
0
0
0
•
0
0
1
0
x • don'1 care
Fig. 21 - l-of·I6decoderuling CD4555Band

CD4556B.
92CM-33361
DIMENSIONS AND PAD LAYOUT FOR DIMENSIONS AND PAD LAYOUT FOR
CD4555BH. CD4556BH.

Grid graduations are in mils (10-3 inch).

represent a chip when it ;s part 01 the wafer. When the
wafer is separated into Individual chips, the angle of
dimensions shown.
370
CD4585B Types
CMOS 4-Bit Magnitude

Comparator AO 10
WORO"A" { A I 7
High Voltage Types (20-Volt Rating) A2
A3 I~
A'B 4
The RCA-CD4585B is a 4·bit magnitude com- Features: CASCADING [ A· B
parator designed for use in computer and INPUTS A<B
logic applications that require the comparison • Expansion to 8,12, 16...... 4N bits by cascading units
BO "
of two 4-bit words. This logic circuit deter- • Medium-speed operation: WORO"B- { 81 ~
mines whether one 4-bit word (Binary or compares two 4-bit words :~ 14
BCD) is "less than", "equal to". or "greater in 180 ns (typ.) at 10 V 1100- 16 IISs·e
than" a second 4-bit word. 92CS-30315
The CD4585B has eight comparing inputs • Standardized symmetrical output characteristics
(A3, B3, through AD, BOI. three outputs (A
<B,A = BA> B) and three cascading inputs - 5-V, 10-V, and 15-V parametric ratings FUNCTIONAL DIAGRAM
(A < B, A = B. A> B) that permit systems • Maximum input current of 1 IlA at 18 V
designers to expand the comparator function over full package temperature range;
to 8, 12, 16 ....... 4N bits. When a single 100 nA at 18 V and 25°C Itt
I
4
CD4585B is used, the cascading inputs are • Noise margin (full package temperature range) E
connected as follows: (A < B) = low. (A = B) range) = 1 Vat VDD = 5 V

= high, (A> B) = high. GATE-TO-SOURCE VOLTAGE (VGS)~15 V
2 V at VDD = 10 V "z
Cascading these units for comparison of more 2.5 Vat VDD = 15 V ~ 25
than 4 bits is accomplished as shown in
• Meets all requirements of JEDEC Tentative ~ 20
Fig. 13.
Standard No. 13A, "Standard Specifications § \5 IOV
The CD45858 types are supplied in lS-lead for Description of '8' Series CMOS Devices" 9
and F suffixes). l6-lead dual-in-line plastic
packages (E suffix), lS-lead ceramic flat
,v
packages (K suffix). and in chip form (H Applications:
5 10 \5
suffix). This device is pin-compatible with DRAIN-TO-SOURCE VOLTAGE (Vasl-V
low-power TTL type 7485 and the CMOS • Servo motor controls - Process controllers
types MC14585 and 40085. Fig. 1 - Typical output low (sink) current
characteristics.

AMBIENT TEMPERATURE (TA)~25·C
DC SUPPLY·VOLTAGE RANGE. (VODI
(Voltages referenced to VSS Terminal) . -0.5 to +20 V 4
E
INPUT VOLTAGE RANGE. ALL INPUTS -0.5 to V DD +0.5 V I
DC INPUT CURRENT. ANY ONE INPUT ±10mA ~15
POWER DISSIPATION PoER PACKAGE (PDI: GATE-TO-SOURCE VOLTAGE (VGSI-15V
For T A = -40 to +600 C (PACKAGE TYPE EI . . . . . . . ''; 500 mW "~12'5

For T A = +60 to +85 Ci, (PACKAGE TYPE EI Derate Linearly at 12 mWI eta 200 mW B 10
For T A = -55 to +100 J: (PACKAGE TYPES D •.£, K) . . . . . . . .. 500mW z
~
10V
For T A = +100 to +125 C (PACKAGE TYPES D. F, K) Derate Linearly at 12 mW/oC to 200 mW 7.5
DEVICE DISSIPATION PER OUTPUT TRANSISTOR ~

FOR T A = FULL PACKAGE·TEMPERATURE RANGE (All Package Typesl
100mW
.g
"
~
25
5
5V
PACKAGE TYPES D, F, K. HI -55 to +12S o C

PACKAGE TYPE E -40 to +85 0 C :5 10 IS
DRAIN-TO-SOURCE VOLTAGE IVasl-V
STORAGE TEMPERATURE RANGE {Tstgl -65 to +1500 C nCS-~4319R'
LEAD TEMPERATURE (DURING SOLDERINGI: Fig.2 - Minimum output low (sink) current
At distance 1/16 ± 1/32 inch fl.S9 ± 0.79 mm) from case for 10 s max. characteristics.
DRAIN-TO-SOURCE VOLTAGE (Vasl-V

-15 -10 -5
AMBIENT TEMPERATURE ITA'-ZS-C
GATE-TO-SOURCE VOLTAGE (VGS1.~5V
RECOMMENqED OPE~ATING CONDITIONS

For maximum reliability, nominai-operating conditions should be selected so that oper-
ation is always within the following ranges'
LIMITS -10101
Min. Max.
-15V
nCS-243?OR3
Fig.3 - Typical output high (source) current

characteristics.
371
CD4585B Types
TRUTH TABLE
INPUTS
OUTPUTS
COMPARING CASCADING
A3. B3 A2. B2 A1. B1 AO. BO AB AB
A3>B3 x x x x X 1 0 0 1
A3= B3 A2> B2 x X x X 1 0 0 1
A3= B3 A2= B2 A1>B1 x x X 1 0 0 1
A3= B3 A2= B2 A1 = B1 AO> BO x X 1 0 0 1
A3= B3 A2= B2 A1 = B1 AO=BO 0 0 1 0 0 1
A3= B3 A2= B2 A1 = B1 AO=BO 0 1 X 0 1 0
A3= B3 A2= B2 A1 = B1 AO=BO 1 0 X 1 0 0
A3= B3 A2= B2 A1 = B1 AO<BO x x X 1 0 0
A3= B3 A2= B2 A1 <B1 x x x X 1 0 0
A3= B3 A2<B2 x x x x X 1 0 0
A3<B3 x x x x x X 1 0 0
x= Don't Care Logic 1 = High Level Logic a = Low Level
~voo
LJvss
*INPUTS PROTECTED BY
COS/MOS PROTECTION
NETWORK
fA<BrN 5
FigA - Logic diagram. 92CL-3100e
DRAIN~TO-SOURCE VOL.TAGE (VosJ-V
'M.IE~~1lliill [ill
-15 -10 -5
AMBIENT TEMPERATURE ITA)*25-C
It
f
(, 00'-' ' tqi ,,.
ItfillllliilllJJ'IP,1
GATE-TO-SOURCE VOLTAGE IVGS'.-5 V t L
~wo .:t 3-
.'j7+ fttW ,.G1m
~ ~,
i
~ ~'i'\...
-..10\'" I ~t
;. ,," i-ii II
1
-IOV ~"'o .~
··IO'l
~z .,~
,>,
o '00
~
~
~
92C$-24)2UU
0
'" 40
60 BO
92Cs--.~2066
'00
Fig. 5 - Minimum output high (source) current Fig. 6 - Typical transition time as a function of Fig. 7 - Typical propagation delay time (Neoro-
characteristics. load capacitance. paring inputs" to outfJurs) as a func-
tion of load capacitance.
372
CD4585B Types
STATIC ELECTRICAL CHARACTERISTICS 10: AMBIENT TEMPERATURE ITA I -2!5·C
LIMITS AT INDICATED TEMPERATURES 1°C) U

N
CHARAC· CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H. Packages I
+25 S
Vo VIN VDD
IV) IV) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent
- 0,5 5 5 5 150 150 - 0.04 5
Device - 0,10 10 10 10 300 300 - 0.04 10 p.A
Current, - 0,15 15 20 20 600 600 - 0.04 20
IDD Max.
- 0,20 20 100 100 3000 3000 - 0.08 100 0.12 468, .2 468 ,0 :2 4681022
CLOCK INPUT FREOUENCY (tINI-IIHz
468 1032 468 104
92CS- 3206~
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - Fig. 8 - Typical dynamic power dissipation as a
Output Low
function of clock input frequency (see
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - Fig. 9-dynamic power dissipation test
•
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 - circuit).
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mJl
Output High
(Sollrce) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage:
- 0,5 5 0.05 - 0 0.05
Low·Level, - 0,10 10 0.05 - 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05 V
Output - 0,5 5 4.95 4.95 5 -

Voltage: - 0,10 10 9.95 9.95 10 -
High·Level,
VOH Min. - 0,15 15 14.95 14.95 15 -
0.5,4.5 - 5 1.5 - - 1.5
Input Low
Voltage 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 - 15 4 - - 4 V
Input High 0.5,4.5 - 5 3.5 3.5 - -

Voltage, 1,9 - 10 7 7 - -
VIHMin.
1.5,13.5 - 15 11 11 - -
voo NOTE:
Input Current ±10- 5 ±0.1 p.A
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ~ MEASURE INPUTS
SEQUENTIALLY,
vss TO BOTH VOD AND Vss'
CONNECT ALL UNUSED
'----;~--l INPUTS TO EITHER
Voo OR Vss'
At TA =25°C;lnputtr , t(=20ns, CL =50pF, RL =200kD.
Vss
LIMITS
CHARACTERISTIC TEST CONDITIONS VDD UNITS 92CS-2740Z
Volts Typ. Max.
Propagation Delay Time: 5 300 600 Fig. 10 - Input current test circuit.
Comparing I nputs to 10 125 250
Outputs, tpH L, tpLH 15 80 160 ns
5 200 400
Cascading Inputs to 10
Voo
80 160
Outputs, tpH L, tpLH 15 60 120
INPUTOOUTPUTS
5 100 200 V,H
tTHL' tTLH 15 40 80 ;-0-
V1l
~
:r
NOTE: .
VSS 6~SYNAp't\~OMBINATION
92CS-27441RI
373
CD4585B Types
INPUTS
o
Vss
'p TOTAL" p (f~~.mRE)+2 •• p (f~~~~~E),AT VOO' 10V

(3 STAGES) 92CM - 31007RI
V5S
9ZCS-Z740IRI '120+2(80)'280 .. (TYP.)
Fig. 12 - Quiescent-device-current test circuit. Fig. 13 - Typical speed characteristics of 8 12./)lt comparator.
TERMINAL ASSIGNMENT
8. 16 V DD
A. '\5 A3
IA-atOuT I. 83
(A>8) IN 13 (A>Bl0UT
(AcS)!N 12 (A·<.B1OUT
fA-S)!N II 80
AI 10 AD
Vss 9 8,
TOP VIEW
9ZCS-31006

represent B chip when it Is parr of the wafer. When the
wa',r is separated into Individual chips, the angle of
Dimensions in parentheses are in millimeters and are cleavage may vary with r.spect to the chip face for
derived from the basic inch dimensions as indicated. diflerent chips. The actual dimensions of the isolated
Grid graduations are in mils (10- 3 inch). chip, therefore, may differ slightly f'om the nominal
dImensions shown.
374
CD4124B Types
:MOS
:J-Bit Addressable Latch
D.TA---...aj
rhe RCA·CD47248 8·bit addressable latch - Serial data input - Active parallel output
5 a serial·input, parallel·output storage regis' - Storage register capability - Master clear
er that can perform a variety of functions. - Can function as demultiplexer
- Standardized, symmetrical output characteristics
lata are inputted to a particular bit in the - 100% tested for quiescent current at 20 V
atch when that bit is addressed (by means - Maximum input current of 1/JA at 18 V
If inputs AO, Al, A2) and when WRITE (full package-temperature range), 100 nA
)ISABLE is at a low level. When WRITE at 18 V and 250 C
)ISABLE is high, data entry is inhibited; Ii Noise margin (full package-temperature
lowever, all 8 outputs can be continuously range) = 1 Vat VDD = 5 V, 2 V at VOD FUNCTIONAL DIAGRAM
ead independent of WRITE DISABLE and
=10V, 2.5 VatVDD= 15 V
- 5·V, H)·V, and 15·V parametric ratings Applications:
Iddress inputs.
- Meets all requirements of JEDEC Tentative _ Multi.line decoders
~ master RESET input is available, which Standard No. 13A, "Standard Specifications _ AID converters
esets all bits to a logic ·0' level when RESET for Description of 'B' Series CMOS Devices"
Ind WRITE DISABLE are at a high level. MAXIMUM RATINGS, Absolute·Maximum Values:
"hen RESET is at a high level, and WRITE DC SUPPLY·VOLTAGE RANGE. (VDD)
)ISABLE is at a low level, the latch acts as (Voltages referenced to VSS Terminal) -0.510 +20 V
INPUT VOLTAGE RANGE. ALL INPUTS -0.510 VDD +0.5 V
I 1·of·8 demultiplexer; the bit that is ad· ±10mA
DC INPUT CURRENT. ANY ONE INPUT
Iressed has an active output which follows
:he data input, while all unadd~essed bits For T A = -4010 +600 C (PACKAGE TYPE E) ......•. , 500mW
Ire held to a logic ·0' level. For T A = +60 10 +85 0 C (PACKAGE TYPE E) . Derale Li nearly al 12 mW/oC 10 200 mW
For TA = -55 10 +1000C (PACKAGE TYPES D,F) • . . . . . • .. 500mW
'he CD47248 types are supplied in l6-lead 0
For TA= +100 10 +125 C (PACKAGE TYPES 0, F) Derale Linearly al 12 mW/oC 10200 mW
lermelic ceramic dual-in-line packages (0 DEVICE DISSIPATION PER OUTPUT TRANSISTOR
.nd F suffixes). l6-lead plastic dual-in-line FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types) 100mW
lackages (E suffix). and in chip form (H OPERATING·TEMPERATURE RANGE (TA):
PACKAGE TYPES D. F. H -55 10 +1250 C
,uffix). PACKAGE TYPE E . -4010 +850C
STORAGE TEMPERATURE RANGE (TSlg ) -651o +1500C
AI diSlance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max.
AD 16 VDD
00 AI 2 ,. RESET
A2
• "13
WRITE DISABLE
00
01
• 12
OATA
07
a2 02 6 06
a. 7 10 a.
a. Vss a Q4
TOP VIEW
92C$·10911
TERMINAL ASSIGNMENT
a&
~_ _1"--.__ ~
WRITE
DISA8L[~WD AI
RESET~A
~~___ f'-
ADDRESS
WD
~
DD D.TA---.j.......j..I
AU. INPUTS ARE

PROTECTED IY
COS/MOS PROTECTION
NETWORK DRAIN-TO-SOURCE YOLTAGE IVDS1-V
Vss
Fig. 2- Typic'" outpur low (sink}
Fig. 1- Logic diagram of CD4724B and detail of 1 of B larches. currenr charactari.ric..
375
CD4724B Types
=
RECOMMENDED OPERATING CONDITIONS at TA 25" C (Unl. othwwltefllll1CifiadJ
MODE SELECTION
For maximum reliability, nominal operating conditions should be -'ected io that optIfation
is always within the following nmges. ADDRESSED UNADDRESSED
WD R
LATCH LATCH
SEE VDD LIMITS
CHARACTERISTIC UNITS 0 0 Follows Data Holds Previous
FIG.15· MIN. MAX.
M State
Supply Voltage Range: 0 1 Follows Data Reset to .0"
(Active High 8·
(At T A = Full Package 3 18 V Channel
Demultiplexer)
Temperature Range)
1 0 Holds Previous State
Pulse Width, tw 5 200 - 1 1 Reset to ·0· Reset to ·0·
Data
8 10
15
100
80
- we = WRITE DISABLE R-RESET
5 400 - ns
Address
0 10
15
200
125
-
-
.0
.,
5 150 - ••
Reset
0 10
15
75
50
-
-
wo~~
Setup Time, ts 5 100 -
Data to WRITE DISABLE
0 10
15
50
35
-
- ns
92CS-2717.RI
Fig. 3- Definition of WRITE DISABLE ON r/"",.
Hold Time, tH 5 150 -

Data to WRITE DISABLE G) 10 75 - ns
15 50 -
• Circled numbers refer to times indicated on master timing diagram.
Note: In addition to tha abo... characteristics, a WRITE DISABLE ON time (the time that WRITE
DISABLE is at a high levell must be observed during an address change for the total time that the
external address lin•• AO, A I, and A2 are setding to a stable leval, to pr....nt a wrong cell from
belngad~~.
~~--------~~---------------------------,
DR".-,ro-"DU"~E YOLTAIlI! CYDsI-Y
Fig. 4- Minimum output low (.inkJ

current chIIracteriltit:s.
(tl<'z'
"
~
START
CONVERSION
DRAIN-TO-SOURCE YOLTAGE(YosI-V
~+- -+- -+- - +LS )&B~~~~:

....B
TO DISPLAY
MSB
.. CD4001
.HYtOMP HC210SLD-2R
OR EOUIVALENT
AN~~~ ____________________________ ~
t2eL- 5091'5
FIII.6 - Typksl output high (SOUfCfIJ
current chII_wl,rieL
Fig. 5- AID convertsr
376
CD4724B Types
STATIC ELECTRICAL CHARACTERISTICS DRAIN-tO-SOURCE WLTAG( IVOSI-V

CONDITIONS Value. at -55, +25, +125 Apply to D,F,H Packages
ISTIC UNITS
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min_ Typ_ Max_
Current, - 0,10 10 10 10 300 300 - 0.04 10
100 Max. I1A
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 D,S 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min.
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 -
rnA Fig] - Minimum output high (sourcs)
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - current characteristics.
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, -
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6
IOH Min.
Output Voltage:
Low-Level,
13.5
-
-
0,15
D,S
0,10
15
5
10
-4.2 -4 -2.8
0.05
0.05
-2.4 -3.4
-
-
-6.8
0
0
-
0.05
0.05
II
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
High-Level. - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3 90 100
VIL Max.
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - - Fig_ 8 - Typical propagation delay time
Voltage, 1,9 - 10 7 7 - - (data to On! vs_ load capacitancs_
VIH Min. 1.5,13.5 - 15 11 11 - -
I nput Current
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 !1A
liN Max.
95-103
(2.413-2.6161
Fig. 9 - Tvpical transition time w. load
capacitance.
AIotBIENT TEMPERATURE ITA I"Z5·C

_ _ _ _ LOAD CAPACITANCE iCLlol'pF
_ _ _ CL"50pF'
92CM- 30918
B3:,~J.311l - - - - - - - . j The photographs and dimensions of each CMOS chip

represent a chip when it is part of the wafef. WhEm the
CD4724BH waler is separated into individual chips, the angl9 of 8 • 6 II • II
cleavage may vary with respect to the chip face for 100 10 1 102 I l 10. 10'
DIMENSIONS AND PAD LAYOUT ADORESS CYCLE TI"'[-,..
different chips. Tho actual dimensions of the isolsted
92:(S'21610
Dimensions in parentheses are in millimeters and chip. therefore. may differ slightly from the nominal
dimensions shown. The ussr should consider a to/srance
fire derived from the basic inch dimensions as of -3 mils to +16 mils applicable to the nominal Fig. 10 - Typical dynamic power dissipation vs.
indicated. Grid graduations are in mils (10- 3 inch). 'dimensions shown. address cvcle time.
377
CD47248 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25" C, CL = 50pF. VDO

Inputt,. tf=20ns, RL =200Kn
CONDITIONS
LIMITS
.
Vss
INPUTS
ALL PACKAGE TYPES

CHARACTERISTIC SEE VDD UNITS
Fig. 15· (V) TYP. MAX.
Propagation Delay: tPLH· 5 200 400
Data to Output.
tpHL 0 10
15
75
50
150
100 '2'S~I"OI"1 Vss
WRITE DISABLE 5 200 400 Fig. 1 1- QultllCllnt dlll/ico current
telt circuit.
to Output, tpLH. @ 10 BO 160 ns
tpHL 15 60 120
5 175 35p INPUTO"1lO
OUTPUTS
V,H
Reset to Output,
CD 10 80 160
'-- ~
tpHL 15 65 130 v~ J:
Address to Output. 5 22,5 450
NOTE:
tpLH· @ 10 100 200 Vss TESf ANY CONBINATION
OF INPUTS
tpHL 15 75 150 92CS-2744IRI

Fig. 12-/nput voltage te.t circuit.
Transition Time, tTHL' 5 100 200
(Any Outputl tTLH 10 50 100 ns
15 40 BO vDO ,NPUDS
"DO NOTE
Minimum Pulse 5 100 200 '--_~_ MEAsuRE INPUTS

o"\.!:.,r- S,EQUENTIALLV'
Width.tw 0 10
15
50
40
100
80
ns Vss TO aoTH Voo ANOVSS
CONNECT ALL UNUSED
INPUt'S TO EITHER
Data VDOMVSS'
5 200 400 "ss
Address @ 10 100 200 ns
Fig. 13- Input current te.tclrcuit
15 65 125
0
5 75 150 AD
2
AO 00
5
DO I
AI AI al
D02
Reset G) 10 40 75 ns A2 3 A2 6. 003
1
a2
A3 14 we a.
- DO 4
15 25 50 13 DATA 0 005
DATA IN ao
100 10
Minimum Setup 5 50 CD47248 05 006
Time.ts @ 10 25 50 ns
06
a1
12
DO 1
DO.
"
R
Data to WRITE DISABLE 15 20 35 15
Minimum Hold 5 75 150 "00

Time.tH G) 10 40 75 ns I AD aD 000
2 AI 01 DOlO
Data to WRITE DISABLE 15 25 50 3 42 02 0011
14 WD 03 0012
13 DATA
Input Capacitance, CIN Any Input 5 7.5 pF 00
10
0013
.. * 1/6 CD4069 CD47248 05 0014

·Clrcled numbers refer to times Indicated on maste~ timIng diagram.
R
06
Q7
"
12
DOI~
0016
15
IZCS-301"
Voo
Fig. /4'- 1 of 16 decoder/demultiplexer.
v
1/4 CD4016 IN/OUT
CD47248 012
!!D'~'~A_ _t-fD <10
::'.-----'-'\1
A2
A.
/
X
/ INIOUT
.,-----j.,J '92CS-27677
Fig. /5- M..ter pmlng thgrem. Fig /6- Mu/Pp/e <election decoding - 4 x 4
crOl.point .wltch.
378
CD40100B Types
CMOS 32-Stage Static Left/Right Shift LEFT/RIGHT

CONTROL
Register High-Voltage Types (20.volt Rating) SHIFT
RIGHT
13 SHIFT
RIGHT
IN OUT
Features: elOCM " I.
The RCA·CD40100B is a 32·stage shift reg·

ister containing 32 D·type master·slave flip· • Fully static operation CLOCK
INHIBIT
• SHIFT
LEFT
flops. • Shift left/Shift right capability SHIFT 2

LEFT
• OUT
The data present at the SHIFT·RIGHT INPUT

• Multiple package casmding
• Recirculate capability
IN
NC·',5,7, • YOD-16
vss·a
IO.'4.1~
is transferred into the first register stage syn· RECIRCULATE
• LIFO or FIFO capability CONTROL
chronously with the positive CLOCK edge,
provided the LEFT/RIGHT CONTROL is at
characteristics
a low level, the RECI RCULATE CONTROL
is at a high level, and the CLOCK INHIBIT FUNCTIONAL DIAGRAM
is low. If the LEFT/RIGHT CONTROL is at over full package· temperature range;
a high level and the RECIRCULATE CON· 100 nA at 18 V and 250C
TROL is also high, data at the SHIFT·LEFT • Noise margin (full package·temperature
INPUT is transferred into the 32nd register range) " Applications:
stage synchronously with the positive CLOCK 1 VatVDD" 5 V • Serial shift registers
transition, provided the CLOCK INHIBIT is 2 V at VDO" 10 V
• Time delav circuits
low. The state of the LEFT/RIGHT CON· 2.5 V at VDO" 15 V
• Expandable N·bit data storage stack
• 5·V, 10-V, and 15-V parametric ratings
TROL, RECIRCULATE CONTROL, and (LIFO operation)
CLOCK INHIBIT should not be changed • Meets all requirements of JEDEC Tentative
when the CLOCK is high. Standard No. 13A, "Standard Specifications
Data is shifted one stage left or one stage
right depending on the state of the LEFT/
first stage when the LEFT/RIGHT CON- ~, \'
RIGHT CONTROL, synchronously with the
TROL is low and from the 1st stage to the
positive CLOCK edge. Data clocked into the
32nd stage when the LEFT/RIGHT CON·
first or 32nd register states is available at the AGEl
SHIFT·LEFT or SHIFT·RIGHT OUTPUT TROL is high.

respectively, on the next negative CLOCK The CD40100B types are supplied in 16-
transition (see Data Transfer Table). No lead hermetic dual-in-line ceramic packages
shifting occurs on the positive CLOCK edge (0 and Fsuffixes), 16-lead dual-in-line plas-
if the CLOCK INHIBIT line is at a high tic packages (E suffix). 16-lead ceramic flat
evel. With the RECIRCULATE CONTROL packages (K suffix), and in chip form (H
low, data in the 32nd stage is shifted into the suffix).
DRAIN-TO-SOURCE VOLTAGE lYos)-V
Fig. 1 - 'Typical output low (sink)

current.characteristics.

(VoltageS referenced to Vss Terminalj ................................................ -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPU~ ........................................... -0.5 to VDD +0.5 V
For TA " -40 to +60·C (PACKAGE TYPE E) .................................................. 500 mW
For TA = +60 to +85·C (PACKAGE TYPE E) ................... Derate Linearly at 12 mW'·C to 200 mW
For TA = -55 to +loo·C (PACKAGE TYPES D. F. K) .......................................... 500 mW
For TA = +100 to +12S·C (PACKAGE TYPES D. F. K) .........• Derate Linearly at 12 mW'·C to 200 mW
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... lOOmW
PACKAGE TYPES D. F. K. H ........................................................ -55 to +12S·C
PACKAGE TYPE E .................................................................. -40 to +85·C DRAIN-Ttl-SOURCE \lCLTAGE
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +lS0·C

LEAD TEMPERATURE (DURING SOLDERING): Fig. 2 - Minimum output low (sink)
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 5 max.......................... +265·C current characteristics.
379
CD40100B Types
DRAIN-lO-SOURCE VOLTAGE (VOSI-V
CLOCK~~
*1
-15
AMBIENT TEMPERATURE ITA'-2S"C
-10 -5
*.
CLOCIC INHIBIT
11"
CL
SHIFT LEFT
~-~~-=<D'
OUTPuT
_L
LEFT/~'GT
MI' T
S
II
.ECI.~U
*9 .TE lr
CONT .... current characteristics.
DRAIN-lO-SOURCE VOLTAGE IVosJ-V
R
-15 -10 -5
AMBIENT TEMPERATURE ITA'.2S"C
VDD
11
*ALlINPUTS PROT:~~D
BY COS/MaS PROTECTION
NETWORK
SHIFT LEFT ------------------+-~~~-O

II.
INPUT Fig. 6 - Minimum output high (source)
.OETAIL OF TYPICAL D·TYPE M-SFLIP-FLOP current characteristics.
AMBIENT TEMPERATURE ITA j-25·C

I
%
j~
~
~
CL TI >
~ t·
~ 10V
15V
20 40 60 BO '00
LOAD CAPACITANCE (CLJ-pF 9ZCS-Ur,6

(CLOCK to SHIFT LEFT/RIGHT)
CLOCK
INPUT_ _ _ _ _ _ _ ',_·~...JFl~I-._-_.H
_ _ __
1---. PLH---!
OUTPU_T_ _ _ _ _ _ _ _-'-_ _ _ ..J-l-

Fig. 4 - Timing diagram defining setup, hold, and propagation delay times.

380
CD40100B Types
RECOMMENDED OPERATING CONTITIONSat TA = 250 C, Except as Noted.
For maximum reliability, nominal operating conditio.,. should be selected so that operation

VDD
(Vl Min. Max.
Supply· Voltage Range (For T A = Full Package·
3 18 V
Temperature Rangel
5 100 - -CL·'OpF
,
--·CL-t'pF
15 10 - '0'
5 275 - I 2 .. "'0 2 .. ""OZ2 .. ",03 2 .. ""0"2 .. "'05
CLOCK INPUT FREQUENCY I 'eli-KHz nCS-ilI1U
Data Hold Time, tH 10 100 - ns
15 75 - as a function of CLOCK frequency.
5 1
•
Clock Input Frequency, fCL 10 dc 2.5 mHz
15 3
5 - 15
Clock Input Rise or Fall Time, trCL, tfCL 10 - 15 j.Ls
15 - 15
Clock I nput Pulse Width:

Low Level, tWL
5
10
450
230
-
- ns
.
Vss
INPUTS
15 190 -
5 280 -
High Level, tWH 10 150 - ns
15 140 -
Vss
CONTROL TRUTH TABLE Fig. 10 - Quiescent-device-current test circuit.

LEFT/RIGHT CLOCK RECIRCULATE INPUT BIT
ACTION
CONTROL INHIBIT CONTROL ORIGIN
1 0 1 Shift left Shift left input

1 0 0 Shift left Sta!le 1
0 0 1 Shift right Shift right input Voo INP(JUS
Voo NOTE'
~ MEASURE INPUTS
0 0 0 Shift right Stage 32 o ~ SEQUENTIALLY,
Vss TO BOTH Yoo AND Vss'
X 1 X No shift - CONNECT ALL UNusm
INPUfS TO EITHER
• Voo OR VSS'
VSS
DATA TRANSFER TABLE.
INITIAL STATE CLOCK RESULTING STATE
DATA CLOCK INTERNAL LEVEL INTERNAL OUTPUT
INPUT INHIBIT STAGE CHANGE STAGE a
0 0 x ~ 0 NC
X 0 0 ~ NC 0
1 0 X ~ 1 NC
'MPUTOVOO
OUTPUTS
X 0 1 ~ NC 1 v,"
X 1 '-- -tA
0'" Low level 1 = High level X
1
= Don't care
X
NC = No change
NC NC
V~L :r
* For Shift-Right Mode NOTE:
Data Input = SHIFT·RIGHT INPUT ITerm. 11) For Shift·Left Mode Vss ~~srN~~~ONBINATION
Internal Stage = Stage 1 (01) Data Inpul = SHIFT·LEFT INPUT (Term. 6) 9lCS-27441RI
Output = SHIFT·LEFT OUTPUT (Term. 4) Inlernal Stage = Stage 32 (Q32)
OulPUI = SHIFT·RIGHT OUTPUT (Term. 12) Fig. 12 - Input-voltage test circuit.
381
CD40100B Types
CONDITIONS Values at -55, +25, +125 Apply 10 D, F, K, H Packages
CHARACTER· Value. at -40, +25; +85 Apply to E Peelulge
ISTIC UNITS
Vo VIN VDD +25
Current,
100 Max.
- 0,10 10 10 10 300 300 - 0.04 10
vA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sinkl Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOLMin.
1.5 0,15 15 4.2 4 2.B 2.4 3.4 6.B -
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
(Source) 2.5 0,5 5 -2 -l.B -1.3 -1.15 -1.6 -3.2 -
Current,
IOHMin.
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
13.5 0,15 15 -4.2 -4 -2.B -2.4 -3.4 -6.B -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low·Level,
VOL Max.
- 0,10 10 0.05 - 0 0.05
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage,
VIL Max.
1,9· - 10 3 - - 3
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
Input Current
liN Max.
- o,lB lB to. 1 iO.l il ±1 - ilo- 5 io.l vA
o 10
90- 1 1

clsavage may vary with respect to the chip face for
dimensions shown.
92eS-2879B

Dimensions in IJ8rentheses are in millimeters and are
Gr;d graduations are in mils (to-3 inch).
382
CD40100B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =250 C, Input t" tf =20 ns,

CL =50 pF, RL =200kn

CHARACTERISTIC V DD UNITS
V Min. Typ. Max.
Clock to Shift Left/Right 10 165 330 ns
Output, tpLH' tpHL 15 115 230
5 100 200
Transition Time, tTHL' tTLH 10 50 100 ns
15 40 80
5 50 100
Minimum Data Setup Time, ts 10 10 20 ns
15 5 10
Minimum Data Hold Time, tH
Maximum Clock Input Frequency, fCL
Minimum Clock Input Pulse Width:

5
10
15
5
10
15
5
10
1
2.5
3
170 275
75 100
50 75
2
5
6
225 450
115 230
ns
MHz
ns
•
Low Level, tWL
15 95 190
5 140 280
High Level. tWH 10 75 150 ns
15 70 140
Input Capacitance, C, N Any Input - 5 7.5 pF
NC I· I. Voo
CLOCK INHIBIT NC
CLOCK " NC
"
SHIFT LEFT OUT
NC "
I.
LEFT/RIGHT CONTROL
SHIFT RIGHT OUT
SHI FT LEFT IN SHIFT RIGHT IN
NC 10 NC
Vss RECIRCULATE CONTROL

TOP VIEW
NC~NO CONNECTION
92C5-27568
TERMINAL ASSIGNMENT
383
CD40101 B Types
CMOS 9-Bit Parity Features:

• 100% tested for maximum quiescent
Generator/Checker current at 20 V
\100- 14
• Maximum input current of 1 /lA at 01 1
vss·r
High-Voltage Types (20-Volt Rating) 18 V over full package-temperature
.22
The RCA·C040101 B is a 9-bit (8 data bits

range; 100 nA at 18 V and 25 0 C
range): 1 Vat VOO ~ 5 V
...
.3 3
plus 1 parity bit) parity generator/checker.

It may be used to detect,errors in data trans-
mission or data retrieval. Odd and even
2 V at VOO = 10 V
2.5 V at VDO = 15. V
."
0' 10
0712
outputs facilitate odd or even parity genera·

tion and checking.
When used as a parity generator, a parity
•
•
5-V, 10-V, and 15-V parametric ratings
Standardized, symmetrical output
characteristics
.9.
0813
bit is supplied along with the data to generate • Meets all requirements of JEDEC
an even or odd parity output. Tentative Standard No.13A, "Standard FUNCTIONAL DIAGRAM
When used as a parity checker, the received Specifications for Description of '8'
data bits and parity bits are compared for Series CMOS Devices."
correct parity. The even or odd outputs are
used to indicate an error in the received MAXIMUM RATINGS, Absolute-Maximum Values:
data. DC SUPPLY-VOLTAGE RANGE, (VDD)
Word-length capability is expandable by (Voltages referenced to VSS Terminal) ................................................ -0.5 to +20 V
cascading. The C0401 01 B is also provided INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -0.5 to VDD +0.5 V
with an inhibit control. If the inhibit control DC INPUT CURRENT, ANY ONE INPUT ..................................................... ±10 mA
is set at logical "1", the even and odd out· POWER DISSIPATION PER PACKAGE (PO):
puts go to a logical "0". For TA = -40 to +60·C (PACKAGE TYPE E) ................................................. 500 mW
The C0401 01 B types are supplied in 14- For TA = +60 to +85·C (PACKAGE TYPE E) ............. ,..... Derate Linearly at 12 mW/·C to 200 mW
lead dual-in-line ceramic packages (0 and F For TA = -55 to +100·C (PACKAGE TYPES 0, F, K) .................. , ....................... 500 mW
suffixes), 14-lead dual-in-line plastic pack- For TA = +100 to +125·C (PACKAGE TYPES 0, F, K) ...... ,... Derate Linearly at 12 mW/·C to 200 mW
ages (E suffix), 14-lead ceramic flat pack- DEVICE DISSIPATION PER OUTPUT TRANSISTOR:
ages (K suffix), and in chip form (H suffix). ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW
PACKAGE TYPES 0, F, K, H ........................................................ -55 to +125·C
PACKAGE TYPE E .. , .................. , ............................................ -40 to +85·C
STORAGE TEMPERATURE RANGE (Tstg) .................................... , ........ -65 to +150·C
TERMINAL ASSIGNMENT At distance 1/16± 1/32 inch (1.59 ± 0.79 mm) from case for IDs max.......................... +265·C
14 Voo RECOMMENDED OPERATING CONDITIONS

13 08
.3 12 07 For maximum re~iability. nominal operating conditions should be selected
•••• •• II
10
06
05 so that operation is always within the fol/owing ranges:
000 OUT 9 EVEN OUT.
Vss B INH LIMITS
'-TO:C:P""VC":,E"'W.J CHARACTERISTIC UNITS
MIN. MAX.
Supplv·Voltage Range (For T A =
Full Package·Temperature Range) 3 18 V
01
D3
04
D5 Truth Table
nOD
Inputs Outputs
D. 01·09 Inhibit Even Odd X = Oon't Care
LogiC 1 = High
I1's=Even 0 1 0
07 Logic 0 = Low
D. A~IN~
PROTECTED BY
COS/MOS PROTECTION
Vss
I1's=Odd
X
0
1
0
0
1
0
NETWORK
09
Fig. 7 - CD40707B logic diagram.
384
CD401 01 B Types
LIMITS AT INDICATED TEMPERATURES laC)
CHARACTER· Values at -40·, +25, +85 Apply to E Package
ISTIC UNITS
Vo VIN VDD +25
IV) IV) IV) -55 -40 +85 +125 Min. Typ. Max.
Current. - 0,10 10 10 10 300 300 - 0.04 10
100 Max. IJA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - DRAIN-TO-SOURCE VOlTAGE IVDSI-V
ISink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOlMin.
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 - Fiq.2 - Typical output low (sink)
4.6 0.5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA cu"ent characteristics.
Output High
ISource) 2.5 0.5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
9.5 0,10 10
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
low·Level.
- 0,10 10 0.05 - 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min. - -
0,15 15 14.95 14.95 15
Input low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3 DRAIN-lO-SOURCE YOl.TAGE (VOSI-V
Vil Max.
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - - Fig.3 - Minimum output low (sink)
Voltage,
VIH Min.
1,9 - 10 7 7 - - current characteristics.
1.5,13.5 - 15 11 11 - - DRA1N-lO-SOURCE VOLTAGE IVosl-V

Input Current
0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 IJA
liN Max.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25D C; Input tr,tt =20 ns,

Cl = 50 pF, Rl = 200 kn

(V) Typ. Max.
5 350 700
Data Propagation Delay Time, Fig.4 - Typical output high (source)
10 150 300 current characteristics.
tPHL,tPlH 15 100 200
5 140 280
Inhibit·to·Qutput Propagation
Delay Time,
10 70 140 ns
tPHl, tPLH
15 50 100
5 100 200
Transition Time, tTHl' tTLH
10 50 100
15 40 80
Fig.5 - Minimum output high (source)

385
CD40101 B Types
LOAD CAPACITANCE ICI.I-pf' LOAD CAPACITANCE ICLJ-pF

..10 to Z Ie)!
INPUT FREQUEN'( l'IN1-.H1
,0' '0
Fig.6 - Typical propagation delay time as a function Fig. 7 - Typical transition time as a function Fig. 8 - Typical dynamic power dissipation as
of load capacitance. a function of input frequency.
Voo
Voo
.
V~UTO"~:.:t
INPUTS
Vss
'NPU(JS
Voo NOTE:
Voo MEASURE IN. PUTS
~ ~~a:T~T~DL~~NoVss' V~L
\Iss CONNECT ALL UNUSED
INPUTS TO EITHER
"DO OR Vss NOTE:
Vss Vss TEST ANY
COMBINATION
Vss 92CS-27441RI OF INPUTS
Fig.9 - Dynamic power dissipation Fig.TO - Quiescent-device- Fig. II - input-feakage Fig.12 - Input-voltage
test circuit. current test circuit. current. test circuit.
DIMENSIONS AND PAD LAYOUT FOR CD40101B
The photographs and dimen8ions 01 88Ch CMOS chip

represent 8 chip when it is part of the wafer. When the
waler is separated into indIvidual chips, the angle o~ Dimensions in parentheses are in millimeters and
cleavage may vary with respect to the chip face for are derived from the basic inch dimensions as in-
different chips. The actual dimensions of the isolated dicated_ Grid graduations are in mils (10- 3 inch)_
0' -3 mlts to +18 mils applicable to the nominal
dimension, shown.
386
CMOS a-Stage Features:

Presettable Synchronous • Synchronous or asynchronous preset
• Medium-speed operation: fCL =
Down Counters 3_6 MHz (typ_) @ VDD = 10 V
• Cascadable
CD40102B - 2-Decade BCD Type • Maximum input current of 1 /-IA at 18 V

over full package-temperature range; 100
CD40103B - 8-Bit Binary Type nA at 18 V and 25 0 C I
I 8-STAGE
I DOWN
• Noise margin (full package-temperature I
range) = 1 Vat VDD = 5 V J1, COUNTER COIZO
The RCA-CD40102B, and CD40103B con- CLOCK
sist of an 8·stage synchronous down counter 2 Vat VDD = 10 V
with a single output which is active when the 2.5 Vat VDD = 15 V
internal count is zero. The CD40102B is con- • Standardized, symmetrical output
CD40102B, CD40103B
figured as two cascaded 4-bit BCD counters, characteristics FUNCTIONAL DIAGRAM
and the CD40103B contains a single 8-bit • 5-V, 10-V, and 15-V parametric ratings
binary counter. Each type has control inputs
•
• Meets all requirements of JEDEC Ten-
for enabling or disabling the clock, for clear· tative Standard No.13A, "Standard
ing the counter to its maximum count, and Specifications for Description of 'B'
for presetting the counter either synchro- Series CMOS Devices"
nously or asynchronously. All control inputs
and the CARRY-OUT/ZERO-DETECT out· Applications:
put are active-low logic. • Divide-by-"N" counters
In normal operation, the counter is decre- • Programmable timers
mented by one count on each positive tran- • I nterrupt timers
sition of the CLOCK. Counting is inhibited '. Cycle/program counter
when the CARRY-IN/COUNTER ENABLE
/Ci7CE) input is high. The CARRY-OUTI
ZERO-DETECT (CO/ZD) output goes low
when the count reaches zero if the Ci7CE"" RECOMMENDED OPERATING CONDITIONS AT TA = 250 C, Unless Otherwise Specified
input is low, and remains low for one full For maximum reliabilitv, nominal operating conditions should be selected so that operation
clock period. is always within the following ranges.
When the SYNCHRONOUS PRESET-ENA-
BLE (SPE) input is low, data at the JAM in-
LIMITS
put is clocked into the counter on the next
positive clock transition regardless of the Characteristic VOD Min_ Max. Units
state of the Cl/cE input. When the ASYN-
Supply Voltage Range (At TA - Full Package-
CH RONOUS PRESET-ENABLE (APE") in- 3 18 V
Temperature Range)
put is low, data at the JAM inputs is asyn-
chronously forced into the counter regard- 5 300 -
less of the state of the SPE", Cl/cE, or Clock Pulse Width, tw 10 180 - ns
CLOCK inputs. JAM inputs JO-J7 represent
two 4-bit BCD words for the CD401 02B and
15 80 -
a single 8-bit binary word for the CD40103B. 5 320 -
When the CLEAR (ClR) input is low, the Clear Pulse Width, tw 10 160 - ns
counter is asynchronously cleared to its 15 100 -
maximum count (9910 for the CD40102B
and 25510 for the CD40103B) regardless of 5 360 -
the state of any other input. The precedence APE" Pulse Width, tw 10 160 - ns
relationship between control inputs is indio 15 120 -
cated in the truth table.
If all control inputs except CiiCE are high at
5 - 0.7
the time of zero count, the counters will Clock Input Frequency, fCL 10 - 1.8 MHz
jump to the maximum count, giving a count- 15 - 2.4
ing sequence of 100 or256 clock pulses long. 5 -
The CD40102B and CD40103B may be cas- Clock Rise and Fall Time, trCl, tfCl 10 - 15 /-Is
caded using the Ci7CE""input and the CO/ZD
output, in either a synchronous or ripple
15 -
mode as shown in Figs.21 and 22. 5 280 -
The CD40102B and CD40103B types are SPE" Setup Time, tSu 10 140 - ns
supplied in 16-lead hermetic dual-in-line 15 100 --
ceramic packages (D and F suffixes), 16-
5 200 -
16-lead ceramic flat packages (K suffix), Jam Setu'p Time, tsu 10 80 - ns
and in chip form (H suffix). 15 60 -
5 500 -
CI/CE Setup Time, tsu 10 250 - ns
15 150 -
387
(Voltages referenced to VSS Terminal) .•....................•.........•.•............. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS .......•..•.•.•.•...•..............•....•.• -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .......•.•.....••.......•.....•......•.......•...•... ±10 mA
For TA = -40 to +60°C (PACKAGE TYPE E) ......•.............•.•...•...•...•.......•...•.. 500 mW
For T A = +60 to +65°C (PACKAGE TYPE E) .•.•......•.....•.• Derate Linearly at 12 mW/oC to 200 mW
For T A = -55 to +lOO°C (PACKAGE TYPES 0, F, K) .............•...•...••.........•......... 500 mW
For T A = +100 to +125°C (PACKAGE TYPES 0, F, K) .......•.. Derate Linearly at 12 mW;oC to 200 mW
FonA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW
• I
PACKAGE TYPES 0, F, K, H ......•...••....•..•....................•••............. -55 to +125°C DRAIN-lO-SOURCE VOLTAGE IVDS1-V
PACKAGE TYPE E .....•.•.•.....•...........•....•.....•..................•........ -40 to +65°C
STORAGE TEMPERATURE RANGE (Tstg) ...........................•................. -65 to +150°C
characteristics.
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max............•...•.....•... +265°C

CHARACTER· Values at -40, +25, +85 Apply to E ..... b ..
ISTIC UNITS
+25
Vo VIN VOO
IV) (VI IVI -55 -40 +85 +125 Min. Typ. Max.
Quiescent Device -. 0,5 5 5 5 150 150 - 0.04 5
DRAII'-Te'-SO"RCE VOLTAGE
Current, - 0,10 10 10 10 300 300 - 0.04 10
jlA
100 Max.
- 0,15 15 20 20 600 600 - 0.04 20 '=;9. 2 - Minimum output low (sink) current
characteristics.
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - ORA IN- TO- SOURCE VOLTAGE IVosl- V
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOLMin.
1.5 0,15 15 4.2 4 2.B 2.4 34 6.B -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
Output High
(Source) 2.5 0,5 5 -2 -1.B -1.3 -1.15 -1.6 -3.2 -
Current,
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.B -2.4 -3.4 -6.B -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low·Level, - 0,10 10 0.05 - 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5 Fifl. 3 - Typical output high (source) current
characteristics.
Voltage,
VIL Max.
1,9 - 10 3 - - 3
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - - ORAIH-TO-SOURCE VOLTAGE IVDSI-V
-,. -'0
Voltage, 1,9 - 10 7 7 - - EIFt:R~TURE
VIH Min. 1.5,13.5 - 15 11 11 - - ·TQ·SOURC' 'WLT... '" ,,'.'."

Input Current
- - ±10-5
'I
O,IB 18 ±0.1 ±0.1 ±1 ±1 to.1 jJA
liN Max.
-
~m~wumm!llim!i_W ]
mmwmmllllllUllUllllWillliftlllID I
9lC5-14UIIII
Fig. 4 - Minimum output high (sourcs) current

characteristics.
388
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25 0 C, CL = 50 pF,
Input t r, tf = 20 ns, RL = 200 kn
Conditions Limiu
Characteristic Units
VDD All Packages
(V) Min. TVp. Max.
Propagation Delay Time (tPHL. tPlH):
5 - 300 600
Clock-to-Output (See Fig. 6) 10 - 130 260
15 - 95 190
5 - 200 400
Carry InlCounter Enable·to·Output 10 - 90 180
15 - 65 130
ns
5 - 650 1300 LOAD CAPACITANCE ICLI-pF
92CS-24S22
Asynchronous Preset Enable·to·Output 10 - 300 600 Fig. 5 - Typical transition time as a function of
15 - 200 400 load capacitance.
5 - 375 750
Clear-to-Output 10 - 180 360
15 - 100 200
Transition Time ('THL.'TlH)

5
10
15
-
-
-
100
50
40
200
100
80
ns
III
5 - 150 300
Minimum Clock Pulse Width, (tW) 10 - 90 180
15 - 40 80
5 - 160 320
Minimum ClR Pulse Width (tW) 10 - 80 160
15 - 50 100
5 - 180 360
Minimum APE Pulse Width (tW) 10 - 80 160 LOAD CAPACITANCE ICL.J-IIF
15 - 60 120 ns Fig. 6 - Typical propagation delay time as ~

tion of load c_ciranc. (clock to COIZD).
5 - 110 220
Minimum APE Removal Time (tRM) 10 - 50 100
15 - 35 70
5 - 140 280
Minimum SPE Set-Up Time (tSU) 10 - 70 140
15 - 50 100
5 - 250 500
Minimum CIICE Setup Time (tsul 10 - 125 250
15 - 75 150
5 - 100 200
Minimum JAM Set-Up Time (tSU) 10 - 40 80
(Synchronous presetting) 15 - 30 60
Maximum Clock I nput Frequency (fCll 5 0.7 1.4 -
SUPPLY VOLTAGE IVool-V
(See Fig. 7) 10 1.8 3.6 - MHz
15 2.4 4.8 -
Fig. 7- Typical maximum clock input frequency
Input Capacitance (CIN) - 5 7.5 pF as a function of supply voltage.
. ..
., 10"6 ...MaIENT TEMPERATURE ITAI- 25·C
t r ,lf- 2O ...
RL -200 kO
~;
1
'l'
!
.1 ~.
~t'
'.
~ .048
C •
:~UTO'·O~; ~'(J' E.:s:~

~ : .<$'.">
;t,j ~
INPUTS
~
~
;;;
is
.
w3a
,
,
o
Vss
; de
~ ., Cl-!Opf
~,
CONNECT ALL UNUSED
INPUTS TO EITHER
~~~ .
... .... ....

-CL-15pF
'0
10-'
, ... ,
I
• • 0
10
, 102
CLOOC INPUT FREOUENCYlfCll-kHr
10 3 '0'
IISS TEST ANY COMBINATION
OF INPUTS
92CS-21.... IRI
IISS
t2CS·2"I'
Fig~ 8 - TVPical dynamic power dissipation lIS a Fig. 9 - Quiescent device
function of frequency. current testcircuit. Fig. 10 - Input voltage test circuit. Fig. 11 - Input current test circuit.
389
TO
FFt-FF1
~
*C~~~E________________~
e Vss
*ALL INPUTS ARE
PROTECTED BY COSfMOS
PROTECTION NETWORK

92CI.-28812i111
390
TO
FFI-FF7
,---.,
I
*
FF4 FF' FF6 FF7
8. * ALL INPUTS ARE

PROTECTED BY COS/MOS
PROTECTION NETWORK
TRUTH TABLE
CONTROL INPUTS PRESET ACTION
CLR APE SPE CIICE MODE
1 1 1 1 Inhibit counter
1 1 1 0 Synchronous Count down
1 1 0 X Preset on next positive
clock transition
1 0 X X Asynchronous Preset asynchronously
0 X X X Clear to maximum count
2. Clock connected to clock input
Notes: 1. 0 = Low level 3. Synchronous operation: changes occur on neg8tiw·to~
1 = High level positivI clock transitions
X = Oon"t care 4. JAM inputs: CD40102B BCD; MSD = J7.J6.J5.J4 (J7 is MSBI
LSD = J3.J2.Jl.JO (J3 is MSBI
CD40103B Binary; MSB = J7. LSB = JO
391
CD401028, CD401038 Types
TO GATING
~::::::~t=::::::::::t:::~t:::::~, TO GATING
SP£--------~::::::::::r-----~------~~1I"
sP£---------------------1--,
~,::::::~~::::::::=t::::::~~
CLR--------------------------~~
Fig. 14 - Detail logic diagram for flip·f1op •• FFD - FF1,

u.ed in logic diagram. for CD401028 and CD401038.
eLK JL rL
_--1
r- l.. rL rL rL r-t-It- "l ~[LrL IL~ n-ILn.. L
~
rh
'-- l.W
.J
JO
-
" --
J2
,-
J4 -
-
J' -
J7 -
.. . .. •• .... ... ••
CO/ZO
'--
CD40102B COUNT
• 2 I 0
•• 9T
• 7
• 5 4
•• .7
C040103B COUN T 255 254
• • I 0
••• 254 254 2•• B 7
• • 4 255 2.2
92CL-288115
Fig. 15 - Timing diagram for CD401028 and CD401038.
CLOCK I. 16 voo
CL.EAR 15 SY"""NC"'H"'RO"'N"'O"'US'P"'R"ES;; E"'i'"1E'"N'"'SaiL"E
CARRY IN/COUNTER ENABLE 14 CARRY OUT I ZERO DETECT
JO 13 J7
JI 12 J6
J2 II J5
J3 10 J4
Vss ".S'"V"'NC"'H; ;oRON=O"'US"P"R"'ES"E"'T"£'"N'".""L·£
92CS-28B21RI
CD40102B.
CD40103B
TERMINAL ASSIGNMENT
392
Voo
!5001'F
CLOCK Voo
JO COIZO
I.
,. CLOCK
Jt
J' ClleE
•
I.
'2
4
.{ J'
J4
JO
J6
SPE
APE
CLR
J7 CLOCK t--t--f'N
10
Vss 92C5-27713
92C5-28819 92C5-28820
Fig. 16 - Maximum clock frequency Fig. 17 - Dynamic power dissipation test circuit
test circuit. (+2 mode}. Fig. 18 - Divide·by·uNn counter.
Voo
Voo
·t
JO
Jt
J'
J3
J4
'"
J.
J7
COIZO
eIleE
TIME-OUT
COUNT DOWN
PRESET
,-
MICROPROCESSOR
DATA
BUS
[ L
Jo
J,
J.
J3
J4
J.
J.
COIlO
eIICE
SPE
APE
CLEAR
lJ~_~~ltt-1
J7 CLOCK
asc.
EXT.
TO
MICROPROCESSOR
INTERRUPT LINE
CLOCK
ENABLE
~~ ---+-----4------<>--J
* An output spike (160 ns @ VDD = 5 VI occurs

whenever two or more devices are cascaded in
the parallel-clocked mode because the clock-to-
I
carry out delay is greater than the carry-in-to-
VSS carry out delay. This spike is eliminated by
gating the output of the last device with the
N-TIME OUT It tiN VS5
92C5-27115
clock as shown.
92CS-21714RI
Fig. 19 - Programmable timer. Fig.20 - Microprocessor interrupt timer. Fig.21 - Synchronous cascading.
CLOCK CASCAIE
ENABLE OUTPUT
INPUT
CLOCK

represent /J Chip when it Is part of the wafer. When the
Fig.22 -" Ripple cascading. cleavage may vary with respect to the chip face for
are derived (rom the basic inch dimensions as in· chip, therefore, may differ slightly from the nominal
dicated. Grid graduations are in mils (10- 3 inchJ. dimensions shown. The user should consider a tolefance
dimensions shown.
Dimensions and pad layout for CD401028. Dimensions and pad layout for CD401038.
393
CD401048, CD401948 Types
CMOS 4-Bit Bidirectional OUTPUT

ENABLE
Universal Shift Register DO
IS
QO
14
01 QI
IS
High-Voltage Types (20 Volt Rating) 02 Q2
12
SHIFT'l3 Q3
The !,!CA-CD40104B Is a universal shift Features: IN LEFT
register featuring parallel Inputs, parallel
outputs, SHIFT RIGHT and SHIFT LEFT • Medium-speed: fCl = 12 MHz. SHIFT
IN RIGHT 2
serial Inputs, and a high-impedance third (typ-) @ YOO = 10 Y
9
output state allowing the device to be us- • Fully static operation .MOOE {SO
8ELECT 81 10
ed In bus-organlzed systems. • Synchronous parallel or serial operation
• Three-state outputs (C040104B) VOO-16
In the parallel-load mode (SO and Sl are • Asynchronous master reset (C040194B) vss.a CLOCK
high), data is loaded into the associated • Standardized, symmetrical output 92CS.24B16R2 CD40104B
flip-flop and appears at the output after characteristics FUNCTIONAL DIAGRAM
the positive transition of the CLOCK In- • S-Y, 10-Y, and 1S-Y parametric
put. During loading, serial data flow Is In- ratings.
hibited. Shift-right and shift-left are ac- • Meets all requirements of JEOEC
complished synchronously on the Tentative Standard No; 13A, "Stan-
positive clock edge with serial data dard Specifications for Descrip-
entered at the SHIFT RIGHT and SHIFT tion of 'B' Sarles CMOS Devices DO IS QO
LEFT serial Inputs, respectively. Clearing 01 14 QI
the register Is accomplished by setting 02 13 Q2
both mode controls low and clocking the 03 Q3
register. When the output enable Input is Applications: SHIFT
low, all outputs assume the high im- • Arithmetic unit bus registers IN LEFT 7
pedance state. • Sarlallparanel conversions SHIFT
IN RIGHT 2
• General~purpose register for bus-
The RCA-CD40194B is a universal shift organized systems
register featuring parallel Inputs, parallel • General-purpose registers MODE {SO 9
SELECT 51 10
outputs SHIFT RIGHT and SHIFT LEFT
serial Inputs, and a direct overriding clear '---r.:--'
Input. In the parallel-load mode (SO and Sl CLOCK
92CS-24B22R2
are high), data Is loaded Into the CD40184B

associated flip-flop and appears at the FUNCTIONAL DIAGRAM
output after the positive transition of the
CLOCK Input. During loading, serial'data AM.'
flow is inhibited. Shift right and shift left
are accomplished synchronously on the
positive clock edge with data entered at
The C0401048 and C0401948 types are
supplied in 16-lead ceramic dual-in-line 11
the SHIFT RIGHT and SHIFT LEFT serial packages (0 and F suffixes), 16-lead dual- 1:=
Inputs, respeCtively. Clocking of the In-line plastic packages (E suffix), 16-lead
register Is Inhibited when both mode con- ceramic flat packages (K suffix), and In chip
trol Inputs are low. When low, the RESE'F form (H suffix).
Input resets all stages and forces all out- The C040194.8 Is similar to Industry types
puts low. 340194 and MC40194.
It
I
ORAIN-TO-SOURCE VOLTAGE IVosl-V
Fig. 1-Typlcal n-channel output low (sink)
MAXIMUM RATlNGS,Absolute-Maximum Values:
(Voltages referenced to VSS Terminl!l) ................................................ -0.5 to +20 V
For T A = -40 to +60·C (PACKAGE TYPE E) ................................................. 500 mW
For T A = +60 to +85·C (PACKAGE TYPE E) .•. ..... .•. ....•••. Derate Linearly at 12 mW/·C to 200 mW
For T A = -55 to +l00·C (PACKAGE TYPES 0, F, K) ................... , ...................... 500 mW
For T A = +100 to +125·C (PACKAGE TYPES 0, F, K) .......... Derate Linearly at 12 mW/·C to 200 mW
OPERATING-TEMPERATURE RANGE (T A):
PACKAGE TYPES 0, F, K, H , ....................................................... -55 to +l25·C
PACKAGE TYPE E .................................................................. -4010 +85·C
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +150·C DR."'-TD'-' ' '.CE yell.TAGE U"CS-Z4)19Rt
LEAD TEMPERATURE (DURING SOLDERING): Fig. 2-Mlnlmum n-channel output low (sink)
At distance 1116± 1/32 Inch (1.59 ± 0.79 mm) from case for 10 8 max.•••••••.......•••••••.••• +285·C current characterIstics.
394
CD401048, CD401948 Types
RECOMMENDED OPERATING CONDITIONS at TA = 250C, Except as Noted. DRAIN-lO-SOURCE VOLTAGE (Vasl-V
I
that operation Is always within the following ranges:
VDD LIMITS
CHARACTERISTIC (V) Min. Max. UNITS
Supply-Voltage Range (For Package-Temperature Range) 3 18 V
5 100
Setup Time, ts
DO, 03, SRIN, SllNto clock
10 70 -
15 50 -
5 400 -
SELECT 0, SELECT 1 to clock 10 220 -
15 130 -
Hold Time, tH
5 0 - Fig. 3-fTyplcal p-channel output high (source)
DO, 003, SRIN' SllN to clock
15 0 -
•
5 0
ns DRAIN-lO-SOURCE VOLTAGE (Vesl-v
,
SELECT 0, SELECT 1 to clock 10 0 -
15 0 -
5 180
Clock Pulse Width, tw 10 80 -
15 50 -
5 - 3
Ciock Input Frequency fCl 10 - 6 MHz
15 - 6
5 1000 -
Clock Input Rise or Fall Time, trCl, tfCl 10 100 - I's
15 100 -
5 300 - Fig. 4-M'nimum p-channel output higii'/so":Jrce)
Reset Pulse Width, * tWR 10 200 - ns current characteristics.
15 140 -
For CD40194B series only.
CONTROL TRUTH TABLE FOR CD40194B SERIES

MODE SELECT
CLOCK· OUTPUT
ENABLE ACTION
So S1
J 0 0 1 Reset
J 1 0 1 Shift right (00 toward 03)
J 0 1 1 Shift left (03 toward 00)
J 1 1 1 Parallel load LOAD CAPACITANCE - pF

UCS-32282
X X X 0 Operations occur as shown Fig. 5-Typical propagation delay time as a

function of load capacitance,
above, but outputs assume high (CLOCK to Q).
Impedance
CONTROL TRUTH TABLE FOR CD40194B SERIES

MODE SELECT
ACTION
CLOCK So S1 RESET
X 0 0 1 No Change
.r 1 0 1 Shift Right (00 toward 03)
I 0 1 1 Shift Left (03 toward 00)
.r 1 1 1 Parallel Load
X X X 0 Reset
1 = High level X = Don't care Fig. 6· - Typical 'ran sit/on time as a function
0= Low level • = level change of load capacitance.
395
OE
}-®oo
9. S5
OUTPUT
EN~
*~OE
CL
Csg.::K \"-....
*~CL
f'.... t f'..... _
.E
8 ---
00
*INPUTS PROTECTED BY
COs/ MOS PROTECTION
NETWORk
V55
Fig. 7-CD40104B logic diagram.
396
R~_
*~R
C~K f'..... f"....

Cl
t r--.... _
•
*~CL
8_- Voo * INPUTS PROTECTED BY
"
COS/MOS PROTECTION
NETWORK
Fig. 8-CD40194B logic diagram.
397
STATIC ELECTRICAL CHARACTERISTICS AMBIENT TEMPERATURE ITA 1'2S G C
• - - LOAD CAPACITANCE (CL )-!SOpF
LIMITS AT INDICATED TEMPERATURES
("C)
CHARAC·
TERISTIC
CONDITIONS Valuei at -55,+25,+125 Apply
to D, F, K, H Packages U
·
IO~!:---+--t---+~-h'f-7L--1
·
N 10',1:=----+---
Values at -40, + 25, + 85 Apply to E
I
Package T
+25 S I02:1:=-----f~r_;t4_'t__7''---_+--+_-___1
Vo
(V)
VIN
(V)
VDD
(V) -55 -40 +85 +125 Min. Typ. Max. · 2 "681()2 2 "68103 :2 "68 104
Quiescent - 0,5 .5 5 5 150 150 - 0.04 5 FREQUENCY (tf)- kHz
Device - 010 10 10 10 300 300 - 0.04 10

/lA
Current, - 015 15 20 20 600 600 - 0.04 20 Fig. 9- Typical power dissipation as a function
100 Max. - 0,20 20 100 100 3000 3000 - .0.08 100 of frequency.
Output Low 0.4 05 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) 0.5 0,10 10 1,6 1.5 1.1 0.9 1.3 2.6 -
Current,
IOlMln.
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
Output
High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Volt - 0,5 5 0.05 - 0 0.05
7,
age: Low· - 0,10 10 0.05 - 0 0.05
•
Level, 0,15 15 0.05 0 0.05
VOlMax. L - - - - - - - - - J CL ·eopFOR 15pF
Output Volt - 0,5 5 4.95 4.95 5
age: High- 0,10 10 9.95 9.95 10 ~
Level, I I I I
VOH Min.
- 0,15 15 14.95 14.95 15 - V
~~POflEL 1111 fill
Input low 0.5;4.5 - 5 1.5 - - 1.5 ~ill~
Voltage, 1,9 10 3 3
VllMax. 1.5,13.5 - 15 4 - - 4 92CS,:,32283
Input High 0.5,4.5 - 5 3.5 3.5 - - Fig. 10-Dynamlc power dissipation test circuit.
Voltage, 19 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
Input
Current
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 /lA
3·State
Output
leakage 0,18 0,18 18 ±0.4 ±0.4 ±12 ±12 - 10-4 ±0.4 /lA D
INPUTS
Current, Vss
lOUT Max.
Fig. l1-Quiescent-device-current test circuit.
398
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25DC,
Input tr, tf = 20 ns, CL = 50 pF, Rl = 200 kQ
TEST
CONDITIONS LIMITS
CHARACTERISTI C VDD UNITS
V Min. Typ. Max.
Clock to Q tPHl, tPlH 10 - 100 200
15 70 140 92CS·27441RI
3·State Outputs:- Fig. 12-lnput·voltage test circuit.

High Impedance 5 - 80 160
tPZH, tPZl, 10 - 35 70
tpI7 15 - 25 50
5 - 45 90
DD
tPHZ 10 - 25 50
Veo 1NPU05
V NOTE'
15 - 20 40
Output Transition Time 5 - 100 200 ~ ~:~~:;,!~~~:S
tTHl, tTlH 10 - 50 100
Vss TO BOTH Voo ANO Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
15 40 80 Vao OR Vss'
Minimum Setup Time: ts 5 - 80 100 V55
DO, 03, SRIN, SllN to 10 - 35 70 ns
Clock 15 - 20 50 Fi'g. 13-lnput current test circuit.
SELECT 0, SELECT 1 5 - 200 400
to Clock 10 - 110 220
15 65 130
Minimum Hold Time: tH 5 - -65 0
DO, 03, SRIN, SllN 10 - -25 0
to Clock 15 - -15 0
TERMINAL DIAGRAMS
SELECT 0, SELECT 1 5 - -170 0
to Clock 10 - -95 0
15 - -55 0 Top View
Width tw 10 - 40 80
15 - 25 50
OUTPUT ENABLE
SHIFT RIGHT IN
I·
2 ,.
I. VDD
00
Maximum Clock Input 5 3 6 - 00

01
I.
13
01
02
Frequency tCl 10 6 12 - MHz 02 12 Q3
15 8 15 - 03
SHIFT LEFT IN "
10
CLOCK
SELECT 1
Maximum Clock Rise or SELECT a
V55
Fall Time 5 - - 1000 TOP VIEW
trCl, ttCl 10 - - 100 I's
15 - - 100
CD40104B
Mininum Reset Pulse
Width· 5 - 150 300
tWR 10 - 100 200
1<; 7n 1.dn
- 230 460 ns
Reset Propagation Delay· 5
tPRHl 10 - 90 180 Top View
15 - 65 130
Input Capacitance CIN Any Input - 5 7.5 pF R'ES'ET
SHIFT RIGHT
,e
2
IS
15
Vao
00
• For CD401048 series only. • For CD401948 series only. DO 3 14 01
DI413Q2
0251203
03 II CLOCK
SHIFT LEFT 10 51
V55 L·=TO~PV=IE=W--,9 SO
CD40194B
399
CD401048, CD401948 Types
~v~",, _ _ _ _ _---l 92CM-32266
Dimensions and pad layout for CD401048H
100
._"'.'''0 2 .540 )
92CS-32287
Dimensions and pad layout for CD401948H

represent 8 chip when it is PSlt of the wafer. When the
DimensIons in parentheses are in millimeters and wafer is separated into individual chips, the angle of
dicated. Grid 9faduations are in mils (tq-3 inch). chip, therefors, may differ slightly from the nominal
dimensions shown. The user should considers tolerancB
dimensions shown.
400
CD40105B Types
CMOS FIFO Register
4 Bits X 16 Words 3-STATE
CONTROL
High-Voltage Types (20-Volt Rating) 13 QO
00
01 12 QI
The RCA-CD401058 is a low-power first-in- Features: 02 Q2

03 10 Q3
first-out (FIFO) "elastic" storage register • Independent asynchronous inputs and outputs
that can store 16 4-bit words. It is capable of • 3-state outputs • Expandable in either direction SHIFT IN
14 DATA-OUT
READY
handling input and output data at different • Status indicators on input and output • Reset capability SHIFT OUT 15 DATA-IN
shifting rates. This feature makes it particu- READY
larly useful as a buffer between asynchronous Voo= 16
• 100% tested for quiescent current at 20 V ~t:liR \lss= B
systems. • 5-V, 10-V, and 15-V parametric ratings 92CS-Z128ZRZ
Each word position in the register is clocked • Maximum input current of 1 J.l.A at 18 V
by a control flip-flop, which stores a marker over full package-temperature range;
bit. A "1" signifies that the position's data is 100 nA at 18 V and 250 C
FUNCTIONAL DIAGRAM
filled and a "0" denotes a vacancy in that • Noise margin (over full package-temperature
position. The control flip-flop detects the range): 1 Vat VDD = 5 V
state of the preceding flip-flop and com- 2 Vat VDD =10 V 2.5 Vat VOD =15 V
municates its own status to the succeeding
flip-flop. When a control flip·flop is in the
"0" state and sees a "1" in the preceding
flip-flop, it generates a clock pulse that
Applications:
II Bit rate smoothing
II
transfers data from the preceding four data
• CPU/terminal buffering
latches into its own four data latches and
• Data communications
resets the preceding flip-flop to "0". The
• Peripheral buffering
first and last control flip-flops have buffered ferred to the second location. The flag will • Line printer input buffers
outputs. Since all empty locations "bubble" remain low when all 16-word locations are II Auto dialers
automatically to the input end, and all valid filled with valid data, and further pulses on
• CRT buffer memories
data ripple through to the output end, the the 51 input will be ignored until 01 R goes • Radar data acquisition
status of the first control flip-flop (DATA- high.
IN READY) indicates if the FIFO is full, when DaR goes high. Unloading of data is
Unloading Data - As soon as the first word
and the status of the last flip-flop (DATA- has rippled to the output, DATA-OUT inhibited while the 3-state control input is
OUT READY) indicates if the FIFO con- READY (DOR) goes high, and data can be high. The 3-state control signal should not be
tains data. As the earliest data are removed removed by a falling edge on the SO input. shifted from high to low (data outputs
from the bottom of the data stack (the out- This falling edge causes the DaR signal to turned on) while the SHIFT-OUT is at logic
put end), all data entered later will automati- go low while the word on the output is O. This level change would cause the first
cally propagate (ripple) toward the output. word to be shifted out (unloaded) immedi-
dumped and the next word moves to the ately and the data to be lost.
Loading Data - Data can be entered when- output. As long as valid data are available
ever the DATA-IN READY (DIR) flag is in the FIFO, the DaR signal will go high Cascading - The' CD401 05B can be cascaded
high, by a low to high transition on the again signifying that the next word is ready to form longer registers simply by connecting
SHIFT-IN (51) input. This input must go low at the output. When the F I Fa is empty, the 01 R to SO and DaR to 51. In the cas-
momentarily before the next word is accepted DaR will remain low, and any further caded mode, a MASTER RESET pulse must
by the FI Fa. The 01 R flag will go low commands will be ignored until a "1" marker be applied after the supply voltage is turnJLd
momentarily, until the data have been trans- ripples down to the last control register, on. For words wider than 4 bits, the 01 R
and the DaR outputs must be Qated to~ether
with AN 0 gates. Their outputs drive the
51 and SO inputs in parallel, if expanding
is done in both directions (see Figs. 4 and 5).
3-State Outputs - In order to facilitate data
MAXIMUM RATINGS. Absolute-Maximum Values: busing, 3-state outputs are provided on the
DC SUPPLY-VOLTAGE RANGE, (VDD) data output lines, while the load condition
(Voltages referenced to VSS Terminal) ................................................ -0.5 to +20 V of the regisler can be detected by the state
INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -0.5 to VDD +0.5 V of the DaR output.
DC INPUT CURRENT, ANY ONE INPUT ............................... : ..................... ±10 rnA
Master Reset - A high on the MASTER
RESET (MR) sets all the control logic marker
bits to "0". DaR goes low and 01 R goes
For TA = +60 to +85°C (PACKAGE TYPE E) ... ........ ........ Derate Linearly at 12 mW/oC to 200 mW
high. The contents of the data register are
For TA = -55 to +loo°C (PACKAGE TYPES D, F, K) .......................................... 500 mW
not changed, only declared invalid, and will
For TA = +100 to +125°C (PACKAGE TYPES D, F, K) .......... Derate Linearly at 12 mW/oC to 200 mW
be superseded when the first word is loaded.
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW The shift·in must be low during Master Reset.
.OPERATING-TEMPERATURE RANGE (TA): The CD40105B types are supplied in 16-
PACKAGETYPESD,F,K,H ........................................................ -55to+125°C lead hermetic dual-in-line ceramic pack-
PACKAGE TYPE E .................................................................. -40 to +85°C ages (0 and F suffixes), 16-lead dual-in-line
STORAGE TEMPERATURE RANGE (T stg) ............................................. -85 to +150°C plastic packages (E suffix). 16-lead ceramic
LEAD TEMPERATURE (DURING SOLDERING): flat packages (K suffix), and in chip form (H
At distance 1116± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max .......................... +265°C suffix).
401
CD40105B Types
RECOMMENDED OPERATING CONDITIONS at 250 C, Except as Noted
is always within the fol/owing ranges:
CHARACTERISTIC VOD LIMITS UNITS

IV) Min. Max.
Supply·Voltage Range (For TA = Full Package-
5 - 1.5
Shift·ln or Shift·Out Rate 10 - 3 MHz
15 - 4
5 200 - Fig. 2 - CD40105B functional block diagram.
Shift-In Pulse Width (Pin 3) 10 80 - ns
15 60 -
5 180 -
Shift-Out Pulse Width (Pin 15) 10 75 - ns
15 55 -
5 - 15
Shift·1 n or Shift·Out Rise Time 10 - 15 IlS
15 - 15
5 - 15 :"MASTER RESET pulse must be applied when
cascading bv 16 N bits.
Shift·ln Fall Time 10 - 15 IlS
15 - 15
Fig. 3 - Expansion, 4-bits wide·by·16 N·bits long.
5 - 15
Shift·Out Fall Time 10 - 5 IlS
15 - 5
5 350 -
Data Hold Time 10 150 - ns
15 120 -
5 220 -
Master Reset Pulse Width 10 90 - ns
15 60 -
I
DAAIN-lO-SOURCE VOLTAGE ('1051-11
Fig. 4 - Typical output low (sink! current

characteristics.
POS I Voo pos 2
*ALL INPUTS
COS/MOS PROTECTED B : &
PROTECTION
NETWORK -----
I
DRAIN-lO-SOURCE VOLTAGE tVosl-V
Vss Fig. 5 - Minimum output low (sink!

Fig. 1 - Logic diagram for the CD40105B.
402
CD401058 Types
STATIC ELECTRICAL CHARACTERISTICS DRA1N-TO-SOURCE VOLTAGE IVosJ-V
LIMITS AT INDICATED TEMPERATURES (OCI U

N
CHARAC· CONDITIONS Values at-55, +25, +125 Apply to D, F, K, H, Packages I
TERISTIC Values at ~40, +25, +85 Apply to E Package T
+25 S
Vo VIN VDD
- 0,5 5 5 5 150 150 - 0.04 5
Quiescent
Device - 0,10 10 10 10 300 300 - 0.04 10 p.A
Current, - 0,15 15 20 20 600 600 - 0.04 20
IDD Max.
- 0,20 20 100 100 3000 3000 - 0.08 100
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - ucs·z.noll"
Output low Fig. 6 - Typical output high (source)
IOl Min.
•
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 - DRAIN-lO-SOURCE VOLTAGE IVosl-V
-I~ -10 -,
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA AMBIENT TEMPERATURE ITA)-25·C
Output High
-2 -1.8 -1.3 -1.15 -1.6 -3.2 - GATE-TO-SOURCE VOLTAGE (VGS'. -~ V
(Source)
Current,
IOH Min.
2.5
9.5
0,5
0,10
5
10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - ..
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
-IOV
Output Voltage:
- 0,5 5 0.05 - 0 0.05 .K>
low·level, - 0,10 10 0.05 - 0 0.05

VOL Max. - 0,15 15 0.05 - 0 0.05 V
-1!5 v
.,.
Output - 0,5 5 4.95 4.95 5 -
Voltage: - 0,10 10 9.95 9.95 10 -
High·level,
VOH Min. - 0,15 15 14.95 14.95 15 - Fig. 7 - Minimum output high (source)
Input Low
Voltage 1,9 - 10 3 - - 3
Vil Max. 1.5,13.5 - 15 4 - - 4 V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIHMin. - -
1.5,13.5 - 15 11 11
Input Current _. 0,18 18 ±0.1 ±1 ±1 - ±10- 5 ±0.1 p.A
±0.1
liN Max.
3·State
Output
Leakage 0,18 0,18 18 ±0.4 ±0.4 ±12 ±12 - ±10- 4 ±0.4 p.A
Current
lOUT Max.
t2tS-24322
·•
10. AMBIENT TEMPERATURE IT,,t-2S-C
Voo
I V
~~I05. ~ V
l~ •
"f%~.;J.
INPUTS
!9 4
°
Vss
~s I ....,.~
!CD-IO·
~[H :.0'::
,p
.
00
,4
~ #:
1~1a!
• 4 CL- 50 pF
, CL. 15 pF ____
10'
, V .~ 32 488 10.2
IIII I II
4 fii 810
Vss
9ZtS-2740IRI
I 48'10 2 4 6'. 22 4 PULSE GEN. I • fiN
INPUT fREQUENCY Iflf~- kHz
92CS-29904
PULSE GEN. 2 - ¥ 9ZCS·Zste03
Fig. 9 - Typical dynamic power dissi- Fig. 10 - Dynamic power dissipation Fig. 17 - Quiescent~evice-current
pation as a function of frequency. test circuit. test circuit.
403
CD401058 Types
DYNAMIC ELECTRICAL CHARACTERiStiCS at T A = 25°C;
= = =
Input tr,tf 20 ns, CL 50 pF, RL 200 kn
CHARACTERISTIC TEST CONDITIONS LIMITS UNITS INPUTOV""

OUTPUTS
VDDIVI Min. Typ Max. V,.
'-- ~
Shift·Out or Reset to Data·Out
5
10
-
-
185 370
90 180 ns
v~ J:
Ready, tpHL 15 - 65 130
Vss
5 - 160 320 NOTE:
Shift·ln to Data·ln Ready, tpHL 10 - 65 130 ns OF INPUTS 92CS-Z744IRt
15 - 45 90
5 - 485 970
Shift-Out to an Out, Fig. 12 - Input-voltage test circuit.
10 - 190 380 ns
tpHL, tpLH 15 - 125 250
3-State Control to Data Out 5 - 140 280

tpZH' tpZL
10 - 60 120 ns
15 - 40 80
5 - 100 200
tpHZ' tpLZ 10 - 50 100 ns
15 - 40 80
5 - 2 4 Yoo INP(JUS
V"". NOTE'
Ripple·Through Delay Input to Output,
tpLH
10 - 1 2 p.s
~ ::~~:I~~~~
15 - 0.7 1.4 Vss TO BOTH Vap AND VSS·
CONNECT ALL UNUSED
5 - 100 200 INPUTS TO EITHER
Transition Time, tTHL' tTLH 10 - 50 100 ns
V$S
Vao ORYSS·
15 - 40 80
Max.imum Shift·ln or Shift·Out Rate, 5 1.5 3 -

fl
10 3 6 - MHz
15 4 8 -
Minimum Shift·ln Pulse Width, 5 - 100 200
(Pin 3)
10 - 40 80 ns
tw 15 - 30 60
Minimum Shift·Out Pulse Width, 5 - 90 180

10 - 35 75 ns
(Pin 15) tWL 15 - 25 55
Maximum Shift·ln or Shift·Out Rise 5 - - 15

Time, tr
10 - - 15 p.s
15 - - 15
Maximum Shift·ln Fall Time, 5 - - 15

tf
10 - - 15 p.s
15 - - 15
Maximum Shift·Out Fall Time.

5 - - 15 3-STATE
10 - - 5 p.s CONTROL I. 16 Volo
tf OIR 15 SO
15 - - 5 SI OOR
00 "
13 00
5 - - 0 01 12 01
Minimum Data Setup Time, tsu 10 - - 0 ns 02
O'
10
10
02
O.
15 - - 0 Vss 9 MR
5 - 175 350
15 - 60 120 TERMINAL ASSIGNMENT
5 - 260 520
Data·1 n Ready Pulse Width, tWL 10 - 100 200 ns
(Pin 2) 15 - 70 140
5 - 220 440
Data·Out Ready Pulse Width. tWL 10 - 90 180 ns
(Pin 14) 15 - 65 130
5 - 100 200
Minimum Master Reset Pulse Width,
10 - 45 90 ns
tWH
15 - 30 60
Input Capacitance CIN (Any Input) - - 5 7.5 pF
404
CD401058 Types
~ ________________________ ~rL--
(UNKNOWN)
*ATVDD.~V-RIPPLE TIME FROM POSITION I TO POSITION 16 I NVALID
•
"AT VOD.~V-RIPPLE TIME FROM POSITION 16 TO POSITION I 92CS- 29233 Rt
#OAT A VALID goes to-h"j"ih I~ ... el in advanee of the OAT A OUT
by a mlJllimum of 50 nsat VOO· 5 V. 25 Rsat VOO '" 10 V,
and 20 ns at Veo • 15 V for Cl = 50 pF and T A = 250C.
Fig. 14 - Timing diagram for the CD40105B.
DATA OUT
READY
8 BIT
DATA
DATA IN
READY
# MASTER
RESET +-.-p-"'..-m-"..-b-'-.-pp-lied......fO-'-'.., "'-i"-9-bY-,-6-N-b~ib~._..J
......
Fig. 15 - Expansion, 8·bits·wide-by·16 N-bits long using CD40105.

wafer is separated into individual chips. the angle of
chip, therefors, may diffsr slightly from the nominal
dimensions shown.
Dimensions. in parentheses are in millimeters and

dicated. Grid graduations ar~ in mils (10- 3 inch).
Dimension and pad layout for CD40105B.
405
CD40106B Types
Features:
CMOS Hex • Schmitt-trigger action with no external components
Schmitt Triggers • Hysteresis voltage (typ_) 0_9 Vat VDD =5 V, 2_3 V at l~G.i
VDD = 10 V, and 3_5 V at VDD = 15 V
High-Voltage Types (20-Volt Rating) • Noise immunity greater than 50% 8~H.i
• No limit on input rise and fall times
• Standardized, symmetrical output characteristics C~I.'C'
The RCA-CD40106B consists of six Schmitt-
trigger circuits_ Each circuit functions as an
D~"'.'D
• Maximum input current of 1 J.l-A at 18 V over full
inverter with Schmitt-trigger action on the
input_ The trigger switches at different points
package-temperature range; 100 nA at 18 V and 25 0 C E~ ••l
for positive- and negative-going signals_ The • Low VDD
input ramp
to vss
current during slow
F~L ..1
difference between the positive-going voltage
(VP) and the negative-going voltage (VN) is • 5-V, 10-V, and 15-V parametric ratings YDD" 14
YSS·7
defined as hysteresis voltage (VH) (see Fig_6)_ • Meets all requirements of JEDEC Tentative
The CD40106B types are supplied in 14- Standard No_ 13A, "Standard Specifications
FUNCTIONAL DIAGRAM
for Description of'S' Series CMOS Devices"
lead hermetic dual-in-Iineceramic packages
(D and Fsuffixes). 14-lead dual-in-Iine plas- Applications:
tic package (E suffix). 14-lead ceramic flat
• Wave and pulse shapers
package: (K suffix). and in chip form (H • High-noise-environment systems
suffix)_ • Monostable multivibrators
• Astable multivibrators
* ALL INPUTS PROTECTED BY
MAXIMUM RATINGS, Absolute-Maximum Values: COS/MOS PROTECTION
NETWORK.
(Vollages referenced 10 VSS Terminal) __ ...........•......•..... _• . . . . . . • . • • . • . • . . .. .. -0.510 +20 V
INPUT VOLTAGE RANGE. ALL INPUTS ...•................•.•.•.........•...••.•• -o.510VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ... _.........•....•..... _..................•.•.•. _... ±10 rnA
ForTA =-40lo+60·C (PACKAGE TYPE E) .•.............. _............................ _... 500mW v..
For TA = +60 10 +85·C (PACKAGE TYPE E) . _...•.•.....•.. _.. Derale Linearly al12 mW/·C 10 200 mW
For TA = -5510 +100·C (PACKAGE TYPES D. F. K) ..................... _.......... _......... SOO mW Fig. 1 - Logic diagram
(1 of 6 Schmitt triggers).
For TA = +100 to +12S·C (PACKAGE TYPES D. F. K) .....•.... Derate Linearly al12 mW/·C to 200 mW
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...•....•.•.•.•..... _. 100 mW
OPERATING-TEMPERATURE RANGE (TA): ~,Rt::' ";tlWiITifiltlll InH
PACKAGE TYPES D. F. K. H ........................... _.•. _.................... _... -55 to +125·C
PACKAGE TYPE E ........................................ _......................... -4010 +85·C
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +150·C
t ;v:
AI dislance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. .. ............... _....... +265·C
I fIT
RECOMMENDED OPERATING CONDITIONS I,
For maximum reliability, nominal operating conditions should be selected
so that operation is always within the following ranges:
r~
LIMITS , ,
MIN. MAX. DRAIN-TO-SOURCE VOLTAGE (\los)-\I
Supply-Voltage Range (For T A Fig.2 - Typical output low (sink)

Full Package·Temperature Range) 3 18 V current characteristics.

At TA = 2!PC, Input tr, tf = 20ns, CL = 50pF, RL = 200kn

CHARACTERISTIC VDD UNITS ,_.
(V) TYP. MAX_
tPHL, 10 70 140 ns
tpLH 15 60 120
tTHL, 10 50 100 ns
DRAIN-TO-SOURCE VOLTAGE (\Iosl-V
tTLH 15 40 80
Input Capacitance, CI N Any Input 5 7.5 pF Fig.3 - Minimum output low (sink)
406
CD40106B Types
lTATIC ELECTRICAL CHARACTERISTICS DRAIN-lO-SOURCE VOLTAGE (VOSI-V
-15 -10 -5
liMITS AT INDICATED TEMPERATURES (OC)

CONDITIONS Values at -55, +25, +125 Apply to 0, F, .K, H, Packages
CHARACTERISTIC Values at -40,+25,+85 Apply to E Packlges UNITS
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent Device
- 0,5 5 1 1 30 30 - 0.02 1
'Current, 100 - 0,10 to 2 2 60 60 - 0.02 2
p.A
Max. - 0,15 15 4 4 120 120 - 0.02 4
- 0,20 20 20 20 600 600 - 0.04 20
Positive Trigger - - 5 2.2 2.2 2.2 2.2 2.2 2.9 -
Threshold Voltage - - 10 4.6 4.6 4.6 4.6 4.6 5.9 - Fig.4 - Typical output high (source)
VpMin.
- - 15 6.B 6.B 6.B 6.8 6.8 B.8
V current characteristics.
- - 5 3.6 3.6 3.6 3.6 - 2.9 3.6
Vp Max. - - 10 7.1 7.1 7.1 7.1 - 5.9 7.1
- - 15 10.8 10.B 10.8 10.8 - 8.8 10.8
DRAIN-fO-SOURCE VOLTAGE \VosJ-V
-15 -10 -!I 0
Negative Trigger - - 5 0.9 0.9 0.9 0.9 0.9 1.9 -

Threshold Voltage
VNMin.
- - 10 2.5 2.5 2.5 2.5 :2.5 3.9 -
- - 15 4 4 4 4 4 5.8 -
V
- - 5 2.B 2.B 2.B 2.8 - 1.9 2.B
VN Max. - - 10 5.2 5.2 5.2 5.2 - 3.9 5.2
- - 15 7.4 7.4 7.4 7.4 - 5.8 7.4
- - 5 0.3 0.3 0.3 0.3 0.3 0.9 -
Hysteresis Voltage - - 10 1.2 1.2 1.2 1.2 1.2 2.3 -
VH Min. - - 15 1.6 1.6 1.6 1.6 1.6 3.5 - V
- - 5 1.6 1.6 1.6 1.6 - 0.9 1.6
VH Max. - - 10 3.4 3.4 3.4 3.4 - 2.3 3.4
- - 15 5 5 5 5 - 3.5 5 Fig.5 - Minimum output high (source)
Output low (Sink) 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
Current,
IOlMin.
0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
1.5 0,15 15 4.2 4 2.B 2.4 3.4 6.B -
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 .- mA
(Source) 2.5 0.5 5 -2 -1.B -1.3 -1.15 -1.6 -3.2
--
Current,
loHMin.
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
13.5 0,15 15 -4.2 -4 -2.B -2.4 -3.4 -6.B - OUTPUT
CHARACTERISTIC
INPUT
CHARACTERISTIC
Output Voltage - 5 5 0.05 - 0 0.05
low·level, - 10 10 0.05 - 0 0.05
VOL Max. - 15 15 0.05 - 0 0.05
V
Output Voltage - 0 5 4.95 4.95 5 -
High level,
VOH Min.
- 0 10 9.95 9.95 10 -
- 0 15 14.95 14.95 15 -
Input Current,
liN Max. - 0,18 lB ±D·,1 to.l I tl tl - ±10- 5 to.l p.A Fig.7 - Input and output characteristics.
Vp ~N
__ 1-00
VDO~i
VIN
Vss
1. ..
I
-- -
--1- ----- -
--.,--
I
..
~" v0[R" "'H • Vp -'IN
:=LS
VIN
'IN Vp
VSS---
_I Definition of Vp, VN. V H bJ Transfer characteristics of 1 of 6 gates Fig.8 - Typical current and voltage
Fig.6 - Hysteresis definition, characteristics, and test set-up_ transfer characteristics.
407
CD401068 Types
LOAD CAPACITANC( ICLI-pF

Fig.9 - Typical voltage transfer characteristics Fig. to - Typical propagation delay time as a
as a function of temperature. Fig. 11 - Typical transition time as a function
A~81.E~~ TEMPERATURE fTAI'250-C i

I
,!I , , :HI
i; ~ I:1
"
I' d
10 15- 20
SUPPLY VOLTAGE (Voo!-V
Fig. 14 - Typical per cept hysteresis as a function

Fig. 13 - Typical trigger threshold voltage as a of supply voltage.
Fig. 12 - Typical power dissipatIon per trigger function of supply voltage.
'0:
,~----~--~~--
~ '°1 --~----~~~
1 '
f IO~~"""'=-::-''=''--i~ APPLICATIONS
~ :
~ I----::-:II-:=--l-
.0 10
:;;...--__"'--c.,,---+-- R 1'· r -
1/3CD40D1UB I n 2 n· vOD
'00 -r-;-r- ~ n n-"o, '00 n

vss.-J L
JI-,
~J1/6
C ..J Lv"
vss.L.-~-- ~
I16C04DIOfiB
...J LJ Lvss
'ss
+ C04DI06S '1.'1' RCln(-'!M.-)
50hn'!R~IMn
Veo· Vp
'0' FREQUEt«:T RANGE OF WAVE SHAPE

IOOpF'!C'!I ...r
'0' ISFROM DC TO I MHz FOR THE RANGE OF RAND C
GIVEN 5/o1S < ,,,,,<II
RISE AND rALL TINE II,,',I-IIS
Fig. 15 - Typical power dissipation as a function

of rise and 'all times. Fig. 16 - Wave shapero
Fig. 17 - Monostable multivibrator.
VOO
INPUTS
116 C040106B
VODJU
1-" -1
o
V55
8:r
vss Voo 1 N P U Voo
O S NOTE.
" 'Re ,"[~)(Vgg:~~)l ~ ~:~~~N~I~~~~~

501tQ:s R:s IMO Vss TO BOTH VOO ANO VSS·
T
vss
C
IODpFS Cs; II'F CONNECT ALL UNUSED
INPUTS TO EITHER
FOR THE RANGE OF RAND C GIVEN Voo OR Vss·
2,...., < IA <O.4s VS5
v.s
92CS'29429
Fig. 18 - Astable multivibrator. Fig. 19 - Quiescent device current test circuit. Fig.20 - Input current test circuit.
408
CD40106B Types
'00 '~'.
r""" G'A
H'B
A
,, "
I.
"
"
Voo
F
L 'F
[ pui..~
~
IU ' C "
10
E
k .f
[·e
r
9 0
CL vss 7 8 J '0
Vss -=- ITOP VIEWI
92CS-2942&
Fig.21 - Dynamic power dissipation test circuit. TERMINAL ASSIGNMENT
l 73-81
(1.854-2.057)

dicated. Grid graduations are in mils 00- 3 inch}.
The photographs and dimensions of elch CMOS chip

represent a chip when it ;s part 01 the wafsr. When the
waler ;s separaled into individual chips, the anI/'e 01
cleavage may vary with r8&pect to the chip 'ac. lor
chip, therefore, may diltsr slightly 'rom the nominal
dimensions shown. The uSer should cons ide, 8 tol.ranca
Of -3 mils to +16 mils applicable to the nominal
dimenaions shown.
92CS-35085
Dimensions and Pad Layout for CD40l068H
409
CD40107B Types
CMOS Dual 2-lnput Features:
• 32 times standard B-Series output current
NAND BufferIDriver . drive sinking capability - 136 mA typo
@VOO=10V,VOS=1 V
High-Voltage Type (20-Volt Rating) • ll!O% tested for quiescent current at 20 V
• Maximum input current of lilA at 18 V
The RCA-CD40107B is a dual 2-input NAND ov.r full package-temperature range;
buffer/driver containing two independent 2- 100 nA at 18 V and 250 C
input NAND buffers with open-drain single
n-channel transistor outputs. This device
• Noise margin, full package temperature
features a wired-OR capability and high
range, RL to VDD = 10 kn:
output sink current capability (136 mA typo
=
at VDD = 10 V, VDS 1 V). The CD40107B 1 VatVDD= 5 V
is supplied in the 8-lead dual-in-line plastic 2VatVDD= 10V
92CS-29434RI
(Mini·DIP) package (E suffix), 14-lead her- =
2.5 V at VOD 15 V
metic frit-seal ceramic package (F suffix), • Meets all requirements ofJEOEC Tentative FUNCTIONAL DIAGRAM
Standard No.13A, "Standard Specifications
Applications
e
dV~ - • Driving relavs, lamps, LEOs
• Line driver
:';'.
TRUTH TABLE
• Level shifter (up or down)
~:~(71 ~yl
A B C
0 0 1* z#
~2(61 J 1 0 l ' z#
0 1 l ' z#
1 1 0
*Requires external TEMPERATURiEI~~~I~m
v VDD" [!!] •• AMBIENT ',I,.".:
I'11'tllin-l;llii~Wllttjt:IHlt:::!jj"I'~
pull~up resistor
___ .:. Voo 55 V~S.[!].4 (RL) to VDD.
1
.. ALL INPUTS PROTECTED #Without pull-up I iEwil ""'ill .
BY COSIMOS
PROTECTION NETWORK resistor (J.state). ~o .. GATE-lO-SOURCE VOLTAGE(VGS'-15V- .---.......
~aoo ,"" • ' .. "H

Vss 92CS-29435RI
Fig. 7 .,. Schematic diagram of CD407078 (one of 2 gates) U640

~
z
§48C 10V

DC SUPPLY:VOLTAGE RANGE. (VDD) ,v
(VoHages referenced to VSS Terminal) ................................................ -0.5 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS ........................................... -0.5 to VDD +0.5 V !5 10 15
DC INPUT CURRENT. ANY ONE INPUT ..................................................... ±10 mA DRAIN-lO-SOURCE VOLTAGE (11051-11
nCS-2t444RI
POWER DISSIPATION PER PACKAGE (PD) .................................................. 500 mW
For TA = -40 to +62,5°C (PACKAGE TYPE E) .......... , .................................... 250 mW Fig.2 - Typical output low (sink)
For TA = +62.5 to +85°C (PACKAGE TYPE E) .................. Derate Linearly at 8 mW/oC to 156 mW current chara.cteristics.
For TA = -55 to +87.5°C (PACKAGE TYPES F. H) ............................................ 250 mW
For TA = +87,5 to +125°C (PACKAGE TYPES F. H) .............. Derate Unearty at 8 mW/oC to 94 mW
PACKAGE TYPES F. H ......................................... , ..... , ... , ......... -55 to +125°C
PACKAGE TYPE E ............. , .................................................... -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) .............. , .............................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING): '
At distance1/16± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max, ......................... +285°C

For maximum reliability. nominal operating conditions should be selected
so that operation is always within the following ranges:
,v
LIMITS.
CHARACTERISTIC UNITS 5 10 15
MIN. MAX. DRAIN-lO-SOURCE VOL.TAGE {Vosl-V
92CS·294""RI
Supply-Voltage Range (For T A=
Full Package-Temperature Range) 3 18 V Fig.3 - Minimum output low fsink}
410
CD40107B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 0 C, CL = 50 pF,lnputtr,t,= 20 ns

Volts Typ. Max.
5 100 200
Propagation Delay:
RL*=120n 10 45 90 ns
High·to·Low, tpHL
15 30 60
5 100 200
Low·to·High, tpLH RL*=120n 10 60 120 ns
LOAD CAPACITANCE CCLI-pF
15 50 100 92CS-:29431
5 50 100 Fig.4 - Typical transition time as a function of

Transition Time:
RL*=120n 10 20 40 ns load capacitance.
High·to·Low, tTHL
15 10 20
5 50 100
Low·to·High, tTLH
Average Input Capacitance, CI N

RL*=120n
Any Input
10
15
35
25
5
70
50
7.5
ns
pF
II
Average Output Capacitance, COUT Any Output 30 - pF
* R L is external pull·up resistor to VDD.
LOAD CAPACITANCE 'Ct.) - pF

9ZCS-2'436Rt
Fig.5 - Typical propagation delay time as a


CONDITIONS Values at -55, +25, +125 Apply to F,H Packages
ISTIC UNITS
Vo VIN VOD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent Device
- 0,5 5 1 1 30 30 - 0.02 1
Current - 0,10 10 2 2 60 60 - 0.02 2
- 0,15 15 4 4 120 120 - 0.02 4 J1A
IDO Max.
- 0,20 20 20 20 600 600 - 0.04 20
Output low
0.4 0,5 5 21 20 14 12 16 32 -
(Sink) Current 1 0,5 5 44 42 30 25 34 68 -
IOlMin. 0.5 0,10 10 49 46 32 28 37 74 - 10°2 .. 68101 2 .. 6~02 2 4.68103 2 4 6~04 2 4 6~05
1 0,10 10 89 85 60 51 68 136 - mA INPUT FREQUENCY If1) - kHz
0.5 0,15 15 66 63 44 38 50 100 - 92CS-Z9438AI
Fig.6 - Typical power dissipation as a

Output High function of input frequency.
(Source)
Current No Internal Pull·Up Device
IOH Min.
Input Low 4.5 - 5 1.5 - - 1.5
Voltage 9 - 10 3 - - 3 ~.rF~~------~~
VIL Max." 13.5 - 15 4 - - 4
V
500l£F
Input High 0.5,4.5 - 5 3.5 3.5 - -

Voltage
VIH Min.'
1,9 - 10 7 7 - -
PULSE
GENERATOR
1.5,13.5 - 15 11 11 - -
Input Current
liN Max. - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10· 5 to.l J1A
Output Leakage
Current 18 0,18 18 ,2 2 20 20 - 10.4 2 J1A 92CS-2943~
10Z Max.
Fig. 7 - Power·dissipation test circuit
* Measured with external pull·up resistor, RL = 10 kn to VDD. for CD40101BE.
411
CD40107B Types
INPUTS
o
Vss
Fig.8 - Quiescent-device
current teSt circuit.
Voo INP(JU
VDO S NOTE'
92CS-29410R2
~ ~i~~~:il~~~~~S
VSS TO BOTH VOO ANOVSS'
NOTE: NOS. IN PADS FOR CD40107SE CONNECT ALL UNUSED
INPUTS TO EITHER
NOS. OUTSIDE CHIP FOR CD401078F Voo OR VSS'
VSS
Dimensions and Pad Layout for CD401078H.

are dedved from the basic inch dimensions as in-
Fig. 9 - Input-current test
dicated. Grid graduations are in mils (10- 3 inch),
circuit.
The photographs and dimensions of 98Ch CMOS chip

represent B chip when it is part of the wafer. When the
wafef is separBted into individual ChiPS, the angle of
chip, rherefore, may differ slightly from the nominal
01 --3 mils to + 16 mils applicable to the nominal
dimensions shown. V ,H
I N P UVDO
TO. OUTPUTS~VO:Okn
~
V IL
+
_
AD.
B
c=A.B
2
3
7
6
Voo
0
E
NC
NC
C.t;:B
I.
13
12
10
Voo
NC
NC
NOTE:
OF INPUTS
Fig. to
Vss
TEST ANY COfIjBINATION
- Input-voltage
test circuit.
92CS'29411
NC F-o:E
Vss" S F" M VSS NC
TOP VIEW TOP VIEW

Special Considerations for CD40107B
CD40107BE CD40107BF 1. Limiting Capacitive Currents for Cl >
500 pF, VDD > 15 V.
TERMINAL ASSIGNMENTS For VDD> 15 V, and load capacitance
(Cll from output to ground> 500 pF,
an external 25 n series limiting resistor
should be inserted between the output
terminal and Cl. No external resistor is
necessary if Cl < 500 pF or VDD <
15 V. .
2. Driving Inductive loads
When using the CD40107B to drive in-
ductive loads, the load should be shunted
with a diode to prevent high voltages
from developing across the CD401078
output.
412
CD401088 Types
CMOS 4 x 4 Multiport WRITE
reatures:
Register • Four 4-bit registers
ENABLE
High-Voltage Types (20-Volt Rating) • One input and two output buses
DATA {
DO
01
,, QD}01 WORD A
• Unlimited expansion in bit and word INPUTS ~2 6 02 OUTPUT
directions , "
• Data lines have latched inputs
II 3-state outputs
The RCA-CD40108B is a 4 x 4 multipart
"}"
register containing four 4-bit registers, write .. Separate control of each bus, allowing
simultaneous independent reading of
address decoder, two separate read address
anv of four registers on Bus A and ""2 01
02
WORO E!
OUTPUT
decoders, and two 3-state output buses.
Bus B and independent writing into ,
When the ENABLE input is low, the cor- anv of the four registers
responding output bus is switched, inde-
pendentlv of the ciock, to a high-impedance
• CD40108B is pin-compatible with "1
3-STATE B
industrv tvpe MC14580
state. The high-impedance third state pro-
vides the outputs with the capability of being .. Standardized, svmmetrical output FUNCTIONAL DIAGRAM
connected to the bus lines in a bus-organi zed characteristics
svstem without the need for interface or .. 100% tested for quiescent current at 20 V
.. Maximum input current of 1 IlA at 18 V
pull-up components.
over full package-temperature range; wo WI ROA RIA ROB RIB
When the WRITE ENABLE input is high, 100 nA at 18 V and 25 0 C
all data input lines are latched on the positive .. Noise margin (over fuli package-
transition of the CLOCK and the data is temperature range):
entered into the word selected bV the write 1 Vat VDD = 5 V
address lines. When WRITE ENABLE is low,
2 V at VDD = 10 V
the CLOCK is inhibited and no new data is
entered. In either case, the contents of anv 2.5 V at V DD = 15 V
word mav be accessed via the read address .. 5-V, 10-V, and 15-V parameVic ratings
lines independent of the state of the CLOCK II Meets all requirements of JEDEC
input. Tentative Standard No. 13A, "Standard

ENABLE 8
Specifications for Description of 'B'
The CD401088 types are supplied In Series CMOS Devices"
hermetic 24-lead dual-In-Ilne ceramic
packages (0 and F suffixes); 24-lead dual- Applications:
Fjg. 1 - Block djagram.
In-line plastic packages (E suffix). 24-lead II Scratch· pad memories
ceramic flat packages (K suffix), and In chip .. Arithmetic units
form (H suffix). • Data storage
(Voltages referenced to VSS Terminal) ................................................ -D.S to +20. V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -D.S to VDD +D.S V
;'0• • • • • •
"z
DC INPUT CURRENT, ANY ONE INPUT ..................................................... ±1D mA ~ 25
.
~ 20
For T A = -40. to +60'C (PACKAGE TYPE E) ................................................. SDO mW
For T A =+60 to +8S'C (PACKAGE TYPE E) ................... Derate Linearly at 12 mWI'C to 20.0. mW § 15
For TA = -55 to +1OO'C (PACKAGE TYPES D, F, K) .......................................... SOO mW g

For TA =+100 to +12S'C (PACKAGE TYPES D, F, K) .......... Derate Linearly at 12 mW/'C to 20.0 mW ~ 10
DEVICE DISSIPATION PER OUTPUT TRANSISTOR: 5 ,

For TA =FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 10.0 mW
PACKAGE TYPES D, F, K, H ........................................................ -SS to +125'C ORAIN-TO-SOURCE VOLTAGE (VOs)-V
PACKAGE TYPE E .................................................................. -40. to +8S'C

Fig. 2- Typical output low (sink)
STORAGE TEMPERATURE RANGE (T stg) ............................................. -65 to +15D'C
current characterjst;cs.
At distance 1/16± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.......................... +26S'C
TRUTH TABLE
_.-
CLOCK WRITE WRITE WRITE READ READ REAO READ~NABLE ENABL7 On DnA °nB
ENABLE 1 0 1A OA 1B DB A B
1--- ---- 1---- _. ---- f---- 1 - - -
~ Sl 52 51 52 Sl 52 1 1 1 1
~
~'-
51 52 Sl 52 SI 1
0._1- 0. 0
X X X 0 X Z Z
~ Dil to W(lid 1 Word?
word a
1---
~ I Word 0 WOld 1 Word')
not .11\(', ..11 out
-- --- ---- f - - 1---- ------ C----
X X X 0 0 1 1 1 X WOld 2 Word 1
0(1\ out
-- ---- - - - I - - 1--- ------ - - 1--- - - 10 15
DRAIN-TO-SOURCE VOLTAGE
~
(VDS)~V
X X X X X X X 1 1 X NC NC
1 HIGHLEVEl,O LOWLEVEL,X DON TCAFlf l~HI(;HIMPf[)ANU Fig. 3- M;njmum output low (s;nk)
S I ..Inn S2 refer til Input stdU'S 01 "'1h .. , 1 or 0 current characteristics.
413
CD40108B Types
RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted. DRAIN-lO-SOURCE vOLTAGE (Vos)-V
-IS -10 -5
VDD LIMITS
(V) MIN. MAX.
Supply Voltage Range
(For TA = Full Package - 3 18 V
Temperature Range)
Set·Up Time: 5 0 -
Data to Clock, tS(D) 10 0 - ns
15 0 -
Write Enable to Clock, 5 250 -
tS(WEI 10 100 - ns Fig. 5- Tvpical output high (source)
Write Address to Clock, 5 250 - .,
DRAIN-TO-SOURCE VOLTAGE \Vos)-V
tS(WA) 10 100 - ns
15 70 -
Hold Time: 5 220 -
Data to Clock, tH(D) 10 100 - ns
15 80 -
tH(WE) 10 130 - ns
15 80 -
Write Address to Clock, 5 330 - E,tt""+:.,.,t"'T,,,,I,.,,±""',EH""'j·"
tH(WA) 10 140 - ns
15 90 - :::: i::
Clock Input Frequency, 5 - 1.5
Fig. 6- Minimum output high (source)
tCl 10 - 3.5 MHz
15 - 4.5
Clock Pulse Width, 5 350 -
Clor WE 10 130 - ns
tw 15 90 -
5 - 15
Clock Rise or Fall Time, 10 - 5 JlS
trCl or ttCl 15 - 5
Fig. 7- Typical propagation delay t;;:;S;;';'9

function of load capacitance (CL or
WE to a).
Do
WE
WA--~---------4----~~------~~J~~~'------------
RA---+,--~------r.---------------r.-----r-~~
Q.
Fig. 4- Timing diagram.
LOAD CAPACITANCE [CL1-pF

"11(';-:>-4122

of load cBpilcitsnce.
414
CD40108B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
Cl =50 pF, Rl = 200 kn
=25°C; Input tr,tf =20 ns,
•
,·
"". _ENT T'-.'T:rl'jl~~l !
' ~~.SJ ./~~
1""",•
CHARACTERISTIC

VDD
(V)
5
Min.
-
LIMITS
Typ.
360
Max.
720
UNITS C •,
~
ilD".
II.~
,/-
...
,,0 ;r"
fJ
:
•• ,
...
: :
tpHL' tplH 10 - 140 280 ns ~ : 1

I 1/ VI/ 00 ·.
• 0
Clock or Write Enable to Q 15 - 100 200 Ill/. II I. ·.

Read or Write Address to Q 5 - 300 600
i2 "",• " !.-' :
· ... . ... ... r:'li'I-7,-..
• II I'
r:.'1I' o
Cl.-5QpF-.
10 - 120 240 ns
15 - 85 170 .,.,lilt"
, V Ii ,
jl
24' •
i
3-State Disable Delay Time: 5 - 100 200 10
INPUT FREQUENCY IIII-IiHI
10 - 50 100 ns 92C5-292.16
tpZH' tpHZ 15 - 40 80 Fig. 9- Typical powsr dissipation 11$ a

tpZl' tplZ 5 - 130 260
•
10 - 60 120 ns
15 - 50 100
Output Transition Time: 5 - 100 200
tTHL' tTLH 10 - 50 100 ns
15 - 40 80
Minimum Setup Time: 5 - -95 0
"00 INPuQs
VOO NOTE
Data to Clock tS(DI 10 - -35 0 ns ~ ~:~~::I~~~~~S
15 - -20 a 'Iss TO BOTH YaD AND Vss
CONNECT ALL. UNUSED
5 - 125 250 INPUTS TO EITHER
VOD OR Vss'
Write Enable to Clock tS(WEI 10
15
-
-
50 100
70
ns VSS
35
5 - 125 250
Write Address to CloCk tS(WAI 10 - 50 100 ns Fig. 10- Input leakage current
15 - 35 70 test circuit.
Clock Rise and Fall Time: 5 - - 15

trCL, tfCl 10 - - 5 JJS
15 - - 5
Minimum Hold Time: 5 - 110 220
Data to Clock tH(DI 10 - 50 100 ns
15 - 40 80
Write Enable to Clock tH(WEI 10

5 -
-
135
65
270
130 ns
.
Vss
INPuTS
15 - 40 80
-- 5 - 165 330
Write Addtess to Clock tH(WA) 10 - 70 140 ns
15 - 45 90
5 1.5 3 -
Maximum Clock Input Frequency,
10 3.5 7 - MHz
VSS
tCl 15 4.5 9 - Fig. ,,- Ouiescent-devjce-current
Minimum Clock Pulse Width, 5 - 175 350 test circuit.
Clock or Write Enable 10 - 65 130 ns
.tW(CLI 15 - 45 90
Write Address 5 - 150 300
tW(WA/ 10 - 75 150 ns
15 - 45 90
Average Input Capacitance,
- - 5 7.5 pF 'NPUTOVOIlOUTPUTS
(Any Input) CI V'N
'- ~
V~L ~
NOTE:
Vss ~SJN~"u~~0M8IN.TION
9ZCS-iil7441RI
Fig. '2- Input-voltage test circuit.
415
CD401088 Types
liMITS AT INDICATED TEMPERATURES (OCI
CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H, Packages
ISTIC UNITS
Vo VIN VDD +25
Current, - 0,10 10 10 10 300 300 - 0.04 10
p.A
100 Max. - 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - 0'8
,. 2" VDD
028
(Sinkl Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - ~-STATE A "
22
0'.
008
IOlMin.
- 3- STATE B
,.,.
00 A 2'
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 0' A 20 DO
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
.
02A
Output High 0'
0" 02
(Sourcel 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - WRITE 0 ',7 D'
Current,
IOH Min.
9.5
13.5
0,10
0,15
10
15
-1.6
-4.2
-1.5
-4
-1.1
-2.8
-0.9
-2.4
-1.3
-3.4
-2.6
-6.8
-
-
WRITE I
READ 19
READ 08
•
'0 ..,. CLOCK
WRITE ENABLE
READ IA
Vss "
'2
" READ OA
Output Voltage: - 0,5 5 0.05 - 0 0.05 TOP VIEW
low·level, -
- 0,10 10 0.05 0 0.05 92CS-Z7697
VOL Max.
- 0,15 15 0.05 - 0 0.05
V TERMINAL ASSIGNMENT
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·level, - 0,10 10 9.95 9.95 10 .-
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
Vil Max.
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
Input Current
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 p.A
3·State Output
Leakage Current 0,18 0,18 18 ±0.4 ±0.4 ±12 ±12 - ±10-4 ±0.4 p.A
lOUT Max.
Dimensions in parentheses ~re in millimeters and are


cleavage may vary with respect to the chip 'ace fOl
different chips. The actual dimensions of the isolaled
dimensions shown. The user should conSIders tolerance
dimensions shown.
Dimensions and Pad Layout for CD4010BBH
416
CD40108B Types
•
*3-STA'rE
B ENABLE
r-----------------T--------------l
d
PIN 24 = 1100
PIN 12 = Vss
! 0 :A i ENABLE
VDD
I I
I ~OUT
PUT
q
I
I
IWo-___ ~---.--J
* ALL INPUTS PROTECTED I

QB
BY COSfMOS INPUT I
PROTECTION NETWORK Vss
I
92CL-2'l422 I
I DETAIL OF
I MEMOAY
L ___ CELL
__________ _
Fig. 13- Schematic diagram 92CL-29422
P.G. I J1J1.Jl.Il.. CL
P,G. 2 ~NABLE
ENABLE VDD
INPtJT sO%"\- 1;)'%
'..... t\....-...A ~.. -VSS
IPLl '- I.!PlL
I.- 90% -liDO
Q {IO% VOL
OUT- YOH
PUTS 10% -VSS
TEST VOLTAGE I PHZ

!-l plH
CHAR at 0 at Q
91CM-29217
lpHZ liDO VSS QnA,B~
IpZH liDO IISS
tpLZ IISS 1100 !-- REPETITIVE WAVEFORMS - -~
IPZL \ISS 1100 92CN-2g218RI
Fig. 14- Ourput-enable-delay-times test Fig. 15- Power-dissipation test circuit

circuit and waveforms. and wa veforms.
417
CD401098 Types
CMOS Quad Low-to-High

Voltage Level Shifter Features:.
• Independence of power supply sequence
considerations-Vee can exceed VOO, input
The RCA-C040109B contains four low-to- signals can exceed both Vee and VDD
high-voltage level·shifting circuits. Each cir· • Up and down level-shifting capability
cuit will shift a low·voltage digital·logic • Three-state outputs with separate enable controls
input signal (A, B, c, 0) with logical 1 = VCC • Standardized, symmetrical output characteristics
and logical 0 = VSS to a higher·voltage out·
put signal (E, F, G, H) with logical 1 = VOO
and logical 0 = VSS. • Maximum input current of llJA at 18 V
over full package-temperature range; FUNCTIONAL DIAGRAM
The RCA-C040109, unlike other low-to· (1 of 4 units I
100 nA at 18 V and 25 0 e
high level-shifting circuits, does not require • Noise margin (full package-temperature
the presence of the high·voltage supply range)
(VOO) before the application of either the = 1 Vat Vee = 5 V, VDD = 10 V
low-voltage supply (VCe) or the input sig· = 2VatVce= 10V, VDD =15V
nals. T~ere are no restrictions on the se· • 5-V, 10-V, and 15-V parametric ratings
quence of application of VOO, VCC. or the • Meets all requirements of JEDEC Tentative
input signals. In addition. with one exception Standard No. 13A, "Standard Specifications
there are no restrictions on the relative for Description of 'B' Series CMOS Devices"
magnitudes of the supply voltages or input RECOMMENDED OPERATING CONDITIONS
signals within the device maximum ratings. For maximum reliability, nominal operating conditions should be selected
provided that the input signal swings so that operation is always within the following ranges:
between VSS and at least 0.7 Vee; Vee may
exceed VOO, and input signals may exceed LIMITS
Vee and VOO. When operated in the mode MIN. MAX.
Vee> Voo, the e040109 will operate as a
Supply-Voltage Range (For T A =
high-to-Iow level-shifter.
Full Package·Temperature Range) 3 1B V
The C040109 also features individual three·
state output capability. A low level on any MAXIMUM RATINGS, Absolute-Maximum Values:
of the separately enabled three-state output DC SUPPLY-VOLTAGE RANGE, (VOO)
controls produces a high·impedance state in (Voltages referenced to VSS Terminal) ................•............................... -0.5 to +20 v
the corresponding output. INPUT VOLTAGE RANGE. ALL INPUTS .............................•............• -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................•..... : ............................. ±10 mA
The e0401 09B-Series types are supplied in POWER DISSIPATION PER PACKAGE (PO):
16-lead ceramic dual-in-line packages (0 For T A = -40 to +60· C (PACKAGE TYPE E) ....................................•............ 500 mW
and F suffixes), 16-lead dual-in-line plastic For T A = +60 to +85·C (PACKAGE TYPE E) ................... Derate Linearly at 12 mW/·C to 200 mW
packages (E suffix), 16-lead ceramic flat For T A =-55 to +100·C (PACKAGE TYPES D, F, K) .......................................... 500 mW
packages (K suffix), and in chip form (H For T A = +100 to +125·C (PACKAGE TYPES D, F, K) •......... Derate Linearly at 12 mW/·C to 200 mW
suffix). DEVICE DISSIPATION PER OUTPUT TRANSISTOR:
For T A =FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW
Applications: PACKAGE TYPES D. F. K, H ........................................................ -55 to +12S·C
PACKAGE TYPE E .................................................................. -40 to +8S·C
• High-or-Iow level-shifting with three-state
STORAGE TEMPERATURE RANGE (Tstg) ................................•............ -65 to +IS0·C
outputs for unidirectional or bidirectional LEAD TEMPERATURE (DURING SOLDERING):
bussing At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. . ........................ +265·C
• Isolation of logic subsystems using separ-
ate power supplies from supply sequenc·
ing, supply loss and supply regulation VDO
considerations
d
TRUTH TABLE
INPUTS OUTPUTS
~"'31
A,B,C,D
0
1
X
LOGIC 0 = LOW(Vss)
ENABLE
A,B,C,D
1
1
0
X = DON'T CARE
LOGIC 1 = VCC at "I NPUTS and VDDat OUTPUTS
E,F,G,H
0
1
Z
Z - HIGH IMPEDANCE
fr cc
--
.
*AlL INPUTS PROTECTED
NETWORK
Vss
9
Vss
VCC"!
Voo= 16
Vss'" 8
92CS-29446
Fig. I - CD40109810gic diagram (I of 4 un/to).
418
CD40109B Types
CONDITIONS Values ai-55, +25, +125 Apply to D, F, K, H Packages
ISTIC UNITS
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min_ Typ_ Max.
Current, - 0,10 10 2 2 60 60 - 0.02 2
100 Max. jJ.A
- 0,15 15 4 4 120 120 - 0.02 4
- 0,20 20 20 20 600. 600 - 0.04 20
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - DRAIN-lO-SOURCE VOlTAGE IVosl-V
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. Fig.2 - Typical output low 'sink}
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 - current characteristics.
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
qurrent. 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
Output Voltage:
13.5
-
0.15
0,5
15
5
-4.2 -4
0.05
-2.8 -2.4 -3.4
-
-6.8
0
-
0.05
I
Low·Level, - 0 0.05
- 0,10 10 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0.5 5 4.95 4.95 5 -
High-Level. - 0,10 10 9.95 9.95 10 -
VOH Min. 14.95 14.95 15 -
- 0.15 15
Input Current
0.18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 jJ.A I
liN Max. DRAIN-TO-SOtJRCE VOLTAGE (Vosl-V
3-State Output Fig.3 - Minimum output low (sink)

Leakage Current 0,18 18 ±0.4 ±0.4 ±12 ±12 - ±1O-4 ±0.4 jJ.A curren t characteristics.
lOUT Max.
Vo VCC VOO QRAaN-To-IOWtCE VOLT"" IVost-y
(V) (V) (V)
Input Low
Voltage,
1,9 5 10 1.5 - - 1.5
VIL Max. 1.5,13.5 10 15 3 - 3
V
Input High 1,9 5 10 3.5 3.5 - -
Voltage, 1.5,13.5 10 15 7 7 - -
VIH Min.
Fig.4 - Typical output hIgh ',ourcs).
DRAIN~TO-SOURCE *TAGE IVos)-Y
LOAD CAPACITANCE ICLI-p~2CS_2144'
Fig.5 - Minimum output high 'source} Fig.6 - Typical transition time as a function Fig.7 - Typical high-to-Iow propagation de/ay time
current characteristics. of load capacitance. • 8 function of load capacitance.
419
CD40109B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A; 25°C. Input t r • tf; 20 ns. I i I..BI •• T TEMPERATUR. 11 1
CL =50 pF. RL = 200 kn unless otherwise specified

11"
;;
CHARACTERISTIC
SHIFTING
MODE
VCC
(V)
VDD
(V)
LIMITS
Typ. Mal<. UNITS I~
I~
Propagation Delay - Data Input 5 10 300 600
to Output: L-H 5 15 220 440
10 15 180 360
High·to·Low Level. tpHL ns
10 5
II
250 500
H-L 15 5 250 500
15 10 120 240 100
5 10 130 260
Fig.8 - Typicallow~to-high propagation delay time
L-H 5 15 120 240 as a function of load capacitance.
10 15 70 140
Low·to·High Level. tpLH ns
10 5 230 460
H-L 15 5 230 460
15 10 80 160
3·State Disable Delay: 5 10 60 120
RL = 1 kO L-H 5 15 75 150
Output High to High 10 15 35 70
Impedance. tpHZ ns
10 5 200 400
H-L 15 5 200 400
15 10 40 80
5 10 370 740
L--H 5 15 300 600
Output Low to High
10 15 250 500
Impedance, tpLZ ns
10 5 250 500 Fig.9 - Typical input switching as a function of
H-L 15 5 high-level supply voltage.
250 500
15 10 130 260
5 10 320 640
L-H 5 15 230 460
High Impedance to 10 15 180 360
Output High, tpZH ns
10 5 300 600
H-L 15 5 300 600
15 10 130 260
5 10 100 200
L-H 5 15 80 160
High I mpedance to
10 15 40 80
Output Low. tpZL ns
10 5 200 400
H-L 15 5 200 400
15 10 40 80 SUPPLY VOLTAGE 1Va:I-V
5 10 50 100
Fig. 10 - High·level supply voltage ....
L-H 5 15 40 80 low·leve~ supply voltage.
10 15 40 80
Transition Time. tTHL, tTLH ns
10 5 100 200
H-L 15 5 100 200 ~ AMBIENT TEMPERATURE ITA 1-2e-c
15 10 50 100
Input Capacitance, CI Any Input 5 7.5 pF
Fig. t 1 - Typical dynamic power dissipation as a

420
CD401098 Types
TEST CIRCUITS
TEST va.T"GE
HAR.
• ee• •Vss
.
'PHZ
'PLZ
tplH
V
V
vee
VDD
V
vss
INPUTS .-L-'--,
o
Vss
v,,
Fig. 13 - Ouies::ent device current.
Fig. 12 - Output enable delay times test circuit and waveforms.
II
O
" NPUe ' V VDO
Vee :~:~URE INPUTS

~ SEQUENTIALLY.
"ss TO BOTH "00 ANOVSS'
CONNECT ALL UNUSED
INPUTS 10 [ITHER
Ycc OR "ss
HOTE:
v,,
Of INPUTS
Fig. 14 - Input voltage. Fig. 15 - input current. Fig. 16 - Dynamic power dissipation test circuit.
Vee
ENABLE A
••
15
Voo
ENABLE 0
•, ••
E
F "
12
H
Ne
• •
ENABLE 8 7 "
.0
G
Vss •TOP VIEW

ENABLE C
CD40109B
TERMINAL ASSIGNMENT
Dimensions in parentheses are m millimeters and

are derived from the baSIC inch dimensions as in·

represent a chip when it is part 01 the waief. When the
waler is separated mto individual chips, the angle of
differsnt chips. The actual dimensions of the isolated
Chip, therefore, may differ slighlly from the nominal
92CS-36897
dimensions shown.
421
CD40110B Types
CMOS Decade Up-Down

Counter/Latch/Display Driver
:5:~:~ }~g
.
ClK UP 9
High-Voltage Type (20-VRating)
B
ClK ON 7
DISPLAY 12 e f3
b RESET 5 3 f III
lal/lr131~1516111B191
o I 2 3 a 4 6 7 9
"
d
, mH
lATCH
ENABLE 6
4 2
IOCARRY
t!-
II BORROW
Features:
92CS-31380
~-.---F~
• Separate clock-up and clock-down lines
VOO"16
• Capable of driving common cathode LEOs and other
displays directly vss·a
92CS-3137S
• Allows cascading without any external circuitry
• Maximum Input current of 1pA at 18 Vover full package-
temperature range; 100 nA at 18 V and 25° C FUNCTIONAL DIAGRAM
The RCA-C040110B is a dual-clocked up/down counter • Noise margin (full packagectemperature range) =
with a special preconditioning circuit that allows the 1 Vat VOO =5 V
counter to be clocked, via positive going inputs, up or down 2 Vat VOO =10 V
regardless of the state or timing (within 100 ns typ.) of the 2.5 Vat VOO= 15 V
other clock line. • 5 V, 10 Vand 15 V parametric ratings
The clock signal is fed into the control logic and Johnson • Meets all requirements of JEDEC Tentative Standard
counter after it is preconditioned. The outputs of the No. 13S, "Standard Specifications for Description of
Johnson counter (which include anti-lock gating to avoid 'S'Series CMOS Devices".
being locked at an illegal state) are fed into a latch. This Applications:
data can be fed directly to the decoder through the latch or
• Rate comparators
can be strobed to hold a particular count while the Johnson • General counting applications where display is desired
counter continues to be clocked. The decoder feeds a
• Up-down 'counting applications where input pulses are
seven-segment bipolar output driver which can source up random in nature
to 25 mA to drive LEOs and other displays such as low-
voltage fluorescent and incandescent lamps.
A short durating negative-going pulse appears on the The C040110B types are supplied in 16-lead dual-in-line
BORROW output when the count changes from 0 to 9 or the ceramic packages (0 and F suffixes), and 16-lead dual-in-
CARRY output when the count changes from 9 to O. At the line plastic package (E suffix), and also available in chip
other times the BORROW and CARRY outputs are a logic 1. form, (H suffix).
The CARRY and BORROW outputs can be tied directly to
the clock-up and clock-down lines respectively of another
C040110B for easy cascading of several counters.
CLOCK uP-LJ'""-----,
CLOCk OOWN I "L...===':=
RESET'1""-j--------'
Toro~OO~l~E~£~Mq~lE~r-----~
LATCH ENABLE - ; - - - - - - . ,
92CS-29200RI
Fig. 1 - Functional diagram.
422
CD40110B Types
MAXIMUM RATINGS, AHolute Maximum Vldue.:
DC SUPPLY-VOLTAGE RANGE. (VDO)

(Voltages referenced to VSS Terminal) .............................................................................. -0.5 to +20 V
INPUT V9LTAGE RANGE. ALL INPUTS ••.•..••...•.•......••.•.•.•..••..••••.••••.••.••.•••••••••••••••.•..••• -0.5 to VOD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................. ± 10 mA
POWER OISSIPATION PER PACKAGE (PO):
For TA = -40 to +60·C (PACKAGE TYPE E) ............................................................................... 500 mW
For T A = +60 to +85·C
(PACKAGE TYPE E) ..................................................................... Derate Linearly at 12 mW/· C to 200 mW
ForTA = -5510 +l00·C (PACKAGE TYPES D. F) ......................................................................... 500 mW
For TA = +100 to +125·C
(PACKAGE TYPES D, F) ................................................................. Derate Linearly at 12 mW/· C to 200 mW
ForTA = FULL PACKAGE-TEMPERATURE RANGE
(All Package Types) .................................................................................................... 100 mW
O~~~~~~~::SE~~;~R.~ ~~~~.~ ~:~).: •...•....••.••......••.•.•..•.•....••.•....••.••.••••.••.•.•....•..•..•.. -55 to +125·C

PACKAGE TYPE E .................................................................................................-40 to +85·C
I
STORAGE TEMPERATURE RANGE (Tstg) .. • . • • . .. .. . . . • . . . . . . • . • • . .. . . . . . .. . . . . . • . .. .. . . . . .. .. • .. . • • • . . • .. . . • • .. .• -65 to +150· C
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm)
from case for lOs maX. . • • .. . • . . • .. • . . . • .. . . . . . . . .. . . . . . .. • .. . .. .. .. • • . • . .. . . .. • . .. . .. . .. . • . . • . .. . . . • .. . .. . . . .. . . • . . . ... +265· C

For maximum reliability, nominal operating condltlonl Ihould be lelected 10 that operation II alwaYI within the following
rangel: .

V MIN. MAX.
Supply-Voltage Range (For TA = Full Package Temperature Range) - 3 18 V
5 - 1
Clock -Input Frequency fCL 10 - 3 MHz
(Sum of CLUP & CLON Freqs.) 15 - 5
5 110 -
Clock Pulse Width tw 10
15
40
30
--
5 110 -
Latch Enable Pulse Width 10 30 -
15 24 - ns
5 550 -
Reset Removal-Time 10 200 -
15 130 -
5 350 -
Reset Pulse Width 1Q 170 -
15 120 -
423
CD40110B Types
Conditions LImits at Indicated Temperatures (0 C)

Values at -55, +25, +125 for D, F, H Packages
Charecterlstlc Values at -40, +25, +85 'or E Packages Units
'OH VOH VIN VDD +25

(mA) (V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent Device - - - 5 5 5 150 150 - 0.04 5

Current - - - 10 10 10 300 300 - 0.04 10 pA
Max. 100 - - - 15 20 20 600 600 - 0.04 20
- - - 20 100 100 3000 3000 - 0.08 100
Output Voltage - - 05 5 0.05 - ..Q ....!l.O5..

low-level - - 010 10 0.05 - 0 :0.05 V
Max. VOL - - 0,15 15 0.05 - 0 0.05
H~h-level ,. - - 05 5 - - - - - 4.55 -
In. VOH - - 010 10 - - - - - 9.lt5 V
- - 015 15 - - - - - 14.55 -
I~ut low Voltage - 0.5 3.8 - 5 1.5 - - 1.5
ax. Vil - 1,8.8 - 10 3 - - 3 V
- 1.5,13.8 - 15 4 - - 4
Imut High Vol tag - 0.5,3.8 - 5 3.8 3.5 - -

In. VIH - 1 8.8 - 10 7 7 - - V
- 1.5,13.8 - 15 11 11
•
-5
-
-
-
-
3.9
3.65
4
3.7
3.9
3.7
4.5
4.3
-
-
-10 - - 5 3.55 3.65 3.65 4.25 -
-15 - - 3.5 3.5 3.6 4.15 -
-20 - - 3.45 3.35 3.45 4 -
-25 - - 3.4 3.3 3.4 3.9 -
7-Segment Output! -5
• -
-
-
-
8.75
--'i4S
8.85
B.55
8.75
8.55 ~
9.5 -
-
Output Drive -10 - - 10 8.42 8.5 8.5 9.25 - V
Voltage, High -15 - - 8.4 8.47 8.47 9.2 -
Min. VOH -20 8.4 8.40 8.45 9.1
-25 - - 8.3 8.25 8.3 9
•
-5
-
-
-
-
13.8
13.65
13.9
13.75
13.8
13.75
14.5
14.35
-
-
-10 - - 15 13.6 13.72 13.72 14.3 -
-15 - - 13.6 13.7 13.7 14.2 -
-20 - - 13.6 13.6 13.65 14.1
-25 - - 13.3 13.25 13.3 14.0 -
7-Segment Outputs
Output low
- 0.4 05 5 1.28 1.22 0.84 0.72 1 2 -
(Sink) Current
- 0.5 0,10 10 3.2 3 2.2 1.8 2.6 5.2
1.5 0, 15 15 8.4 8 5.6 4.8 6.8 13.6
Min. IOl
Carry Outputs
Output low
- 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current
- 0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8
Min. IOl
Output High - 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 -

~ource) Current
2.5 05 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2
in. IOH - 9.5
13.5
0, 10
0,15
10
15
-1.6
-4.2
-1.5
-4
-1.1
-2.8
-0.9
-2.4
-1.3
-3.4
-2.6
-6.8
-
Input Current
Max. liN
- 0, 18 0, 18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 pA
• 0(10 pA)
424
CD40110B Types
i'"E~z
R®-[)o-{>---I)o-W
I
x x x x x
o Q Q o Q o Q o Q
o
Y CLA Y CL B Y CLC Y CLo Y CL E
~
z TE ~ Z TE "0"
R R
w w
DETAIL LOGIC
'------Ii-+- Q
I - - - -...... -a
CL~CL
r-:- CL OUTPUT
DRIVER
---i>-
(ALL 7 SEGMENTS)
92CL-31384
Fig. 2 - Logic diagram with flip-flop and output-driver details.

(cont'd on pageS)
425
CD40110B Types
L
QA A
0
r
L
A
Qs 11"
A
E
Qc
'f"
C
A
s
Qo 0
QE
A-
T
'C"
0
c
"U
Qo,~~
-O:~CARRY
92CL-31384
Fig. 2 - Logic diagram with flip-flop and output-driver detailS.
TERMINAL ASSIGNMENT
DISPLAY SEGMENTS I 16 Voo

7-SEGMENT { :
OUTPUTS
a I c 7-SEGMENT
3 14
· ·J
'I-Ib
d OUTPUTS
TOGGLE ENABLE 4 13
RESET 5 12 •
,,_0 Ie LATCH ENABLE
CLOCK DOWIt·,
Vss
6
7
8
"
10
9
BORROW
CARRY
CLOCK UP
d TOP VIEW
92CS-31376 92CS- 31377
426
CD401108 Types
DYNAMIC ELECTRICAL CHARACTERISTICS al TA =25°C,lnpullr,I, =20 ns, CL =50 pF, RL =200 kQ

CHARACTERISTIC
Clock Up/Clock Down

5 - 300 600
Clock to Carry or Borrow tPLH. tpHL 15 - 70 140
5 - 925 1850
Clock to Segment tPLH. tPHL 10 - 360 720 ns
15 - 250 500
5 - 55 110
Minimum Clock Pulse Width 10 - 20 40
,
•
15 - 15 30
5 1 2.5 -
Maximum Clock Input Frequency feL 10 3 6 - MHz
(Sum of CLUP & CLON F) 15 5 8.5 -
5 - 175 350
Minimum Toggle Enable Pulse Width 10 - 75 150
15 - 55 110
5 - 55 110
Minimum Latch Enable Pulse Width 10 - 15 30
15 - 12 24
5 115 230 -
Output Pulse Width: 10 60 120 -
Carry 15 40 75 -
ns
5 140 275 -
Borrow 10 65 130 -
15 45 85 -
5 - 85 170
Transition Time: tTLH. tTHL 10 - 45 90
Carry or Borrow 15 - 30 60
5 - 100 -
Minimum Delay Time 10 -- 80 -
Between CLUP & CLON 15 - 60 -
5 - - 15
Maximum Clock Rise or Fall Time trCL. tfCL 10 - - 15 ps
15 - - 15
Resel
5 - 650 1300
Propagation Delay Time tpLH. tPHL 10 - 350 700
Reset to Output 15 - 160 320
5 - -275 0
Minimum Reset Removal Time 10 - -100 0 ns
15 - -65 0
5 - 175 350
Minimum Reset Pulse Width 10 - 85 170
15 - 60 120
427
CD401108 Types
TRUTH TABLE
CLOCK CLOCK LATCH TOGGLE RESET COUNTER DISPLAY

UP· DOWN * ENABLE ENABLE
.-r- x 0 0 0 Increments by 1 Follows Counter
X -f 0 0 0 Decrements by 1 Follows Counter
~ ~ X X 0 No Change No Change
X X 1 X 1 Goes to 00000 Remains Fixed
X X 0 X 1 Goes to 00000 Follows Counter
(Display =[7)
X X X 1 0 Inhibited Remains Fixed
-f X 1 0 0 Increments by 1 Remains Fixed
X
~ 1 0 0 Decrements by 1 Remains Fixed
X = Don't Care 1 = High State 0= Low State

• Typically 100 ns between clock-up and clock-down positive transitions are required to ensure proper counting.
AMBIENT TEMPERATURE {TA1=Z5°C
~
e
I
-~
J'30 GATE-IQ-SOURCE VOLTAGE (VGS)=15 V
i
~
25
~GATE
,
TO SOURCE VOLTAGE (VGSI" 15 V
.
~ 20
§ 10V
~ 10V
15 Vi 7.5_
~
'3 ~
~
0
10 '3 5
~
a o
~
a
5 5V ~ 2.5 5V
o
5 10 15 5 10 15
DRAIN-IO-SOURCE VOLTAGE (VOS)-V DRAIN-iO-SOURCE VOLTAGE (VOS1-V
Fig. 3 - Typical carry or borrow output low (sink) Fig. 4 - Minimum carry or borrow output low
current characteristics. (sink) current characteristics.
DRAIN-iO-SOURCE VOLTAGE (Vos)-V DRAIN-iO-SOURCE VOLTAGE (Vos)-V

-15 -10 -5 -15 -10 -5
AMBIENT TEMPERATURE (TAI=25°C AMBIENT TEMPERATURE (TA)"25°C
GATE-iO-SOURCE VOLTAGE {VGS1"-5V

-d GATE -TO-SOURCE VOLTAGE (YGSI; -5 v
~
e
I
~
10 >< -5 ~
§ ~
z
w
-15 ~ ~
~
o
u
-IOV
20 ~ -IO~
I5V
-ISV
Fig. 5 - Typical carry or borrow output high Fig. 6 - Minimum carry or borrow output high
(source) current characteristics. (source) current characteristics.
428
CD40110B Types
AMBIENT TEMPERATURE(~A I- 2S-C
- ,
~ 50
:!i~ 2.
~ .
5 ~ m ~ ~ ~ w ro 00 ~ ~ 20 40 60 80 100
LOAD CAPACllANE (CL}-pF LOAD CAPACITANCE lel l-pF
92C$-32846 92CS-J21147
Fig. 7 - Typical carry or borrow transition time Fig. 8 - Typical carry or borrow propagation
vs. load capacitance. delay time vs. load capacitance.
2 AMBIENT TEMPERATURE (TA ). 25-C
. ·,
,. •,
AMBIENT TEMPERATURE IT A 1=2S-C
+1+-
~
z
I
·,
'1- -
'f-- 1-- 3~~
__ ,6)
,.
/
I
~~
0
i ~~ ,0
/
··,,
iiiQ
"''"
RV
~~ct<~~I-l"
"
i? "~ -1/
u
~ ··,, LOAD CAPACITANCE

CL -15 pF
1>
1/ c~ '~O;~, I I I-~
10 15 20 25 30 10.,2 468, 2 .. 68. 0 2 468,022 .. 68,032 .. 68,0"
OUTPUT SOURCE CURRENT ('OHI-rnA
92CS-32848 CLOCK INPUT FREQUENCY (f cL ) - kHz
92CS-32849
Fig. 9 - Voltage across bipolar transistor vs. Fig. 10 - Typical dynamic power dissipation vs.
output source current. frequency.
voo
TEST CIRCUITS
16
CL
15
CL CL
14
CL CL
4 13
CL
12
CL
6 II
CL
7 10
8 9
VSS
92CS-2740LRI
92CS- 32850
Fig. 11 - Dynamic power dissipation test circuit. Fig. 12 - Quiescent device current.
NOTE,
MEASURE INPUTS
SEQUENTIALLY.
VSS TO 80TH Voo ANO VSS'
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS' NOTE:
VSS TEST ANY COMBINATION
VSS OF INPUTS
92CS-27402 92CS-27441RI
Fig. 13 - Input current. Fig. 14 - Input voltage.
429
CD40110B Types
..fL
CLuP
CLDN
..fL 92CS-328~3RI
Fig. 15 - Cascading diagram.
145
o
I- 4-10
(0.102-0.254)
142 -150~,~,..--_ _ _ _ _ _--t
(3.606-3.
92CS-34617
Dimensions and pad layout for CD4011 OB.
Dimensions In parentheses are in millimeters and The photographs and dimensions of each CMOS chip
are derived from the basic inch dimensions as represent a chip when it is part of the wafer. When the wafer
indicated. Grid graduations are in mils (10-3 inch). Is separated into individual chips, the angle of cleavage may
vary with respect to the chip face for different chips. The
actual dimensions of the isolated chip, therefore. may differ
slightly from the nominal dimensions shown. The user
should consider a tolerance -3 mils to +16 mils applicable
to the nominal dimensions shown.
430
Preliminary Data CD40117B Types
CONTROL
Programmable Dual I STROBE' DATA \
• •
4-Bit Terminator I. T
High-Voltage Types (20-Volt Rating) 4 PULL-UP OR
2. E
R
PULL-DOWN M
Features:
• One standard "8" output will drive eight terminator circuits.
RESI STORS
OR
4 LATCHES
4.
3' I
N
•
T
• Will terminate a CMOS data bus with up to 40 8-series inputs inputs or 3-state I.
0
R
outputs connected at VDD of 5 V. 4 PULL- UP OR S
• Input terminals protected by standard "8" series ESD protection network. PULL- DOWN 2. T
0
• Preserves final logic state.
• Output after switching is closer to VDD or Vss rail than with a resistor.
RESISTORS
OR
4 LATCHES
3.
4. •
U
S
E
• Requires only one solder connection. S
• Open circuited terminator not used will not affect performance. STROBE DATA
• Can be connected to any CMOS I/O line.

\ • •I 92CS·3!5283
• Draws current only when logic state is changing.

CONTROL
FUNCTIONAL BLOCK DIAGRAM
'.
• Can be preset.
I
The RCA CD40117B is a dual 4-bit terminator that can be Applications:
programmed by means of STROBE and DATA control bits • Error state identification.
to function as pull-up or pull-down resistors. The CD40117B • Replaces pull-up or pull-down resistors
can also be programmed to function as latches to terminate • Avoids floating inputs in modular systems
any open or unused CMOS logic when used with 3-state • Sharpens transistors (hysteresis)
logic or during a power-down condition. Considerable • Anti-bounce circuit
savings in power and board space can be realized when this
device is used to replace pull-up or pull-down resistors. STROBE A 14 VDD
When the STROBE is in the logic "1" state, the terminator STROBE B 13 DATA A
functions as a pull-up resistor if the DATA input is a logic
IA 3 12 DATA 8
"1" oras a pull-down resistor if the DATA input isa logic "0".
2A 4 II IB
When the STROBE is in the logic "0" state, the terminator
3A 10 28
performs the latch function, i.e., it follows the changing
states of the bus. If the bus goes into the high-Z state or into 4A 6 9 38
a power-down condition, the latched terminator retains the VSS 7 8 48
data ("1" or "0") that the bus carried before it switched to the TOP VI EW
high-Z or power-down state. If and when the bus changes
92CS- 34607
from the high-Z state to the state opposite to that which the
latch is storing, the bus will override the latch and the
terminator will reflect the state on the bus. The small TERMINAL DIAGRAM
geometries chosen for the inverters in the latch allow this
override mode. When checking the data bus whose last TRUTH TABLE
state is being preserved by the terminator, a resistor should
be used in series with the probe whose input capacitance
STROBE DATA 1A(B) 2A(B) 3A(B) 4A(B)
could trip the small latches. The resistance should be in
excess of the output impedance of the latch, i.e., R should
1 0 0" 0" 0" 0"
be >30 KQ at Voo =10 V. 1+ 1+ 1+ 1+
1 1 , ,
The STROBE and DATA inputs in each section can be 0 X * *
paralleled allowing this device to be used as an a-bit bus
terminator. 1 = High, 0 = Low, X = Don't Care
The CD40117B types are supplied in 14-lead hermetic dual- A Equivalent to pull-down resistor.
in-line ceramic packages (D and F suffixes), 14-lead dual- + Equivalent tn pull-up resistor.
in-line plastic packages (E suffix), and in chip form (H
'Equivalent to a latch.
suffix).
431
CD40117B Types
DC SUPPLY-VOLTAGE RANGE, (Voo)

(Voltage referenced to Vss Terminal) ................................................................................. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS .................................•..•.............•....................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................................................. ± 10 mA
ForTA = -40 to +60·C (PACKAGE TYPE E) ............................................................................... 500 mW
ForTA = +60 to +85·C (PACKAGE TYPE E) .......... , ...................................... Derate Linearly at 12 mWfOC to 200 mW
ForTA = -55 to 1OO·C (PACKAGE TYPE D, F) ............................................................................ 500 mW
ForTA = +100 to +125·C (PACKAGE TYPE D, F) ............................................ Derate Linearly at 12 mW/·C to 200 mW
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................... 40 mW
PACKAGE TYPE D, F, H ...........................•.............................................................. -55 to +125·C
PACKAGE TYPE E ..............................................................•..................................-40 to +85· C
STORAGE TEMPERATURE RANGE (Tstg) ..............•..........•................................................. -65 to +150·C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265·C

For maximum reliability, nominal operating conditions should be selected so thai operation Is always within the following
ranges:
LIMITS

(V) MIN. TYP.
Supply-Voltage Range (For TA=Full Package-Temperature Range) - 3 18 V
STROBE AlB) OATA AlB)

* 1(2) * 13(12)
50-58
2AIB)
4(10)
I~'
3AIB)
5(9) .1
92CS-35084
4AIB) Dimensions and pad layout for CD40117B.

6(8)
VOO=14
JEl
VSS= 7 Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
VOO 92CS - 34594RI as indicated. Grid graduations are in mils (10- 3
inch).
* INPUT PROTECTION
NETWORK The photographs and dimensions of each CMOS chip
represent a chip when it is part of the wafer. When the wafer
is separated into individual chips, the angle of cleavage may
Vss vary with respect to the chip face for different chips. The
actual dimensions of the isolated chip. therefore, may differ
Fig. 1 - Logic diagram (14 of CD40117B) should consider 8 tolerance -3 mils to +16 mils applicable
432
CD40117B Types
TYPICAL APPLICATIONS
""1"--------1/2 CD40117B----------.j
DATA
I
I
STROBE
I I
I I
I I
I I
I I
I
I
CPU I
CDPI802 I ______ 1
r---------------------~-----;_--~} ~~ DATA BUS
92CL-34592R1
Fig. 2 - Schematic of CD401178 interfacing with

microprocessor terminating an 8-bit bus line and
1/2 of CD401178 as a programmable pull-up/pull
down logic controller.
DATA
I----~JSTROBE
Vss 92CS-3460BRI
Fig. 3 - Schematic of CD401178 in anti-bounce circuit

application.
433
CD40117B Types

CONDITIONS Values at -55, +25, +125 Apply to 0, F, H Packages
CHARACTERISTIC Values at -40, +25, +85 Apply to E Package UNITS
r~ ~~~
VDD +2:»
(V) -55 -40 +85 +125 Min. Tm Max.
Quiescent o5 5 0.25 0.25 7.5 7.5 0.01 0.25
Device 0, 10 10 0.5 0.5 15 15 0.01 0.5
JlA
Current 100 - 0, 15 15 1 1 30 30 - 0.01 1
Max. - o 20 20 5 5 150 150 0.02 5
Output low 0.4 o5 5 - - . - - - 25 -
Sink Current IOl 0.5 0, 10 10 - - - - 60 -
Min. 1.5 o 15 15 - - - - - 250 -
Output High 4.6 0,5 5 - - - - - -25 - JlA
(Source) 2.5 0,5 5
Current IOH 9.5 o 10 10 - - - - - -60 -
Min. 13.5 0,15 15 - -250
Output Voltage: - o5 5 0.05 - 0 0.05
low-level VOL - 0, 10 10 0.05 - 0 0.05
Max. 0,15 15 0.05 0 0.05 V
Output Voltage: 0,5 5 4.95 4.95 5
High-level VOH ,1 1 9.95 9.95 10
Min. - o 15 15 14.95 14.95 15 -
Input low 0.5,4.5 - 5 1.5 - - 1.5
Voltage Vil 1 9 - 10 3 - - 3
Max. 1.5,13.5 - 15 4 4 V
Input High 0.5,4.5 5 3.5 3.5
Voltage VIH 1,9 - 10 7 7 - -
Min. 1.5,13.5 - 15 11 11 - -
Input Current
Max.
liN - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 JlA
DYNAMIC ELECTRICAL CHARACTERISTICS at T A=25° C; Input t" t,=20 ns, Cl =50 pF, RL =200 kC'l
TEST LIMITS
CHARACTERISTIC CONDITIONS All Pack@ges UNITS
Voo (V) MIN. TYP. MAX.
Propagation Delay Time tpHL 5 1.7 JlS
Strobe, Data to Outputs 10 - 850 - ns
15 - 575 - ns
5 1.5 Jls
tPLH 10 - 625 - ns
15 - 500 - ns
Transition Time 5 - 3.3 -
tTHl, 10 - 1.6 - Jls
tTl H 15 - 1.1 -
Minimum Strobe Pulse tw 5 - 1.5 Jls
Width 10 - 600 - ns
15 - 475 - ns
Minimum Data Pulse tWH, 5 - 1.6 - JlS
Width tWL 10 - 700 - ns
15 - 500 - ~
Minimum Terminator tw
Input/Output Pulse 5 - 10 - ns
Width
Minimum Data tsu 5 - 0 -
Setup Time 10 - 0 - ns
Data to Strobe 15 - 0 -
Input Capacitance CIN Any Input - 5 pF
434
CD40147B Types
Fe'!.tures:
IO-line to 4-line • Encodes 10-line to 4-line BCD
BCD Priority Encoder a Active low inputs and outputs
High-Voltage Types (20-Volt Rating) .100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings ,-----,.-0 ~,
rhe RCA-CD40147B CMOS encoder fea- • Meets all requirements of JEDEC Tentative Standard
C 2'
B 2'
tures priority encoding of the inputs to ensure No_ 13A, "Standard Specifications for Description of 'B' '--_-"-. ,0
that only the highest-order data line is en- Series CMOS Devices"
92CS-30552
:oded. Ten data input lines (0·91 are en- • Maximum input current of 1 /J-A at 18 V over full
package-temperature range; 100 nA at 18 V and 250 C
:oded to four·line (8.4,2,1) BCD. The highest
Jriority line is line 9. All four output lines are
range) = 1 Vat VDD =5 V
ogic 1 (VSSI when all input lines are logic O.
2 Vat VDD = 10 V
1\11 inputs and outputs are buffered, and each
2.5 V at VDD = 15 V FUNCTIONAL DIAGRAM
Jutput can drive one TTL low-power Schottky
Applications:
oad. The CD40147B is functionally similar to
•
;I)e TTL 54/74147 if pin 15 is tied low. • Keyboard encoding
The CD40147B types are supplied in 16- • 10-line to BCD encoding
lead ceramic dual-in-Iine packages (0 and F • Range selection
suffixes), 16-lead dual-in-line plastic pack- RECOMMENDED OPERATING CONDITIONS
ages (E suffix). 16-lead ceramic flat pack-
ages (K suffix), and in chip form (H suffix).
operation is always within the following range:
IFUNCTIONA~GATiNG ------1
1 B I LIMITS
.*@)---()o- 0 1 9. I CHARACTERISTIC UNITS
I Min. Max:
I 7 _-,6"---,.-I-1-.J I
I Supply Voltage Range (For T A = Full Package
I .. Temperature Range) 3 18 V
~*~22 I 5 -"'=H'P--'
I TRUTH TABLE (Negative Logic)
I*®----[>-- "3 I 3
INPUTS OUTPUTS
I
I 0 1 2 3 4 5 6 7 8 9 0 C B A
I
I 0 0 0 0 0 0 0 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0
X 1 0 0 0 q 0 0 0 0 0 0 O. 1
X X 1 0 0 0 0 0 0 0 0 0 1 0
X X X 1 0 0 0 0 0 0 0 0 1 1
1i
. X
X
X
X
X
X
X
X
1
X
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
~VOO X X X X X X 1 0 0 0 0 1 1 0
:;
5 6 X X X X X X X 1 0 0 0 1 1 1
~LJvss
"I X X X X X X X X 1 0 1 0 0 0
E-INPUTS PROTECTED BY
• B
92CM-10956 X X X X X X X X X 1 1 0 0 1
Fig. I - CD401478 logiC diagram. o High Level Low Level X Don't Care

AMBIENT TE!APERATURE (TAI-ZS·C
-'!!I -10 -5
AMIlIENT TEMPERATURE (TAI.~·C
GATE-TO-SOURCE VOLTAGE IVGSI.t~ v
-IOV
10V
~ 10
~
-15Y
5
5 10 15 5 10 15
DRAIN-lO-SOURCE VOLTAGE IVoSI-V DRAIN-lO-SOURCE VOLTAGE (\IOSI-V
Fig. 2 - Typical output low (sink) current Fig. 3 - Minimum output low (sink) current Fig. 4 - Typical output high (source) current
435
CD401478 Types
MAXIMUM RATINGS, Absolute-Maximum Values: DRAIN-lO-SOURCE VOLTAGE IVDSI-V

-I~ -10 .,
DC SUPPLY-VOLTAGE RANGE, (VDD) AMBIENT TEMPERATURE tTA)-25-C
(Voltages referenced to VSS Terminal) ........................................ ,....... -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS .............•.......•....................• -0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ..................................................... ±10 rnA ·s
POWER DISSIPATIDN PER PACKAGE (PD):
For T A = -40 to +60"C (PACKAGE TYPE E) ................................................. 500 mW
For T A = +60 to +B5"C (PACKAGE TYPE E) ..•....•.......•... Derate Linearly at 12 mW/"C to 200 mW -IOV
.K)
For TA = -55 to +100"C (PACKAGE TYPES D, F, K) .......................................... 500 mW ., .
For TA =+100 to +125"C (PACKAGE TYPES D, F, K) ...•..•.•. Derate Linearly at 12 mW/"C to 200 mW H. B ~t
+0
DEVICE DISSIPATIDN PER OUTPUT TRANSISTOR: ·-1'';
For T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) •.•...........•.••••.. 100 mW
:
PACKAGE TYPES D. F, K, H ...•.... , ............•......•.........•...•........•.... -55 to +125"C
PACKAGE TYPE E .................................................................. -40 to +85"C
STORAGE TEMPERATURE RANGE (Tstg ) ............................................. -65 to +150"C
LEAD TEMPERATURE (DURING SOLDERING): Fig. 5 - Minimum output high (source) current
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max....•.•.•..............••• +265"C characteristics.
~-
LIMITS AT INDICATED TEMPERATURES (DCI
U
CONDITIONS Values at -~5, +25, +125 Apply to D, F, K, H, Packages
N
I
TERISTIC +25
Vo VIN VDD T
(VI !VI (VI -55 ~O +85 +125 Min. Typ. Max. S
Quiescent - 0,5 5 1 1 30 30 - 0.02 1 92CS-24322

Device - 0,10 10 2 2 60 60 - 0.02 2 /J.A load capacitance.
Current, I DO - 0,15 15 4 4 120 120 - 0.02 4
Max. - 600 -
0,20 20 20 20 600 0.04 20 I ~·-·~~~~E' ~~~~~T~U"<' '.'
Output Low
(Sink)
0.4 0,5 5 0.64 0.61 0.42 0.36 0,51 1 -
0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
Current
1.5 0,15 15 4.2 4 2.8 2.4 3.4 - 11
I~
IOL Min. 6.8
Output High
(Source)
4.6
2.5
0,5
0,5
5 -0.64 -0.61 -0.42 -0.36 -0.51
5
-1
-2 -1.8 -1.3 -1.15 -1.6 -3.2
-
-
rnA
I;
Current,
IOH Min.
9.5
13.5
0,10
0,15
10
15
-1.6 -1.5 -1.1 -0.9 -1.3 -2.6
-4.2 -4 -2.8 -2.4 -3.4 -6.8 I
Output Voltage: - 0,5 5 0.05 - 0 0.05 LOAD CAPACITANCE (ell - pF 92CS-309'5
Low·Level, - 0,10 10 0.05 - 0 0.05

Fig. 7 - Propagation delay time as a function
VOL Max. - 0,15 15 0.05 - 0 0.05 of load capacitance.
V lOS AMBIENT TEMPERATURE (TAl. 25-
Output Voltage: - 0,5 5 4.95 4.95 5 -

LX
High·Level, - 0,10 10 9.95 9.95 10 - •jlO4
VOH Min. - 0,15 15 14.95 14.95 15 - ~• %I)' .(:I: ~
~ ,,7~~
........f:j~ ~
~
Input Low 0.5,4.5 - 5 1.5 - - 1.5 z ~ov
Voltage, 1,9 - 10 3 - - 3 "i lOS

RV
~
I'
VILMax. 1.5,13.5 - 15 4 - - 4
g ~.
V ~
~I02 LOAO CAPACITANCE
Input High 0.5,4.5 - 5 3.5 3.5 - - CL EI5 pF
/
Voltage, 1,9 - 10 7 7 - - CL·50pF
,n
VIHMin. 1.5,13.5 - 15 11 11 - - , '0 '0' '0' '0' '0'
INPUT FREQUENCY (f .. ) - kHr
'ZCS-SO'54
Input Curren1
liN Max. - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±0.1 /J.A Fig. 8 - Typical dynamic power dissipation
436
CD40147B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , tf =20 ns,
CL = 50 pF, RL = 200 kn Voo
LIMITS
TEST CONDITIONS ALL TYPES UNITS
CHARACTERISTIC
VDD
(V) Typ. Max.
tpLH' tpHL 10 200 400 ns
In·Phase Output
Any input to any 15 150 300
\l2eS-30S53
output 5 425 850
Out·ot·Phase Output 10 175 350 ns
15 125 250 Fig. 9 - Dynamic power dissipation
test circuit.
5 100 200
Transition Time. tTHL' tTLH 10 50 100 ns
Input Capacitance. Cl Any Input

15 40
5
80
7.5 pF
II
VOIl
V~NPU(J"
... ::~••~
INPUTS
Vss
o I"PUTOVOIlOUTPUTS
VIH
'- ~ o~ SIE:OUENTIALLV, .
v~ ~ Vss TO BOTH YDD AND VsS'
CONNECT ALL UNUSED
INPUTS TO EITHER
NOTE: VDD CftYss'
Vss ~SJN"'':,~~OMaINATION Vss
Vss 92C$.-2140'RI
Fig. 10 - Quiescent device Fig. 17 - Input voltage test circuit. Fig. 12 - Input CUrrent test circuit.
I' VOD
0
"
• 14
I'
12
1\
10
VSS A
TOP VIEW
92CS'aoH7
CD401478
TERMINAL
ASSIGNMENT

dicated. Gfld graduations are in mils ,,0-
3 inchJ.
The photographs and dim.nslons of each CMOS chip

represent I chip when it is part of the ."ater. When the
wa'f" is separated Into Individual chips, the angl. of
different chips. The actual d;mena/ons of the isolated
dimensions shown. The us.r should consider. tolerance
dimensions shown.
437
CD40160B, CD40161B, CD40162B, CD40163B Types
CMOS Synchronous Features:

• Internal look-ahead for fast counting
Programmable 4-Bit • Carry output for cascad'ing PE
10
I.
01
Counters • Synchronously programmable

Ii Clear asynchronous input
TE
CLEAR 13
02
LoiD
High-Voltage Types (20-Volt Rating) (C040160B, C040161B)
CLOCK 0'
• Clear synchronous input "
PI
CD40160B - Decade with Asynchronous (C040162B, C040163B)
Clear • Synchronous load control input •• ••
P'
o.
CD40161B - Binary with Asynchronous • Low-power TTL compatibility I. CARRY
P' OUT
Clear • Standardized, symmetrical output
CD40162B - Decade with Synchronous characteristics V OO·/6
Clear Yss -8
CD40163B - Binary with Synchronous over full package-temperature range;
9ZCS-286Z8AI
Clear 100 nA at 18 V and 250 C Functional Diagram

RCA·C040160B, C040161B, C040162B, • NOise margin (over full package-tempera-
and C040163B are 4·bit synchronous pro- ature range): 1 Vat VOD = 5 V
grammable counters. The CLEAR function 2 Vat VDD = 10 V 2.5 VatVOD= 15V Applications:
of the C040162B and C040163B is synchro- • 5-V, 10-V, and 15-V parametric ratings • Programmable binary and decade counting
nous and a low level at the crEAR input sets • Meets all requirements of JEDEC • Counter control/timers
all four outputs low on the next positive Tentative Standard No. 13A, "Standard • Frequency dividing
CLOCK edge. The CLEAR function of the Specifications for Description of 'B'Series
C040160B and C040161 B is asynchronous CMOS Devices"
and a low level at the CLEAR input sets all duration approximately equal to the positive
four outputs low regardless of the state of portion of the Ql output. This positive
the CLOCK, LOAO, or ENABLE inputs. A overflow carry pulse can be used to enable
low level at the LOAO input disables the successive cascaded stages. Logic transitions
counter and causes the output to agree with at the PE or TE inputs may occu r when the
the setup data after the next CLOCK pulse clock is either high or low.
regardless of the conditions of the ENABLE The C040160B, C040161 9, C0401629, and
inputs. C0401639 types are supplied in 16-lead
The carry look-ahead circuitry provides for hermetic dual-in-line ceramic packages (0
cascading counters for n·bit synchronous and F suffixes), 16-lead dual-in-line plastic
applications without additional gating.lnstru- packages (E suffix), 16-lead ceramic flat
mental in accomplishing this function are
suffix).
two count-enable inputs and a carry output
The C040160B through C040163B types
(COUT)' Counting is enabled when both PE
are functionally equivalent to and pin-com-
and TE inputs are high. The TE input is fed
patible with the TTL counter series 74LSl60
forward to enable COUTo This enabled out- Fig. 1- Typical output low (rink)
through 74LSI63 respectively.
put produces a positive output pulse with a current characteristics.

(Voltages referenced to VSS Termjnal) .................•.•.......•....•............... -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ..........•........•...•.....•..•.......... -0.5 to VDD +0.5 V
For TA = +60 to +85°C (PACKAGE TYPE E) .........•...•.•... Derate Linearly at 12 mWrC 10 200 mW
For TA =-5510 +loo°C (PACKAGE TYPES D, F, K) .......................................... 500 mW
For TA = +100 to +125'C (PACKAGE TYPES D, F, K) ..•.••.... Derate Linearly at 12 mW/oC to 200 mW
ForTA = FULL PACKAGE-TEMPE~ATURERANGE (All Package Types) ...................... 100 mW
PACKAGE TYPES D, F, K, H ........................................................ -55 to +125°C I
PACKAGE TYPE E .................................................................. -40 to +85'C DRAIN-TO-SOURCE VOLTAGE IVOsI-V
STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 to +150°C

LEAD TEMPERATURE (DURING SOLDERING): Fig. 2- Minimum output low (rink)
At distance 1116± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max.......................... +265°C
438
CD40160B, CD40161B,CD40162B, CD40163B Types
C040160B AND CD401628 BCD DECADE COUNTERS
* * * * *
* INPUTS PROTECTED
NETWORK
800 _ _ _
15 COUT
Vss
92CL - 29224RI
Fig. 3- Logic diagrams for CD40160B and CD401628 BCD decade counters.
CD40161B C04DI61B AND CD401638 BINARY COUNTERS

ASYNCHRONOUS CLEAR
* *5 p,
>--------+--'---- \
>o----_---'--!-==t~=t:=:~~---.l
* INPUTS PROTECTED & 1
BY COSltwilOS PROTECTION __ _
Voo
NETWORK
92CL"Z9225RI
Vss
Fig. 4- Logic diagrams for CD40161B and CD40163B binary counters.
439
RECOMMENDED OPERATING CONDITIONS at TA = 2!PC, Except as Noted DftAIN-TO-SOURCE VOLTAGE('t'os)-V
For maximum reliability, nominal operating conditions should be selected so that 1
CHARACTERISTIC liMITS UNITS

VDD
(VI MIN. MAX.
Supply Voltage Range (Full TA = Full Package-
Temperature Rangel - 3 18 V
Setup Time: tsu 5 240 -
Data to Clock 10 90 - ns
15 60 -
5 240 -
load to Clock 10 90 - ns
15 60 Fig. 5- Typical output high (source)
5 340 -
PE or TE to Clock 10 140 - ns DRAIN-lO-SOURCE VOLTAGE [VosJ-V
15 100 -
Clear to Clock
5 340 -
(CD40162B, CD40163B)
10 140 - ns
15 100
5 0 -
All Hold Times, tH 10 0 - ns
15 0 -
Clear Removal Time, t rem
5 200 -
(CD40160B, CD4016181
10 100 - ns
15 70 -
Clear Pulse Width,
5 170 -
tWl 10 70 - ns '2tS·24UIRl
(CD40160B, CD40161 BI Fig. 6- Minimum output high (source)
5 - 2
Clock I nput Frequency, fCl 10 - 5.5 MHz
15 - 8
5 170 -
15 50 -
5 - 200
Clock Rise or Fall Time, trCl or ttc l 10 - 70 j.lS
15 - 15
10
ov
m ~ ~ ~ ~
LOAD CAPACITANCE (ClJ-pF 92CS-29971

function of load capacitance
TRUTH TABLE (CLOCK to OJ.
CLOCK ctR lOAD PE TE OPERATION
J 1 0 X X PRESET
J 1 1 0 X NC
.r 1 1 X 0 NC
.r 1 1 1 1 COUNT
X 0 X X X RESET (CD40160B, CD40161BI
.f 0 X X X RESET (CD40162B, CD40163BI
\.. 1 X X X NC (CD40162B, CD40163BI

1 - HIGH LEVEL 0= LOW LEVEL X· DON'T CARE NC = NO CHANGE of load capacitanc~.
440

LIMITS AT INDICATED T.EMPERATURES (oC) I~
CHARAC- CONDITIONS Values ai-55, +25, +125 Apply 10 0, F, K, H, Packages I
TERISTIC Values at -40, +25, +85 Apply 10 E Packages T
+25 S
Vo VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min_ Typ_ Max_
- 0,5 5 5 5 150 150- 0.04 5
Quiescent
Device - 0,10 10 10 10 300 300 - 0.04 10 iJA
Current, - 0,15 15 20 20 600 600 - 0.04 20
100 Max.
- 0,20 20 100 100 3000 3000 - 0.08 100
Output low
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - 92CS-29967
Fig. 9- Typical power dissipation as a

(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - function of CLOCK frequency.
IOlMin. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -
•
VOD
Output High
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mP
(Source) 2.5 0,5 5· -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low-Level, - 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05 V
Output - 0,5 5 4.95 4.95 5 -
Voltage: - 0,10 10 9.95 9.95 10 - 9ZCS-Z9972
Hi gh- Level,
VOH Min. - 0,15 15 14.95 14.95 15 - Fig. 10- Dynamic power dissipation test
Input Low
0.5,4.5 - 5 1.5 - - 1.5 circuit.
Voltage 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 - 15 4 - - 4 V
YCO
Input High 0.5,4.5 - 5 3.5 3.5 - - o
INPUTS
Yss
Voltage, 1,9 - 10 7 7 - -
VIHMin.
1.5,13.5 - 15 11 11 - -
Input Current ±1O- 5 ±0.1 iJA
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 -
Vss
92CS-Z1401RI
Fig. 11- Quiescent-device-current test circuit.
V~.'U(J' =~'::'
TERMINAL ASSIGNMENT
'. I..UTOVCOOUTPUTS
V,M ctE'iR 16 VOD
~
CLOCK I. CARRY OUT
••
Vss TO BOTH VDO AND 'Iss' o _
CONNECT ALL UNUSED '--
VIL _
PI
P2 "13
01
02
I~S 10 EITHER
VDOClRVSS'
P'
P4 •
6
12 O.
O.
VSS NOTE: PE 7 "
10 TE
VS$ TESf ANY COMaINATIClil
OF INPUTS
vss 8
TOP VIEW
9
=
92CS-2744IRI 92CS-29459
Fig. 12- Input-current test circuit. Fig. 13- Input-voltage test circuit.
-------------------------------------------------------------------441
DYNAMIC ELECTRICAL CHARACTERISTICS at T A· 26OC;
Input"tr , tt· =
20 ns, CL 60 pF, RL • 200 kn
TEST LIMITS
CHARACTERISTIC CONDITIONS ALL TYPES· UNITS
VDD(VI Min. Typ. Max.
CLOCK OPERATION
Propagation Delay Time. tpHL,tpLH 5 200 400 -
Clock ioO 10 80 160 - ns
16 60 120 -
5 - 225 450
Clock to COUT 10
15
-- 95
70
190
140
ns
5 - 125 250
TE t? COUT 10 - 55 110 ns
15 - 40 80
Minimum Setup Time. tsu

5 - 120 240
Data to Clock 10 - 45 90 ns
15 - 30 60
5 - 120 240
Load to Clock 10 - 45 90 ns
15 - 30 60
5 - 170 340
PE toTE to Clock 10 - 70 140 ns
15 - 50 100
5 - - 0
Minimum Hold Time. tH 10
15
-
-
-- 0
0
ns
.'
5 - 100 200
Tra~siiion Time. tTHL·tTLH 10 - 50 100 ns
15 - 40 80
5 - 85 170
Mini~uin Clock Pulse Width. tw HI - 35 70 ns
15 - 25 50
" 5 2 3 -
Maximum Clock Frequency. tCL 10
i5
5.5
8
8.5
12
-- MHz
Maximum Clock Rise or Fall Time. t

5
10
200
70
-- -
- p.s
trCL. ttCL 15 15 - -
CLEAR OPERATION
P.ropagation, Delay Time, tpHL 5 - 250 500
(0040,1&08. C040161 BI 10 - 110 220 ns
Clear to'O 15 - 80 160
Minim'urn'Setup Tim~. tsu 5 - 170 340
(C0401628. C040163BI 10 - 70 140 ns
Clear to Clock ' 15 - 50 100
Minim!lrii ':I0ld Time. tH 5 - - 0
(CP40162B. C040163BI
Clear t9 ClOck
10
15
-- -
-
0
0
ns
Minim,um Clear Removal Time. t rem

5 - HIO 200
(C040160B. CP401~lBI
10 - 50 HiD ns
1!) - 35 70
0'
Minimum Clear Pulse Width. tWL
S - 85 170
(C040160B. C0401~lBI
10 - 35 70 ns
15 - 25 50
• Exc:ept as noted. ,
t " more 'than on. unit is caScaded in the parall.1 clocked application. t,CL should be made less than or equal
to the' sum of the fixed propagation delay at 50 pFand the transition time of the carry output drivingstagll
for the estimated ",!paCitiv.. Il!~d.
442
mAR(CD40160BI~r.A:::S::YN::;C:;;:HR;::0::;NO;;;U;;;S----------------
-- ,
CLEAR(CD40=1~r;S;VY;:;;NC,"H;;;:Ron.N;n0;;;us;------------------
OATA
/1
LOAD
p,-.J
P2--l
I U
:
l
'NPUTS P 3 - . J r - - ; I - - " l_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
1
p.-----~I~--------------------
CLOCKICD40160BI---M
CLDCK(CD40162B I
ENABLES{PE r-l:---------~------,L__
OUTPUTS {::~~~~~------~
CARRY OUT
-~f--------+I-------
Q3- - -
I I 1
Q.----~----I--I------
II
I 0 17 IB
I n
9
!
1
0!---:----::---:'131t--------·1
•
I I I"I-O-----::c=OU"T ---j.I·O-------iN-H:::'B:::'T~---t
.. ..
CLEAR PRESET
92CL·Z92Z8RI
Fig. 14- Timing diagram for CD40160B, CD40162B.
ct'EAR IC040J6IBI--urA"S"'YNmC"'H"'RO""N;noU"'S..--------------..".--
---
CLEAR fCD40163B ' - U'r:;v;:;;~~~--------------
SYNCHRONOUS
LoA5 ----;.-'-,
IU
I
I
I
~I
-r-~~
,
I
I r--1 I
CARRY OUT ----+-:;-'1'1;o'2,...-j1"'3;-;:;"'--;!15 0!--..,..---,2rtl-'-----------.,
I ~I·~--~C~O~UN~T~-~....Ir.<-----~'N~H~'B::;'T~-~
CLEAR PRESET
92CL~29229RI
Fig, 15- Timing diagram for CD40161B, CD40163B.
443
10 20 '" 40 50 60 70 80 00 100 109
9ZCM-i!9226
Fig. 16- Detail of flip·flops of CD40160B and CD40T6T B (asynchronous clear).
~
TN 92CM-299SU
Vc~
Dimensions and pad lavour for CD40160BH. Dimensions and pad layout
for CD40161BH.CD40162BH. and CD40163BH are identical.
The photographs and dimensions of each CMOS chIp
represent 8 Chip when it ;s part of the wafer. When the
chip, therefore. may differ slightly f,om the nomina'
dimensions shown. The USBr should considers tolerance
dimensions shown.
Fig. 17- Detail of flip·flops for CD40T62B and CD40T63B (synchronous clear).
~------~~------------------~-------------------~----------~
CLOCK----~-1-----------------4--~----------------~4_----------~
92CM-29969
Fig. 18 - Cascaded counter packages in the para/lel-clocked mode.

~------~------------------~--------------------t-----------~
VDD
CLOCK
~-- ____ ~ __________________-4____________________+-__________ ~
92CM-29970
Fig. 19 - Cascaded counter packages in the ripple-clocked mode.
444
CD40174B Types
CMOS Hex 'D'-Type Features:

" -'----f--l-~
• 5-V, 10-V, and 15-V parametric rating
Flip-Flop • Standardized symmetrical output
characteristics
The RCA-CD40174B consists of six identical D Maximum input current of 1 IlA at 18 V
over full package-temperature range'
'D'-type flip-flops having independent DATA
100nAat 18Vand25°C '
inputs_ The CLOCK and CLEAR inputs are
common to all six units_ Data is transferred • Noise margin (over full package-temperature
range): 1 Vat VDD '" 5 V 0.5 13
to the Q outputs on the positive-going
transition of the clock pulse_ All six flip-flops 2 V at VDD = 10 V
are simultaneously reset by a low level on 2.5 Vat VDD = 15 V 06 14
the CLEAR input_ • Meets all requirements of JEDEC Tentative CLOCIC-'-.r-----L_----'

CLEAR-L......_ _ _....J
The CD40174S types are supplied in 16- Standard No. 13A, "Standard Specifications \Iss' 8
lead hermetic dual-in-line ceramic packages for Description of'S' Series CMOS Devices" "00'16
(D and F suffixes), 16-lead dual-in-line FUNCTIONAL DIAGRAM

plastic packages (E suffix), 16-lead ceramic
suffix)_ Applications:
• Shift Registers
• Buffer/Storage Registers
(Voltages referenced to VSS Terminal) __ __ __ __ ____ ___ __ __ ___ ___ __ __ __ __ __ __ __ __ __ ___ __ -0_5 to +20 V • Pattern Generators
INPUT VOLTAGE RANGE, ALL INPUTS ___________________________________________ -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ___ . _____ . _. _.... ___ . ___ . ____ . _. _______ . _. _____ . _, . _, ±10 mA TRUTH TABLE FOR 1 OF 6 FLIP-FLOPS
For TA = -40 to +60·C (PACKAGE TYPE E) ___ . __ . _. _. _. ___ . _. ______ .. ____ . _....... _. ___ . ___ 500 mW INPUTS OUTPUT
For TA = +60 to +B5·C (PACKAGE TYPE E) ___ . _.. _. _. _____ . _. Derate Linearly at 12 mW/·C to 200 mW
For TA = -55 to +100·C (PACKAGE TYPES D, F, K) _. _. _____ . _. _____________ .. _. _... _.. _. _... 500 mW
CLOCK DATA CLEAR a
For TA =+100 to +125·C (PACKAGE TYPES D, F, K) ........ _. Derate Linearly at 12 mwrc to 200 mW 0 1 0
-----
---
1 1 1
For TA =FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW
PACKAGE TYPES D, F, K, H ..................................................... __ . -55 to +125·C
PACKAGE TYPE E . ____ . _______ .. ____ . __ ...... ____ . __ . __ . __ . __ .. __ . __ . ____________ .. -40 to +B5·C
-----
X
X
X
1
0
NC
0
STORAGE TEMPERATURE RANGE (Tstg) __ . ____ . ____ . __ . ____ . __ ... __ . __ . __________ . __ -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING): 1 = High Level x = Don't Care
At distance 1/16 ± 1132 inch (1.59 ± 0.79 mm) from case for 10 s max. __ . __ .... __ ............. , +265·C 0= Low Level NC = No Change
*ALL INPUTS (TERMS 1,3,4,6,9,

cc
11,13,14) PROTECTEO BY COSIMOS
PROTECTION NETWORK
CLI(*~CL
Fig_ 1 - Logic diagram (1 of 6 flip-f1opsl.

445
CD401748 Types
RECOMMENDED OPERATING CONDITIONS at T A = 25"C, Except as Noted.

VDD
(V) Min. Max.
Supply·Voltage Range (For T A = Full Package·
Temperature'Range) - 3 18 V
5 40 -
Data Setup Time, tsu 1(} 20 - ns
15 10 -
5 80 - DRAIN-TO-SOURCE VOLTAGE (Vosl-V
Data Hold Time, tH 10 40 - ns Fig. 3- Typical output low (sink) current

15 30 - characteristics.
5 - 3.5
Clock Input Frequency, fCl 10 de 6 MHz
15 8
5 - 15
Clock Input Rise or Fall Time, trCl;tfCl 10 - 15 J..Ls
15 - 15
5 130 -
Clock Input Pulse Width;tWl. tWH 10 60 - ns
15 40 -
Clear Pulse Width. tWl

5
10
100
50
-
- ns
II
15 40 - DRAIN-TO-SOURCE VOLTAGE (Yosl-Y
5 0 - Fig. 4- Minimum output low (sink) current

Clear Removal Ti~e. tREM 10 0 - ns characteristics.
15 0 -
ORAIN-TO-SDURCE VOLTAGE: (Yos)-V
-15 -10 -5
10 20 30 40 50 60 70 AMBIENT TEMPERATURE (TA'*25*C
I I I I I I I GATE-TO-SOURCE VOLTAGE (VGS'o-5V
-IOV
-15V
9ZCS-24320R)
Fig. 5- Typical output high (source) current
characteristics.
ORAIN-TO-SOURCE VOLTAGE (VDS)-V

-15 -10 -5
AMBIENT TEMPERATURE (TA).25·C
92CS-29B35
-IOV
The photographs and dimensions of each CMOS chip -15 V

Dimensions and pad layout for CD40174BH. represent a Chip when it is part of the wafer. When the
Dimensions in parentheses are in millimeters and are chip, tharefore, may differ slightly from the nominal
dimens;onsshown. The USBr shouldconsidera tolerance
derived from the basic inch dimensions as indicated. 01 -3 mils to +16 mils applicable to the nominal Fig. 6-- Minimum output high (source) current
Grid graduations are in mils (10- 3 inch). dimensions shown. characteristics.
446
CD401748 Types
STATIC ELECTRICAL CHARACTERISTICS 10 6 AMBIENT TEMPERATURE ITA)-25-C

U
CONDITIONS Values at -55, +~5, +125 Apply to D, F, K, H. Packages N
I
TERISTIC +25 T
Vo VIN VDD
IV) (V) IV) -55 -40 +85 +125 Min. Typ. Max. S
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0,10 10 2 2 60 60 - 0.02 2 J.lA
Current, I DD - 0,15 15 4 4 120 120 - 0.02 4
Max. - 0,20 20 20 20 600 600 - 0.04 20 I 2 4 68 10 2 4 68102 2 4 88103 2 4 68104
Output Low CL.OCK INPUT FREQUENCY (feLl-kHz
(Sink)
0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - Fig. 7- Typical dynamic power dissipation as a
Current
0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - function of CLOCK frequency.
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 -

4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
II
Output High
(Source) 2.5 0,5 5· -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current, 9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6
IOH Min. 13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8
Output Voltage: - 0,5 5 0.05 - 0 0.05

Low·Level, - 0,10 10 0.05 - 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level, - 0,10 10 9.95 9.95 10 - LOAD CAPAC!TANCE (CLJ-IJF
VOH Min. - 0,15 15 14.95 14.95 15 -

Fig. 8- Typical propagation delay time (CLOCK
to OUTPUT) as a function of load
Input Low 0.5,4.5 - 5 1.5 - - 1.5 capacitance.
Voltage, 1,9 - 10 3 - - 3
VIL Max. 1.5,13.5 - 15 4 - - 4
V Voo
Input High 0.5,4.5 - 5 3.5 3.5 - -

Voltage, 1,9 - 10 7 7 - -
VIHMin. 1.5,13.5 - 15 11 11 - -
Input Current
liN Max. - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 J.lA
-=- Vss
NOTE: PUL.SE GEN. I • fiN
PULSE GEN.2'~
Fig. 9- Dynamic power dissipation test circuit.
Voo
Voo
INPUTS
o
Vss
*(1.HI OR (HLI OPTIONAL

Voo 1,.+------
CL"E"Aii- -50% 92CS-20069R4
o I
Fig. 10- Definition of setup, hold, propagation delav,
and removal times.
Vss
Fig. 1 t - Quiescent device current test circuit.
447
CD401748 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C;

Input t f • tf = 20 ns. CL = 50 pF. RL'" 200 kn
TEST
CHARACTERISTIC CONDITIONS LIMITS UNITS
Propagation Delay Time

5 - 150 300
Clock to Output,
10 - 70 140 ns
tpHL, tpLH
15 - 50 100
5 - 100 200
Clear to Output, tpHL 10 - 50 100 ns
15 - 40 80
5 - 100 200
Transition Time, tTHl, tTlH 10 - 50 100 ns
15 - 40 80
Minimum Pulse Width,

5 - 65 130
Clock,
10 - 30 60 ns
tWL' tWH 15 - 20 40
5 - 50 100
Clear, tWL 10 - 25 50 ns
15 - 20 40
5 - 20 40
Minimum Data Setup Time, tsu 10 - 10 20 ns
15 - 0 10
5 - 40 80
15 - 15 30
5 3.5 7 -
Maximum Clock Frequency • fCL 10 6 12 - MHz
15 8 16 -
5 15 - -
Maximum Clock Rise or Fall 10 15 - - J.l.S
Time, trCl, tfCl 15 15 - -
I nput Capacitance, CI N
Clear - - 25 40 pF
All other - - 5 7.5
Minimum Clear Removal

5 - -40 0
Time, tREM
10 - -15 0 ns
15 - -10 0
INPUTQVOO
OUTPUTS
Voo INPu(
VooJ s NOTE.
V,H
TERMINAL ASSIGNMENT
~
Vss
~:~~~:i,!~~~S
TO BOTH Voo ANDYss'
'-
VIOL
~
:x CLEAR
QI
I·
2
I.
IS
Voo
06
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS' NOTE:
DI
D2
02
.
I.
12
D.
DO
as
Vss Vss ~srN~~~~OMBINATION D. II D.
0> 10 a.
Vss
TOP VIEW
• ClOCK
Fig. 12 - Input current test circuit. Fig. 13 - Input voltage test circuit.
448
CD401758 Types
CMOS Quad '0'-Type Flip-Flop

01 4 QI
Features: • Meets all requirements of JEDEC Ql
•100% tested for quiescent current Tentative Standard No. 13B, 02 5 7
Q2
6
at 20 V "Standard Specifications for Q2
• Maximum input current of 1 /lA at Description of 'B' Series CMOS 03 12 10
Q3
18 V over full package- Devices" II Q3
temperature range; 100 nA at 18 V • Output compatible with two HTL 15
04 Q4
and 25°C loads, two low power TTL loads, 14
(f.f
• Noise margin (full package- or one low power Schottky TTL
load
temperature range) = CLOCK 9
VSS'8
1 Vat VDD = 5 V • Functional equivalent to TTL 74175 CLEAR I
• Standardized symmetrical output VOO'I6
2 Vat VDD = 10 V 92CS-3450S
2.5 Vat VDD = 15 V characteristics
Applications:
I
• 5-V, 10-V, and 15-V parametric
ratings • Shift registers CD40175B
• Buffer/storage registers FUNCTION DIAGRAM
• Pattern generators
The RCA CD40175B consists of four identical D-type flip-

flops. Each flip-flop has an independent DATA D input and
complementary Q andQ outputs. The CLOCK and CLEAR
inputs are common to all flip-flops. Data are transferred to
the Q outputs on the positive-going transition of the clock CLEAR 16 VOD
pulse. All four flip-flops are simultaneously reset by a low QI 15 Q4
level on the CLEAR input. Ql 14 Q4
These devices can function as shift register elements or as 01 4 13 04
T-type flip-flops for toggle and counter applications. 02 12 03

Q2 6 II Q3
The CD40175B is supplied in hermetic dual-in-line ceramic
Q2 10 Q3
packages (D and F suffixes), 16-lead dual-in-line plastic
packages (E suffix), 16-lead ceramic flat packages (K Vss 8 9 CLOCK
suffix), and in chip form (H suffix).
Voo =PIN 16
92C5- 34507
Vss 'PIN 8
TERMINAL ASSIGNMENT

(Voltages referenced to VSS Terminal) ................•...•........•........................................... -0.5 to VDD +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ...........•......................................•..............•....... -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............................................................•...................... ±10 rnA
ForTA = -40 to +60°C (PACKAGE TYPE E) .......•..............................•.••..•..•........•......•.......•...... 500 mW
ForTA = +60 to +65°C (PACKAGE TYPE E) .......•............................•........... Derate Linearly at 12 mW/oC to 200 mW
For T A = -55 to +100° C (PACKAGE TYPES 0, F, K) .•.............................•••................•......••..•...•...... 500 mW
ForTA = +100 to +125°C (PACKAGE TYPES 0, F, K) ....................•...•........•...... Derate Linearly at 12 mW/oC to 200 mW
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ..•...........•............................••.•...• 100 mW
OPERATING-TEMPERATURE RANGE (TA): .
PACKAGE TYPES 0, F, K, H ......... , .........•.................................................................. -55 to +125°C
PACKAGE TYPE E .............................••...............................•. , .....•. ,....................... -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) ......•.................................•................................•. -65 to +150°C
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max .....................••..•...•••..•••................•.. +265°C
449
CD40175B Types
RECOMMENDED OPERATING CONDITIONS al TA = 25° C, Except as Noted.

For maximum reliability, nominal operating conditions should be selected so that operation Is always within the
follQwlng ranges:
LIMITS
CHARACTERI.STlC VDD UNITS
(V) MIN. MAX.
Supply-Voltage Range (For TA = Full Package-Temperature Range) - 3 18 V

5 120 -
Data Setup Time tsu 10 50 - ns

15 40 -
5 80 -
Data Hold Time tH 10 40 - ns
15 30 -
5 - 2
Clock Input Frequency fCl 10 dc 5 MHz
15 - 6.5
5 - 15
Clock Input Rise or Fall Time trCl, tfCl 10 - 15 f.JS
15 - 15
5 250 -
Clock Input Pulse Width tWl, tWH 10 100 - ns
15 75 -
5 200 -
Clear Pulse Width tWl 10 80 - ns
15 60 -
5 250 -
Cie8rRemoval Time tREM 10 100 - ns
15 80 -
~_O:D
L4ss• I n puts Protected
by CMOS Protection CL
Network * CLK~CL 92CM-34S09
Fig. 1 - Logic diagram (1 of 4 flip-flops).
450
STATIC ELECTRICAL CHARACTERISTICS CD40175B Types

CHARACTERISTIC CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H Packages UNITS
+25
VO VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Quiescent - 0,5 5 1 1 30 30 - 0.02 1
Device - 0, 10 10 2 2 60 60 - 0.02 2
Current - 0, 15 15 4 4 120 120 - 0.02 4 J.lA
Max. 100 - 0,20 20 20 20 600 600 - 0.04 20
Output Low 0.4 0,5 5 0.64 0.61 OA2 0.36 0.51 1 -
(Si nk) Current 0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
Min. IOL 1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 -
Output High
(Source)
Current
4.6
2.5
9.5
0,5
0,5
0, 10
5
5
10
-0.64
-1.6
-2
-0.61
-1.8
-1.5
-0.42
-1.3
-1.1
-0.36
-1.15
-0.9
-0.51
-1.6
-1.3
-1
-3.2
-2.6
-
-
-
rnA
II
Min. IOH 13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low-Level - 0, 10 10 0.05 - 0 0.05
Max. VOL - 0, 15 15 0.05 - 0 0.05
Output Voltage: - 0,5 5 4.95 4.95 5 - V
High-Level - 0, 10 10 9.95 9.95 10 -
Min. VOH - 0, 15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage 1,9 - 10 3 - - 3
Max. VIL 1.5,13.5 - 15 4 - - 4
Input High 0.5,4.5 - 5 3.5 3.5 - - V
Voltage 1,9 - 10 7 7 - -
Min. VIH 1.5,13.5 - 15 11 11 - -
Input Current Max. liN - 0, 18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 J.lA
TRUTH TABLE FOR 1 OF 4 FLIP-FLOPS

(Positive Logic)
INPUTS OUTPUTS
voo
CLOCK DATA CLEAR Q Q
'--t----J-----'O
~ 0 1 0 1
~ 1 1 1 0
----- 1!"
OUTPUT
X 1 Q
X X 0 0 1
1=High Level X=Don't Care O=Low Level

*ILHI OR IHLl OPTIONAL
voo
92CS-20069R3
o
Fig. 2 - Definition of setup, hold, propagation
delay, and removal times.
451
CD40175B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25°C; Input tr, II =20 nl, CL =50 pF, RL =200 kCl
LIMITS
TEST
VDD (V) MIN. TYP. MAX.
5 - 100 200
Transition Time tTHl, tTLH 10 - 50 100
15 - 40 80
Propagation Delay Time 5 - 220 400
Clock to Q Output tPHl, tPlH 10 - 90 160
15 - 70 120
Propagation Delay Time 5 - 325 500 I
CLEAR to Q Output tPHl 10 - 130 200 ns
15 - 100 150
Minimum Pulse Width 5 - 110 250
Clock tWH 10 - 45 100
15 - 35 75
5 - 100 200
Clear tWl 10 - 40 80
15 - 30 60
5 2 4.5 -
Maximum Clock Frequency fel 10 5 11 - MHz
15 6.5 14 -
5 15 - -
Maximum Clock Rise or Fall Time trel, tIel 10 15 - - ps
15 15 - -
5 - 60 120
Minimum Data Setup Time tsu 10 - 25 50
15 - 20 40
5 - 40 80
Minimum Data Hold Time tH 10 - 20 40 ns
15 - 15 30
5 - 125 250
--
Minimum Clear Removal Time :j: tREM 10 - 50 100
15 - 40 80
Input Capacitance CIN - - 5 7.5 pF
:I: CLEAR signal must be high prior to positive-going transition of CLOCK pulse.
400 AMBIENT TEMPERATURE (TA 1_25°C
!3S0
I
}
'::.
}2S
...
",.... 200
~ ISO
z
~ 100
~
~50
10 20 30 40 50 60 70 80 90 100
LOAO CAPACITANCE (CL)-pF LOAD CAPACITANCE (CL)- pF
92CS-35980 92CS-M322
Fig. 3 - Typical propagation delay time (CLOCK Fig. 4 - Typical transition time as a function of
to OUTPUT) as a function of load load capacitance.
capacitance.
452
CD40175B Types
AMBIENT TEMPERATURE (TA)·25-C
.E .
AMBIENT TEMPERATURE ITAI-25-C
-...
I
~30
E
I
~1!5
0-
z 0- GATE-TO-SOURCE VOLTAGE (VGS)-I!5V
::!"" Wl2 ,5
~
'i 20
z
a 10
~
10V z 10V
; 15 ~ 7.5
g
E 10
"g
0-
•
~
6 • 'V "-
~ 2.~
o 'V
o 5 10 15 5 to 15
DRAIN-lO-SOURCE VOLTAGE (Vosl-V DRAIN-lO-SOURCE VOLTAGE lVosl-V
Fig. 5 - Typical output low (sink) current Fig. 6 - Minimum output low (sink) current
DRAIN-lO-SOURCE VOLTAGE (Vosl-V DRAIN-lO-SOURCE VOLTAGE IVos)-V

-15
AMBIENT TEMPERATURE (TA)-2S-C
-10 -5
•
-IOV
-15 V
Fig. 7 - Typical output high (source) current Fig. 8 - Minimum output high (source) current
10' G AMBIENT TEMPERATURE ITA1~25DC
"I
~ 4
g 104.
2
~ ~fu ., 1/
6
4
., ,0
2
,,~~~I.;. /;p:..), 15
'~" •r-r-
~
ri
10'
·
4
2
r- .,cr.
';:Jl~~
"/'
/
/
~
1
\---4----14
5
14
13
12
21 / I II
is 102a
ffi
"
~
10
·
4
2
7- V- - - - CL=15pF
I III
CL~50pF
10
4 6 8 10 2 4 S 8102 2 4 6 8'03 2 4 •• Vss

CLOCK INPUT FREQUENCY (fCL)- kH:
NOTE' PULSE GEN. I ~ fiN
fiN
PULSE GEN.2~2 92CS -35981

function of CLOCK frequency. Fig. 10- Dynamic power dissipation test circuit.
453
CD40175B Types
Voo
INPUTQVDD
OUTPUTS
o
Vss
INPUTS
vC -.!@
v~ J;
NOTE:
OF INPUTS
92CS-2144IRI
92CS-27401RI
Fig. 11 - Quiescent device current test circuit. Fig. 12 - Noise immunity test circuit.
Voo 1NPUOS
Voo NOTE'
~ MEASURE INPUTS
o ~ SEQUENTIALLY,
Vss TO BOTH Voo AND Vss'
CONNECT ALL UNUSED
INPUTS TO EITHER
VDO ORVSS'
Vss
Fig. 13 - Input leakage current test circuit.
Dimansions in parentheses are in millimeters

and are derived from the basic inch dimensions
as indicated. Grid graduations ara in mils (10-3
inch).

represent a chip when it is part of the wafer. Wilen the wafer
is separated into individual chips, the angle of cleavage may
vary' with respect to the chip face for different chips. The
actual dimensions of the isolated chip, therefore, may differ
should consider a tolerance -3 mils to +16 mils applicable
92CS-350B3
454
CD40181 B Types
Features:
CMOS 4-Bit • Fuillook·ahead carry for speed operations on long words
Arithmetic Logic Unit •
•
Generates 16 logic functions of two Boolean variables
Generates 16 arithmetic functions of two 4·bit binary words
• A = B comparator output available
High-Voltage Types !20-Volt Rating)
• Ripple·carry input and output available
• Typical addition time 200 ns @ VDD = 10 V
The RCA·CD40181B is a low·power four·bit • Standardized, symmetrical output characteristics
parallel arithmetic logic unit (ALU) capable • 100% tested for quiescent current at 20 V
of providing 16 binary arithmetic operations • Maximum input current of lilA at 18 V
on two four·bit words and 16 logical func· over full package temperature range;
tions of two Boolean variables. The mode 100 nA at 18 V and 250 C
control input M selects logical (M = High) or • Noise margin (full package temperature range)
arithmetic (M = Low) operation. The four = 1 Vat VDD = 5 V (Activo·low data)
select inputs (SO, 51, 52, and 53) select the =2VatVDD=10V FUNCTIONAL DIAGRAM
desired logical or arithmetic functions, =2.5VatVDD=15V
which include AND, OR, NAND, NOR, and • 5·V, 10·V, and 15·V parametric ratings
•
exclusive-OR and-NOR in the logic mode, • Meets all requirements of JEDEC Tentative
and addition, subtraction, decrement, left· Standard No. 13A, "Standard Specifications rUNCTlONSELECT
INPUTS
shift and straight transfer in the arithmetic for Description of 'B' Series CMOS Devices" ~
mode, according to the truth table. The
CD40181 B operation may be interpreted
with either active·low or active·h igh data at
Applications:
• Parallel arithmetic units
WORD
A
{" ,
AI
A2
23
21
FO}
FI
F2
OUTPUT
FUNCTION
"
{
A319
the A and B word inputs and the function • Process controllers
outputs F, by using the appropriate truth • Low·power minicomputers " , 14 A-a COMPARE
0",
table.
WORD
8 " "
822Q 16Cft+4 'it:;:
8318 CO,
The CD40181B contains logic for full look·
ahead carry operation for fast carry gener· CARRY IN Cn 7 " G} LOOI<
MODE M 8 l!i <P ~~~~
ation using the carry·generate and carry· CONTROL OUTPUTS
propagate outputs G and is for the four bits

of the CD40181B. Use of the CD40182B IActive-high data)
look·ahead carry generator in conjunction FUNCTIONAL DIAGRAM
with multiple CD40181B'5 permits high·
speed arithmetic operations on long words. MAXIMUM RATINGS, Absolute-Maximum Values:
A ripple carry output Cn+4 IS available for DC SUPPLY-VOLTAGE RANGE. (VDD)
use in systems where speed is not of primary (Voltages referenced to VSS Terminal) ................................................ -O.S to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS ........................................... -o.S to VDD +O.S V
importance.
DC INPUT CURRENT. ANY ONE INPUT ..................................................... ±10 mA
Also included in the CD40181B is a com·
parator output A = B, which assumes a high For TA; -40 to +60·C (PACKAGE TYPE E) ................................................. SOO mW
level whenever the two four·bit input words For TA; +60 to +8S·C (PACKAGE TYPE E) .••................ Derate Linearly at 12 mW/·C to 200 mW
A and B are equal and the device is in the ForTA ;-55to +100·C (PACKAGE TYPES D. F. K) .................................. ········ SOO mW
subtract mode. In addition, relative magni· For TA; +100 to +12S·C (PACKAGE TYPES D. F. K) .......... Derate Linearly at 12 mWI"C to 200 mW
tude information may be derived from the DEVICE DISSIPATION PER OUTPUT TRANSISTOR:
carry·in input Cn and ripple carry-out out· For TA ; FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................... 100 mW
put Cn+4 by placing the unit in the subtract OPERATING-TEMPERATURE RANGE (TA):
mode and externally decoding using the PACKAGE TYPES D. F. K. H ...•................•.................•...•........•.... -SS to +12S·C
information in Table III. PACKAGE TYPE E .................................................................. -40 to +85·C
The CD40181 B types are supplied in 24- STORAGE TEMPERATURE RANGE (Tstg) ............................................. -65 t6 +IS0·C
lead hermetic ceramic dual-in-line pack- LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16± 11321rich (1.59 ± 0.79 mm) from case for 10 s max..•••........•.•••••...... +26S·C
ages (0 and F suffixes), 24-lead dual-in-line
plastic packages (E suffix). 24-lead ceramic
flat packages (K suffix). and in chip form (H
suffix).
The CD40181 is similar to industry types
MC14581 and 74181.

CHARACTERISTic LIMITS UNITS
Min. Max.
DRAIN-lO-SOURCE VOLTAGE IVDSl-V DRAIN-lO-SOURCE YOllAGE (Yosl-V
(For TA=Full Package· 3 18 V
Temperature Range) Fig. 1 - Typical output low (sink) Fig_ 2 - Minimum output low fsin:;S<2.3I9R.
current characteristics. current cha~acteristics.
455
CD40181 B Types
800 A•• ,ENT TENP. . ATURE ITA
I}
If
l.OAD CAPACITANCE ICLI-pF
Fig. 6 - Tvpical propagation delav time as a

function of load capacitance (for A
or B to F. logic m~deJ.
Fig. 7 - Tvpical transition time as a function

: 8<>--_ _ _--1 -ALL INPUTS PROTECTED of load capacitance.
~••7 _ - - -.... ::>o----------.J :ITc:&.1MOS PROTECTION
Fig. 3- CD40181B logic diagram lactlve%wdata).
DRAIN-lO-SOURCE VOLTAGE IVosI-V DRAIN-TO-SOURCE VOLTAGE tVosI-V

_I"
I~~'''.N.T.
, "OLTAGE
2 .... 2 .. 6. 2 .. 611 2".' 2 of • •
10 102 103 104 lOS
INPUT FREQUENCY (fiN 1- kH: _ _
2CI 2
Fig. 8 - Typical dynamic dissipation as a function

of input frequency (see Fig. 11 - dynamic
power dissipation test circuit).
INPUTS ,-.1--,
nCS-2'320Rl
Fig. 4 - Typical output high Isource) Fig. 5 - Minimum output high
Vss
Fig. 9 - Ou;escenr·dev;ce-current test circuit.
456
CD40181 B Types
CONDITIONS Values ai-55, +25, +125 Apply 10 D, F, K, H, Packages
CHARACTER· V.lue. It -40, +25, +85 Apply to E Pocka..
ISTIC UNITS
Vo VIN VDD +25
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Mox.
Quiescent Device - D,S 5 5 5 150 150 - 0.04 5
Current,
100 Max.
- 0,10 10 10 10 300 300 - 0.04 10
IJA
- 0,15 15 20 20 600 600 - 0.04 20
HCS-2M4IRI
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
10L Min.
1.5 0,15 15 4.2 4 2.8 2.4' 34 6.8 -
Output High 4.6 D,S 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
(Source) 2.5 D,S 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current,
IOH Min.
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - c·
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage:
Low·Level,
VOL Max.
-
-
-
D,S
0,10
0,15
5
10
15
0.05
0.05
0.05
-
-
-
0
0
0
0.05
0.05
0.05
II
V
H igh·Level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
TEST CONDITIONS:
Voltage,
VIL Ma •.
1,9 - 10 3 - - 3 AD,AI,At. A3. SO, 53, M,en· Voo
BO,BI.B2.B3- t 'N
1.5,13.5 - 15 4 - - 4 51,52- VSS
V
Input High 0.5,4.5 - 5 3.5 3.5 - - (ALL OUTPUTS SWITCHING EXCEPT G 1
Voltage, 1,9 - 10 7 7 -
VIH Min. 1.5,13.5 - 15 11 11 - - Fig. 11 - Dvnamic power dissipation test circuit.
Input Current
lIN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - tl0- 5 to.l IJA
Veo rNPUOS
Vco NOTE
?-@+ ::C::i::,~~~~S
Vss TO BOTH Voo AND Vss·
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =250 C; Input t r , tf =20 ns, CONNECT ALL UNUSED
INPUTS TO EITHER
CL =50 pF, RL =200 kn Yoo CRYss·
Vss
LIMITS UNITS
CHARACTERISTIC VDD
(V) Typ, Max, Fig. 12 - Input current test circuit.
Propagation Delay Time: tpHL' tpLH 5 400 800

A or B to F (logic model, 10 160 320 ns
A or B to G or P, 15 120 240
5 500 1000
A or B to F, Cn +4, or A = B, 10 200 400 ns iili I 24 VDD
15 140 280 Ai) 2 23 Ai
53 22 iii
5 320 640 52 4 21 Ai
Cnto F 10· 135 270 ns 51 5 20 B2
15 100 200 50 6 19 AS
Cn 18 53
5 200 400 M 17 Ii
Cn to Cn +4 10 100 200 ns Fa 16 Cn +4
Fi" 10 15 P
15 70 140 F2 14 A-a
5 100 200 V55 "
12 13 F3
Transition Time: tTHL, tTLH 10 50 100 ns 92C5-21708
Top View
15 40 80
Terminal Assignment
Input Capacitance, CIN (Any Input) - 5 7.5 pF (Active-low Data)
457
CD40181 B Types
TABLE I
TRUTH TABLE
I NPUTli/oUTPUT ACTIVE LOW
FUNCTION LOGIC ARITHMETIC* FUNCTION
SELE:CT FUNCTION M=L
S3 S2 S1 SO M=H c" = L c" = H
0 0 0 oA A minus 1 A
0 0 0 1 AS ABmlnus 1 AB
0 0 1 0 A+B ABmlnus 1 .AB
0 0 1 1 lOgic 1 minus 1 Zero
0 1 0 0 ~ A plus (A + Bi A plus (A +Bi phis 1
0 1 0 1 B AB plus (A + Bi AB plus (A + 11) plus 1
0 1 1 0 Act)! A minus B minus 1 A minus B
0 1 1 1 A+B A+S (A + B) plus 1
1 0 0 0 AB A plus (A + B) A plus (A + B) plus 1
1 0 0 1 A<t)B A plus B A plus B plus 1
1 0 1 0 B AS plus (A + B) AS plus (A + B) plus 1
1 0 1 1 A + B A +B A + B plus 1
1
1
1
1
1
1
0
0
1
0
1
0 AB
;ot cO A plus A
Aj!pluS A
ABplus A
A plus A plus 1
A.!!.plus A piUs 1
AB plus A plus 1
1 1 1 1 A A A plus 1
INPUTS/OUTPUTS ACTIVE HIGH

FUNCTION LOGIC ARITHMETIC· FUNCTION Dimensions and pad layout for CD40181BH.
SELECT FUNCTION M=L
S3 S2 S1 SO M=H c" = H Cn - L
0 0 0 0 A A A plus 1
0 0 0 1 A+B A+B (A + ~ plus 1
0 0 1 0 AB A+B (A + B) plus 1 Dimensions in parentheses are in millimeters and
0 0 1 1 lOgic 0 minus 1 Zero are derived (rom the basic inch dimensions as in-
dicated. Grid graduations are in mils (10- 3 inchJ.
0 1 0 0 AB A pius A"B'" A plus AS plus 1
0 1 0 1 B (A + B) plus Ali (A + B) plus AS plus 1
0 1 1 0 Act)B A minus B minus 1 A minus B The photographs and dimensions of .ach CMOS chip
0 1 1 1 AS AS minus 1 AS represent,. chip when It ;s part 01 the wafer. When the
wafer is separated into individual chi~, the angle of
1 0 0 0 A+B A plus AB A plus AB plus 1 cl.avage may vary with respect to the chip 'ace for
1 0 0 1 AEf)B A plus B A plus B plus 1 dille rent chips. The actual dimensions of the ;sola'ed
chip, thereforB, may diffe, slightly from the nominal
1 0 1 0 B (A + S) plus AB (A + "9) plus AB plus 1 dimensions shown. The us., should consider I tolerance
1 0 1 1 AB of -3 mils to +16 mils applicable to the nomlnl'
ABmlnus 1 AB dimensions shown.
1 1 0 0 lOglqJ A plus A A plus A plus 1
1 1 0 1 A+B (1'\ + B) plus A (A + !!) plus A plus 1
1 1 1 0 A+B (A + Ii).plus A (A + B) plus A plus 1
1 1 1 1 A A minus 1 A
• Expressed as two's complement 1 = HIGH LEVEL 0= LOW LEVEL
458
CD40181 B Types
TABLE II
AC TEST SETUP REFERENCE (ACTIVE·lOW DATA)
TEST ACPATHS DC DATA INPUTS
DELAY TIMES MODE'"
INPUTS OUTPUTS TOVSS TOVD D
SUMIN to SUMOUT 60 Any F Bl, 62, B3, All A's ADD

M,C n
SUMIN to P AO P Al,A2,A3, All ih ADD

M, Cn
SUMIN to G 60 G All ih B1,B2,B3 ADD

M,Cn
•
SUMIN to Cn+4 BO Cn+4 AliA's, 61,62,63 ADD r
M,Cn
Cn to SUMOUT Cn Any F All A's, All U's ADD

M
Cn to Cn+4 Cn Cn+4 AliA's, All 8's ADD
M
SUMINto A= 6 60 A=6 All A's, Cn SU6TRACT
61,62,63,
M
SUMIN to SUMOUT All 6's Any F AliA's, M EXCLUSIVE
(logic Mode) Cn OR
• ADD Mode: 50,53 = VOO; 51, S2 = VSS' SUBTRACT Mode: SO, S3= V SS ;SI, S2 = V OO -
TABLE III
MAGNITUDE COMPARISON
ACTIVE - HIGH DATA ACTIVE -lOW DATA
INPUT OUTPUT INPUT OUTPUT
MAGNITUDE MAGNITUDE
Cn Cn+4 Cn Cn +4
1 1 A ';;6 0 0 A ';;6
0 1 AB 0 1 A>6
0 0 A;;;> 6 1 1 A;;;> 6
1 = HIGH lEVEL
0= lOW lEVEL
459
CD40182B Types
CMOS Look-Ahead
Carry Generator
Features:
• Generates high-speed carry across four adders
or adder grou ps
_
G _
l~ GI
G2
i5
· 12
• High·speed operations:
The RCA-C040182B is a high-speed look-
ahead carry generator capable of anticipating
a carry across four binary adders or groups
tpHL = tpLH = 100 ns (typ.) @ VOD = 10 V
• Cascadable for fast carries over N bits
• Designed for use with CD40181B ALU
.{
- -"
'2
~
P3
4
of adders. The C040182B is cascadable to • 100% tested for quiescent current at 20 V en 13 10

perform full look·ahead across n-bit adders. • 5·V, 10-V, and 15-V parametric ratings
\l'DO~ 16
Carry. propagate·carry. and generate-carry
• Standardized~ symmetrical output vss-e
functions are provided as enumerated in the characteristics
terminal designation below. • Maximum input current of 1 /J.A at 18 V FUNCTIONAL DIAGRAM
over full package·temperature range; 100
The C040182B, when used in conjunction nA at 18 V and 25°C
with the C040181 B arithmetic logic unit • Noise margin (full package·temperature
(ALUI, provides full high-speed look·ahead range) = 1 VatVOD=5V III I·
"
VDD
Pi Po
carry capability for up to n-bit words. Each 2 V at VOO = 10 V
2.5 Vat VOO = 15 V Gli " G2
C040182B generates the look-ahead (antici- n " c,
• Meets all requirements of JEOEC Ten· 1r!
4
" Cnt.
pated carry I across a group of four A LU 'so tative Standard No. 13A. "Standard 1'3 " Cnt.,
In addition, other C040182B's may be em· Specifications for Description of 'B' .".. 10 G
ployed to anticipate the carry across sections Series CMOS Devices" VSS 9 Cnt,
TOP VIEW
of four look-ahead blocks up to n-bits. Carry Applications:
inputs and outputs of the C040181 Bare • High-speed parallel arithmetic units TERMINAL ASSIGNMENT
active·high logic. and carry-generate (GI and • Multi·levellook·ahead carry generation for
carry-propagate (PI outputs are active-low. long word lengths
Therefore the inputs and outputs of the
C040182B are compatible.
The C040182B types are supplied in 16-
lead hermetic dual-in-line ceramic pack-
ages (0 and F suffixesl, 16-lead dual-in-line
plastic packages (E suffix), 16-lead ceramic
suffix).
The C040182B is similar to industry type

MC14582.
TERMINAL DESIGNATIONS
DESIGNATION TERM. FUNCTION
Active·Low
GO,Gi',G2,G3 3,1,14,5 Carry-Generate
Inputs
Active-Low
PO, PT, P2, P3 4,2,15,6 Carry-Propagate
Inputs
Active-High
Cn 13
Carry Input 92CN-2:1&2S
Cn+x , Cn +y , Active-H igh

12,11,9
Cn+z Carry Outputs
Fig. 1 - C0401828/ogic diagram_
Active-Low
Group CD40182B Logic Equations:
G 10
Carry-Generate
Output Cn+x = GO + PO . Cn
Active-Low Cn+y = G1 + P1 ·GO + Pl . PO . Cn

Group Cn+z = G2 + P2 . G1 + P2 . Pl . GO + P2 . P1 . PO • Cn
p 7
Carry-Propagate G = G3 + P3 . G2 + P3 . P2 . Gl + P3 . P2 . P1 . GO
Output
P = P3 . P2 . P1 . PO
460
CD40182B Types
LIMITS
MIN. MAX.
Supply Voltage Range (For T A = Full

Package·Temperature Rangel
3 18 V •g 1t t!f I;'
~ 10
. ItI
5 ,
MAXIMUM RATINGS, Absolute-Maximum Values: 10 15
ORAIN-lO-SOURCE VOLTAGE (VOSI-V
DC SUPPLY-VOLTAGE RANGE, (VDDI
(Voltages referenced to VSS Terminal) ................................................ -0.5 to +20 V Fig. 2 - Typical output low (sink)
INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -0.5 to VDD +0.5 V current characteristics.
•
For TA = -40 to +60" C (PACKAGE TYPE E) ................................................. 500 mW I.M.'.NT nM..".TURE ,·,,·c
For T A = +60 to +85"C (PACKAGE TYPE E) ........ ... ..... ... Derate Linearly at 12 mWI"C to 200 mW
For T A = -55 to +100"C (PACKAGE TYPES 0, F, K) .......................................... 500 mW
For TA = +100 to +125"C (PACKAGE TYPES 0, F, K) .......... Derate Linearly at 12 mW/"C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR: -SOU"" >'"
PACKAGE TYPES 0, F, K, H ........................................................ -55 to +125"C
PACKAGE TYPE E .................................................................. -40 to +85" C
STORAGE TEMPERATURE RANGE (Tstg ) ............................................. -65 to +150"C
At distance 1/16± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.......................... +265"C
, ,
DRAIN-lO-SOURCE VOLTAGE (Vosl-V.
STATIC ELECTRICAL CHARACTERISTICS Fig. 3 - Minimum output low (sink)

CONDITIONS Values 81-55 +25, +125 Apply to 0, F, K, H Packages
DRAIN-lO-SOURCE VOLTAGE IlJosl-V
CHARACTER· Values at -40, +25, +85 Apply to E Package- I
UNITS
ISTIC +25
Vo VIN VDD
(V) -55 -40 +85 +125 Min. Typ. 'M--;;-
(V) (V)
Current, - 0,10 10 10 10 300 300 - 0.04 10
IJA
100 Max. - 15 20 20 600 600 - 0.04 20
0,15
- 0,20 20 100 100 3000 3000 - 0.08 100
Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
IOL Min. 2.4 34 -
1.5 0,15 15 4.2 4 2.8 6.8
-0.64 -0.61 -0.42 -0.36 -0.51 -1 rnA
Output High 4.6 0.5 5 -
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -

Current, -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - Fig. 4 - Tvpical output high (source)
9.5 0,10 10
IOH Min. current characteristics.
13.5 0.15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Qutput Voltage: - 0,5 5 0.05 - a 0.05 ORAIN-TO-SOURCE VOLTAGE IVosl-V
Low·Level.
VOL Max.
- 0,10 10 0.05 - 0 0.05
- 0,15 15 0.05 - a 0.05
v
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·Level, - 0.10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
VIL Max.
1.5,13.5 - 15 4 - - 4
V
Input High 0.5.4.5 - 5 3.5 3.5 - -
Voltage, 1,9 - 10 7 7 - -
VIH Min. 1.5,13.5 - 15 11 11 - -
Input Current ±J()-5
liN Max.
- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±0.1 IJA Fig. 5 - Minimum output high (source)
461
CD40182B Types
At TA = 2!JC; Input tr , tf =20 ns, CL = 50 pF, R L =200 kn
LIMITS
CHARACTERISTIC Voo UNITS
(V) Typ. Max.
tpHL' tpLH 10 100 200 ns
p. G In to p. G Out and Carry Outs 15 75 150
5 240 480
Cn to Carry Outs 10 120 240 ns
15 90 180
5 100 200
Transition Time: tTHL' tTLH 10 50 100 ns Fig. 6 - Typical transition time as a function of
15 40 80 load capacitance.
I nput Capacitance CI N (Any Input) - 5 7.5 pF
CL-!50pF-
CL"nll-i
2 .. 6810 Z .. 6 8102 2 4 68103 2 4 68104
INPUT FREQUENCY (Fr)- kHz

of load capacitance (P, G In to P, GOut Fig. 8 - Typical power dissipation as a function of Fig. 9 - Power dissipation test circuit.
and Carry-Ours). input frequency.
INPUTS
o INPUTQVOO
OUTPUTS
DD
Vss VIH
'- ~
PUC
"'DOV ' NOTE IN
VIOL ::J: ~ ~i~~~:i,~~~~~S

\Iss TO BOTH Voo AND \Iss
CONNECT ALL UNUSED
NOTE: INPUTS TO EITHER
VSS TEST ANY COMBINATION Vao OR "'ss'
OF INPUTS
Vss
92CS-2744!R!
Vss
Fig. 10 - Quiescent device current test circuit. Fig.· 11 - Input voltage test circuit. Fig. 12 - Input current test circuit.
Applications
CARRY CARRY
IN OUT
I LOOK-AHEAD
OUTPUTS
92CS·27626RI
Fig. 13 - 16·8it two-level look-ahead ALU.
462
CD40182B Types
Fig. 14 - 64·Bit full carry look ..hBBd ALU in 31.viJI••
•
1
Fig. 15 - Combined two-level look-ahead and ripple-carrv ALU.
DIMENSIONS AND PAD LAYOUT FOR CD40182BH
9ZCM-3336Z
Dimensions in parentheses are in millimeters and The photographs and dimensions of each CMOS chip
are derived from the basic inch dimensions as 'f
r.present I chip when Is part 01 the wa''', When the
wa'er is s.parated into individual chips, the angle of
indicated. Grid graduBtions are in mils (10-3 inch I. cleavage may vary with respect to the chip lIce for
dlffersnt chips. The actual dimensions of the Isolafed
dimensions shown. The user should considers to/efance
dimensions shown.
463
CD401928, CD401938 Types
CMOS Presettable Features:

Up/Down Counters • Individual clock lines for counting up or counting down
mID
ENAm
• Synchronous high·speed carry and borrow propagation
(Dual Clock With Reset) delays for cascading ,)1 '5 , 01
• Asynchronous reset and preset capability

J' 'OI
•s 0'
High-Voltage Types (20-Volt Rating) J3 0'
7 04
CD40192 - BCD Type • Medium·speed operation-fCl = 8 MHz (typ.) @ 10 V J4 •
CLOCK UP 5 13 BORROW
12Ciiffi'Y'
CP40193 - Binary Type • 5·V. 10·V. and l5·V parametric ratings CLOCK DOWN 4
• Standardized, symmetrical output 14

RESET
characteristics
The RCA·CD40192B Presettable BCD Up/ • 100% tested for quiescent current at 20 V
Down Counter and the CD40193B Preset· • Maximum input current of 1 J.1A at 18 V CD40192B, CD40193B
over full package temperature range; 100 FUNCTIONAL DIAGRAM
table Binary Up/Down Counter each consist
nA at 18 V and 25°C
of 4 synchronously clocked, gated "0" type
• Noise margin over full package temperature ~2CS- Z1561RI
flip·flops connected as a counter. The inputs range:
consist of 4 individual jam lines, a PRESET 1 Vat VDD = 5 V 2 V at VDD = 10 V
ENABLE control, individual CLOCK UP 2.5 V at VDD = 15 V
and CLOCK DOWN signals and a master R E· • Meets all requirements of JEDEC Tentative J. I. I. ·00
SET. Four buffered Q signal outputs as well Standard No. 13A, "Standard Specifications o. 15 JI
for Description of 'B' Series CMOS Devices" 01 14 RESET
as CARRY and BORROW outputs for mul·
CLOCK DOWN J3 BORROW
tiple·stage counting schemes are provided. CLOCK UP I. EmiY
0' PRESEt ENAOLE
The counter is cleared so that all out·
Applications: 04 10 J3
puts are in a low state by a high on the RE· Vss J4
SET line. A RESET is accomplished asynchro· • Up/down difference counting TOP VIEW
• Multistage ripple counting
nously with the clock. Each output is
• Synchronous frequency dividers
individually programmable asynchronously
• AID and D/ A conversion CD40192B, CD40193B
with the clock to the level on the cor· • Programmable binary or BCD counting TERMINAL ASSIGNMENT
responding jam input when the PRESET
ENABLE control is low.
The counter counts up one count on the
positive clock edge of the CLOCK UP sig·
nal provided the CLOCK DOWN line is high.
The counter counts down one count on the R'
positive clock edge of the CLOCK DOWN 54
signal provided the CLOCK UP line is high.

The CARRY and BORROW signals are high CONTROL LOGIC I • SAME AS CONTROL LOGIC I
when the counter is counting up or down.
The CARRY signal goes low one·half clock
cycle after the counter reaches its maximum
count in the count·up mode. The BO R ROW
signal goes low one·half clock cycle after
the counter reaches its minimum count in the
count·down mode. Cascading of multiple pack·
ages is easily accomplished without the need
for additional external circuitry by tying the
BORROW and CARRY outputs to the
CLOCK DOWN and CLOCK UP inputs,
respectively, of the succeeding counter
package.
The CD40192B and CD40193B types are
ceramic packages (0 and F suffixes), 16-
16"lead ceramic flat packages (K suffix),
* COS/MOS
PROTECTION NETWORK

Fig. 1 - CD40192Blogic diagram (BCD).
464
RESET
* 14}-------------------~--------~----~------~--------~
CLR I h
_0
PE 1 +--
?
JI 0 -
1
J2 0
R4
J3 0
1
-
54 J41 -
o
Cb~ 6- I - rr.
CONTROL LOGIC I • SAME AS CONTROL LOGIC I ClK I
DN 0
,
r rr-
,-- f--
010
f-- I--
020
,
030
,
-- I--
040 -- r--
CARRY I
o
BORROW I I--
o
COUNT -----to 0 7 8 9 0 1 2 1 0 9 8 7
* ALL INPUTS PROTECTED 8'1'

COS IMOS PROTECTION NETWORK I
f--
Fig. 2 - CD401g38 logic diagram (binarv).
~- - - - - - - - - - - - ---: r-
I IT CL EL I r--- r-- - r-
I I r--- I-- - ~
I 0 I , --
I I r---
04 0 , f-- I-- --
I I
I I CARRY b
I I BORROW 6
I I COUNT ---+ 0 I] 14 I~ 0 1 2 1 0 I~ 14 I~
I I
I I
IL __________________ JI Fig. 5- CD401938 timing diagram.
Fig. 4- Internallog;c of Flip-flop.
AMBIENT TEMPERATURE (TA)" Z5"C
TRUTH TABLE
CLOCK CLOCK PRESET GATE~TO-SOURCE VOLTAGE (VGS)oI5 V

RESET ACTION
UP DOWN ENABLE
~ 1 1 0 COUNT UP
"'"'- 1 1 0 NO COUNT ,ov

1 ~ 1 0 COUNT DOWN
~ 10
1 ~ 1 0 NO COUNT § ,
X X 0 0 PRESET
, 10
CRAIN-TO-SOURCE VOLTAGE (Vos)-V
X X X 1 RESET
1 = HIGH LEVEL 0= LOW LEVEL x = DON'T CARE current characteristics.
465
For T A = -40 to +60' C (PACKAGE TYPE E) ............................................. , ... 500 mW
For T A = +60 to +85'C (PACKAGE TYPE E) ........ ........... Derate Linearly at 12 mW/'C to 200 mW
For T A = -55 to +100'C (PACKAGE TYPES D, F, K) .......................................... 500 mW
For T A = +100 to +125'C (PACKAGE TYPES D, F, K) ••..•.•... Derate Linearly at 12 mW/'C to 200 mW
PACKAGE TYPES D, F, K, H ........................................................ -55 to +125'C DRAIN-lO-SOURCE VOLTAGE lVosl-V
PACKAGE TYPE E .................................................................. -40 to +85'C Fig. 7 - Minimum output low (sink)
STORAGE TEMPERATURE RANGE(Tstg) ............................................. -65 to +150'C current characteristics.
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. . ........................ +265'C
DRAIN-lO-SOURCE VOLTAGE lVosl-V
RECOMMENDED OPERATING CONDITIONS at TA = 25 0 C (unless otherwise specified)

always within the following ranges.
LIMITS UNITS
CHARACTERISTIC VDD
(VI Min. Max.
Supply Voltage Range (For T A = Full Temp. Range) - 3 18 V
5 80 -
Removal Time:
10 40 - ns
RESET or PE 15 30 -
Pulse Width:
5 480 - Fig. il- Typical output high (source) m5-lomQ)
10 300 - ns .- . . current characteristics.

RESET
15 260 -
5 240 - DRAIN-lO-SOURCE VOLTAGE (VOSI-V
PE 10 170 - ns
15 140 -
5 180 -
CLOCK 10 90 - ns
15 60 -
5 2
Clock Input Frequency 10 DC 4 MHz
15 5.5
5 - 15
Clock Rise & Fall Time 10 - 15 /lS
15 - 5
Fig. 9- Minim,!ffl output high (source) .2CS-ZUll'"
r--'WH~IWL .....,
I 1 I
CLOCK
RESET
PRESET ENABLE
I
i
I '
I
*(=::t:=====
~Irrm
*
*RESET OR PRESET ENABLE

REMOVAL TIME
92CS-21562At
Fig. 10 - Timing diagram defining trem .

Fig. 11 - Typical transition time as a
466
CONDITIONS Values at-55, +25, +125 Apply to 0, F, K, H Packages
ISTIC UNITS
Vo
+25
VIN VDD
(V) (V) (V) -55 -40 +85 +125 Min. Typ. Max.
Current, - 0,10 10 10 10 300 300 - 0.04 10
100 Max. IJA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
Output low 0.4 0,5 5 0.64 0.61 0.42 .0.36 0.51 1 -
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - LOAD CAPACITANCE (ell - pF
IOl Min.
1.5 0,15 15 4.2 4 2.8 2.4 34 6.8 -
rnA Fig. 12 - Typical propagation delay time
Output High 4.6 D,S 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 -
(Source) 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
•
2.5 D,S
Current, -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
9.5 0,10 10
IOH Min.
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Low·Level, - -
0,10 10 0.05 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High·level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input low 0.5,4.5 - 5 1.5 - - 1.5
Voltage, 1,9 - 10 3 - - 3
VIL Max.
1.5,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - - 'r-~~~~~t-t-HHt-t-HH+-+-t+H
10'
Voltage, 1,9 - 10 7 7 - - "6 ~02 2 "6 ~03 2
24S9
10 2 4 6 '0" 2
VIH Min. 1.5,13.5 - 15 11 11 - - INPUT FREQUENCY ('IN) -KHz
Input Current Fig. 13 - Dynamic power dissipation.

- 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10- 5 ±D. 1 IJA
liN Max.
80-1E;;:a~1I1
88-96
(2.235- 2.438)
l •
~~0.I024-10
- 0.254)
111-119
(2.819 - 3.022) 92C5.28930RI .1
,Dimensions and pad layout for the CD40192BH The photographs and dimensions of each CMOS chip
(dimensions and pad layout for the CD401938H represent a Chip when it is part of the wafer. When the
are identical). wafer Is separated into individual chips, the angle of
different chips. The actusl dimensions of the isolated
Dimensions in parentheses are in millimeters and dimensions shown. The ussr should consider B tolerance
are derived from the basic inch dimensions as in- of -3 mils to +16 mils applicable to the nominal
dicated. Grid graduations are in mils (10- 3 inch). dimensions shown.
467
CD401928, CD401938 Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C
Input t r, tf = 20 ns, CL = 50 pF, RL = 200 kn
VDD
'(V) Min. Typ. Max.
5 - 250 500
Propagation Delay Time tpHL, tpLH:
10 - 120 240 ns
CLOCK UP or CLOCK DOWN to Q, RESET to Q
15 - 90 180
5 - 200 400 Fig. 14 - Dynamic power dissipation test circuit.
PE to Q 10 - 100 200 ns
15 - 70 140
vOO
5 - 160 320
CLOCK UPto CARRY, CLOCK DOWN to BORROW 10 - 80 160 ns INPUTS r--~-,
o
15 - 60 120 Vss
5 - 300 600
RESETorPEtoBORROWorCARRY 10 - 150 300 ns
15 - 110 220
5 - 100 200
Transition Time, tTHL' tTLH 10 - 50 100 ns
15 - 40 80 <JZCS-2740IRI
5 - 40 80 Fig. 15 - Ouiescent-device-current test circuit.

Min. Removal Time, t rem * RESET or PE 10 - 20 40 ns
15 - 15 30
5 - 240 480
Min. Pulse Width, tw RESET 10 - 150 300 ns
15 - 130 260
5 - 120 240
PE 10 - 85 170 ns
15 - 70 140
5 - 90 180 92CS-21441RI
CLOCK 10 - 45 90 ns
15 - 30 60 Fig. 16 - Input-voltage test circuit.
5 2 4 -
Max. Clock Input Frequency, fCl 10 4 8 - MHz
15 5.5 11 -
5 - - 15
Clock Rise & Fall Time, t r, tf 10 - - 15 /JS Voo 1NPUO'
VOO NOTE"
15 - - 5
~ ~i~~::,~~~~~S
Input Capacitance, CI N: Vss TO BOTH Voo AND VsS'
CONNECT ALL UNUSED.
RESET - - 10 15 pF INPUTS TO EITHER
Voo OR VSS'
All Other Inputs - - 5 7.5 pF Vss
* The time required for RESET or PRESET ENABLE control to be removed before clocking (see timing
diagram, Fig. 10. Fig. 17 - Input current test circuit.
Jl J2 J] J4 JI J2 J3 J4
CLOCK UP ~~_--.J;bQ!~~~~~;;-1 CARRY

CLOCK DOWN '-T-'--'--'--'---r'F'""'''--''''''''''''''I.,-:.~~=.-,J BORROW
RESET ----~--t---
~~;~~------~------------~
92CS-27'56)RI
Fig. 18 ~- Cascaded counter packages.
468
CD40208B Types
CMOS 4 x 4 Multiport Features:

• Four 4-bit registers WRln:
Register • One input and two output buses

ENABLE
1"
• Unlimited expansion in bit and word
High-Voltage Types 120-Volt Rating) directions 0I.1A 01
~' : .O}01 WORD A
.
INPUTS O~ 111 6 02 OUTPUT
• Data lines have latched inputs , "
• 3-state outputs
, "
The RCA-C040208B is a 4 x 4 multipart • Separate control of each bus, allowing
register containing four 4·bit registers, write
address decoder, two separate read address
decoders, and two 3-state output buses.
simultaneous independent reading of
any of four registers on Bus A and
Bus B and independent writing into
any of the four registers RUDla
::
,
"}.,,,
QO
02
"
.
OUTPUT
When the ENABLE input is low, the cor- FlUOOIi

responding output bus is switched, inde- • Standardized, symmetrical output
pendently of the clock, to a high-impedance characteristics
state. The high-impedance third state pro- • 100% tested for quiescent current at 20 V
vides the outputs with the capability of being • Maximum input current of 1 /lA at 18 V
connected to the bus lines in a bus·organized over full package-temperature range; FUNCTIONAL DIAGRAM
system without the need for interface or 100 nA at 18 V and 250 C
pull-up components. • Noise margin (over full package-
When the WR ITE ENABLE input is high, temperature range):
all data input lines are latched on the positive
transition of the CLOCK and the data is
entered into the word selected by the write
address lines. When WRITE ENABLE is low,
1 Vat VOO =5 V
2VatVDD=10V
2.5 V at VDO = 15 V
II
the CLOCK is inhibited and no new data is WOROA
• Meets all requirements of JEOEC OUTPUT
entered. In either case, the contents of any Tentative Standard No. 13A, "Standard
word may be accessed via the read address Specifications for Description of 'B' WORDB
lines independent of the state of the CLOCK Series CMOS Devices" OUTPUT
input.
Applications:
ENABLE B
The C0402088 types are supplied in her- • Scratch-pad memories
metic 24-lead dual-in-line ceramic packages • Arithmetic units
(0 and F suffixes), 24-lead dual-i n-line plas- • Data storage
tic packages (E suffix), 24-lead ceramic flat Fig. 1 - Block diagram.
suffix).
TRUTH TABLE
CLOCK WRITE WRITE WRITE READ READ READ READ ENABLE ENABLE On QnA °nB
ENABLE 1 0 1A OA 1B OB A B
~ 1 51 52 51 52 51 52 1 1 1 1 1
1 51 52 51 52 51 52 1 1 0 0 0
-------
X X
1
X
0
X
0
X
0
X
1
X
1
X
0
0
1
0
1 On to
X Z
Word 1 Word 2
Z
~
word 0 oul oUI
0 0 0 0 1 1 0 1 1 Word 0 Word 1 Word 2
ol. I· 2' VDD

-------
X X X X 1 0 0 1 1 1
nOI altered
X
Oul oUI
Word 2 Word 1
02. 2l 01. oul oul
ENABLE A 22 aDa
~ X X X X X X X 1 1 X NC NC
00 A 21 ENABLE B
01 A 20 DO
1 = HIGH LEVEL, o· lOW lEVEL. X - DON'T CARE. l= HIGH IMPEDANCE
o2A 01 S1 <Jnd 52 refer to mpul slates ot {'Ither 1 no 0
O>A "
la 02
WRITE 0 17 Dl
WRITE I
READ 08 10 ,.
I. CLOCK
WRI Tt ENABLE MAXIMUM RATINGS. Absolute-Maximum Values:
READ 18
V•• "
12
,." READ IA
READ OA DC SUPPLY-VOLTAGE RANGE, (VDD)
TOP VIEW
(Voltages referenced 10 VSS Terminal) ................................................ -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................... -0.510 VDD +0.5 V
92CS- 28550RI
TERMINAL ASSIGNMENT POWER DISSIPATION PER PACKAGE (PO):
For TA = -4010 +60°C (PACKAGE TYPE E) ................................................. 500 mW
For TA = +60 10 +85'C (PACKAGE TYPE E) ... ................ Derate Linearly at 12 mW/oC 10 200 mW
ForTA = -5510 +l00°C (PACKAGE TYPES 0, F, K) .......................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPES 0, F, K) .....•.•.. Derale Linearly al12 mW/OC 10 200 mW
PACKAGE TYPES 0, F, K, H ........................................................ -55 to +125°C
PACKAGE TYPE E .................................................................. -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) ............................ , ................ -8510 +l50°C
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. . .•...................... +265°C
469
CD40208B Types
*3-STATE
B ENABLE
PIN 24. VCD

PIN 12 z \ISS r-----------------r--------------l
I
I
I D
I A
QA I
I
ENABLE dVDO I
I
I
I I I
1 I ~ ...... our I
* ALL INPUTS PROTECTED

8'1' COS/MOS INPUT
1
II w
I
8 II
.B I
I
1r-rv PUT 1
II
I
PROTECTION NETWORK I I Yss 1
I I I
'2CL·29n~
I : I
I DETAIL OF I DETAIL OF' I
LM~~R~C~~ _ _ _ _ _ _ _ _ _ _ _ L3:.S~T..:~T~~ ______ -'
92Cl-29222
D.
WE
WA---+----____~-----J~------~--A-~-n------------
..
RA--_t.--~----~~~----------_t.----_t~~~fi~--"~-
92CM-29221
470
CD402088 typeS
RECOMMENDED OPERATING CONDITIONS at TA = 250 C. Except as Noted.
VDO LIMITS
(VI MIN. MAX.
Supply Voltage Range
(For TA ~ Full Package - 3 18 V
Temperature Rangel
Set· Up Time: 5 0 -
Data to Clock. tS(DI 10 0 - ns
15 0 - DRAIN-lO-SOURCE VOLTAGE I'IOSI-V
tS(WEI 10 100 - ns Fig. 4 - Typical output low (sink)
15 70 - current characteristics,
Write Address to Clock, 5 250 -

tS(WA) 10 100 - ns 1m
15 70 -
Hold Time: 5 220 -
Data to Clock, tH(D) 10 100 - ns "I
15 80 - :::
Write Enable to Clock. 5 270 -
tH(WE) 10 130 - ns
15 80 -
Write Address to Clock. 5 330 -
tH(WA) 10 140 - ns
15 90 - DRAIN-lO-SOURCE VOl.TAGE 1\'051-\'
Clock Input Frequency. 5 - 1.5

fCl 10 - 3.5 MHz current characteristics.
15 - 4.5
Clock Pulse Width, 5 350 - DRAIN-lO-SOURCE VOLTAGE lVoSI-V
Clor WE 10 130 - ns
tw 15 90 -
5 - 15
Clock Rise or Fall Time. 10 - 5 p.s
trCl or tfCl 15 - 5

DRAIN-lO-SOURCE VOLTAGE IlJesl-V
." '10
'."'.".'. 1.'.".N~I.v"'. ~ :~':
'.'.~'.~~' :'.de'' ' '
il ,zes·2tZI'
Fig. B - Typical propagation delay time as a
Fig. 7 - Minimum output high (source) function of load capacitance (eL or Fig. 9 - Typical transition time as a function
current characteristics. WE to 0). of load capacitance.
471
CD40208B Types
CONDITIONS Values at-56,+25, +125 Apply\oD,K,F,H PlckIges
CHARACTER- Values at -40, +2&, +85 Apply to E PIckage
ISTIC UNITS
Vo V,N VDD +25
(V) (V) (V) -56 -40 +85 +125 Min_ Typ. Max.
Current,
100 Max.
- 0,10 10 10 10 300 300 - 0.04 10
IJA
- 0,15 15 20 20 600 600 - 0.04 20
- 0,20 20 100 100 3000 3000 - 0.08 100
2 ... 1 a .... 2 .. ,e 2.... 2 45
Output low 0.4 0.5 5 0.64 0.61 0.42 0.36 0.51 1 - 10 oZ lOS 10"
I"UT FREOUENCY (lI)-IIHI:
(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - I2CS- 29211
'OlMin.
1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 - Fig. 10 - Typical power di..ipotion as a
function Df input frequency.
Output High 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - rnA
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 -
Current,
IOHMin.
9.5 0,10 10 1.6 1.5 -1.1 -0.9 -1.3 -2.6 -
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
low·level,
- -
V~NPU(JS
VDO ~~:~URE INPUTS
0,10 10 0.05 0 0.05
VOL Max.
- 0,15 15 0.05 - 0 0.05
V
High-level. - 0,10 10 9.95 9.95 10 - o~ SEQUENTIALLY.
VOH Min.
- 0.15 15 14.95 14.95 15 - Vss TO BOTH Yoo AND Vss'
CQHNECT ALL UNUSED
Input low 0.5,4.5 - 5 1.5 - - 1.5
INPUTS 10 EITHER
Voc OR Vss'
Voltage,
Vil Max.
1,9 - 10 3 - - 3 Vss
15,13.5 - 15 4 - - 4
V
Input High 0.5,4.5 - 5 3.5 3.5 - - Fig. 11 - Input leekag. current
Voltage, 1,9 - 10 7 7 - ~
ten circuit.
VIH Min. 1.5,13.5 - 15 11 11 - -
Input Current
liN Max.
- 0,18 18 to. 1 to. 1 tl tl - tl0-5 to.l IJA
3-State Output
leakage Current
lOUT Max.
0,18 0,18 18 to.4 to.4 t12 t12 - ±10-4 to.4 IJA .
vss
INPUTS
Fig. 12 - Ouiescent-device-current
ten circuit.
Dimensions and Pad Layout for CD4020BBH
Dimension, in psrenthtnl!1$ are in millimeters and are

derived from the basic inch dimensions B8 indicated.
Grid graduation. are in mil. (10-3 inth}.
The photographs and dimensions of sach CMOS chip

represent a chip when it Is part 01 the wal.r. When the
wafer Is separated into Individual chips. the angle of
4-10 chip, the/efore, may differ slightly from the nominal
102-0.254) dimensions shown. The user should consider a tolerance
126-134 of -3 mils to +16 milS applicable to the nominal
92CM-Z9234
(3.200-3.403) dimensions shown.
472
CD40208B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25°C; Input tr.tt =20 ns.
Cl =50 pF. Rl = 200 k!1
'NPUTOVOO
OUTPUTS
VDD LIMITS V'H
(V) Min. Typ. Max. '---
v~
~
~
tpHl' tplH 10 - 140 2BO ns
NOTE:
Clock or Write Enable to Q 15 - 100 200 vss ~srN",~~~ONBINATION
Read or Write Address to Q 5 - 300 600 92CS-27441IAI
10 - 120 240 ns
15 - B5 170 Fig. 13 - Input-voltage test circuit.
3·State Disable Delay Time: 5 - 100 200
10 - 50 100 ns Voo
tpZH. tpHZ
tpZl' tplZ
Output Transition Time:

tTHl' tTlH
15
5
10
15
5
10
-
-
-
-
-
-
40
130
60
50
100
50
BO
260
120
100
200
100
ns
ns
t
o""
l'O"
TO
ANY
OUT-
PUT
PULSE GEN. 2
II
15 - 40 BO
Minimum Setup Time: 5 - -95 0
Data to Clock tS(D) 10 - -35 0 ns
15 - -20 0
5 - 125 250
Write Enable to Clock tS(WE) 10 - 50 100 ns
. . . .LE
INPUT ~ .r,c;;. VDD_V'S
...... 1\...-.....A_ ..
15 - 35 70 'Pl.Z I:: ~PZL
'IO,.,_Voo
5 - 125 250 BuT-{
PUTS
10" VOL
YOH
Write Address to Clock tS(WA) 10 - 50 100 ns 1)% -Vss
15 - 35 70 TEST VOLTAGE
•PHZ I-'PZH
CHAR
Clock Rise and Fall Time: 5 - - 15 •• D .'0 UCM-29217
'PHZ VDD VSS
trCl. tfCl 10 - - 5 /ls tpZH V V
15 - - 5 'Pl.Z
Ipll
VS5 VOO
VDD
VS5
Minimum Hold Time: 5 - 110 220
Fig. 14 - Output-enable·delay-times test
Data to Clock tH(D) 10 - 50 100 ns
circuit and waveforms.
15 - 40 BO
5 - 135 270
Write Enable to Clock tH(WE) 10 - 65 130 ns
15 - 40 BO
5 - 165 330
Write Address to Clock tH(WA) 10 - 70 140 ns
15 - 45 90
5 1.5 3 -
Maximum Clock Input Frequency.
10 3.5 7 - MHz
fCl 15 4.5 9 -
Minimum Clock Pulse Width. 5 - 175 350
Clock or Write Enable 10 - 65 130 ns P.G.I
tW(Cl) 15 - 45 90 P.G.2
Write Address 5 - 150 300 P.G.3

tW(WA) 10 - 75 150 ns O'A.8~
15 - 45 90
!--REPETITIVE WAVEFORMS----..j
Average Input Capacitance.
(Any Input)
- - 5 7.5 pF 92.CN-29218RI
CI
,Fig. 15 - Power-dissipation test circuit
and waveforms.
473
CD40257B Types
CMOS Features:
• lostate outputs OUTPUT
Quad 2-Line-to-1-Line • Standardized, symmetrical output characteristics

DISABLE
Data Selector/Multi • 100% tested for quiescent current at 20 V

• Maximum input current of 111-A at 18 V
.," '"
01
plexer over full package-temperature range;

.2
.2 02
High-Voltage Types (20-Volt Rating) 100 nA at 18 V and 250 C •• " D.

•••• "
10
• Noise margin (over full package-
temperature ·range): 13 12
B' O.
The RCA·CD40257B is a Data Selector/Multi- 1 VatVDD = 5 V I
plexer featuring three-state outputs which VOO'16
2 Vat VDD = 10 V INPUT
SELECT vss's
can interface directly with and drive data
lines of bus·oriented systems. 2.5 Vat VDD = 15 V
The CD402578 types are supplied in 16- • 5-Y, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC FUNCTIONAL DIAGRAM
lead hermetic dual-in-line ceramic packages
(D and Fsuffixes), 16-lead dual-in-line plas- Tentative Standard No, 13A, "Standard
Specifications for Description of 'B'
tic packages (E suffix), 16-lead ceramic flat
Series CMOS Devices"
suffix).
Applications:
• Digital Multiplexing
MAXIMUM RATINGS, Absolute-Maximum Values: • Shift-right/shift-Ieft registers
DC SUPPLY-VOLTAGE RANGE, (VDD) • True/complement selection
(Voltages referenced to VSS Terminal) ..•..•...•.••.••••.•.•.•••...••......••.•...•.•. -0.5 to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS ....•.•.•...•.. ____ . __ , ____ .... __ • __ . ____ .• -0.5 to VDO +0.5 V RECOMMENDED OPERATING CONDITIONS
DC INPUT CURRENT, ANY ONE INPUT .. ______ • __ . __ . ____ ' __ . ____ .... __ ' ____ •... ____ • __ ' __ . ±10 mA
POWER DISSIPATION PER PACKAGE (PO): . conditions should be selected so that oper-
ForTA = -40 to +6O'C (PACKAGE TYPE E) __ ' ____ . __ . ____ . __ . ____ ....... ____ • __ . ____ • ____ •. 500mW
ation is always within the following ranges:
For TA = +60 to +85'C (PACKAGE TYPE E) •••...•••..•.•••... Derate Linearly at 12 mwrc to 200 mW
For TA = -55 to +loo'C (PACKAGE TYPES 0, F, K) • __________ . __ • ____ ..• __ .. __ ... __ • ______ .• 500 mW
For TA = +100 to +125'C (PACKAGE TYPES 0, F, K) __ . ____ ' __ Derate Linearly at 12 mW/'C to 200 mW LIMITS
DEVICE DISSIPATION PER OUTPUT TRANSISTOR: Min. Max.
ForTA = FULL PACKAGE-TEMPE~ATURE RANGE (All Package Types) ____ •.... __ .. __ . ____ •. 100 mW Supply· Voltage Range
OPERATING-TEMPERATURE RANGE (TA): (ForTA=Full Package· 3
PACKAGE TYPES 0, F, K, H __ . __ . __ ••. ____ •.. __ .. ______________ . __ ...... __ • __ . __ . __ -55 to +125'C 18 V
PACKAGE TYPE E . __ .... __ ... __ ... __ ' __ c.. __ . ____ ...... __ . ____ . __ • ____ •.. ____ .. ____ -40 to +85'C Temperature Range)
STORAGE TEMPERATURE RANGE (Tstg) __ • __ .. __ • __ . ____ ' __ • ____ . __ •. __ .. __ ' __ . __ . __ -65 to +15O'C
At distance 1116 ± 1132 inch (1.59 ± 0.79 mm) from case for 10 s max. __ "" ____ • __ . ____ .... __ ' +285'C TRUTH TABLE
INPUTS OUTPUT
3-STATE
OUTPUT
DISABLE OUTPUT SELECT A B D
*15 DISABLE
1 X X X Z
0 0 0 X 0
0 .0 1 X 1
0 1 X 0 0
0 1 X 1 1
X = DON'T CARE LOGIC 1 = HIGH
LOGIC 0 = LOW Z = HIGH IMPEDANCE
*5 A2
... B2 02
3 ADDITIONAL IDENTICAL CIRCUITS
* Al
" o•
110'0 83
*I. •• •
O.
*13 84 12
92CIoI-281'4IAI
DFfAIN- TO-SOUflC£ VOLTAGE (VOS)·- V
F;g.2 - Typical output low {sink J

Fig. 1 - Logic diagram for CD40257B. current cha;acteristics,
474
CD40257B Types

Values aI-55, +25, +125 Apply 10 D, F, K. H Packages
CHARAC-
CONDITIONS V.lues at -40,+25 ..+85 Apply to E PkIP. UNITS
TERISTIC
Vo VIN VDD +25
IVI IVI IVI -55 -40+-~ __5-+_+_125
__~M_I_'n_'1-_T~y~p_-r_~
__X'+-__~
Quiescent 0,5 5 30 30 0.02
Device 0,10 10 2 2 60 60 0.02 2
IJA
Current 0,15 15 4 4 120 120 0.02 4 ~ 25 5V
100 Max. 0,20 20 20 20 600 600 0.04 20

o s ~ ~
DRAIN-lO-SOURCE VOL.TAGE CVosl-V
Output Low
(Sink) 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - Fig.3 - Minimum output low (sink)
Current, 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 - current characteristics.
IOL Min. 1.5 0,15 15 4.2 4 2.8 2.4 3.4 6.8 - mA
DRAIN-lO-SOURCE VOLTAGE (YoSI-V
-IS I
4.6 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1
Output High f--'-'~-+-==-i-::""'+---=-=";+-="-'--+-=~=+-""::';;~+-='-+-~
0,5 :~'.'~.'.
i-=-
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - -TO-SOUR' . ,V,,
Current,
IOH Min.
Output Volt·
9.5
13.5
0,10
0,15
10
15
-1.6 -1.5 -1.1 -0.9 -1.3 -2.6
-4.2 -4 -2.8 -2.4 -3.4 -6.8
-
- II
age: - 0,5 5 0.05 - 0 0.05
Low· Level, - 0,10 10 0.05 - 0 0.05
VOL Max. - 0,15 15 0.05 - 0 0.05
V
Output Volt·
age:
High- Level,
-
-
0,5
0,10
5
10
4.95
9.95
4.95
9.95
5
10
-
-
~
VOH Min. - 0,15 15 14.95 14.95 15 - Fig.4 - Tvpical output high (source)
.2CS-l.SZOII,
Input Low 0.5,4.5 - 5 1.5 - - 1.5 current characteristics.

Voltage, 1,9 - 10 3 - - 3
, VIL Max. 1.5,13.5 - 15 4 - - 4
V
DRAIN-lO-SOURCE VOLTAGE (VDSJ-V
-IS -10
Input High 0.5,4.5 - 5 3.5 3.5 - - I~~~.~'. !.'.~~~'.~ ::~':~,':
Voltage, 1,9 - 10 7 7 - - '-'"

VIH Min. 1.5,13.5 - 15 11 11 - -
Input
Current, - 0,18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 IJA
liN Max.
3·State Output
Leakage
Current
lOUT Max.
0,18 18 ±0.4 ±0.4 ±12 ±12 ±10-4 ±0.4 IJA
'; ,
DYNAMIC ELECTRICAL CHARACTERISTICS al T A = 25°C; Input Ir' If = 20 ns,
Cl = 50pF, Rl = 200 Kn Fig.5 - Minimum output high (source)
CHARACTERISTIC TEST CONDITIONS liMITS UNITS
VDDIVI Typ_ Max.
Data Input to Output, 10 70 140 ns
tPHl, tPlH 15 50 100
Select to Output,
5 190 380 ,:: ,;; P~fIW: Hfr~ i~
tPHl, tplH
10 85 170 ns Iif ~:iJpU::"''-TAGE ivool" v
15 65 130
5 95 190
Output Disable to Output. 10V
10 50 100 ns IOV
tPHL. tPlH
15 40 80
5 100 200 20 40 60 80 100
Transition Time.
10 50 100 ns
ITHl.lTlH 15 40 80 Fig. 6 - Typical propagation delay time as a
function of load capacitance (DA TA
Input Capacitance. CIN Any Input - 5 7.5 pF INPUT to OUTPUT).
475
CD40257B Types
""l
·•
AMBIENT TEMPERATURE CTAJ.U-C
INPUT RISE OR
11,,1,.-20 .. -+
tifF-
LOAD RESISTANCE (RLJ-r=tr --
~.~
~
~~
11 V:;;·
,.104. i 1
oo
e •
~ , 1t~<'v;. INP(JUS
Y
. Voo NOTE:
*
it ~ MEASURE INPUTS
R• ~ ~
1).1
:
SS
SEQUENTIALLY•
TO BOTH Voo ANDVss
to:· I) II
CONNECT ALL UNUSED
INPUTS TO EITHER
· -1 V
LOAD CAPACITANCE ceLl-SO "
CL -15 p'_ Vss
VDD """ss'
10
.
2 ....
10
III I IIII I IIII I III
... 1,01 2 .",OS2 ... ',0"246'
INPUT FREQUENCY ( ' . I-11Hz
Fig.9 - Input current test circuit.
"CS·2IT4,
Fig.8 - Typical dynamic power dissipation as a
Fig. 7 - Typical transition time as a function function of input frequency (one
of load capacitance. INPUT to one OUTPUT).
I. I.
.
INPUT SELECT VDO
INPUTS
.,AI •
3
IS
"13
OUTPUT OIUILa
A'••
Vss 01
A.
8'
D'
"
"
10
..
D.
83
VSS 9 03
TOP VIEW
9ZCSL Z7321
92CS-Z744IRI
Fig. to - Input voltage test circuit. Vss TERMINAL ASSIGNMENT

Fig. 11 - Ouiescent device
'current test circuit.

represent a chip when It Is part of the wafer. When the
wafer Is separated Into Individual chips. the angle of
Dimensions In parentheses are In millimeters and are cleavage may vary with respect to the chip face for
derived from the basic Inch dimensions as Indicated. different chips. The actual dimenSions of the Isolated
Grid graduations are In mils (10-3 Inch). chip. therefore. may diller slightly from the nominal
dimensions shown. The ussr should consider a tolerance
dimensions shown.
476
CMOS A-Series
Integrated Circuits
Technical Data
477
CD4000A, CD4001A, CD4002A, CD4025A Types
CMOS NOR Gates FUNCTIONAL DIAGRAMS
r-----,
.
Dual 3 Input
plus Inverter-CD4000A
Ne "."D'ii'+"F .. _Gtit
.
VDO
Quad 2 Input-C04001 A
Dual 4 Input-C04002A
Triple 3 Input-CD4025A
The RCA-C040ooA, C04001A, C04002A,

and C04025A NOR gates provide the system 92CS-24757 Vss
92CS·2 .. 762
designer with direct implementation of the
C04000A 92CS-Z47se
NOR function and supplement the existing CD4oo1A
CD4025A
family of CMOS gates. ,----.-_Yoo CD4002A
These types are supplied in 14-lead her- n-......-'\I'V'v.............. GATES

metic dual-in-line ceramic packages (0 and IN
01 ALL INPUTS ARE PROTECTED
F suffixes), 14-lead dual-in-line plastic Yss BY COS/MOS PROTECTION NETWORK
packages (K suffix), and in chip form (H MAXIMUM RATINGS, Absolute·Maximum Values:
suffix). STORAGE.TEMPERATURE RANGE (Tslgl . . . . . . . . • • . • • . . . . . . . . . . • . . -66 to +150°C
PACKAGE TYPES 0, F, K, H . . • • • • . . . . • . • • • • • • • • • . . . . .• -55 to +125"C
PACKAGE TYPE E . . . • • . • • • • • • . • • • . • . • . . . • • . • • . . .• -40 to +OS"C
(Voltage. referenced 10 VSS Termlnan: . • . . . . . . . . • . . . . . . . . . • • . • . • . .. -0.610 +16 V
Features: POWER DISSIPATION PER PACKAGE (POl:
• Quiescent current specified to 15 V FORTA=-40lo+50oC(PACKAGETYPE E'I . . . . . . . . . . . . . . . . . . . . . . • • 500mW
FOR TA = +50 to +85°P (PACKAGE TYPE E I ...... Derale Linearly al 12 mWi" C to 200 mW
• Maximum input leakage of 1 J.lA at 15 V For TA =-55 to +100"C (PACKAGE TYPES 0, F, K) • • • • • • • • • • • • • • • 500 mW
(full package·temperature rangel For TA = +100 to +125"C (PACKAGE TYPES 0, F, KI . • •• Derate Linearly at 12 mwrc to 200 mW
• 1-V noise margin (full package-tempera- DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ture rangel FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPESI ....... 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . ..(1.510 VOO +0.5 V
LEAD TEMPERATURE (DURING SOLDERINGI:
AI dlslance 1I16± 1/32 inch (1.59 ± 0.79 mml!rom case for 10 s max. . .......•..•. +2SSoC
For maximum reliability, nominal operating conditions should be selected so that ~11[NT.f£lIPE:"ATU"E ITA).25·C
operation is always within the following ranges: IS IW'PLY VOLTAGE: 1Voo)·.,v
> ~D
LIMITS
CHARACTERISTIC
MIN. MAX.
UNITS
I
~ -iLrVD
: 10 10
Supply·Voltage Range (For TA =
Full Package·Temperature ~
Range) 3 12 V
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, CL = 15pF, Input t r• tf= 20ns
LIMITS '"
INPUT VOLT... GE 1VII-V
TEST
D,F,K,H E
CHARACTERISTIC CONDI~ PACKAGES UNITS
PACKAGE Fig. 1 - Minimum & maximum voltage transfer
VDO characteristics.
(Volul TYP. MAX. TYP. MAX.
Propagation Delay Time: 5 35/60 50195 35/60 SO/95
High·to·Low Level, ns os
10 25/35 40/60 25/35 55/60
tpHL r
!
.... 1 soc
Low·to·High Level, 5 35/S0 95/120 35/S0 120/120 ::: 10

IOV
ns
tpLH 10 25/40 45/65 25/40 65/65
Transition Time: 5 65 125 65 200
High·to·Low Level, ns
10 35 70 35 115
tTHL
Low·to·High Level, 5 65 175 65 300 10 ..
ns INPUT VOLT.... CVII-V
tTLH 10 35 75 35 125
Input Capacitance, CI Any Input 5 - 5 - pF
Note: Numbers to the rl9ht of slash mark are for C04025A:_
numbers to the left of slash mark are for 4OO0A, 4001 A, and 4002A.
478
CD4000A, CD4001A, CD4002A, CD4025A Types

PftLy VOLTS IY
LIMITS AT INDICATED TEMPERATURES 1°c)
CONDITIONS
D, F, K, H PACKAGES E PACKAGE ~ '"
CHARACTERISTICS UNITS ~ 10
+25 +25
Vo V IN V DD
-55 +125 -40 +85 g
(V) (V) (V) TYP. LIMIT TYP. LIMIT ~ 7.~
- - 5 0.05 0.001 0.05 3 0.5 0.005 0.5 15

Quiescent Device
- - 10 0.1 0.001 0.1 6 5 0.005 5 30 ~A
Current, IL Max.
- - 15 2 0.02 2 40 50 0.5 50 500
Output Voltage: 2' 7.~ 10 12.~
Low Level,
- 0.5 5 a Typ.; 0.05 Max INPUT VOLTS (VI'
VOL
- 0,10 10 a Typ.; 0.05 Max Fig. 3 - Typical current & voltage transfer
V characteristics.
High Level - 0,5 5 4.95 Min.; 5 Typ.
V OH - 0,10 10 9.95 Min.; 10 Typ.
Noise Immunity: - AM80fT TUIPERAT\m (T... ' • 2.~·e
3.6 5 1.5 Min.; 2.25 Typ.
Inputs Low, TYPICAl. TEWPERATUR£ COEFFICIENT FOR 100 -0.3 "4l"e
V NL 7.2 - 10 3 Min.; 4.5 Typ.

V
GATE-TO-SOURCE ',(lLTAGE{VGS'ol,V
Inputs High 1.4 - 5 1.5 Min.; 2.25 Typ.
V NH 2.8 - 10 3 Min.; 4.5 Typ.
Noise Margin: 4.5 - 5 1 Min.
Inputs Low,
V NML 9 - 10 1 Min.
V
Inputs High, 0.5 - 5 1 Min.
V NMH 1 - 10 1 Min.
Output Drive ORAIN-TO-SOl.IACE VOLTAGE IVosl
Current:
N·Channel Fig. 4 - Typical n<hannel drain characteristics.
(Sink), 0.4 - 5 0.5 1 0.4 0.28 0.35 1 0.3 0.24
ION Min. 0.5 - 10 1.1 2.5 0.9 0.65 0.72 2.5 0.6 0.48
rnA NOR GATES
P-Channel DRAIN-TO-SOURCE VOLTS IVosl
(Source) : 2.5 - 5 -0.62 -2 -0.5 -0.35 -0.35 -2 -0.3 -0.24 -IS. -12.S -10 -7.S
lOP Min. 9.5 - 10 -0_62 -1 -0.5 -0.35 -0.3 -1 -0.25 -0.2 V~.voo
IIGS
"~ ) -2.'
Input Leakage
Current,
IIL,IIH
Any Input
15
±10- 5 Typ .• ±1 Max.
~A
-- '
I
OTHER GATE
INPUTS GROUNDED
VOS
-1.'
.
~
GATE TO SOURCE VOLTS ( , o-IS

-'0 ~
-12.5~
AMBIENT TEMP[RATURE ITA'o 2S"C

TYPICAL TEMPERATURE COEFFICIENT FOR 100 -0.3% I·C
Fig. 5 - Typical p-channel drain characteristics.
DRAIN-fO-SOURCE VOlTS I"'OSI
CERAMIC PACKAGES m ..... BIENT TEMPERATURE ITA' • 2.~·C

LOAO CAPACITANCE (C L). "pF
PLASTIC PACKAGES___ -10
.0
fE-fO-SOURCE VOLTAGE (YG )'I!.V
-'0
~'" .
'0
ffi
~ 7.5 '"
CERAMIC PACKAGES
P.o'-SlIC PACKAGES--- GATE -TO- SOURCE VOLTS. - 15
I
2.'
25 , " 7.' 10 IZ.!I I' ~

SIJPPLY VOLTSIVool
20
DRAIN - TO - SOURCE ¥OLTAGE tyos)-'1
nCS-178"
Fig. 6 - Minimum n-channel drain characteristics. Fig. .7 - Minimum p-channel drain characteristics. Fig. 8 - Typical propagation delay time vs. V DD.
479
CD4000A,CD4001A,CD4002A, CD4025A Types
! 150
I
~~ lENT TEMII£RATUIIE IT"I- ZI'"C
~~ TEMPE_TUIII! COEFfiCIENT FOR ALL
O.S"'''C
"'WIS
~ !!~.!.~ IT"I'Z5-t
~O.~'- CCEFFICIENT FOR AU VALUES .05 =:TD~SEs,:!~~~~!}~~~I: ;POUlESC£NT [
~
I 104
;e
i
II ...
1()3 SUPf'LY VOL.T$I'" ,.1
00
'_T...... ·
II ,02
LOAD CAP/lCLTANCE ICll'I!!,F
111 CL"!iOpF---
tlCI-I71I' nCI-I77I.
Fig. 9 - TVplcal propagation delav tims .... CL· Fig. 10 - TVPical transition time or. CL. Fig. 11 - Typical dissipation characteristics.
YIID
.
Yss
INPUTS . . - - ' - - ,
"'-
V:L
'N'UTOYIIDOUTPUTS
VOO-VNH
~
l
NOTE:
V~NPUO' ; :~:,:",:':':.'
Vss
'.
TO BOTH VOD AND VsS'
TEST ANY ONE INPUT, CONNECT ALL UNUSED
Vss WITH OTHER INPUTS AT INPUTS TO EITHER
'll2cs-,r.. oo Yeo OR Vss YOO OR VSS'
Vss
II NOTE:
C04000, (04oo2,CD4025-
TEST ANY ONE INPUT WITH
Vss OTHER INPUTS AT Voo OR \Iss'
CD4ool- TEST ANY
COMBINATION Of'INPUTS.
Fig. 12 - Quiescent device current test circuit. Fig. 13 - Noise immunity test circuit. Fig. 14 - Input leakage current test circuit.
480
CD4006A Types
Features:
CMOS 18-Stage
Static Shift Register •
•
Fully static operation
Shifting rates up to 5 MHz 01 1
• Permanent register storage with clock line high or

The RCA-CD4006A types are comprised of low - - no information recirculation required 02 4
4 separate shift register sections: two sec- • Quiescent current specified to 15 V CLOCK ~
tions of four stages and two sections of five • Maximum input leakage current of 1 J.IA.
stages with an output tap at the fourth at 15 V (full package-temperature range) D. •
stage_ Each section has an independent • 1-V noise margin (full package-temper-
single-rail data path_ ature range)
A common clock signal is used for all stages_ D. •
These types are supplied in 14-lead her-
Data are shifted to the next stage on nega-
tive-going transitions of the clock_ Through metic dual-in-line ceramic packages (D and
L _ _ _-,.,! 0",
appropriate connections of inputs and out- F suffixes). 14-lead dual-in-line plastic
CD4006A Vss
puts, multiple register sections of 4, 5, 8, packages (E suffix), 14-lead ceramic flat i2CS-U049
FUNCTIONAL DIAGRAM
and 9 stages or single register sections of 10, packages (K suffix). and in chip form (H
12, 13, 14, 16, 17 and 18 stages can be suffix)_
implemented using one CD4006A package_
longer shift register sections can be assem-
bled by using more than one CD4006A_
Applications:
MAXIMUM RATINGS, Absolute-Maximum Values: • Serial shift registers
•
• Time delay circuits
STORAGE-TEMPERATURE RANGE (TSlg ) . • . • • . • • . • • • • • . . • . • • . . • • • • • . • -65 to +150 oC • Frequency division
PACKAGE TYPES D, F, K, H . . . • . . . _ •.• __ . . . . . . . . . _ . _ . _ -55 to +125°C
PACKAGETYPEE . . . . ___ . _ . • . . . . . . . . . . . ____ . . . • . . -40to+85°C
DC SUPPLY-VOLTAGE RANGE, (VDri)
(Voltages referenced to VSS Terminal)' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +15 V
FOR TA= -40 to +60 oC (PACKAGE TYPE E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
FOR TA= +60 to +8SoC (PACKAGE TYPE E) . . . . . . . . .Derate Linearly at 12 mW/oC to 200 mW
FOR TA = -55 to +100·C (PACKAGE TYPES D, F, K) •. __ • ___ • __ • _ .. _ . . . 500 mW
FOR TA = +100 to +125·C (PACKAGE TYPES D, F, K) • _. Derate Linearly at 12 mW/oC to 200 mW
DEV ICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A= FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) ......... 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . _ . -0.5 to VDO +0.5 V
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max . . . . . . . . . . . . . . . . +26SoC
RECOMMENDED OPERATING CONDITIONS at T A = 25°C, Except as Noted_

operation is always within the following ranges: CL
D"
liMITS
VDD D,F,K,H E
CHARACTERISTIC
(VI
PACKAGES Package
UNITS
,0
I... ___
-{>--D OUT
IF4'hOR
Min_ Max_ Min. Max. CL 51hSTAGE
Supply-Voltage Range (For T A = Full TRUTH TABLE FOR SHIFT REGISTER STAGE
Package· Temperature Rangel 3 12 3 12 V
0 CL' 0" I = HIGH
0= LOW
Data Setup Time, ts

5 80 - 100 - ns
0 '\. 0 IIIC = 1110 CHANGE
x = DON'T CARE
10 40 - 50 - , '\. I ... = LEvEL C~ANGE

5 500 - 830 - ns
X J NC
92C~· 17881RI
10 200 - 250 -
5 dc 1 de 0.6 MHz Fig. 1 - Logic diagram and truth table
10 dc 2.5 de 2 lone register staga).
Clock Rise and Fall Time, trCl, tfCl'

5 - 15 - 15
j.IS
10 - 5 - 5
• If more than one unit is cascaded trCL should be made less than or aqual to the sum of the transition time
and the fixed propagation delav of the output of the driving stage for the estimated capacitive load,
481
CD4006A Types
Limits at Indicated Temperature. (oel

Conditions
D, F, K, H Packages E Package
Units
Characteristic Vo VIN VOO +25 +25
-55 +125 -40 +85
(VI (VI (VI Typ. Limit Typ. Limit
Quiescent Device - - 5 0.5 0.01 0.5 30 5 0.03 5 70
Current, I L Max. -.
- 10 1 0.01 1 60 10 0.05 10 140 JJA
- - 15 25 0.5 25 1000 250 2.5 250 2500
Output Voltage:
Low-Level,
- 5 5 oTyp.; 0.05 Max.
VOL - 10 10 oTyp.; 0.05 Max. V
LOAD CAPACITANCE
High Level. - 0 5 4.95 Min.; 5 Typ. Fig. 2 - Typical propagation delay time vs.
VOH - 0 10 9.95 Min.; 10 Typ. load capacitance.
Noise Immunity:
Inputs Low,
4_2 - 5 1.5 Min.; 2.25 Typ.
VNL 9 - 10 3 Min.; 4.5 Typ_
V AM8.ENT TEUPERATUR[ tTA,oZ5"t
Inputs High, 0.8 - 5 1.5 Min.; 2.25 Typ. TYPICAL TEUPEJIATUA[ C()[FFICI[NT
VNH 1 10 3 Min.; 4.5 Typ. FOR ALL VALUES OF VDD-o.:S"./ec

Inputs Low,
VNML 9 - 10 1 Min.
V
VNMH 1 10 1 Min.
Output Drive
Current:
n-Channel 0.5 - 5 0.155 0.25 0.125 0.085 0.072 0.25 0.06 0.048
(Sinkl,
20 30 40 50 60
ION Min. LOAD CAPACITANCE ICLI-pF
0.5 - 10 0.31 0.5 0.25 0.175 0.15 0.5 0.125 0.1
Fig. 3 - Typical transition time vs. load
mA
p-Channel
(Sourcel:
4.5 - 5 -0.125 -0.15 -0.1 -0.07 -0.06 -0.15 -0.05 -0.04 capacitance.
lOP Min_ 9.5 - 10 -0.25 -0.3 ·0.2 -0.14 ·0.12 ·0.3 ·0.1 ·0.08
Input Leakage
Current. -AnllnT
- 15 ±1O- 5 Typ., ±1 Max. JJA
IIL,IIH
J
Jl ~t------<ouC?
fUr--
I IF' 4tnOR Fig. 5 - Typical output n·channel drain
I v';;l 5th STAGE) characteristics.
Cl CL I VDO
L
.~ ' ~r: 0
£\ \'ss
FROM
PREVIOUS
STAGE
(OR INPUT
IF 1st
STAGE)
kCL
i
ro;:-
1 f.-
'lvss
Oil
~~
• ALL INPUTS ARE PROTECTED
BY COSIMOS PROTECTION
NETWORK.
irs
:I hss 92CS-17894R,
Fig. 6 - Minimum output n-channel drain

characttlri$tics.
482
CD4006A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA"" 25°C, Input t r , tt =20 ns,
Cl = 15 pF, Rl = 200 kn
liMITS
TEST D,F,K,H E
CHARACTERISTIC CONDITIONS Packages Package UNITS
VDD
IV) Min, Typ, ~ax. Min. Typ. Max.
Propagation Delay Time; 5 - 250 400 - 250 500

ns
tplH ,tpHl
10 - 125 200 - 125 250
Transition Time; 5 - 250 400 - 250 500
ns
tTHl' tTlH
10 - 125 200 - 125 250 Fig. 7 - Typical output p-channBI drain
charactsristics.
Maximum Clock Input 5 1 2.5 - 0.6 2.5 - MHz
Frequency, fCL
10 2.5 5 - 2 5 -
Minimum Clock Pulse
Width, tw
5 - 200 500 - 200 830
ns
10 - 100 200 - 100 250
Clock Rise & Fall Time; 5 - - 15 - - 15
/JS
trCL, tfCl•
10 - - 5 - - 5
Minimum Data Set Up 5 - 50 80 - 50 100

ns
Time, t8
10 - 25 40 - 25 50
Average Input Data Input - 5 - - 5 - pF
Capacitance, C I
Clock Input - 30 - - 30 - pF
* If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time Fig. 8 - Minimum output p·oh.nnel drain
and tha fixad propagation delav of the output of tha driving stage for the estimated capacitive load. characteristics.
'''SIENT TEMPERATURE tT"Jo ZS"C

., ALTUM",TING ·0·
:t. ",.0"." PA
~a04
~ 103
CL.. I~"f
---C L"50"F
,.' '.' Sl.l'PU VOLTSIYooI

INPUT FREQUEtCY u40I-Hz
Fig. 10 - Typical clock input frequency vs.
Fig. 9 - Typical dissipation characteristics. supply volraga.
o
Vss
INPUTS
VOO-VNH 'NPUTOV'"'OUTPUTS
"'-- ~
Y~ ~ Voo INPUOS
Voo NorE'
""YE: '----0--- MEASURE INPUTS
TEST ANY ONE INPUT, o ~ SEQUENTIALLY,
Vss WITH ontER INPUTS AT
Vss TO BOTH VDD AND Yss'
nCS.Z'400 Voo ORVss'
CONNECT AU UNUSED
INPUTS TO EITHER
VDD ORVSS'
Vss
V55
92C5-2740.
Fig. 11 - Qu;escent-de.,iclI-current test circuit. Fig. 12 - Noise-immunity test circuit. Fig. 13 - Input-leakage-current test circuit.
)
483
CD4007 A Types
CMOS These types are supplied in 14-lead her-

metic dual-in-line ceramic packages (D and
F suffixes). 14-lead dual-in-line plastic
Dual Complementary packages (E suffix). 14-lead ceramic flat
Pair Plus Inverter packages (K suffix). and in chip form (H
suffix).
The RCA-CD4007 A types are comprised of Features:
three n·channel and three p·channel enhance·
• Medium-speed operation.
ment·type MOS transistors. The transistor
elements are accessible through the package tPHL = tPLH = 20 ns (typ.) at CL = 15 pF,
'li!.CS- 2:503~
terminals to provide a convenient means for +VDD = 10 V
constructing the various typical circuits as • Low "high" and "low" output impedance.
Terminal No.14 - VDD
shown in Fig. 2. 500 n (typ.) at VDD - VSS = 10 V
Terminal No. 7 - VSS
• Quiescent current specified to 15 V
More complex functions are possible using
CD4007A
multiple packages. Numbers shown in paren· • Maximum input leakage current of 1/JA
SCHEMATIC DIAGRAM
theses indicate terminals that are connected at 15 V (full package-temperature range)
together to form the various configurations • 1-V noise margin (full package-temper-
listed. ature range)

STORAGE·TEMPERATURE RANGE IT"gl
OPERATING· TEMPERATURE RANGE ITAI
ADD
PACKAGE TYPES D. F. K. H -55 to +125 0 C
*A~IN~
PACKAGE TYPE E -40 to +85 0 C
DCSUPPLY·VOLTAGE RANGE. IVDDI
(Voltages referenced to VSS Terminal) . -0.5 to +15 V
PROTECTED BY Vss
POWER DISSIPATION PER PACKAGE IPDI COSI MOS PROTECTION
NETWORK
FOR'T A = -4010 +SOoC IPACKAGE TYPE E I 500mW
FOR TA = +6010 +85 0C (PACKAGE TYPE E I Derate Linearly at 12 mW/oC to 200 mW
FOR T A = -5510 +IOOoe IPACKAGE TYPES D. F. K) 500 mW
FOR TA = +10010 +12SoC IPACKAGE TYPESD,F,K) Derate Linearly at 12 mW/oC to 200 mW Applications:
• Extremely high-input impedance amplifiers
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . 100 mW
INPUT VOLTAGE' RANGE. ALL INPUTS --0.5 to V DD +0.5 V • Shapers
LEAD TEMPERATURE lOURING SOLDERING} • Inverters
At distance 1/16 f 1/32 Inch 1159 ± 0.79 mm) from case for 105 max +265 0 C • Threshold detector
RECOMMENDED OPERATING CONDITIONS • Linear amplifiers
.....IENT TfllJlt:ftATURE
operation is always within the following ranges: IT.. l-ZS·C
Y VOLTI(\Ioo'.I'
LIMITS
12.5
D. F. K. H E
Packages Package
Min. Max. Min. Max.
3 12 3 12 V f"
Package Temperature Range)
,.•
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 250 C. Input t r , tf = 20 ns, CL = 15 pF, 75 10 12: 5 15
INPUT VOLTS lVI'
RL = 200 kH
Fig4 1 - Minimum and maximum voltage.transfer
LIMITS characteristics for inverter.
CHARACTERISTIC TEST CONDITIONS D.F.K.H E UNITS

rvoo ..
AMBIENT T[MPfRATUA£ IT..,· 25-e
Packages Package
PPLT VOLTS I ,. I
(V) Min. Typ. Max. Min. Typ. Max.
Propagation Delay
Time;
5 35 60 - 35 75
Il!'
,.
10 20 40 20 50
tPLH. tPHL
Transition Time; 5 - 50 75 50 100

tTHL. tTLH 10 30 40 30 50
IlS
,.
-Average Input
AllY Illput 5 5 pF Z5 T.' 10 12:.5 15
Capacitance, CI INPUT VOLTS lVI'
Fig. 2 - Typical current and voltage-transfer

characteristics for inverter.
484
CD4007A Types
Limits at Indicated Temperatures (OC)

Conditions
Characterinic o,F,K,H Packages E Package
Units
Vo VIN VOO -55 +25 +125 --40 +25 +85
(V) (V) (V) Typ. Limit Typ. Limit
Quiescent Device - - 5 0.05 0.001 0.05 3 0.5 0.005 0.5 15
Current: - - 10 0.1 0.001 0.1 6 1 0.005 1 30 J.1.A
IL Max. 15 2 0.02 2 40 50 0.5 50 500
Output Voltage
Low Level
- 5 5 o Typ.; 0.05 Max.
VOL
- 10 10 o Typ.; 0.05 Max.
V
High Level - 0 5 4.95 Min.; 5 Typ. Fig. 3 - Typical voltage-transfer characteristics
VOH - 0 10 9.95 Min.; 10 Typ. for NAND gate.
Noise Immunity:
3.6 - 5 1.5 Min.; 2.25 Typ.
Inputs Low
7.2 - 10 3 Min.; 4.5 Typ.
VNL
Inputs High - V
1.4 5 1.5 Min.; 2.25 Typ.
VNH 2.8 - 10 3 Min.; 4.5 Typ.
Noise Margin:
4.5 - 5 1 Min.
•
Inputs Low
9 10 1 Min.
VNML
V
Inputs High 0.5 - 5 1 Min.
VNMH 1 - 10 1 Min.
Output Drive
Current:
N·Channel
(Sink) g0.5 VI= 5
10
0.75
1.6
1
2.5
0.6
1.3
0.4
0.95
0.35
1.2
1
2.5
0.3
1
0.24
0.8
VDD
IDN Min.
rnA
P·Channel
(Source) : 2.5 t VI= 5 -1.75 -4 -1.4 -1 -1.3 -4 -1.1 -0.9 Fig. 4 - Tvpical voltage-transfer characteristics
lOP Min. VDD '9.5 10 1.35 2.5 1.1 -0.75 -0.65 -2.5 -0.55 -0.45 for NOR gate.
I nput Leakage
Any Input
Current:
IIL,IIH -I - 115 ±1 0- 5 Typ., ±1 Max. J.1.A
*Maximum noise-free low-level bipolar output voltage. tMinimum noise-free high-level bipolar output voltage.
DRAIN - TO - sounCE VOLTS evos. AMBIENT TEr.lPERATURE ITA" 25'C
-t5 -12.5 10 7.!I -!I -2.' TYPICAL TEIoFERATURE COEFFICIENT FOR 10' -03% /'C
'"I
}
DO
to t
-. -. ATE-TO- sOURCE VOLTS 'YoS!'1
1,lJ~ Ves -10 :
-2iJ
VGS
~-
TERM. [14 TO GND.
CONN. 7 TO ,
OAll- TO - 5OLRC( VOLTS !Vasl • - I!I

CERAMIC PACKAGES
PLASTIC PACKAGrs- -
AMBIENT TEUP£RATUAt: IT"I • 2!1"'C

TYPICM. TEMPE~"'T\JRE COEFFICIENT FOIl! IO • - 0.3'" I"'C
;),
7,5 to 125 15
llttltllW
DRAIN - TO - SOURCE VOLTS IVosl
Fig. 5 - Minimum output p·channel drain Fig. 6 - Typical output p·channel drain Fig. 7 - Minimum output n-channel drain
characteristics. characteristics. characteristics_
AMSIENT TEMPERATliRE (TAl • 2~·C
]0 TEMPERATURE COEFFICIENT FOR 10' - 0 3%
l! t trFH
~
I'C8+t~
.... 'lENT T[MP[ft"TUftf I T.. l • 25'C
f IJ ~IC!!"L~EEs~"AV~~~ ~r:::~ClENT 'Oft
+HJ:tIW-::::j i 1fT :pi:l: ;:l ! 1
- HtIl;::11t1111 IUIII"'
~ 25 GATE-TO-SOURCE VOLTS (\10.,1'15 :f4-fmn~:Hf
~
"I
::I
'0
15 10-+..
-
_
.j"
1 10
5 I
~ '0 uJ~ 'os
, ~~~
TERIoIJ 7 TO GNO
CONN ll4 TO 3
DRAIN - TO - SOURCE VOLTS IVOS) INPUT VOI..TAG( 1Vrl-V " CAPACITANCE ICLI- pF
Fig. 8 - Typical output n·channel drain Fig. 9 - Typical voltage-transfer characteristics as a Fig. 10 - Typical propagation·delay tima vs. load
characteristics. function of temperature. capacitance.
485
CD4007 A Types
:; :::; lU H III J~O

""IENT T[WEftAruMIT"loU"C
LOlD CAPACITANCE lel,o",'
,I~: •
::li
I
(D4OO,.,
HH" ....
.". .. CD;oo;:r
I ,
.. . .... fiiITiiil II
20504050607010
CA'ACITAMCE le L 1- pF SUPPLY
'0
va.'s "
I\lDOI
••
Fig. 11 - Tvpical transition time VS. Fig. 12 - Maximum propagation-delay time Fig. 13 - Typical dissipation characteristics.
load capacitance. VI. supply vo/rage.
(14,2,11); (8,13);
(1,12,13); (2,14,111;
(1,5); (7.4,9) (13,2); (1,11); (4,8); (5,9)
(12,5,8); (7.4,9)
a) Triple Inverters b) 3-lnput NOR Gate c) 3-lnput NAND Gate

(13,12,5); (4,9,8);
(14,2); (1,11) (6,3,10); (8.5,12);
(11,14); (7,4,9)
(6,3,10); (13,1,12);
(OPTIONAL "DO PULL-UP) (14,2,11); (7,9)
eo
t---+--+--<!!OU1s:'
c
OUT
c~~---------1f----1
A
Y _. OUT Ivoo,oa.ii
MIVsS'oC".ce
• ALL "UNIT SUBSTRATES ~vss
ARE COHN£C:TEO TO VOD
AlL N-","IT SuBSTRATES I-*-
ARE CONNECTED TO Vss
~Vss
(OPTIONAL "SSPULL-DOWN)
92CS-I!)!27
d) Tree (Relay) Logic e) High Sink·Current Driver f) High Source-Current Driver
J-r:;:-~f-c-f---,II--JO
1'-_ I~ ,riJ:,®-t-----1
'~d~O-{>
-¥--~---~ (1,5,12);(2,9);
(11,4); (8,13,10);
(6,3,10); (14,2,11); v" (6,3)
(7.4,9); (13,8,1,5,12)
h) Dual Bi-Directional Transmission Gating
g) High Sink- and Source-Current Driver
Fig. 14 - Sample COS/MOS logic cirr:uit arrangements using type CD4007A.
"DO
•..,un
"CS-2"'4! "ssne'-INO!
Fig. 15 - Noise-immunity test cirr:uit. Fig. 16 - Ouiescent-dtJvice-currenttestcirr:uit Fig. 17 - Input-leekage-current test circuit
486
CD4008A Types
Features:
CMOS 4-Bit Full Adder
• 4 sum outputs plus parallel look-ahead carry-output
With Parallel Carry Out
Applications • Quiescent current specified to 15 V
• Maximum input leakage of 1 jJ.A at 15 V
The RCA-CD4008A types consist of four (full package-temperature range)
• 6inary addition/arithmetic units
full-adder stages with fast look-ahead carry • l-V. noise margin (full package-temperature
provision from stage to stage_ Circuitry is in- range)
cluded to provide a fast "parallel-carry-out"
MAXIMUM RATINGS, Absolut!l-Maximum Values:
bit to permit high-speed operation in arith-
metic sections using several CD400SA's_ STORAGE·TEMPERATURE RANGE (T5Ig)' . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150 oC
CD4008A inputs include the four sets of bits OPERATING-TEMPERATURE RANGE (TA):
to be added, A1 to A4 and 61 to 64, in ad- PACKAGE TYPES D, F. K. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 to +125:C
dition to the "Carry In" bit from a previous PACKAGE TYPE E . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85 C
section_ CD400SA outputs include the four DC SUPPLY-VOLTAGE RANGE, (VDD)
sum bits, 51 and 54, in addition to the high- (Voltages referenced tD VSS Terminal): . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +15 V
speed "parallel-carry-out" which may be POWER DISSIPATION PER PACKAGE (POl:
utilized at a succeedin!l CD4008A section_ FOR T A = -40 to +60:C (PACKAGE TYPE E) . . . . . . _ ... '.' . . . . . . . . . ;" .. 500 mW
FOR TA = +60 to +85 C IPACKAGE TYPE E) . . . . . . Derate Linearly at 12 mWI C to 200 mW
FORTA =-5510+100·C(PACKAGETYPESD,F,K) .,. _ . . . . . . . . . . . . . . • . . . 500mW
metic dual-in-line ceramic packages (D and
FOR T A = +100 10 +125° (PACKAGE TYPES D. F. K) ., .Derate Linearly at 12 mW/oC to 200 mW
F suffixes), 16-lead dual-in-line plastic
packages (E suffix). 16-lead ceramic flat
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) . . . . . . . lOa mW
INPUT VOLTAGE RANGE. ALL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0_5 V
suffix). LEAD TEMPERATURE (DURING SOLDERING):
Conditions
At distance 1116 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max . . . . . . . . . . • . . . +265 0 C
Limits at Indicated Temperatures (oCI RECOMMENDED OPERATING CONDITIONS

I
I D, F, K. H Packages E Package
Characteristic Units conditions should be selected so that opera-
Vo VIN VDD -55 +25 +25 tion is always within the following ranges.
+125 -40 +85
(V) (V) (VI Typ. Limit Typ. Limit
Characteristic Min_ Max. Units
Qu ieseent Device - - 5 5 0.3 5 300 50 0.5 50 700
Current,1 L Max. - - 10 10 0.5 10 600 500 1 100 1400 jJ.A Supply-Voltage Range
(TA; Full Package- 3 12 V
- - 15 50 1 50 2000 500 5 500 5000
Temp. Range)
Output Voltage: - 0,5 5 o Typ.; 0.05 Max.
low-level,
VOL - 0,10 10 o Typ.; 0.05 Max. V
High level, - 0,5 5 4.95 Min.; 5 Typ.
VOH - 0,10 10 9.95 Min.; 10 Tvp.
Noise Immunity: 4.2 - 5 1.5 Min.; 2.25 Typ.
Inputs low,
VNl 9 - 10 3 Min.; 4.5 TVp. "
"" rl'"
V
Inputs High, O.S - 5 1.5 Min.; 2.25 Typ.
VNH 1 - 10 3 Min.; 4.5 Typ.
Noise Margin: 4_5 - 5 1 Min_
()!.~-------' .~ ':~SS
Inputs low,
VNMl 9 - 10 1 Min.
V
VNMH 1 - 10 1 Min.
Output Drive
· 0.5 - 5 0.31 0.5 0.25 0.175 0.155 0_5 0.13 0.105
VDD"·
v•• ,.
PROTECTEO BY
COS/MaS PROTECTION
Current:
n-Channel
(Sink),
·
...
0.5
3
-
-
10
5
0.93 1.5 0.75 0.53
0.012 0_2 0,01 0.007 0.009
0.6 1.5
0.2
0.5 0_4
0.007 0.005
NETWORK
Fig. 1 - CD400BA logic diBgram.
92C5- 25077R2'
TRUTH TABLE
IDN Min.
... 3 - 10 0.31 0.5 0.25 0.175 0_24 0.5 0.2 0.16 C1 Co SUM
·· mA Ai Bi
p-Channel
4_5 - 5 -0.31 -0.5 -0.25 -0.175 ·0.155 -0_5 -0.13 -0.105
a
a 0 0 0
(Source), 9_5 - 10 -0.93 -1.5 -0.75 -0.53 -0.6 -1.5 -0.5 -0.4 a a
IDPMin. ... 2 - 5 -0.01 -0.2 -0.01 -0.007 -0.008 -0.2 -0.007 -0_005
1
a 1
0
0 a
1
1
... 7 - 10 -0.185 -0.3 -0.15 -0.105 -0.12 -0.3 -0.1 -O.OS 1 I a 1 a
Input leakage a Q 1 a I
Any 1 a 1 I 0
Current, 15 ±10-5 Typ.; ±1 Max. jJ.A
Input a 1 1 1 0
Ill, IIH Max.
1 1 I I I
* Carry Output "'Sum Output
487
CD4008A Types
DYNAMIC ELECTRiCAL CHARACTERISTICS at TA =25°C; Input t r• tf =20 ns. CL =15 pF. AM81ENT TEMPERATURE ITAI02~'C
I- TYPICAL TEMPERATURE COEFFICIENT
RL = 200 Kf! ±=t:-:c±:-:ci
i·""" ,., . .
?i! 600 FOR "'LL ...... LUES OF "'0000' "'·C
LIMITS ~booo '1 :::: ::::\:: :: 1:::

I·':t:'· ,.;:::.
VDD D,F,-K,H E ~ + : tIP :i~~t:L~'''OL~~r:::
(V) Packages Package -~ 'u' i" :::. ::
Typ. Max. Typ. Max. ~;;.
~~
500
200
t.~ I;;: ~:::
:-tP: ;:::
Propagation Delay Time: tpHL' tPLH 5 900 1300 900 2000 eo'' ' ....
..
"'-I~"'"
ns
Sum In to Sum Out 10 325 500 325 650 z .... tOO
'~' ......
5 900 1300 900 2000
~ ~o
r t:E ::::
6Cl~10'0
::H
Carry In to Sum Out ns 30 40
10 325 500 325 650 LOAOC ... PACITANCE ICLI-pF
Sum In to Carry Out 5 320 600 320 800 ns

Fig. 2 - Typical sum-in to carry out propagation
10 120 200 120 240 delay time vs. CL.
Carry In to Carry Out

5 100 175 100 200 ns
10 45 75 45 90
Transition Time: tTHL' tTLH 5 1250 2200 1250 2900 ns
At Sum Outputs 10 550 900 550 1100
At Carry Output 5 125 225 125 290 ns
10 45 75 45 90
Input Capacitance, CI
(Any Input)
- 10 - 10 - pF
~-o~06Cl
LOAD CAl'lflCITANCE ICLI- pF
Fig. 3 - Typical sum·in or carry-in to sum-out

propagation delay time vs. CL'
"".fNT TEMPE"ATURE ITAI.2~·C

..",tENT TEMPEftATURE (TAl. 2!5"C L.OAO CAPACITANCE ICL)·'5 pF
TYPICAL TEMP£RATUAE COEFFICIENT
fOt! ALL VALUES OF VOo"O;'"4'"C
LOAD C... PACITANCE tcLJol~pF

--CL·~OpF
, I I In
30 40 50 60 10 ., 20 102 10' '0'
LOAD CAPACITA..a: ICLI-pF SUPPLY VOLTS {V oo ' INPUT FREQUENCY tf",l-kHI
Fig. 4 - Typical carry-in to carry-out propagation Fig. 5 - Typical maximum propagation delay time
deray time VS. CL , vs. V DO for carry-in to carry-out.
A",. {
813-16
INPUTS , - - ' - - - ,
o A9_" {
89-12
''''
Fig. 8 - Noise immunity test circuit.
'~"U~'J'OO :~ ~u" ONM'

As-a{
Bs-a }S,-a
o ~ SEQUENTIAllY,
A,_. [
\Iss TO 80TH Vco lHOVSS
CONNECT All UHUSro
8.·4 }SH
___ IHPI./TSTO[ITH(It
vOD OR "ss
Fig. 7 - Quiescent device current test circuit. 'ss Vss
Fig. 9 - Input leakage current test circuit. Fig. 10 - Typical connection for a 16·bit adder.
488
CD4009A, CD4010A Types
CMOS ~2~
A~G.A
Hex Buffers/Converters
Inverting Type: CD4009A
Non-Inverting Type: CD4010A ~,~.
(~"C
~6~
e~,.e
r--~-.VDO ~,
O~J.o
f'...... 'U~ -
The RCA-Co4009A and Co4010A Hex
Buffer/Converters may be used as CDS/MaS
to TTL or oTL logic-level converters or
I. .,
o-+-'VI!'V-""'.,..GATES
HCoJ]
CMOS high sink-current drivers. . "ss Vee: o--L
ALL INPUTS ARE PROTECTED BY vsso-.! Ne~
The Co4049A and Co4050A are preferred COS/MOS PROTECTION NETWORK.
\/DOo.1!
hex buffer replacements for the Co4009A 92C5-22887AI Veeo--..!.
and Co4010A, respectively, in all applica-
tions except multiplexers. For applications
CD4009A Vsso--.!
VDD~
~
4
F L 'F
..
Features: I2SS·4142"~
not requiring high sink current or voltage CD4010A

conversion, the Co4069B Hex Inverter is • Quiescent current specified to 15 V
Fig. 1 - Logic diagrams.
recommended. • Maximum input feakage of 1 p.A at 15 V
(full package-temperature range)
These types are supplied In 16-lead hermetic • High sink current for driving 2 TTL loads
dual-in-line ceramic packages (0 and F • High-to-Iow level logic conversion A.a".T TE.PERAro. .,,-c MAX.
Applications:
age (E suffix), 16-lead ceramic flat packages
• CMOS to DTLmL hex converter
~
I
~g~tTlD": "C~'5\
• CMOS current "sink" or "source" driver
• CMOS hlgh-to-Iow logic-level converter
• Multiplexer - 1 to 6 or 6 to 1

LIMITS
CHARACTERISTIC UNITS Fig. 2 - Minimum & maximum voltage transfer
Min. Max. characteristics - CD4009A.
Temperature Range: Voo, Vce) 3 12 V
Input Voltage Range (VI) Vec· 12 V
• The C04009 and CD4010 have high-ta-Iow level voltage conversion capability but not low-ta-high level,
therefore it is recommended that Vee;;;' VI ;;;. Vee.
...
INPUT VOUS t~11

as function of temp. - CD4009A.
""SIUtTTEMP[RATUR£ tTAI'ii!~C ":t:"!f;~"

COL.LECTOA SUPPL'W vOUAGE IVcd'SII .j.~:;f:::;fl!::
ORAIII SUPPLY ~OLT"GE I~D ,. 5y~, '>:1".11"
r;Lf .~.T_'" 1,.1
.!~.. ..
1"'
t' •
,
IN~UT
.,
VOLTS 1\\ I
Fig. 4 - Minimum & maximum voltage transfer Fig. 5 - Minimum & maximum voltage transfer Fig. 6 - Minimum & maximum flo/tage transfer
characteristics (VDD = 5) - CD4010A. characteristics (V DD = 10) - CD4010A. characteristics (VDD = 15) - CD4010A.
489
Limits at Indicated Temperature. (oC)
Condition.
0, F, K, H Packages E Psckage
Vo VIN VCC· +25 +25
(V) (VI (V)
-55 +125 -40 +85
Typ. Limit Typ. Limit
Current,l L Max. - - 10 0.5 0.01 0.5 30 5 0.05 5 70 ~
- - 15 10 0.02 10 100 50 0.5 50 500
.
Output Voltage:
Low· Level ,
- 0,5 5 oTyp.; 0.05 Max.
VOL - 0,10 10 oTyp.; 0.05 Max. V
IMP'UT¥CIlTl"'11 ....._
High Level - 0,5 5 4.95 Min.; 5 Typ. Fig. 7 - Typical voltaga tran,"r characteri.tic.
VOH - 0,10 10 9.95 Min.; 10 Typ. .. a' function of tlJmporatJJfB - C040 'OA.
Noise Immunity:
Inputs Low, 3.6 - 5 1.5 Min.; 2.25 Typ.
"'''.'T~
~.
VNL
C04010A 7.2 - 10 3 Min.; 4.5 Typ.
lil
-
~.
Inputs High 1.4 5 1.5 Min.; 2.25 Typ.
VNH V
All Types 2.8 - 10 3 Min.; 4.5 Typ.
Inputs Low, 3.6 - 5 1 Min.; 1.5 Typ.
I.,e
VNL i ';P~I
C04009A 7.2 - 10 2 Min.; 3 Typ.
Noise Margin:
Inputs Low, 4.5 - 5 1 Min.
SUPPLY VOLTS Woo' Veel
VNML
Fig. 8 - Maximum propagation dalay tim. v..
C04010A 9 - 10 1 Min.
V VOO - C040'OA.
Inputs High,
VNMH
0.5 - 5 1 Min.
C04010A 1 - 10 1 Min.
Output Orive
Current:
N-Channel 0.4 - 5 3.75 4 3 2.1 3.6 4 3 2.4
(Sink),
ION Min. 0.5 - 10 10 10 8 5.6 9.6 10 8 6.4
mA
P-Channel 4.6 - 5 -0.31 -0.5 -0.25 -0.175 ·0.3 ·0.5 -0.25 -0.2
(Source),
lOP Min.
2.5 - 5 -1.85 -1.75 -1.25 ·0.9 -1.5 ·1.75 -1.25 -1
9.5 - 10 ·0.9 -0.8 -0.6 ·0.4 ·0.72 -0.8 -0.6 -0.48
I nput Leakage
Current, Any Input 15 ±10-5 Typ.; ±1 Max. ~
IIL,IIH
Fig. 9 - Typical n-channel drain characteristics.
'Vcc=Voo
,.
ORAIN-TO-SOURCE VOLTS 1VosJ
I2C5-1787.
Fig. 11 - Typical high·to·low 10 vel propagation Fig. 12 - Typicallow·to-high I.vol propagation
Fig. 10 - Minimum n"l:hannfll drain
dB/ay time vs. CL" delay tima v.. CL'
characteristics.
490
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25°C; Input tr ,tf =20 ns, CL = 15 pF,
RL =200 Kn
CONDITION LIMIT
VDD V, Vee Typ. Max.
(VI (VI (VI
D, F, K; H Packages
5 5 5 50 80
Propagation Delav Time:
10 10 10 25 55
Low·to-High, tpLH
10 10 5 15 30
ns
5 5 5 15 55 Fig_ 13 - Typical high-to-Iow Isvel propagation
delay time VI. CL (driving TTL, OTLI.
High-to-Low, tpHL 10 10 10 10 30
10 10 5 10 25

Low-to-High, ~LH
10 10 10 50 100
ns
5 5 5 20 45
•
High-to-Low, tTHL
10 10 10 16 40
Input Capacitance, C,
CD4009A
- - - 15 - pF
CD4010A - - - 5 -
E Package
5 5 5 50 100 LOAD CAPACITANCE ICLI-,F

Fig_ 14 - Typical low-to-high level propagation
Low-to-high, tpLH 10 10 10 25 70 delay time VI. CL (driving TTL. 0 TLI
10 10 5 15 40
ns
5 5 5 15 70
High-to-Low, tpHL 10 10 10 10 40
10 10 5 10 35
Low-to-High, tpLH
10 10 10 50 120
ns
5 5 5 20 60
High-to-Low, tTHL
10 10 10 16 50
Input Capacitance, C,
CD4009A
- - - 15 - pF 100
~D4010A - - - 5 - LOAD CAPACITANCE ICL)- "

tlCI· .., . "
Fig. 15 - Typical high-to-Iow "'vel transition titH

VI. CL'
; ~~.:. ~~.!'!':~ ~ :';~ ~ ,,-
f ' ,~L:
I .~,
i, ,~
ii,;
,':<:':'
I
ISO 10 100
CAPl'CITANC[ ICll-pF 92(S-178'1
Fig_ 16'- Typicallow-to-high level tranlition time

,,,"PLY I ;LTSI ).~~
Fig_ 17 - Maximum propagation dlJlay tims VI.
4 ' 1 10 2 2 4' I,b,
INPUT FREQUENCY II., Uti
2 ... <0
VI. CL- VOO - C04009A. Fig. 78 - Typical dissipation characteristics.
491
CD4011A, CD4012A, CD4023A Types
CMOS NAND Gates

Features:
Quad 2 Input - CD4011A
Dual 4 Input - CD4012A
Triple 3 Input - CD4023A
• Maximum input leakage of 1 J.IA at 15 V
(full package-temperature range)
The RCA-CD4011A. CD401.2A. and CD- • 1-V noise margin (full package-temperature
4023A NAND gates provide the system range)
designer with direct implementation of the
NAND function and supplement the existing RECOMMENDED OPERATING CONDITIONS
family of CMOS gates. For meximum reliability. nominal operating

conditions should be selected so
that opera- '92CS-2476J
tion is always within the following ranges: CD4011A

metic dual-in-line ceramic packages (0 and
F suffixes). 14-lead dual-in-line plastic Characteristic Min_ Mex_ Units
packages (E suffix). 14-lead ceramic flat SupplV Voltage Range
packages (K suffix). and in chip form (H (over full package 3 12 V
suffix). temperature range)
STORAGE-TEMPERATURE RANGE (Tstgl . . . . • . . . • • • • • . • . . . • • . . • • • . • -65 to + 150°C

He
OPERATING·TEMPERATURE RANGE (TAl: °
PACKAGE TYPES D. F. K. H . . . . . • . . • • . . . • • . . . • . • • . • . . . •-55 to +125 C
'ss Nt
PACKAGE TYPE E . . . . . . • • . • . . . . . . . . . . . • • . . • . . . . • . . • . • • . -40 to +85 0 C
'92CS-Z47S'J
DC SUPPLY-VOLTAGE RANGE. (VDDI
CD4012A
(Voltages referenced to VSS Terminal!: . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PDI:
FOR TA = -40 to +60 oC (PACKAGE TYPE E I . . . • . . . . . . . . . . . . . • . 500 mW
FOR TA = +60 to +85 0 C (PACKAGE TYPE E I . . . . • . Derat. Linearly at 12 mW/C to 200 mW
FOR TA= -55 to +l00'C (PACKAGE TYPES D. F. KI . . . . . • • • . . . • . • . . . . • . . • 5OOmW
FOR T A = +100 to +1 25'C (PACKAGE TYPES D. F. K) ... Derate Linearly at 12 mW/oC to 200 mW
FOR T A = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . • . • . . . 100 mW
INPUT VOLTAGE RANGE_ ALL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING);
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mml.from case for 105 max . . . . . . . . . . • • . . +265 0 C
SUPPLY VOl.TAGE
.IYoD'-ISV
CD4023AH
Fig. 1 - Functional diagrams.
o-+-'11',"""+j~ GATES
.." 'N
ALL INPUTS ARE PROTECTED BY
0'
'55
COSI MOS PROTECTION NETWORK.
10 15 92cs-22Se7i'f1
INPUT VOLTAGE IVII-V
"It-
Fig. 2 - Minimum & moximum tlD/loge tran.for Fig_ 3 - Typical tlDltagtl t,an.fer eharactllri.tic.
chBl7ICteristics. 8$ a function of tempsrBtulll.
ANIIENT TEMPERATURE (TA) • 2S-C AM81ENT TEMPERATUREITAI" ZS"C I~OO

TYPICAL TEMPERATURE COEFFIClENT 14
"SUPPLY'OLTS""'-:", o ~ ~
"~F~"'~'~O~.-~O·i'''I/~·CIIIII~VGS . , os
I V
I
Ilo~I~IA;T~."EI-~Tlo~:~ISO"i~u';R<~El,o~LTlsl"IGSI;ICI:·; ,!.t~ :~HE~R~ ~:o; :-'~l

~125 b
i 10
10 • c
7.5 a b
' .. i
j
z
~
~~NSeE~
2.5
1'1 INPUT
b'2 INPUTS
C" INPUTS
Ci
~.
10
} C040IlAD,AE,AF,AK
CD4023AO,AE,AF, AI(
4-4 INPUTS
~,
'AU.., OTHE,!-}~~T~ ~o VaD 5 m10
~ ___ ~LCD4012AD,AE,AF.AK
2.' 1.5 10 12.S 15 5 10 15

INPUT VOlTS (VII DRAIN - TO -SOURCE VOLTS tVes}
Fig. 4 - Typical multiple input switching transfer Fig. 5 - Typical eummt & IIOlt. trllTl.f"
characteristics for CD4012A.
Fig. 6 - Typical n-channei drain characteristics.
characteristics.
492
STATIC ELECTRICAL CHARACTERISTICS DRAIN- TO- SCUIC[ VOLTAGE (Yos)-V
Limits at Indicatad Temperature. (oCI OY
Chlractllriltic
Conditions
D,F,K,HPackages E PIICkage
Units y~.".'D I~
I VDS 10V
Vo VIN VDD -55 +25 +25 +85
+125 -40 -----~
(V) (V) (V) Typ. Limit Typ. Limit OTHER WI:
INPUTS GROUNDED
au iescent Dev ice - 5 0.05 0.001 0.05 - 3 0.5 0.005 0.5 15

Current. IL Max. -
10 0.1 0.001 0.1 - 6 5 0.005 5 30 jlA
- -
Output Voltage:
Low· Level
0,5
15
5 -
2 0.02 2
o
40
Typ.;
50
0.05
0.5
Max.
50 500
.... [NT T[IIIP[RATUM IT... I -zs-c
TYPICAL. TE .. P. COEFFICIENT ...T "'1.1. VAl..UES Of VGS. ·o.l'Xo/-C
.
VOL - 0,10 10 o Typ.; 0.05 Max.
V
High Level, - 0,5 5 4.95 Min.; 5 Typ. Fig. 7 - Typical p-chann,1 drain charactsrl,ticl.
VOH - 0,10 10 9.95 Min.; 10 Typ.
Noise Immunity:
Inputs Low,
3.6 - 5 1.5 Min.; 2.25 Typ.
VNL 7.2 - 10 3 Min.; 4.5 Typ.

V
Inputs High, 1.4 - 5 1.5 Min.; 2.25 Typ.;
VNH 2.8 - 10 3 Min.; 4.5 Typ.
•
Noise Margin:
Inputs Low,
4.5 - 5 1 Min.
VNML 9 - 10 1 Min.
V
VNMH 1 - 10 1 Min.
Output Drive
Current:
N·Channel
(Sink) Fig. 8 - Minimum n-chann,1 drain charactflristics
ION Min. -CD4011A & CD4023A.
0.5 - 5 0.31 0.5 0.25 0.175 0.145 0.5 0.12. 0.095
C04011A
C04023A 0.5 - 10 0.62 0.6 0.5 0.35 0.3 0.6 0.25 0.2
C04012A 0.5 - 5 0.15 0.25 0.12 0.085 0.072 0.25 0.06 0.05
mA
0.5 - 10 0.31 0.6 0.25 0.175 0.155 0.6 0.13 0.105
P·Channel
(Source),
lOP Min.
4.5 - 5 ·0.31 ·0.5 ·0.25 ·0.175 ·0.145 ·0.5 ·0.12 0.095
All Types 9.5 - 10 ·0.75 ·1.2 ·0.6 ·0.4 ·0.35 ·1.2 ·0.3 ·0.24
Input Leakage Any
Current, 15 ±lo-5 Typ.; ±1 Max. jlA
Input
IIL,IIH
OR ... IN·TO-SOURCE VOLTS IVDS'
Fig. 9 - Minimum n-channel drain character·

istics.
DRAIN - TO-SOURCE VOlTAGE (Vosl-V "M8IENT TEMPERATURE (TAl 0 2"C ...... IENT TE .. PER"'TURE IT... ). 2S-C
-I!t -10 -~ I TYPICAL
"'''.IENT TUIP£RA'URl IT"I' 2S-C
TYPICAL TEMPERATURE COEFFICIENT
= I~ FOR
I
TEMPERATURE COEFFICIENT
ALL VALUES OF "co" 0 3'1.t-c I 300
TYPICAL TE.. PERATURE COEfFICIENT
fOR ALL VALUES OF VOO ·O.:l'Ir./-c
FOR 10"·O.' .. ,'"C lOY
lOY :~ =1
'OY -, 1100
! 100
GATE-TO-SOURCEVOLTAGEt I-I!! II
SUPPLY VOLTS IYDO)O!!
i SUPPLY VOLTS 'Y
-'0
10
"
10205040:1060 1010504015015070150
LOAD CAPAClTAHCE t t l 1 - pF !t2CS-171t4 LOAD CAP...CIT... NCE: (CLI- pf ~2c5.nn5
Fig. 10 - Minimum p-channel drain Fig. 11 - Typicallow-to·high level propagetion Fig. 12 - Typical high·to·/ow level propagation
charactBristics. delay time vs. CL. dalay tima vs. CL - CD4011A, &
CD4023A.
493
DYNAMIC ELECTRICAL CHARACTERISTICS at TA" 26°C, CL -16 pF,lnput tr, tf-20 nl,
RL-ZOOKSl
TEST LIMITS
CONDITIONS D,F,k,H E
CHARACTERISTICS Packages Pack.,. UNITS
VDD
Typ. MIX. Typ. MIX.
IVI
Propagation Delay Time: 6 60 75 50 100
ns .0
Low-to-High Level, tpLH TO
10 26 40 26 60
High-to-Low Level, tpHL 6 60 76 60 100 Fig. 13 - Typical high-to-Iow le ••1propagation
ns
CD4011 A and CD4023A del.y time .s. CL - CD4012A.
10 25 40 26 60
6 100 160 100 200
CD4012A ns
10 50 75 50 100
Low-ta-High Level, tyLH ns
10 40 60 40 76
High-to-Low Level, tyHL 5 76 125 76 150
ns
CD4011A and CD4023A
10 50 75 50 100
5 250 375 250 500
CD4012A ns
10 125 200 125 250
Fig. 14 - Typical low-to-hlgh transition tim• ...
Input Capacitance, CI Any Input 5 - 6 - pF
CL'
I _N' TEIIHJtATURt IT"I' 25·C

I TYPICAl. TEMH;RATUfI( COE'FICIENT FOR
loq ILL VALlIU Of' VDO .0.,"'-<:
.~ -"f
...........
=
%
400 SUPPLY VOLTS
+ .. +
·t·· ...
........ · t
1300 +"-1Ei~
~ ':.: tti1f§f:
_,'.. ~::: :::: ~mj
~200
~ "
:m m: g~l ~i~~ ~~£1i
100
t
20 40 50 10 10 10 1020)040 "'60 1080
CAPACITANCf ICLI- II'
9lCS-1771'
lOAD CAPACITANCE lell -p' SU"I'LY VOl. TS I YooJ NCl.'......
Fig_ 15 - Typic.1 high-to-low I.vel transition Fig_ 16 - Typical high-to-low 1tJ",1 transition tim" Fig. 17 - Minimum ProPllfllltion _IllY
tim" .B. CL - C0401 IA & CD4023A. .s. CL - CD4012A. time .s.VDlJo
Yco
VDO
.... YDD~YNH INPUTavDOOUTPUTS v~NPu(Js :~:~U...NPUTS
INPUTS
SUPPl.Y VOLTSey '0' Vco
'-- ~ 0 ~ SEQUENTIALLY,
o _ Vss TO BOTH "DO AND "ss'
"Nl _ ~J;~CioAE~~=fJ)
LOAD CAPACtT ANCE leL ,ol!>pF
"T CL'~~F---
'L NOTE
TEST ANY ONE INPUT, VSS
"DO CIt Vss
VSS WITH cmt£R INPUTS AT

Vss 9:CS-zr400 "DO ORYss'
.02
~PUT FREOl£MCY(lII-Hr
Fig. 19 - Quiescent device current Fig. 21 - Input.'ea~age current
~ig. " - Typical dissipation chaf8CfBristics. test circuit. . test CIrcUit.
494
CD4013A Types
Dual 'D'-Type Flip-Flop

The RCA·C04013A consists of two identical, Setting or resetting is independent of the
independent data·type flip·flops. Each flip· clock and is accomplished by a high level
flop has independent data, set, reset, and on the set (with low·level on reset) or reset
clock inputs, and Q and Q outputs. These (with low·level on set) line, respectively.
devices can be used for shift register appli·
cations, and by connecting Q output to the These types are supplied in 14-lead her-
data input,dor counter and toggle applica· metic dual-in-line ceramic packages (0 and
tions. The logic level present at the 0 input F suffixes). 14-lead dual-in-line plastic
is transferred to the 0 output during the packages (E suffix), 14-lead ceramic flat
positive'going transition of the clock pulse. packages (K suffix). and in chip form (H
suffix).
MAXIMUM RATINGS, Absolute·Maximum Values: CD4013A

STORAGE·TEMPERATURE RANGE ITstgl FUNCTIONAL DIAGRAM
OPERATING· TEMPERATURE RANGE (TAl
PACKAGE TYPES D, F, K, H -55 to +12SoC
PACKAGE TYPE: E -40 to +8SoC Features:
DC SUPPLY·VOLTAGE RANGE. (VDDI
(Voltages referenced to V SS Termmal) . -0.5 to +15 V • Set-Reset capability
POWER DISSIPATION PER PACKAGE (POl • Static flip·flop operation - retains state indefinitely
FOR T A = -40 10 +60 0 C (PACKAGE TYPE E I 500 mW with clock level either "high" or "low"
FOR T A = +60 to +85 0 C (PACKAGE TYPE E ) Derate Linearly at 12 mW/oC to 200 mW • Medium-speed operation - 10 MHz (typ.) clock
FOR T A = -55 to +100'C (PACKAGE TYPES D, F, K)
FOR T A = +100 to +125'C (PACKAGE TYPES D, F, K) .
. .. Derate Linearly at 12 mW/oC 10
500 mW
200 mW
toggle rate at 10 V
• Maximum input leakage of 1 fJ.A at 15 V
I
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES). 100mW (full package-temperature range)
INPUT VOLTAGE RANGE. ALL INPUTS. -0.5 to V DD +0.5 V • 1-V noise margin (full package-temperature
LEAD TEMPERATURE (DURING SOLDERINGL range)
At distance 1/16 ± 1/32 Inch (1.59 ± 0.79 mm) from case for 10 s max. +265 0 C
Applications:
• Registers, counters, control circuits
" ,
'*6(81O----.--------~---___,
SET ./,',','
f •
"j'
1
I
~
,I
0 I 0
110
""'- x' 0 0 0 CHANG!
x:x»>:'
Q
"*5191 )( x 0 I I ~ 0
)( 'X'I'l'I'~
z
LOGIC o· LOW ~ 10
LOGIC I' HIGH
.... LEvEL CHANGE
X' DON'T CARE
N(Nl·FF,/FF2 TERMINAL
ASSIGNMENTS
*4 1RESET
1 0 1 O - - - - - - -..... ~~--~
~
DD
ORAIN-TO-SOURCE VOLTS (Vas) '20;;$-11800
BUFFERED OUTPuTS
1(1)) Fig.2 - Typical n·channel drain characteristics.
*.LL INPUTS ARE DRAIN - TO - SOURCE VOLTS (Vas)

140-\'00 PfIOTECTEO BY -15 -10 -5
COSI MOS PROTEC TION Vss
7 c:r \Iss NETWOAI(
Fig. 1 - Logic diagram and truth table for CD4013A (one of two identical flip flops).
Fig.3 - Typical p·channel drain characteristics.
495
CD4013A Types
RECOMMENDED OPERATING CONDITIONS at TA =25°C, Except II Noted:
For maximum reliability, nominal operating conditions shol!ld be selected so that
operation is always within the following ranges -
LIMITS
CHARACTERISTIC O,F,K,H E
UNITS
VOD Packages Package
(VI Min. Max. Min. Max.
(For T A = Full Package - 3 12 3 12 V
Temperature Rangel
Data Setup Time ts

5 40 - 50 -
10 20 - 25 - ns Fig.4 - Minimum n-channel drain characteristics.
Clock Pulse Width tw

5 200 - 500 - ns
10 80 - 100 -
DRAIN ~ TO - SOURCE VOLTS I\/OS'
Clock Input 5 2.5 1
Frequency fCL 10 dc 7 dc 5
MHz ;E~~-;~c:~~~.::.~~hfitY"'!i'-:-::j'""::~·',-t.cT-f,'~·TTlir----,
Clock Rise or Fall 5 - 15 - 15 ::':~"'~~"~~' ~:~~ FJittitb;}
Time trCL *. tfCL 10 - 5
-
- 5
-
/.IS
:H :; ~fmit~i1, .
Set or Reset Pulse 5 250 500
ns "' wtts
Width 10 100 - 125 - GATE'TO'!OURCE .-15
"MO'ENT TElllfI£JI.TUft£'T",-,,·C
* If more than one unit is cascaded in a parallel clocked operation. trCL should T'l"PICAL Tl:MI'ERATUflE COEFFICIENT
FOR 10.-0.''Io,-t
be made less than or equal to the sum of the fixed propagation delay time at
-7.5
15 pF and the transition time of the output driving stage for the estimated
capacitive load.
Fig.5 - Minimum p*Channel dr:ain characteristics.

DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input tr.lf = 20 ns,
Cl - 15 pF, Rl = 200 kn
LIMITS
D,F,K,H E
VDD Packages Package
(VI Min. Typ. Max. Min. Typ. Max.
Clock to Q or Q Outputs
5 - 150 300 - 150 350
ns
10 - 75 110 - 75 125
tpHl' tplH
Set to Q or Reset to Q 5 - 175 300 - 175 350
ns
tPLH 10 - 75 110 - 75 125
40 '0
Set to Q or Reset to Q 5 - 175 300 - 175 350 LOAD ' ..... cIT.NeE tCLI-pF
ns
tpHL 10 - 75 110 - 75 125
Fig.6 - Typical propagation delay time VI- CL.
Transition Time. 5 - 75 125 - 75 150
ns
ITHL·ITLH 10 - 50 70 - 50 75
Maximum Clock Input 5 2.5 4 - 1 4 - MHz
Frequency. fCL 10 7 10 - 5 10 -
Minimum Clock 5 - 125 200 - 125 500
ns
Pulse Width, tw 10 - 50 80 - 50 100
Minimum Set or Reset 5 - 125 250 - 125 500
ns
Pulse Width. tw 10 - 50 100 - 50 125
Minimum Data Setup 5 - 20 40 - 20 50
ns
Time. ts 10 - 10 20 - 10 25
Clock Rise or Fall Time 5 - - 15 - - 15 "
/.Is ::'rt~: :::~ ::::
trCl. tfCl 10 - - 5 - - 5 o .... +
10
tro' ......
20
+.- ....
$0
Average Input Any
Capacitance. CI Input - 5 - - 5 - pF
Fig.7 - Typical transition time vs. CL .
496
CD4013A Types
STATIC ELECTRICAL CHARACTERISTICS I_a. NT T~"PERA URE
LOAD C,uoIoCITANCE (C Ll o
r. ·2"C
l!5 pF -
tltt j:"g-tIJTlTl
t..i:d!- t-t+itL:;
Conditions
Limits at Indicated Temperatures (OC) llil: t. m
Characteristic D,F,K,HPackages E Package Units :;1 l'
Vo VIN VOO -55 +25 +125 -40 +25 +85
Quiescent Device - - 5 1 0.005 1 60 10 0.01 10 140
Current, - - 10 2 0.005 2 120 20 0.02 20 280 I1A
IL Max. - - 15 25 0.5 25 1000 250 2.5 250 2500
Output Voltage:
Low.Level,
- 0.5 5 o Typ.; 0.05 Max. 10
SI.ltPLT VOLTS!Yoo'
20
- 0.10 10 o Typ.; 0.05 Max.

VOL
V Fig.8 - Tvpical maximum clock input
High·Level - 0.5 5 5 Typ.; 4.95 Min.
frequency VI. VDD'
VOH - 0.10 10 10 Typ.; 9.95 Min.
Noise Immunity:
Inputs Low, 4.2 - 5 2.25 Typ.; 1.5 Min.
VNL 9 - 10 4.5 Typ.; 3 Min.
V
Inputs High 0.8 - 5 2.25 Typ.; 1.5 Min.
t • AMIBIENT TEMTffr~
31: 10"'6
VNH 1 - 10 4.5 Typ.; 3Min. I?
Noise Margin:
-0
~IO'
~
~
~
..'
4.~ ,04.
~-
VNML 9 - 10 1 Min. ~ , -~.;.'0";;;[7
t;- I
Inputs High,
VNMH
0.5
1
-
-
5
10
1 Min.
1 Min.
V
~ lift
~
fg
. -
,is;;
,0'/
1t\=t-
..,
2 CL.·ISpF--
Output Drive
Q
a:: 10 8
I~ Cl*SOpF----
,--t--t-
Current: ~
0.5 - 5 0.65 1 0.5 0.35 0.35 1 0.3 0.24 ~
N·Channel
(Sink)
ION Min.
0.5 - 10 1.25 2.5 1 0.75 0.72 2.5 0.6 0.5 I
10 2
2468
la'
2 468
104
III ,I IIII ,
, ."
CLOCK FREQUENCY (tCll-Hz
.60
10!! 10 6
.
mA
P·Channel
4.5 - 5 -0.31 -0.5 -0.25 -0.175 -0.17 -0.5 -0.14 -0.12 Fig.9 - Typical dissipation characteristics.
(Source)
lOP Min
9.5 - 10 -0.8 -1.3 -0.65 -0.45 -0.4 -1.3 -0.33 -0.27
I nput Leakage
Any
Current, 15 ±1 0- 5 Typ.; ±1 Max. I1A
Input
IIL,IIH
INPUTOVtoOUTPUTS Voo
YOO-YNH
'- ~
Y~ J;
NOTE:
TEST IMY ONE INPUT,
Vss WITH OTHER INPUTS AT INPUTS
92C$-21400 You DRYSS·
o
v"..
Fig. 10 - Noise immunity test circuit.
Yeo 1NPOUS NOTE' VDO
~ MEASURE INPUTS
o ~ SEQUENTIALLY,
Vss TO 80TH Yao AND Yss·
CONNECT AU. UNUSED Fig. 12 - Quiescent dev;ctH;urrent test circuit. Fig. 13-Dynamic power dissipation test
INPUT'S TO EITHER circuit.
Voo CRVSS '
Vss
Fig.lt - Input leakage test circuit.
497
CD4014A Types
CMOS a-Stage
Static Shift Register
Synchronous Parallel or
Sei-ial Input/Serial Output :::~
CONT
RECOMMENDED OPERATING CONDITIONS at TA = 25 v C, Except as Noted. SEF!. II
IN
operation is always within the following ranges: ClOCI(.!9.
LIMITS
VDD D, F, K,H E UNITS
CHARACTERISTIC
Packages Package
(VI
'ss
•
Min. Max. Min. Max.
CD4014A
Supply· Voltage Range (For T A= Full FUNCTIONAL DIAGRAM
3 12 3 12 V
Package· Temperature Rangel
5 350 - 500 - ns
Data Setup Time, ts
10 80 - 100 -
5 500 - 830 - ns The RCA·CD4014A types are 8-stage parallel-
10 175 - 200 - input/serial output registers having common
5 dc 1 dc 0.6 CLOCK and PARALLEL/SERIAL CON-
Clock Input Frequency, fCL MHz TROL INPUTS, a single SERIAL DATA
10 dc 3 dc 2.5
INPUT, and individual parallel "JAM" IN-
Clock Rise and Fall Time, trCL, tfCL * 5 - 15 - 15
JlS
PUTS to each register stage. Each register
-
. 10 - 5 5
..
If more than one Unit IS cascaded trCL should be made less than or equal to the sum of the transition tlma and
stage is a D·type, master-slave flip-flop, In
addition to an output from stage 8, "Q" out-
puts are also available from stages 6 and 7,
the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
Parallel as well as serial entry is made into
the register synchronous with the positive
Limits at Indicated Temperatures (OC) clock line transition and under control of
Conditions
D, F, _K, H Packages E Package the PARALLEL/SERIAL CONTROL input,
Vo VIN VDD +25 When the PARALLEL/SERIAL CONTROL
+25
IV) (V) (V) -55 Typ. Limit +125 -40 +85 input is low, data is serially shifted into the
Typ. Limit 8-stage register synchronously with the pos-
Quiescent Device
- - 5 5 0.5 5 300 50 0.5 50 700 itive transition of the clock line. When the
Currant I L Max, - - 10 10 1 10 600 100 1 100 1400 !lA PARALLEL/SERIAL CONTROL input is
high, data is jammed into the 8-stage register
- - 15 50 1 50 2000 500 5 500 5000
via the parallel input lines and synchronous
Output Voltage: - 5 5 oTyp.; 0.05 Max. with the positive transition of the clock line.
Low·Level, Register expansion using multiple CD4014A
VOL - 10 10 oTyp:; 0.05 Max. V packages is permitted.
High Level - 0 5 4.95 Min.; 5 Typ,
VOH - 0 10 9.95 Min.; 10 Typ. metic dual-in-line ceramic packages (0 and
Noise Immunity: 4.2 - 5 1.5 Min.; 2.25 Typ. packages (E suffix), 16-lead ceramic flat
Inputs Low, packages (K suffix), and in chip form (H
VNL 9 - 10 3 Min.; 4.5 Typ.
V suffix).
VNH 1 - 10 3 Min.; 4.5 Typ.
°1
SER. PAR SER PI-1 PI-n
Noise Margin: CL .... On
Inputs Low,
4.5 - 5 1 Min. IN CONTROL !lNTER-
NALI
-
VNML 9 10 1 Min.
V ./ X 1 0 0 0 0
Inputs High,
VNMH
0.5
1
-
-
5
10
1 Min.
1 Min. ./ X 1 1 0 , 0
Output Drive
Current:
./ X 1 0 1 0 1
n·Channel 0.5 - 5 0.15 0.3 0.12 0.085 0.072 0.3 0.06 0.05 ./ X 1 1 1 1 1
(Sink),
IDNMin. /" 0 0 X X 0 °n-'
0.5 - 10 0.31 0.5 0.25 0.175 0.12 0.5 0.1 0.08

mA ./ 1 0 X X 1 °n-'
"
p·Channel 4.5 - 5 -0.1 -0.16 ·0.08 -0.055 ·0.06 ·0.16 ·0.05 -0.04 X X X X °1 On NC
(Source):
IDPMin. 9.5 - 10 ·0.25 ·0.44 ·0.20 -0.14 -0.12 -0.44 ·0.1 -0.08 X = DON'T CARE CASE .... = LEVEL CHANGE
Input Leakage NC = NO CHANGE
Current, t ±10- 5 Typ.; ±1 Max.
- A r- l T15 !lA Fig. 1 - Truth tabl.,
IIL,IIH
498
CD4014A Types
Features:
- Medium speed operation ..... 5 MHz (typ.) clock _ Quiescent current specified to 15 V Applications:
rate at VOO - VSS = 10 V - Maximum input leakage current of 1 pA - Synchronous parallel inputlserial output
- Fully static operation at 15 V (full package-temperature range) data queueing
- 8 master-slave flip-flops plus output - 1-V noise margin (full package-temper- - Parallel to serial data conversion
buffering and control gating ature range) - General-purpose register
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input t r, tt = 20 nl, CL = 15 pF,
RL=200kn
LIMITS
TEST D,F, K, H E
VDD Min. Typ. Max. Min. Typ. Max.
(V)
ns
tpLH,tpHL
10 - 100 225 - 100 300
Transition Time; 5 - 150 300 - 150 400
ns
tyHL' tTLH
10 - 75 125 - 75 150 Fig. 2 - Typica' dissipation chBracteri,ticl •

Frequency, feL
Minimum Clock Pulse

10
5
3
-
5
200 500
- 2.5
-
5
200
-
830 ns
I
Width,tW
10 - 100 175 - 100 200
Clock Rise & Fall Time; 5 - - 15 - - 15 r.
trCL, ttcL' jlS
L
10 - - 5 - - 5 ad 1
Minimum Data Set Up 5 - 100 350 - 100 500
ns
Time,ts
10 - 50 80 - 50 100
10
Stl'PLY'VOLTSIVooi
Fig. 3 - Typical clock input frequency

Average Input
Capacitance, CI Any Input - 5 - - 5 - pF VI. supply volt8ge .
I AM.'ENT TEMPERATURE IT"I-Z5-C

I TYPICAL TE . .ERATURE COEnlCIEHT n)R
• If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time and AU. VALUES Of VDD* o."",,·c
the fixed propagation delay of the output of the driving stage for the estimated capacitive load. 1
PARALLEL
INPUT - 1 PI.2 PI.4
1
w
~
PARALLEL
SERIAL
CONTROL
10
SERIAL
INPUT 10 20 so 40 50 60 70 80
LOAD CAPACITANCE tCl.I-p,
Fig. 4 - Typical proPllfllltion dBlay time

VL load CspscitBnC8.
CLOCk
10
AMIIENT TEMPERATURE (TAl. 25-C:
* TYPICAL. TEMPERATURE CQt:FFICIENT FOR
AL.L VAL.UES OF Voo. 0.3'" I ~
VDD
w ,.
j: 300
*PROTECTED
AU. LOGIC INPUTS ARE
BY
COS/MOS PROTECTION
! 200
,.
,
NETWORK =
:: 100
10 20 30 40 M) 60 70 80
L.OAD CA,ACITMICE tCL.) - pF
ncs-naoa
Fig. 6 - Typk:al transition time VI. load
clIPacitanCfl.
Fig. 5 - Logic block diagram.
499
CD4015A Types
CMOS Dual 4-Stage Static Shift Register '00
With Serial Input/Parallel Output OATAA
Resetting of all stages is accomplished by a '"

The RCA·CD4015A consists of two identical, CLOCIIA
'"
high level on the reset line. Register expan· RUETA
independent, 4·stage serial·input/parallel· '"
output registers. Each register has indepen' sion to 8 stages using one CD4015A package, '"
or to more than 8 stages using additional OATAe
dent CLOCK and RESET inputs as well as '"
a single serial DATA input. "a" outputs are CD4015A's is possible. CLoelle
'"
Rune " '"
available from each of the four stages on These types are supplied in 16-lead her-
both registers. All register stages are D·type, metic dual'in-line ceramic packages (0 and '"
master·slave flip·flops. The logic level pre· '"
packages (E suffix). 16-lead ceramic flat
sent at the DATA input is transferred into packages (K suffix), and in chip form (H
the first register stage and shifted over one suffix). C04015A
stage at each positive·going clock transition. FUNCTIONAL DIAGRAM
MAXIMUM RATINGS,Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE ITstgl . . . . -65 to +150'C
Features:
OPERATING·TEMPERATURE RANGE (TAl: • Medium speed operation. , ..... , , . , ,
PACKAGE TYPES D, F, K, H -55 to +12SoC
5 MHz (typ.) clock rate at V DD
PACKAGE TYPE E ....... . -40 to +B5'C
-VSS=10V
OC SUPPLY·VOLTAGE RANGE, (VDDI
-0.5 to +15 V • Fully static operation
(Voltages referenced to V 55 Terminal!. . . . . . . .
• 8 master-slave flip·flops plus output
POWER OISSIPATION PER PACKAGE (PDI
500mW
buffering
FOR T A = -40 to + 60'C (PACKAGE TYPE E I
FOR T A = +60 to +B5'C (PACKAGE TYPE E I . Derate Linearly at 12mWfC to 200 mW • Quiescent current specified to 15 V
FOR T A = -55 to +100'C (PACKAGE TYPES D, F, K) " " " " " 500 mW • Maximum input leakage current of 1 /-LA
FOR T A = +100 to +125'C (PACKAGE TYPES D, F, K) .. Derate Linearly at 12 mWfC to 200 mW at 15 V (full package·temperature
DEVICE DISSIPATION PER OUTPUT TRANSISTOR range)
FOR T A = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES)' . . . 100 mW • 1·V noise margin (full package·tempera·
INPUT VOLTAGE RANGE, ALL INPUTS. . .-0.5 to V DD +0.5 V ture range)
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 105 max. Applications:
• Serial·input!parallel·output data queueing
RECOMMENDED OPERATING CONDITIONS at TA = 25"C, Except as Noted. • Serial to parallel data conversion
For maximum reliability, nominal operating conditions should be selected so that • General·purpose register
TRUTH TABLE
LIMITS
Cl"" D R 01 On
CHARACTERISTIC VDD 0, F, K,H E UNITS .../ 0 0 0 °n·l
PACKAGES PACKAGE
(V) .../ 1 0 1 °n·l
MIN. MAX. MIN. MAX, """'- X 0 01 On (N o CHANGE)
X X 1 0 0
3 12 3 12 V ""= LEVEL CHANGE
X = DON'T CARE CASE
Data Setup Time, ts
5 350 - 500 - ns Fig. 1 - Truth table.
10 .80 - 100 -
AM81ENT TEMPERATIJAE ITA) ·es·c

5 500 - 830 - ns
, LOAD CAPACITANCE ICL) • 10 JIoF
10 175 - 200 -
5 dc 1 dc 0.6
Clock Input Frequency, fCl MHz
10 dc 3 dc 2.5
~ ,
5 - 15 - 15 L
10 - 5 - 5
/-LS g
d ,
Clock Reset Pulse Width, tw

5 500 - 830 - ns
,.
SlPPLY \/OLTS1Vooi
10 175 - 200 -
Fig. 2 - Typical clock input frequency
*If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time
ys. supply yoltage.
500
CD4015A Types
AMBIENT TEMPERATURE ITA 1-25·C
TYPICAL TEMPERATURE COEFflCIEHT FOR
LIMITS AT INDICATED TEMPERATURES (OC) ALL. VALUES OF voo·a,s"",·c
CONDITIONS
0, F, K, H PACKAGES E PACKAGE
Vo V IN V DD +25 +25
-55 +125 -40 +85
(V) (V) (V) TYP. LIMIT TYP. LIMIT
Quiescent Device
Current. IL Max.
-
-
-
-
5
10 10
5 0.5
1
5
10
300
600
50
100
0.5
1
50
100
700
1400 /JA
I.
- - 15 50 1 50 2000 500 5 500 5000
Output Voltage:
Low Level,
- 5 5 o Typ.; 0.05 Max 20 50 040 60 10 80
VOL - 10 10 o Typ.; 0.05 Max LOAD CAPACITANCE CCLI- pF
V
High Level - 0 5 4.95 Min.; 5 Typ. Fig. 3. - Typical propagation;ielay time
V OH vs. load capacitance.
- 0 10 9.95 Min.; 10 Typ.
Noise Immunity:
4.2 - 5 1.5 Min.; 2.25 Typ.
Inputs Low.
V NL 9 - 10 3 Min.; 4.5 Typ.
A"SIEHT TEMPERATURE ITAI' 2'"'C
V .. TYPICAL TEMPERATURE COEffiCIENT FOR
- i 0.''''
Inputs High
V NH
0.8
1 -
5
10
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
-,
S500
SOQ ALL VALUES OF Voo' I '0:
•
Noise Margin: ~ I
4.5 - 5 1 Min. ';400
Inputs Low,
V NML 9 - 10 1 Min. !... 300 ~~ \-a~ .~ ;IF -g1 ff
V ~ "/#.,...-4 ~o"" :::: g-£; ~i;
"l: 200 ,0
V NMH
1 - 10 1 Min. :... 100
"
.~ .. ~ ....
Output Drive
Current:
N-<:hannel
(Sink), 0.5 - 5 0.15 0.3 0.12 0.085 0.072 0.3 0.06 0.05
ION Min. 0.5 - 10 0.31 0.5 0.25 0.175 0.12 0.5 0.1 0.08 Fig. 4 - Typical transition time vs
mA load capacitance.
P-Channel
(Source): 4.5 - 5 -0.1 -0.16 -0.08 -0.055 -0.06 -0.16 -0.05 -0.04
lOP Min. 9.5 - 10 -0.25 -0.44 -0.20 -0.14 -0.12 -0.44 -0.1 -0.08
Input Leakage Any Input
Current,
/JA
IIL,IIH -1-115 ± 10- 5 Typ., ± 1 Max.
0" 0" 0..
L.OAD C"""'ITANCE ICL'o"pf

- - - - CL o!loOpf
..., -'T TTT' -rrr
. Fig. 5 - Typical djlSiparion charBcfflr/,tiCi•
."
CL,
'"
£\-'" ':
*PROTECTED
ALL. INPUTS ARE
BY
COS/MOS PROTECTION
v55
CL,
NETWORK
501
CD4015A Types
st TA =2ftC, Input tT, t,=20nll, CL .. 15pF, RL = 200 kn
VOD-VNH
INPUTOVDOOUTPUTS .
LIMITS
CHARACTERISTIC
TEST
CONDITIONS D,F,K,H E UNITS ~::- ~
PACKAGES PACKAGE
~
NOTE:
VSS TEST ANY CCIMIINATlGf
OF INPUTS
MIN. TYP. MAX. MIN. TYP. MAX.
(V)
CLOCKED OPERATION
Fig. 7·- Nolltl-lmmunlrv I8$t circuit.
Propagation Delay
Time;
5 - 300 750 - 300 1000
ns
TpLH. TpHL 10 - 100 225 - 100 300
v~'P(JU'
'. i.~:::::,
Transition Time; 5 - 150 300 - 150 400
ns
tTHl,tTLH 10 - 75 125 - 75 150
Minimum Clock Pulse 5 - 200 500 - 200 830
ns TO 10TH voo AND yts.
Width,tw 10 - 100 175 - 100 200
Vss
CONNECT IILLUNUSED
,..urs 10 EIT"ER
Clock Rise & Fall
Time; trCl, tpL'
5 - - 15 - - 15
jlS v55
YOOOllVSS'
10 - - 5 - - 5
Minimum Data Set· 5 - 100 350 - 100 500
ns
upTime, ts 10 - 50 80 - 50 100
FIg. 8 - Input·leakage-current lB.,
circuit.
Maximum Clock
Input Frequency,
5 1 2.5 - 0.6 2.5 - MHz
fCl
10 3 5 - 2.5 5 -
Average Input
Capacitance, CI - 5 - - 5 - pF
RESET OPERATION
Propagation Delay 5 - 300 750 - 300 1000
ns
Time,. TpHL 10 - 100 225 - 100 300
Minimum
Reset Pulse Width
5 - 200 500 - 200 830
ns
\v 10 - 100 175 - 100 200
*If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time and
the fixed propagation delay of tho output of the driving stage for the estimated capecitve loed.
Test parformed with the following

sequence of "I's" and "O's"
TERMINAL DIAGRAM
51 52 53 TopViaw
10V
Test
Don', Tes'
Don't Test
Don't Test
0
0
1
0
I
0
0
0
0
1
1
0
CLOCK B
0"
,.
• ,.I. VDD
DATA B
03A 3 RESET B
Don', Tes, I 0 0 O'A "
13 01.
Don't Test 0 0 I 01 A 0.0
RESET A " 0.0
Tes, 0 I
"
g;ZCS·11909
Don" Tes,
Test
0
I
0
0
0
0
VSS
DATA A 10
9
OOA
CLOCK A
92C$·24451
Fig. 9 - OUiBlCtlnt.tJeV;otH:Ufrtlllt
",st circuit.
502
CD4016A Types
CMOS Quad _ High degree of linearity: <0.5% distortion

typo @ fis = 1 kHz, Vis = 5 Vp•p,
Bilateral Switch VDD-VSS ;;'10 V, RL = 10 kn
- Extremely low OFF switch leakage result·
For Transmission or Multiplexing ing in very low offset current and high ef·
of Analog or Digital Signals fective OFF resistance:
100 pA typo @ VDD-VSS = 10 V, TA = 25 0 C
The RCA·CD4016A Series types are quad - Extremely high control input impedance
bilateral switches intended for the trans· (control circuit isolated from signal circuit:
mission or multiplexing of analog or digital 1012 n typo
signals. Each of the four independent bi· - Low crosstalk between switches:
lateral switches has a single control signal
-50 dB typo @ fis = 0.9 MHz, R L = 1 kn
input which simultaneously biases both the
p and n device in a given switch ON or OFF. - Matched control-input to signal·output
capacitance:
metic dual-in-line ceramic packages (D and Reduces output signal transients
FUNCTIONAL DIAGRAM
F suffixes), 14-lead dual-in-line plastic - Frequency response, switch ON = 40 MHz
packages (E suffix). 14-lead ceramic flat (typ.)
packages (K suffix). and in chip form (H - Quiescent current specified to 15 V
suffix). - Maximum input leakage current of 1 p.A CONTROL
Features: at 15 V (full package· temperature range) vcO-.....,IN'...........-1'-~
- 15-V digital or ± 7.5-V peak·to·peak switching
App/ications:
- 2BO·n typical ON resistance for 15·V operation
- Analog signal switching/multiplexing
- Switch ON resistance matched to within· 10 n
typo over 15-V signal·input range Signal gating - Modulator
• High ON/OFF output·voltage ratio: Squelch control - Demodulator
65 dB typo @fis= 10 kHz, RL = 10 kn Chopper - Com mutating switch
Fig. I-Schematic diagram - I of 4
RECOMMENDED OPERATING CONDITIONS identical sections.
For maximum reliability. nominal operating conditions should be selected so that - Digital signal SWitching/multiplexing
operation is always within the following range: - CMOS logic Implementation
- Analog-to-digital & digital·to·
LIMITS analog conversIOn
Min. Max. - Digital control of frequency, impedance,
Supply Voltage Range (For TA = Full Package phase, and analog·signal gain
TYPICAL "ON" RESISTANCE CHARACTERISTICS

CHARAC· SUPPLY LOAD
TERISTIC' CONDITIONS CONDITIONS
RL - lk!! RL - 10k!! RL = lOOk!!
VDD VSS VALUE Vis VALUE Vis VALUE Vis
IVI IVI I!!I IVI I!ll IVI I!!I IVI
200 1]5 200 115 180 115
RON +15 0
200 0 200 0 200 0
RONlmax I t15 0 300 111 300 19.3 320 19.2
I
290 110 250 110 240 110 INPUT SIGNAL VOLTS IV,s,
RON +10 0 ,itS-'tllo
290 0 250 0 300 0 Fig.2 - Tvp. "ON" characteristics for 1 of 4
RONlmax.1 110 0 500 +7.4 560 15.6 610 15.5 switches with VOD = +15 V, Vss = 0 V.
860 I 5 470 f 5 450 I 5
RON + 5 0
600 0 580 0 800 0
RONlmax.1 + 5 0 1.7k +4.2 7k +2.9 33k 12.7
200 +7.5 200 17.5 180 17.5
RON t75 -7.5
200 -7.5 200 -7.5 180 -7.5
RONlmax.1 +75 -7.5 290 '0.25 280 '25 400 '0.25
, 260 + 5 250 I 5 240 +- 5
,RON + 5 -5
310 - 5 250 -5 240 -5
·RONlmax.1 + 5 -5 600 '0.25 580 '0.25 760 .10.25
590 +2.5 450 +2.5 490 t2.5
.R ON +2.5 -2.5
720 -2.5 520 -2.5 520 -2.5
+2.5 -2.5 232k ;:.0.25 300k .:.0.25 870k ..:.0.25 Fig.3 - Typ. NON" characteristics for 1 of 4
RONlmax.1
switches with VDD = +10 V, VSS = 0 V.
tt Variation from a perfect switch, RON =on.
503
CD4016A Types
ELECTRICAL CHARACTERISTICS (All inputs. . . . . • . . . . . . Vss< VI": Vool

Recommended OC Supply Voltage IVoo-VSSI .. 3 to 15 VI
Test Conditions Limits
All Voltage Values Values at -55'C. +25'C. +125'C Apply to D. F. K. H Package.
Characteristic ilre in Volts Vailles at -4IPC, +2!)OC, +85 C Apply to E Pm:kage
0 Unit
VOO +25o C
-55° -40 0 +S5° +125°
(V) Typ, Max.
Quiescent Device
Current, I L max
(All switches ON
or all Switches 5 0,25 - - 10 0.01 0.25 INPUT SIGNAL VOlTS {VISI
OFF) 10 0.5 - - 20 0.01 0.5 ~A
O,F,.H Pkgs: 15 2 - - 40 0.01 2 Fig. 4 - TVp. "ON" characteristics for 1 of 4
switches with VOO = +5 V, VSS = 0 v.
5 - 0.25 5 - - 0.25
E,Y Pkgs. 10 - 0.5 10 - - 0.5 ~A
15 - 2 20 - - 2
Signal Input. (Vi.) and Outputs (Vo ,)
VC=
VSS Vis
VOO Typ/Max Typ/Max TyplMax Typ/Max
RL = 10 kU-
+7.5 120/360 130/370 260/520 300/600 200 400
+7.5 -7.5 -7,5 120/360 130/370 260/520 300/r.oO 200 400
±0.25 130/775 160/790 400/1080 470/1230 280 850
+5 130/600 150/610 3401840 400/960 250 660
+5 -5 -5 130/600 150/610 340/840 400/960 250 660
±0.25 325/1870 370/1900 77012380 90012600 580 2000
ON Resistance. l!
+15 120/360 130/370 2601520 300/600 200 400
RON
+15 0 +0.25 120/360 130/370 2601520 300/600 200 400 INPUT SIGNAL VOLTS IV.sl
+9.3 1501775 1801790 400/1080 49011230 300 850
+10 130/600 150/610 340/840 400/960 Fig.5 - Typ. nON" characteristics for 1 of 4
250 660
switches with VOD = +7.5 V, VSS = '7.5 V.
+10 0 +0.25 130/600 150/610 3401840 400/960 250 660
+5.6 300/1870 350/1900 750/2380 880/2600 560 2000
~ON Resistance RL = 10 kn-
Between Any +7.5 -7.5 ±7.5 - - - - 10 - !!
2 of 4 Swi tches
lIRON
+5 -5 ±5 - - - - 15 -
+5 -5 5
Sine Wave
p.p"
Response
RL = 10k!!
(Distortion)
fis -= 1 kHz
,- - - - 0.4 - %
Frequency Response I VOO=+5 1~5

Switch ON Ve=VSS=-5 pop
(Sine-Wave RL=lkl!
Input)
Vas
2010910-=
Vis
- - - - 40 - MHi INPUT SIGNAL VOLTS {V,SI
-3dB
Fig. 6 - TVp. "ON" characteristics for 1 of 4
+5 -5 -5 switches with VOO = +5 V, Vss =·5 V.
pop
Feedthrough RL=lk!!
Switch OFF
20 1091OVas ~ - - - - 1.25 - MHz
SUPPLY VOLTS: Voo. -+ 2.~V; Vss. -2.'-V
-50 d¥iS AMIIENT TEMPERATURE {T... J. 2S·C
Input or Output
Ve=
leakage Current
VOD VSS
Switch OFF
(Effectiv. OFF +7.5 7.5
±7.5 - - - - tl00 - pA
Resistance) +5 -5 ±5 - - - - lOx 10- 3 ±125· nA
,~~~fiO<jJ
£
·2
:t!t~'"
-3 -2 o I 2 ;,
INPUT SIGNAL VOLTS ''''51
Fig.7 - Typ. uON u characteristics for 1 of 4

switches with VOO = +2.5 V; VSS - ·2.5 V.
504
CD4016A Types
ELECTRICAL CHARACTERISTICS ICont'dl . . . . . . . . . . . VSS ~ VI~ Vool
Recommended OC Supply Voltage IVoo-Vssl .. 3 to 15 VI
TIlt Condition. Limits
All Voltage Values Values at -55' C, +25' C, +125' C Apply to D, F, K, H Packages
Characteristic are in Volts Values at -4iPC,+25"C,+85'?C Apply to E Package Unit
VDD +25o C
-J,;5° --40" +850 +1250
(V) Typ. Max.
VCI A I=VDD=·5
Crosstalk Between VCIBI=VSS=-5

Any 2 of 4 VislA} = 5 pop
Switches RL =1 kl! - - - - 0.9 - MHz
If = -50dBI VoslBI INPUT SIGNAL VOLTS tVI.1
2010910Vi IAI =
-50 d~ Fig.8 - Typ. nON" characteristics as a function of
temp. for 1 of 4 switches with V DD :a +5 Vi
.vC: ~JlO VDD VSs=-5 V.
Propagation 5 20 50
VSS = GNO ns
Delay ISignal C L = 50 pF 10 10 25
Input to Vis = 10Sq.
Signal Outputltpd Wave
t r • tf = 20 ns
Capacitance:
Input,Cis VDD=+5 - - - - 4 -
Output,Cos VCC=VSS=-5 - - - - 4 - pF
Feedthrough,Cios - - - - 0.2
Control (Velt
Switch Threshold Vis';VDD,lis=10pA O.7min - - O.2min O.5min
2.7 V
Voltage, VTH VDD-VSS= 15, 10,5 2.9max - - 2.4max 1.5
Input Leakage VOD
Vis<VDD '10- 5 typ; ±1 max. pA
Current,lt L max =15
Crosstalk VC=10 ISq.Wavel
(Control Input t r ,tf=20 ns VDD - - - - 50 - mV
to Signal Output) RL =10 kl! =10
Fig.9 - Typ. feedthru VI. frequency - switch
1"00 VSS-l0 VDD "OFF'~
Turn-On Vc =10 5 - - - - 20 40
ns
Propagation Delay, ISee Fig.25} 10 - - - 10 20
tp dc t(,tf=20 ns
CL=15pF
RL=1kll
VDD=10,
Maximum VSS=GNO
RL =1 kl!,
Allowable Control
Input Repetition Cl =15 pF - - - - 10 - MHz
Rate VcC=10ISq.Wavel
tr,tf -" 20 ns
, -
Av. Input
Capacitance, C, - - - - 5 - pF. I ,orr
l
* Limit determined by minimum feasible leakage current measurement for automatic testing .
... Symmetrical about 0 volts.
Ii
t-
0-'
• For all test conditions.
t All control inputs protected by COS/MOS protection network_ Fig. 10 - Typical crosstalk between ,witch
circuits in the 111mB package.
v..
ALL UNUSED TERMIiIALS ALL UNUSED TER"NALS ARE

ARE CONNECTED TO Vas CONNECTED TO Vas
.zeS-21'.IO
Fig, 12 - "OFF" switch input or output Fig. 13 - Test circuit for square'waWl
/BllktIgB current test circuit. re$fJonse.
505
CD4016A Types
<, ~,
/~'", /
\~// 'v'/
\ I \ I
SCALE: x-o.2tnS/OIV Y"2.0V/DIV SCALE: X = 0.2 mslOIV y .. 2.0 V/DIV SCALE X ~ 100 ns DIV
~~~ ;5~l· +l.SV, v~ ... 7.SV. RL.- lOK~ Voo· Vc • +2.5V, VSs" ·2.5V. RL" IOKn Y-SOVDIV
CL"15 p F '
fIS·' KHz VIS-5Vp-p 'IS -1 KHz VIS" SV pop 92CS-27615
DISTORTION = 0.2" . DISTORTION" 3 '"
92C5-27612 92C5-27614
Fig. 16 - Typicalliquare wave rOlPonse at
Fig. 14 - Typi~1 line wsve nsponse of VOD = Fig. 15- Typical.ino we"" rtllPon.. of VDD = VOD = Vc = +15 V. Vss = Gnd.
+7.5 V, VSS = -7.5 V. +2.5 V, Vss - -2.5 V.
Ves WITH TEST UNIT

11 SWITCH OF CD4016A----....
PLUGGED IN TEST
flXTUREl
Vas fiXTURE ALONE / ' "

[NO UNIT TERM
~CAlE X· 100 ns:Div 5 TO 3 OF SOCKET! Vc: IOV PER OIV
V· 2V DIV Vos - O.:lV PER DIV
CONNECTED TO Vss I lOOns PER OIV
92C5-21617 92CS-27618
Fig. 17 - TypiCBI SfI,!BrB wB~ rBsponSB lit VOD lal Ib)
= VC= +5 V. Vss = Gnd. Fig. 18 - Crosstalk-control input to signal output.
~
p
RATE
Vc
Ir ·'f·20·
.,.,,~
V ·0· 10"
.. 2.
. . IO;J"'""'\..VI, v.. "00 '" 20"1
tr .tt- 2OM Yo.

ARE CONNECTEO TO Vas
ALL UNUSED TERM.NALS ARE
CONNECTED TO VIS
Fig. 19 - Propagation delay time signal input Fig.20 - Max. alloWtlble control·input
(V,S) to signal output (Vas). repetition ratfl. Fig.21- Switch threshold voltage.

STORAGE·TEMPERATURE RANGE IT stg ) -66 to +1500 C
OPERATING·TEMPERATURE RANGE (TA)
PACKAGE TYPES D, F, K, H -55 to +125 oC MEASURED ON 1000TON CAPACITANCE
PACKAGE TYPE E -40 to +85 0 C MtDGE fIiIOD£L 75A (llIftd
DCSUPPLY·VOLTAGE RANGE. (V DD )
(Voltages referenced to V SS Termonal) ............... , ..................... . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE IP D )
Vc--sv
FOR T A = -40 to +600 C (PACKAGE TYPE E) 500mW vss--sv
FOR T A = +60 to +85 0 C IPACKAGE TYPE E) Derate LInearly at 12 mW/oC to 200 mW Voo-+sv
FOR TA = -55 to +l00'C (PACKAGE TYPES D, F, K) 500mW
FOR TA = +100 to +125'C (PACKAGE TYPES D. F, K) . Derate LInearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR ARE CONNECTED TO 'Iss
FOR TA = FULL PACKAGE·TEMPERATURE RANGE IALL PACKAGE TYPES).. ..... 100 mW

INPUT VOLTAGE RANGE. ALL INPUTS -0.5 to V DD +0.5 V Fig.22 - Capacitanco C,OS and COS.
LEAD TEMPERATURE lOURING SOLDERING)
At distance 1/16 ± 1/32 Inch 11.59 ± 0.79 mm) from case for 10 s max.
506
CD4017 A Types
CMOS Decade its zero count. Use of the Johnson decade

"0"
Counter/Divider counter configuration permits high speed

operation, 2·input decimal decode gating,
-,-
CLOCK 14
Plus 10 Decoded Decimal Outputs and spike·free decoded outputs. Anti·lock CLOCI( 13
INHI81T
gating is provided, thus assuring proper FlESET IS 10 "4"
counting sequence. The 10 decoded outputs

The RCA-CD4017A consists of a 5·stage are normally low and go high only at their
Johnson decade counter and an output de· respective decimal time slot. Each decoded
coder which converts the Johnson binary output remains high for one full clock cycle. 11","
code to a decimal number. Inputs include a A CARRY.()UT (COUT) signal completes
CLOCK, a RESET, and a CLOCK INHIBIT one cycle every 10 clock input cycles and is "
CARRY
OUT
signal. used to clock the succeeding decade directly 92CS·25072 A2
The decade counter is advanced one count at in a multi·decade counting chain. CD4017A
the positive clock signal transition if the These types are supplied in 16-lead her- FUNCTIONAL DIAGRAM
CLOCK INHIBIT signal is low. Counter ad· metic dual-in-line ceramic packages (D and
vancement via the clock line is inhibited F suffixes). 16-lead dual-in-line plastic
when the clock INHIBIT signal is high. A packages (K suffix). and in chip form (H Features:
high reset signal clears the decade counter to suffix).
• Synchronous decade counter plus 10 de-
MAXIMUM RATINGS, Absolute-Maximum Values: coded outputs
•
STORAGE·TEMPERATURE RANGE (T,tgl • • • • . • • . . . . . • . . • • • . . • • . • • • • ~5 to +150'C
• Medium speed operation ...
PACKAGE TYPES 0, F, K, H .................................. -55 to +125'C
.•• 5MHz hyp.l at VDD-VSS = 10 V
PACKAGE TYPE E . • • • • • • • • • • . • . . . • . • • . • . . • • • • • • • • . • • •• -40 to + 85'C • Quiescent current specified to 15 V
DC SUPPLY·VOLTAGE RANGE (VDD) • Maximum input leakage current of 1 !lA
(Voltagesreferenced to VSS Terminal) ••••••.••••...••.••••••••••••• -0.5 to +15 V at 15 V (full package·temperature range
POWER DISSIPATION PER PACKAGE (PD): range)
FOR T A = -40 to +60'C (PACKAGE TYPE E) • . • . . • • . • • • • • • • • . . • • • • • • • 500 mW • 1·V noise margin (full package·tempera·
FOR TA = +60 to +85°C (PACKAGE TYPE E,l •..••• Derate Linearly at 12 mWfC to 200 mW ture range)
FOR T A = -55 to +100°C (pACKAGE TYPES D, F, K) ••••••••.•..••••••••••. 500 mW
FOR TA = +100 to +125°<:: (PACKAGE TYPES D, F, K) •.• Derate Linearly at 12 mWfC to 200 mW Applications:
• Decade counter Idecimal decode display
FOR. T A = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) •.••••• 100 mW
• Frequency division
INPUT VOLTAGE RANGE, ALL INPUTS ••••.•....••.••••••.•••.• -0.5 to VDD +0.5 V
• Counter control/timers
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. . . . . . . . . . • . . •• +265°C
• Divide by N counting
N = 2 - 10 with one CD4017A and one
oneCD4001A
N > 10 with multiple CD4017A's
• For further application information, see
ICAN-6166 "CMOS MSI Counter
and Register Design & Applications"
CLOCK
CLOCK INHIBIT
"0"
*PROTECTED
Au.. INPUTS ARE
BY
"I"
COSIMOS PROTECTION "2"
ADD
NETWORK
"3"
J ...... ________ -Jr.I~ ____________________

tERIIINALIfQ I.GMOoVn
TUIIlN4LNO " . '100
.. s.. __________ __________________
-Jr0~
____________ _______________
tss
"6" ~r.;~
"7"
______________ _____________
--JGi~
"8" ________________ ~r.>~ __________
~~::::::::~L:=======r;;~.~:::::::::;,
"9"
"r !:!HII!H
CARRY OUT
j.'SS·ll~Rl
Fig. 1 - Logic diagram. Fig. 2 - Timing diagram.
507
CD4017 A Types
LIMITS AT INDICATED TEMPERATURES I'CI
CONDITIONS
D, F, K, H PACKAGES E PACKAGE UNITS
V~NP(JU'
.. =..~
CHARACTERISTICS
Vo VIN V DD +25 +25
-56 +125 -40 +85
IVI IVI IVI TYP. LIMIT TYP. LIMIT
- - 5 5 0.3 5 300 50 0.5 50 700

Quiescent Device
Current.IL Max, - - 10 10 0.5 10 600 100 1 100 14DO ~A Vss TO BOTH VDD AND 'Iss'
CONNECT ALL UNUSED
- - 15 50 1 5D 2000 500 5 500 5000 INPUTS TO EITHER
VDD ORVSS'
Output Voltage: Vss
Low-Level. - 5 5 o Typ.; 0.05 Max.
VOL - 10 10 oTyp.; 0.05 Max.
V
High Level - 0 5 4.95 Min.: 5 Typ. F;g. 10 - Input*/eakage-current test circuit.
VOH - 0 10 9.95 Min.: 10Typ.
Noise Immunity:
Inputs Low,
4.2 - 5 1.5 Min.; 2.25 Typ.
VNL 9 - 10 3 Min.; 4.5 Typ.

V
Inputs High 0.8 - 5 1.5 Min.: 2.25 Typ.
VNH 1 - 10 3 Min.; 4.5 Typ.
Noise Margin 4.5 - 5 1 Min.
Inputs Low
VNML
9 - 10 1 Min.
V
Inputs High. 0.5 - 5 1 Min.
VNMH 1 - 10 1 Min.
IOPUTQVIlOOUTPUTS
Output Drive
Current: VOo-t..- ~
N-thannel (Sink)
VOL, -
Decoded D.5 - 5 D.06 D.l 0.D5 0.035 0.03 0.1 0.025 0.D2
ION
Outputs 0.5 - 10 0.12 0.4 0.1 0.07 0.085 0.4 0.07 0.D55 NOTE:
Vss :''IN~U~~CMlIN'TICIN
Min
Carry D.5 - 5 D.185 0.4 D.15 D.l05 0.095 0.4 D.08 D.065
tzCS-Zf441
Output 0.5 - 10 D.45 1 D.35 D.25 0.3 1 D.75 D.2
rnA
P-Channel ISource) Fig. l' - Noise';mmunity ttl.t circuit.
Decoded 4.5 - 5 f-o.D375 -D.D75 -0.D3 -D.D21 -0.018 -D.D75 -D.DI5 -D.DI2
lOP
Outputs 9.5 - '10 f-o.12 -D.2 -0.1 -D.07 -D.D85 -D.2 -D.D7 -D.D55
Min 4.5 - 5 f-o.185 -0.4 -D.15 -D. 1D!. 1-0.095 -D.4 -0.D8
Carry -D.D65
Outputl 9.5 - lD ~.45 -1 -D.35 -D.25 -0.3 -1 -D.24 -D.2D
Input Leakage
Current.
IIL.IIH
- 1- Any In p (
15 ±10·5 Typ•• ±1 Max. ~A
When the Nth decoded output is reached

(N th clock pulse) the S·R flip flop (con·
r-----I--------~g~TN 1e6 structed from two NOR gates of the
f. CLOCK;. N
CD4001A) generates a reset pulse which
clears the CD4017A to its zero count. At
this time, if the Nth decoded output is
~=='-+--'!J""''''''''''''-='-+-;~~ENR~~T~OC?~T greater than or equal to 6, the CoUT line
" CLOCK ~ N goes high to clock the next CD4017A
counter section. The "0" decoded output
also goes high at this time. Coincidence of
the clock low and decoded "0" output low
resets the S·R flip flop to enable the
CD4017A. If the Nth decoded output is
9255·4537 R 1 less than 6, the COUT line will not go high
and, therefore, cannot be used. In this case
Fig. 12 - Divide by N counter IN .;;; 10J with N "0" decoded output may be used to perform
decoded outputs. the clocking function for the next counter.
508
CD4017 A Types
LIMITS
CHARACTERISTIC VDD D,F,K,H E UNITS !OOO
I
(V) PACKAGES PACKAGE '0
MIN. MAX. MIN. MAX. IHi!

I0203040~
LOAD (APAtITANCE tCLI-pf
Supply Voltage Range (For T A =Full

3 12 3 12 V Fig. 3 - Typicarpropagation delay time VS.
CL for decoded outputs.
Clock Inhibit 5 500 - 700 - ns
Setup Time, ts 10 200 - 300 -

5 500 - 830 - ns
10 170 - 250 -
5 de 1 de 0.6
Clock I nput Frequency, tCl MHz
10 de 3 de 2
Clock Rise or Fall Time, trCl, ttCl

5 - 15 - 15
JJS
10 - 15 - 15
Reset Pulse Width, tw

5 500 - 830 - ns
10 165 - 250 - '0
LOAD CAPAellA.NeE (CLI-PF
Reset Removal Time

5 750 - 1000 - ns Fig. 4 - Typical propagation delay time vs. CL
10 225 - 275 - for carry output.
" .. alENT TEMPERATURE IT ... )· H"C BlENT TEMPERATURE ITAI· 2'"C

TYPICAL TEMPERATURE COEFFICIENT FOR
ALL VALUES OF VO O "O.3'1o'"C
PlCAL TEMPERATURE COEFflCIEN
300 FOR ALL VALUES Of v ·0.3 ... '"C
1~~~:'1\R.'~~ ..."': UllHm Il~
~ t! ~ ~; n
:;;;
I Ii::
U
IT
g
" , fili
'0 so 40
LOAD CAPACITANCE cell-II"
so 70 10 '0 30 40 3D
LOolD CAPACITANCE ICLI- pF
60 70 80 !W
SlA'L Y \/OLTSlVoo'
Fig. 5 - Typical transition time lIS. CL for Fig. 6 - Typical transition time vs. CL for
Fig. 7 - Typical clock input frequency iii. V DO.
decoded outputs. ca"youtput.
Test performed with the following

soquence of "1'5 and "O's" at each switch .
." S1
1
S2
1
S3
1
S1
0
S2
1
S3
0
0 0 0 0 0 0
0 1 0 0 1 0
0 0 0 0 0 0
0 1 0 0 1 0
0 0 0 0 0 0
0 1 0
10 10' .101 10·

INPUT CLOCK FREOUENC" IICLI- ~HI

Fig. 8 - Typica' dissipation characteristics.
509
CD4017 A Types

At T A =25°C, Input t"lf =20 ns, CL =15 pF, RL =200 kn
LIMITS
TEST
D,F,K,H E
PACKAGES PACKAGE
~ {VI MIN. TYP. MAX. MIN. TYP. MAX.
CLOCKED OPERATION
Propagation Delav
Time; tpHL tplH
5 - 350 1000 - 350 1300
Carry Out Line
10 - 125 250 - 125 300
nS
5 - 500 1200 - 500 1600
Decode Out Lines
10 - 200 400 - 200 500
Transition Time;
tTHl, tTlH
5 - 100 300 - 100 350
Carry Out Line
10 - 50 150 - 50 200
ns
5 - 300 900 - 300 1200
Decode Out Lines
10 - 125 350 - 125 450
Maximum Clock I.nput 5 1 2.5 - 0.6 2.5 -

MHz
Frequency, tCl 10 3 5 - 2 5 -
ns
Width, tw 10 - 100 170 - 100 250
Clock Rise & Fan Time; 5 - - 15 - - 15

I's
trCl, ttCl 10 - - 15 - - 15
Minimum Clock Inhibit 5 - 175 500 - 175 700

ns
Set·Up Time, ts
10 - 75 200 - 75 300
Average Input
Capacitance, C,
Any Input - 5 - - 5 - pF
RESET OPERATION
Propagation Delay
Time;tpHl
5 - 350 1000 - 350 1300
To Carry Out Li ne
10 - 125 250 - 125 300
ns
To Decode Out Lines
5 - 450 1200 - 450 1600
10 - 200 400 - 200 500
Minimum Reset Pulse 5 - 200 500 - 200 830
ns
Width, tw
10 - 100 165 - 100 250
Minimum Reset Removal 5 - 300 750 - 300 1000
ns
Time
10 - 100 225 - 100 275
Measured With respect to carry output line
510
CD4018A Types
CMOS Presettable Divide-By-'N' Counter ~

lliiotl. Voo
MI··S·OII"
The RCA·CD4018A types consist of 5 units. The counter is advanced one count at
Johnson·Counter stages, buffered 0 outputs the positive clock·signal transition. A high
from each stage, and counter preset control RESET signal clears the counter to an all·
gating. CLOCK, RESET, DATA, PRESET zero condition. A high PRESET·ENABLE CLOCK 14
ENABLE, and 5 individual JAM inputs are signal allows information on the JAM inputs
provided. Divide by 10,8,6,4, or 2 counter to preset the counter. Anti·lock gating is
configurations can be implemented by provided to assure the proper counting
feeding the OS, 04, 03, 02, 01 signals, sequence.
respectively, back to the DATA input.
Divide·by-9, 7, 5, or 3 counter configura- These types are supplied in 16-lead hermetic
tions can be implemented by the use of a dual-in-line ceramic packages (D and F
CD4011 A gate package to properly gate the CD401BA
age (E suffix), 16-lead ceramic flat package'
feedback connection to the DATA input. FUNCTIONAL DIAGRAM
(K suffix). and in chip form (H suffix),
Divide·by functions greater than 10 can be
achieved by use of multiple CD401BA
Features:
• Medium speed operation •..• 5 MHz (typ.)

atVOO-VSS= 10V
• Maximum input leakage current of 1 J.lA
at 15 V (full package-temperature range)
• l-V noisa margin (full package·temper-
ature range)
App/ications:
• Fixed and programmable divide-by-l0,
£\
9, 8, 7,6,5,4, 3, 2 counters
RES!T
• Fixed and programmable counters
00 greater than 10
TER».lHAL HO 8· GHO
• Programmable decade counters
• Oivide-by-"N" counters/frequency
*PROTECTED
ALL INPUTS ARE
BY synthesizers
COS/Mas PROTECTION • Frequency division
NETWORK 5
• Counter control/timers
vss Fig. 1 - Logic diagram.
j
("DATA" INPUT TIED TO aS FOR DECADE COUNTER CONFIGURATION) EXTERNAL CONNECTIONS FOR DIVIDE
BY 10. 9,8,7, 6, !I, 4, 3 OPERATION
CLOCK '\.rt rt~ r"lJ '\. "l ~ h- ~ "\. "'\. "lrt ~ ru "'\. "\.rt "\.r'\.. r"\. '\.r- DIVIDE BY 10
DIVIDE BY 8
DIVIDE BY 6
i)S]
o.
03
CONNECTED
~~;~iO
NO EXTERNAL
~~~~~:EEDNTS
RESET -1\ DIVIDE BY 4
DIVIDE BY 2
O2
iii
PRESET ri1 DIVIDE BY 9

1/2 C0401lA
~----Kl CONNECTED BACK TO "DATA"

~ (SKIPS "ALL-I'," STATE)
DON'T CARE UNTIL "PRESET" GOES HIGH

I DIVIDE BY 7
112 C0401lA
Jam3
~1. CONNECTED BACK TO "DATA"
-I-
~
L ___________ J
(SKIPS "ALL-I"" STATE)
-I- DIVIDE BY 5
1-1- _ r ___Yl_91..42.!!~ __ .,
' ,I
r-I-r-
i-f- ~ I CONNECTED BACK TO "OATA"
'""" ,...1- _
03 I ___________ .JI
L
I (SKIPS -ALL-I'." STATE)
.... DIVIDE BY 3
1/2 C0401lA
-, ,-----------"'1
~
_
I I
I
CONNECTED BACK TO "DATA"
(SKIPS "ALL-I"· STATE)
Qz I I
L _ _ _ _ _ _ _ _ _ _ .J 92CS-17071RZ
Fig. 3 - External connections for divide by 10,

Fig. 2 - Timing diagram. 92SS-4148R2 9, 8, 7, 6, 5, 4, 3, 2 operation.
511
CD4018A Types
STORAGE-TEMPERATURE RANGE (Tstg ) . . • . . . . • . . • . • • . . • • • • • . • . . • . . .-65 to +150 oC

OPERATING-TEIo.\PERATURE RANGE ITA): °
PACKAGE TYPES 0, F, K, H . • • • . • . . . . . . . • . . . '.' . • • • . • • . . . . . • -55 to +1250 C
PACKAGE TYPE E . . • • • • • • . • . • • . . . . . • . . . • . . • • . • • . • • • . • . • • -40 to +85 C
(Voltages referenced to Vss Terminal): . . . • . . • . • . • . . • . . . . . . • . • . • • • • • • -0.5 to +16 V ~
POWER DISSIPATION PER PACKAGE (PO)
FOR TA'-40to+60oC (PACKAGE TYPE E)
FOR TA= +60 to +85°C;.(PACKAGE TYPE E)
..•.••••••••.••••...•..••••• 500mW
.. '.' •••.. Dorate Linearly at 12 mW/OCto 200mW
FOR T A = -55 to +100·C (PACKAGE TYPES 0, F, K) •....•.••••••••••••••••• 500 mW
FOR TA = +100 to +125·C (PACKAGE TYPES 0, F, K)· . . . . . Derate Linearly at 12 mW/oC to 200mW
Ii LOAD CAPACITANCE 1ClI- pF

Fill- 4 - Typ/csl propagation dolay time VI.
FOR TA= FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) ...•••.•• 100 mW
load capacitance for decoded outputs.
INPUT VOLTAGE RANGE, ALL INPUTS • • . • • . . • . . . . . • . • . . • • • . • • • • -0.5 to VOO +0.5 V
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10. max •..•.•.•.••.•••. +285 0 C
AM81ENT TEMPERATURE ITAI- 25-C
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C. Input tr .tt = 20 ns.

TYPICAL TEMPERATURE fOR ALL
VALUES OF Vpo ·0.3""·C
Cl = 15 pF. Rl - 200 ten

LIMITS
..
,
TEST
D,F,K,H E
CONDITIONS
CHARACTERISTIC Packages Package UNITS
VDD
(V) Min. Typ. Max. Min. Typ. Max. .
,0
CLOCKED OPERATION
'0 20 70 00
Propagation De(ay Time; 5 - 350 1000 - 350 1300 LOAD CAPACITANCE IC .. I - pF
tPlH. tpHL
ToQ5 0utput 05 output.
10 - 125 250 - 125 300
ns
load capacitance for
To Other Outputs
5 - 500 1200 - 500 1600
10 - 200 400 - 200 500
Transition Time;
tTHL·lyLH
5 - 100 300 - 100 350
ns
To 05 Output 10 - 50 150 - 50 200
To Other Outputs
5 - 300 900 - 300 1200
ns
10 - 125 350 - 125 450
Frequency, tCL 10 3 5 - 2 5 -
Min. Clock Pulse Width. 5 - 200 500 - 200 830
ns
tw 10 - 100 170 - 100 250
.0
/JS
20 30
LOAD CAPACITANC[iCll-pr
trCL, ttCL 10 - - 15 - - 15 Fig. 6 - Typical transition time vs. load

Min: Data Input Set-Up 5 - 175 500 - 175 700
ns
capacirance for decoded outputs.
Time, ts 10 - 75 200 - 75 300
Average Input
Capacitance, CI
PRESET* OR RESET OPERATION

5 - 350 1000 - 350 1300
tpLH, tpHL
To 05 Output 10 - 125 250 - 125 300

ns
To Other Outputs
5 - 500 1200 - 500 1600
10 - 200 400 - 200 500
M in. Preset or Reset
Pulse Width
5 - 200 500 - 200 830
o 10 20 10 40 50 10 7 10
tw 10 - 100 165 - 100 250

ns
LOAD CAPACITANCE ICLI-"
Min. Preset or Reset 5 - 300 750 - 300 1000 Fig. 7- Typical tranlition time VI. losd
Removal Time 10 - 100 225 - 100 275 capacitance for 0'5 output.
• At PRESET ENABLE OR JAM Inputs.
512
CD4018A Types
RECOMMENDED OPERATING CONDITIONS at T A =2SoC, Except as Noted.
For maximum reliability. nominal operating conditions should be salected so that
liMITS
VDD D.F,K,H E UNITS
CHARACTER ISTIC ! ,
(VI Packages Package
Min. Max. Min. Max. L
3 12 3 12 V
ad 1
Data Setup Time. ts

5 500 - 700 - ns
I.
SUl'PLY \/OLTS(Vooi 92CS.IUI7
10 200 - 300 - Fig. 8 - Typical maximum input clock
Clock Pulse Width. tw

5 500 - 830 - ns
frequfJncy vs. supply voltage.
10 170 - 250 - 10 AMBIENT TEMPERATURE
INPUT I.' 1, • ZO nl
(TA)'Z~'C
5 de 1 de 0.6 MHz
10 de 3 de 2
Clock Rise and Fall Time. trCl, tfCl 5 - 15 - 15
JJS
10 - 15 - 15
Preset or Reset Pulse 5 500 - 830 -
Width, tw ns
•
10 165 - 250 -
LOAD CAPACITANCE iCLI'I~pF
--CL '~OpF
Preset or Reset Removal Time 5 750 - 1000 - ns
10 225 - 275 - 10 10 2 10'
INPUT CLOCk FREQUENCY IfCL)-kHI
104
92CS-178l,)~'
Fig. 9 - Typical dissipation characteristics

Voo
Limits It IndlCltlld Tlmpo'IW'" lOCI

VDD-~UTOOUTP~
v~
. T:
~
Conditions
D. F. K. H Packages E PlICbgtl
Vo VIN VOO +25 +25 NOTE
-55 +125 -40 -+65 Vss ~srNApNU~~C»ofBINATI~
!VI IVI IVI Typ. limit Typ. Limit
- - 5 5 0.3 5 300 50 0.5 50 700 Fig_ 10 - Noise-immunity test circuit
Quiescent Device
- - 10
Current I L Max.
- - 15
10
50
0.5
1
10 600
50 2000
100
500
1
5
100
500
1400
5000
JJA
VDD
Output Voltage: o Typ.; 0.05 Max.
Low Level,
- 5 5
Telt performed with
VOL - 10 10 oTyp.; 0.05 Max. the following sequence
V
High Level - 0 5 4.95 Min.; 5 Typ. of "1'5" and "O's" at
VOH - 0 10 9.95 Min.; 10 Typ. each switch.
Noise Immunity. 4.2 - 5 1.5 Min.; 2.25 Typ. 51 52 53 54 55 56 57
Inputs Low,
9 - 10 3 Min.; 4.5 Typ. '0
0 0 0 0
VNL V 0 0
1 0 0
VNH 1 - 10 3 Min.; 4.5 Typ.
0 0 0 0 0
Inputs Low, -
-=-I 'RI 0 1 0 0
g~CS 11~
0 1
VNML 9 - 10 1 Min. 1 0 0 1 0
V 0 0 0 1 0 0 0
- 0 0 0 0 0 0 0
VNMH 1 10 1 Min.
0 0 0 0 0
Output Drive
05
0.5 - 5 0.18 0.4 0.15 0.105 0.095 0.4 0.08 0.065
0 0 0 0 0 0
Current: - 0.45 1 0.35 0.25 0.3 1 0.25 0.2
0.5 10
n-Channel 0 0 0 0 0 0 0
01.0 2 0.5 - 5 0.06 0.1 0.05 0.035 0.03 0.1 0.025 0.02 Fig. 11 - Quiescent-device-current tsst circuit.
15ink)
ION Min. ih11t 0.5 - 10 0.25 0.4 0.2 0.14 0.18 0.4 0.15 0.12
rnA
4.5 - 5 ·0.185 ·0.4 -0.15 ·0.105 ·0.095 ·0.4 ·0.08 ·0.065 Voo
05
"'(]
p·Channel
(Source) 9.5 - 10 ·0.45 -1 ·0.35 ·0.25 ·0.3 ·1 ·0.25 ·0.2
lOP Min. 01.0 2 4.5 - 5 ·0.075 ·0.15 ·0.06 ·0.04 ·0.035 ·0.15 ·0.03 ·0.024 Voo NOTE
Ei3.~ 9.5 - 10 ·0.25 -0.4 ·0.2 -0.14 ·0.18 ·0.4 ·0.15 ·0.12 ~ MEASURE INPUTS
o SEQUENTIALLY,
Input Leakage Vos TO BOTH voo AND VSS
Current, - AT -I"!"'15 ±10- 5 Typ .• ±1 Max. IJA.

CONNECT ALL UNUSED
INPUTS TO EITHER
IlL. IIH Max. 1100 OR IISS'
vss
Fig. 12 - Input-leakage-current test circuit.
513
CD4019A Types
CMOS Quad ANDIOR Select Gate Features:

• Medium-speed operation __ . _ •
The RCA-CD4019A types are comprised of . - - tpHL = tpLH =50 ns (typ.1 at CL = 15 pF,
four AND/OR select gate configurations, VDD= 10V
each consisting of two 2-input AND gates • Quiescent current specified to 15 V
driving a single 2-input OR gate_ Selection • Maximum input leakage current of 1 IJA
is accomplished by control bits Ka and Kb- at 15 V (full package-temperature rangel
In addition to selection of either channel A • l-V noise margin (full package-temper-
or channel B information, the control bits ature range I
can be applied simultaneously to accomplish
the logical A + B function_
Applications:
These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (D and F • AND-OR select gating
suffixes), 16-lead dual-in-line plastic pack- • Shift-right!shift-Ieft registers
age (E suffix), 16-lead ceramic flat packages CD4019A
FUNCTIONAL DIAGRAM • True/complement selection
• AND/OR/Exclusive-OR selection
MAXIMUM RATINGS, AbsolulII-Maximum Values:
STORAGE-TEMPERATURE RANGE (Tug) . . . • . . . . . . . . • • . • • . • • • • . . • • •-6510 +150oC

OPERATING· TEMPERATURE RANGE ITA}:
PACKAGE TYPES D, F, K, H • . • • • . • . • • . . . • • . . . • • . • • . • . . • . • • • •-5510 +126 oC
PACKAGE TYPE E . . • . . . . • . . • . . . . • . . • . • . • . • . • . • • • • • • • • • • -4010 t86°C
DC SUPPLY-VOLTAGE RANGE. (Vool
(Vollage. referenced 10 Vss Terminall: . • . . . . . . • . . • • . • • • • . • • . • • . • • • -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PO)
FOR T A ~ -4010 +60oC (PACKAGE TYPE E' . . . . • . • . . • . . • • . • . . • • • • • • • 500 mW
FOR TA = +60 10 +85 0 C (PACKAGE TYPE E' . . . . . . Derate Linearlv al12 mW/oC to 200 mW
FOR T A = -55 to +100°CJPA~AC3E TYPES D, F, KC . • . • . . . . . • • . • • . • • • ,,' •• 500 mW
FOR T A = +100 to +125°C (PACKAGE TYPES 0, F, K) ..• Oerale Linearlv al 12 mWI C 10200 mW
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES' •.••••• 100 mW Fig. 2 - Typical propagation delay tim. v£ .
INPUT VOLTAGE RANGE. ALL INPUTS . . . . • • . . • • . . • • • . • • . • • • • . -0.510 VOD +0.5 V load cepecltstICtJ.
AI di'lance 1116 ± 1132 inch (1.59 ±0.79 mm) from case for 10. me•••••.••••..••. +266°C

LIMITS
VOO
D,F,K,H E
Packages Psckll(/ll
(VI
Min_ Max. Min. Max,
3 12 3 12 10 lO40 50 60 70
Package-Temperature Range) lO£O CAPACITANCE (Cll-pF
Voo
.,*
0>-----
Fig. 3 - Typical tran.ition time VI. load
capacitance,
~~'~IT"c! ceL' ;i... t!HI:...:t!:!E :::::
ADD
::::
;:: :Hit:"
:r
fvss -ALL INPUTS ARE

PROTECTED BY
COSIMOS PROTECTION
NETWORK
9255-4417 R 1 Fig. 4 -Maximum propagetion delay time v£

Fig. I - Schematic diagram for I of 4 identical.taga •. supply vo/tsge.
514
CD4019A Types
STATIC ELECTRICAL CHARACTERISTCS

'0'
Limits at Indic:atad Temperatures (DC) ."
Conditlonl
D, F, K, _H Packages E Package 00'
ChlrlC18rlltic Units
Vo VIN VDO +25 +25
-55 +125 -40 +85 '0'
(VI (VI (V) Typ. Limit Typ. Limit
Currant,1 L Max. - - 10 10 0.05 10 600 100 0.2 100 1400 IJA
LOAD CAPACITANCE ICLJ'I~pF
- - 15 50 1 50 2000 500 5 500 5000

- --Cl':iOpF
Output Voltage:
Low-Level,
- 5 5 oTyp.; 0.05 Max. 102
INPUT FREQU€NCY 1'.1- kHz
103 IO~
VOL - 10 10 oTyp.; 0.05 Max. V Fig. 5 - Typical dissipation charactIJri,tics.

High Level - 0 5 4.95 Min.; 5 Typ. (per output).
VOH - 0 10 9.95 Min.; 10 Typ.
Inputs Low,
VNL 7.2 - 10 3 Min.; 4.5 Typ.
...
V
Inputs High 1.4 - 5 1.5 Min.; 2.25 Typ. INPUTS
VNH 2.8 - 10 3 Min.; 4.5 Typ.
•
Noise Margin:
Inputs Low,
4.5 - 5 1 Min.
VNML 9 - 10 1 Min.
V
VNMH 1 10 1 Min.
Output Drive
Current:
n·Channel 0.5 - 5 0.6 0.9 0.45 0.3 0.37 1 0.3 0.23 Fig. 6 - Ouiflrcent·dtlvice-current test circuit.
(Sink)
ION'Min.
0.5 - 10 0.9 1.5 0.75 0.55 0.8 1.5 0.65 0.5
mA
p·Channel 4.5 - 5 -0.31 -0.5 -0.25 -0.175 -0_145 -0.5 -0.12 -0_095
(Source) :
IDPMin. 9_5 - 10 -0.95 -1.5 -0.7 -0.5 -0_6 -1.5 -0.5 -0_4 INPurOv"!'ourpurs
VOO-VNH .
input Leakage
Current,
IIL,IIH
- 1-
Any Init
16
±10-5 Typ., ±1 Max. IJA v~
'- ~
NOTE:
~
TEST ANY ONE INPUT,

9IlCS-l1400 Voo DRYsS'
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25°C, Inputtr , tf'" 20 nl, CL '" 15 pF,

RL-200k!l
Fig. 7 - Noise-immunity test circuit.
LIMITS
TEST D,F,K,H E
VDD
(V) Min. Typ. Max. Min. Typ_ Max_
Propagation Delay
Time;
5 - 100 225 - 100 300 Voo 'NPUOVDO NOTE:
ns
- ~
MEASUM INJiIUTS
tPLH. tpHL 10 50 100 - 50 125
Va
SEQUENTIALLY,
10 ICn'N Voo ANDVss
Transition Time; 5 - 100 200 - 100 275 CCNfICT ALLl.INIaID
M'Ul'S 10 EtT"ER
ns YooCIIYss'
lTHL,tTLH 10 - 40 65 - 40 80 Vss
Average Input
All AandB
Inputs
- 5 - - 5 - pF
Fig. 8 - Input-le.kBgtJ·current tim circuit.
Capacitance, CI
Ka and Kb
Inputs
- 12 - - 12 - pF
515
CD4020A Types
counter is reset to its all-zeroes state by a
CMOS high level on the RESET inverter input line.
'DD
14-Stage Ripple-Carry Each counter stage is a static master-slave

flip·flop. The counter is advanced one count 10
16
9
01
Binary Counter/Divider on the negative-going transition of each INPUT
PULSES
7
0' "
~
K
INPUT PULSE. • o. ~
..""
, 06 0
6 07 0
The RCA-CD4020 consists of a PU LSE 13 Q8
These types are supplied in 16-lead hermetic ,40STAGE
RIPPLE
COUNTER IZ Q9
INPUT shaping circuit, RESET line driver dual-in-line ceramic packages (D and F 14 010
I::
circuitry, and 14 ripple-carry binary counter suffixes), l6-lead dual-in-line plastic pack- IS 011
ill
stages. Buffered outputs are externally avail-
able from stages 1 and 4 through 14. The
age (E suffix). l6-lead ceramic flat package.
0"
O'S
'"
RESET " 0"

STORAGE-TEMPERATURE RANGE (Tstgl _ ................................. . Vss 92C$.25063A2
OPERATING-TEMPERATURE RANGE (TAl: CD4020A
PACKAGE TYPES D, F, K, H ........................................... . -5510 +125 0 C FUNCTIONAL DIAGRAM
PACKAGE TYPE E -4010 +S5 0 C
DC SUPPLY-VOLTAGE RANGE, (VDDI
(Voltages referenced to VSS Terminal) ...................................... -0.5 to +15 V
FOR T A = -40 to +600 C (PACKAGE TYPE E I . ......... ................. 500 mW
FOR TA = +60 to +85 0 C (PACKAGE TYPE E I ......... Derate Linearly a.12 mW/oC 10 200 mW
FOR T A = -55 to +100'C (PACKAGE TYPES D, F, K) .. .. .. . . .. . .. . . . .. . . .•. . 500 mW Features:
FOR T A = +100 to +125'C (PACKAGE TYPES D, F, K) ..... Dera.e Linearly al12 mW/oC '0 200 mW • Medium speed operation ...
DEVICE DISSIPATION PER OUTPUT TRANSISTOR 7 MHz (typ.) at VDO-VSS = 10 V
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPESI.... 100 mW • Low output impedance
INPUT VOL TAGE RANGE, ALL INPUTS ...................... _........... -0.5 10 V DD +0.5 V • Common reset
LEAD TEMPERATURE (DURING SOLDERINGI: • Fully static operation
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 105 max. . ........ . • Quiescent current specified to 15 V
• Maximum input leakage current of 1 JlA
RECOMMENDED OPERATING CONDITIONS at T A =25 0 C, Except as Noted. • 1-V noise margin (full package-temperature
For maximum reliabilitY, nominal operating conditions should be selected so that range)
operation is always within the following ranges'
LIMITS
D,F,K,H E Applications:
VDD Packages Package • Frequency-dividing circuits
(V) Min. Max. Min. Max. • Time-delay circuits
Supply-Voltage Range (For T A = Full • Counter control
3 12 3 12 V • Counting functions
Package-Temperature Range)
Input Pulse Width, tw

5 335 - 500 -
ns
10 125 - 165 -
5 dc 1.5 dc 1.5
Input Pulse Frequency, ftj; MHz
10 dc 4 dc 4
Input Pulse Rise or Fall Time, trtj;,tftj;

5 - 15 - 15
JlS
10 - 15 - 15
Reset Pulse Width, tw 5 2500 - 3000 - ns

10 475 - 550
INPUT
.....S<
s.....
0,] INPUTS TO
2nd STAGE
0,
• R-HIGH DOMINATES (RESETS ALL STAGES I
• ACTION OCCURS ON NEGATIVE GOING TRANSITION OF INPUT

PULSE. COUNTER ADVANCES ONE BINARY COUNT ON EACH
92CM-IIOI1112 NEGATIYE • TRANSITION 116.584 TOTAL BINARY COUNTSI.
Fig. 1-Logic diagram for 1 of 14 binary stages.
516
CD4020A Types
AMII(NT TtW'£lllATUM ITAI .. 2!1-C
TYPICAL n .. I"f.....TUIt[ COU1ICIon FOR 10" - 0.3'" rc
10
Fig. 3- Typical output n-channel drain charac-

teristics.
HOTE. SUBSTRATES FOR ALL "," UNITS AItt: COHNECl[O TO Voo

SUBSTRATES FDA ALL " .. " UNITS. UNLESS OTHERWI$[ SHOWN. AM CONfrtECl[O TO GI'OUNO .
• SUBSTRATES FOf' THESE " .. " UNITS ARE COHNfCT[O TOltfSlT llN[
GATE .. TO - SOURCE: VOLTS (Vo I" I~'+
Fig. 2 - Schematic diagram of pulse shapers and 1 of 14 binary stages.

limits at Indicated Temperatures (OC)
Conditions
Otaracteristic
Vo VIN VDD
(V) (V) (V)
-55
D, F, K, H Packages
Typ.
+25
limit
+125 -40
E Package
Typ.
+25
limit
+85
Units
10
! C~... PACKAG S
PLASTIC PACKAGES
I
Cuiescent
Device
- - 5 15 0.5 15 900 50 1 50 700 10 "
[IWN-TO-SOURCE VOl.TS IVos)
- - 10 25 1 25 1500 100 2 100 1400 /lA
Current,
- - 15 50 2.5 50 2000 500 5 500 5000
Il Max. Fig. 4-Minimum output n-channel drain charac-
teristics.
Output
Voltage:
low· level , - 5 5 o Typ.; 0.05 Max. DRAIH-TO-SOURCE VOLTS (VIlIS)
VOL 10 10 o Typ.; 0.05 Max. -IS -10
V
High-level, - 0 5 4.95 Min.; 5 Typ.
VOH - 0 10 9.95 Min.; 10 Typ.
-2 ~
Noise
Immunity:
Inputs low, 4.2
VNl 9
-
-
5
10
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
V
GATE-TO- SOURCE VOLTS t VGSI--I'
J
Inputs High, 0.8 - 5 1.5 Min.; 2.25 Typ.
VNH 1 - 10 3 Min.; 4.5 Typ. AMBIENT TEM,.ERATUAE ITA )-2s·C
TYPICAL T["'PERATURE COEFFICIENT FOR Io" -0.3111.'''C
Noise
Margin:
Inputs low, 4.5 - 5 1 Min. Fig. 5- Tvpical output p-channel drain charac-
9 - 10 1 Min. teristics.
VNMl
V
VNMH 1 - 10 1 Min.
DRAIN-TO- SOU'tCl VOlTS IVos I
Output -10
Drive Cur-
rent:
N-Channel
(Sink).
0.5 - 5 0.09 0.2 0.075 0.05 0.09 0.33 0.08 0.065 1 ~
IDN Min.
0.5 - 10 0.185 0.4 0.15 0.105 0.16 0.5 0.10 0.10
rnA
P-Channel
(Source)
IDP Min.
4.5
9.5
-
-
5
10
-0.11 -0.25 -0.09 -0.065 -0.09 -0.25 -0.06 -0.05
-0.25 -0.5 -0.20 -0.14 -0.18 -0.5 -0.15 -0.12 J
Input Any Input
leakage
15 ±10-5 Typ., ±1 Max. /lA
Current,
Ill,IIH
-1-1 Fig. 6-Minimum output p-channe! drain charac-
teristics.
517
CD4020A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =25 0 C, Input tr,t, - 20 ns,
Cl =15 pF, Rl 200 kn
LIMITS
CHARACTER ISTIC
TEST D,F,k,H E
UNITS
CONDITIONS Packages Package
VDD
Clocked Operation
Propagation Delay
Time.*
5 - 450 600 - 450 650
ns
10 - 150 225 - 150 250 LOAD CAPACITANCE
tpLH. tpHL
Transition Time, 5 - 450 600 - 450 650
ns
Fig. 7- Typical propagation delay time vs. CL •
tTHL' tTLH 10 - 200 300 - 200 350
Maximum Input Pulse 5 1.5 2.5 - 1.5 2.5 - MHz
Frequency, f I/l 10 4 6 - 4 6
Minimum Input Pulse 5 - 200 335 - 200 500
ns
Width, tw 10 - 70 125 - 70 165
Input Pulse Rise & 5 - - 15 - - 15
jJ.s
Fall Time, tr<J>,tf<J> 10 - - 15 - - 15
Average Input
Capacitance, CI
Any Input - - 5 - - 5 pF
Reset Operation
Propagation Delay
Time,' 5 - 2000 3000 - 2000 3500
ns
tpHL
10 - 500 775 - 500 300
Minimum Reset Pulse

Width,
5 - 1800 2500 - 1800 3000
ns Fig. B-Typical transition time va. CL -
tw
10 - 300 475 - 300 550
* Propagation delay is from input pulse to 01 output.
10 AMBIENT TEMPERATUR( (TAI'2~·C
':. 10'
YDO
I
YDO
:i'
~ 10·
~ IO J ~t-- - t--
.
Yss
INPUTS
r '0'
LOAO CAPACITANCE tcLl.l~pF
- --CL"SOpF
'0' IO~ 10' 10' '0' Yss

INPUT f'IiI[QU[M;Y U.,I-Hr
Fig. 9- Typical clock input frequency .s. VDO' Fig. 10- Typical dissipation characteristics, Fig. 1 1-Quiescent-device-current test circuit.
'NPUTQYDO
OUTPUTS
DO
'NP(JUS
Y NOTE:
.
VOO-VNH
YDD
..........
VNL
~- _
'--"i"---
o ~
MEASURE INPUTS
SEQUENTIALLY,
Vss TO BOTH VDO AND Vas
CONNECT ALL IMI..SED
NOTE: IfIIUI'S TO EfTH!"
Vss TEST ANY COMBINAnON VDDCRYSS'
OF INPUTS V55
nCS-27441
Fig. 12-Noise-immunity test circuit. Fig. 13-Input-leakage-current test circuit.
518
CD4021 A Types
CMOS a-Stage Static Shift Register

Asynchronous Parallel Input/Serial Output,
Synchronous Serial Input/Serial Output
~::.--2.
Features: CONT.
SER ...
The RCA·C04021A types are 8·stage paral· • Asynchronous parallel or synchronous serial operation IN·
lei or serial·inputlserial·output shift registers under control of parallel/serial control·input CLOCK!Q.

having common CLOCK and PARALLEL/ • Individual JAM inputs to each register stage
SERIAL CONTROL inputs, a single SER· • Master-slave flip·flop register stages
IAL OATA input, and individual parallel • Fully static operation ...... DC to 5 MHz
Vss•
Jam inputs to each register stage. Each regis· • Quiescent current specified to 15 V
ter stage is a O·type, master·slave flip·flop. • Maximum input leakage .current of 1 p.A
C04021A
Q outputs are available from the sixth, at 15 V (full package·temperature range)
FUNCTIONAL DIAGRAM
seventh, and eighth stages. • 1·V noise margin Ifull package·temper·
ature range)
When the PARALLEL/SERIAL CONTROL tional C04021A packages.
input is low, data are serially shifted into When the PARALLEl/SERIAL CONTROL
the 8·stage register synchronously with the input is high, data are jammed into the 8· These types are supplied in 16-lead hermetic
positive·going transition of the CLOCK stage register via the parallel input lines asyn· dual-in-line ceramic packages (0 and F
pulse. chronously with the clock line. suffixes), 16-lead dual-in-line plastic pack-
age (Esuffix), 16-lead ceramic flat package
Register expansion is possible using addi·
I

Applications:
LIMITS AT INDICATED TEMPERATURES (DCI • Parallel to serial data conversion
CONDITIONS • Asynchronous parallel input/serial output
0, F, K, H PACKAGES E PACKAGE
CHARACTERISTICS UNITS data queueing
Vo V IN V DD +25 +25
(V) (V) (V)
-55 +125 -40 +85 • General purpose register
TYP. LIMIT TYP. LIMIT
- - 5 5 0.5 5 300 50 0.5 50 700

Quiescent Device
Current IL Max.
- - 10 10 1 10 600 100 1 100 1400 IlA
- - 15 50 1 50 2000 500 5 500 5000
Output Voltage:
Low·Level,
- 5 5 o Typ.; 0.05 Max.
VOL
- 10 10 o Typ.; 0.05 Max.
V
High Level - 0 5 4.95 Min.; 5 typo
V OH
- 0 10 9.95 Min.; 10 Typ.
Noise Immunity; 4.2 - 5 1.5 Min.; 2.25 Typ.
Inputs Low,
V NL 9 - 10 3 Min.; 4.5 Typ.
'0
Sl.PPLY VOLTSIVooI
V
V NH 1 - 10 3 Min.; 4.5 Typ. Fig. 1 - Typical clock input frequency va.
Noise Margin: supply vo/rage.
4.5 - 5 1 Min.
Inputs Low,
V NML 9 - 10 1 Min.
V AMBIENT T[M'EAAruRE IT A J - 25-C:
Inputs High, 0.5 - 5 1 Min. TYPICAL TEMPERATURE COEFFICIENT FOR
V NMH ALL VALUES OF Voo - O.3~"·C
1 - 10 1 Min.
Output Drive
Current:
N·Channel
(Sink), 0.5 - 5 0.15 0.3 0.12 0.085 0.072 0.3 0.06 0.05
ION Miri. 0.5 - 10 0.31 0.5 0.25 0.175 0.12 0.5 0.1 0.08
mA
P·Channel
(Source) 4.5 - 5 -0.1 -0.16 -0.08 -0.055 -0.06 -0.16 -0.05 -0.04 "
I-Il-t tll
lOP Min. 9.5 - 10 -0.25 -0.44 -0.20 -0.14 -0.12 -0.44 -0.1 -0.08
'0 50 10 70 110
LOAO CAPACITANCE tCLI-"
Input Leakage
Current,
TinT Fig. 2 - Typical propll/lBtion dO/BY timo v&.
IIL,IIH - - 15 ±1 0- 5 Typ., ± 1 Max.
load capscitBnce.
519
CD4021 A Types
MAXIMUM RATINGS, Absolute·Maximum Values: ""'IEHT U:UPERArURE ITAI. uee
TYPICAL TEMPERATURE COEFfiCIENT FOR
STORAGE·TEMPERATURE RANGE ITstgl • . . . . . . . . • • • . . . . . . . . • . • • • • • -65 to +150°C ALL VALUES OF' Voo. 0,3"'" Ie\:
OPERATlNG·TEMPERATURE RANGE (TA)

PACKAGE TYPES D, F, K, H ., . . . . . . . . . . . . . . . • . . . . . . • • . • • • . . • • .-65 to +125°C
PACKAGE TYPE
E
(Voltages referenced to VSS Terminal) . . . . .

-40 to +85°C
-0.5 to +15 V
" .
POWER DISSIPATION PER PACKAGE (PDI
FOR T A = -40 to +60°C IPACKAGE TYPE EI . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
FOR TA = +60 to +85°C IPACKAGE TYPE E I . . . . • . Derate Linearly at 12 mWfC to 200 mW
FOR T A = -5510 .IOO°C (PACKAGE TYPES D, F, K) • . . . . . . . . • . . • . • . . . • • . • • 500 mW 70 .0
LOAD CAPACITANCE lel' - pF 'lZcs.,reOI
FOR T A = +100 to +125°C (PACKAGE TYPES D, F, K) .•. Derate Linearly at '2 mWfC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR Fig. 3 - Typical transition time v.s.
FOR TA = FULL PACKAGE·TEMPERATURE RANGE IALL PACKAGE TYPESI . . . • . • . 100 mW load capacitance.
INPUT VOLTAGE RANGE, ALLINPUTS • . . . . . . . . . . . . . . • . . . . . • . • • -0.5 to VDD +0.5 V
- LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mmt from case for 10 5 max. . . . . . . . . . . . . .. +265°C
PARALLEL PI-2 PI-6 PI-1 PI-S
.
INPUT-I 106 AMBIENT TEMP[l:IATUR[ ITA)'2$"'
PARALLEL! ALTERNATING '0'
SERIAL 7
;r. AND -I' PATTERN
CONTROL ~,
~ -
PI
i 10· _
~KJ)~E
4 - STAGES
SAME AS STAGE I 1 Cl CL :: 10 2
1i
I
~ ~ 10 LOAD CAPACITANCE tCL,.t,pF
----CL·~pF
CLOCK
10*
Voo =- TERMINAL 16
Vss" TERMINAL 8
Fig. 4 - Typical dissipation
characteristics.
06 07 08
92CM
RECOMMENDED OPERATING CONDITIONS at TA = 25·C, Except as Noted.

TRUTH TABLE operation is always within the following ranges:
Parallell
Serial Serial 0, LIMITS
CL A Input Control PI·' PI·n (Internal) an
x x , 0 0 0 0 CHARACTERISTIC VDD E UNITS
X X , 0 , 0 , (VI
D,F,K,H
PACKAGES PACKAGE
X X , I 0 1 0
X X , 1 , 1 1 MIN. MAX. MIN. MAX.
.r
.r
0 0
0
X X 0 on- 1
On,l Supply·Voltage Range (For TA=Full
12 12
1 X X 1 3 3 V
\.... X 0 X X 0, an
A" LEVEL CHANGE X = DON'T CARE CASE
5 350 - 500 - ns
NO CHANGE 92CS-17141R3 Data Setup Time, ts
10 80 - 100 -
Fig. 6 - Truth table.
5 500 - 830 -
Clock Pulse Width, tw 10 175 - 200 - ns
5 de 1 de 0.6
10 de 3 de 2.5
Clock Rise and Fall Time, trCl, tfCl

5 - 15 - 15
j.ls
10 - 5 - 5
*'f more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time
520
CD4021 A Types
at TA = 2t;OC, Input t" tf= 20ns, CL = 15 pF, RL = 200kfJ.
liMITS
TEST
D,F,K,H E UNITS
CHARACTERISTIC CONDITIONS
PACKAGES PACKAGE
VDD
(VI MIN. TYP. MAX. MIN. TYP. MAX. t2CS-21441

ns
Fig. 7 - Noise-immunitv test circuit.
Time'"
tPLH. tPHl 10 - 100 225 - 300 300
Transition Time; 5 - 150 300 - 150 400

ns Test performed with the following sequence
of .. Ona· ... and .. Z.ro· ....
~Hl,tTlH 10 - 75 125 - 75 150
SI 82838485
Maximum Clock Input 5 1 2.5 - 0.6 2.5 - 00100
MHz
Frequency, fCl 10 3 5 - 2.5 5 - 1 0
1
1 1
0 1 0
o
ns
000 0
1 1
Width, tw 10 - 100 175 - 100 200 VDD
5 - - 15 - - 15
Clock Rise & Fall
Time;trCl & ttcl' 10
5
-
-
-
100 350
5 -
-
-
100 500
5
/lS
I
Minimum Data Set
ns
UpTime, ts 10 - 50 80 - 50 100
Minimum High·level
ParallellSerial 5 - 200 500 - 200 830
ns
Control Pulse 10 - 100 175 - 100 200
Width 1W
92CS 1792C'RI
Input Capacitance CI Any Input - 5 - - 5 - pF Fig. 8 - Quiescent device current test circuit.
-If more than one unit is cascaded treL should be made less than or equal to the sum of the transition time
""From Clock or Parallel/Serial Control Input
PI Pi5*
V~fi\-~NP(JUS
o ~
VDO :~:~U.[ 1.""T5
SEQUENTIALLY,
Yss TO 80TH Yoa ANDVss·
CONNECT All UNUSED
IHP1JTS TO [ITH[R
Vee ORVSS
V55
Fig. 9 - Input4eakage-current
test circuit.
CL
1i ,
I
s:~q,
',7,.'
I
ONLY
Fig. 10 - One typical srage and iU equivalent detailed circuit.
521
CD4022A Types
CMOS Divide-By-8
Counter/Divider
With 8 Decoded Outputs
The RCA-C04022A types consist of a 4- and go high only at their respective decoded
stage divide-by-8 Johnson counter, associ- time slot. Each decode gate output remains
ate decode output gating and a CARRY- high for one full clock cycle. The CARRY-
OUT BIT. The counter is cleared to its zero OUT signal completes one cycle every 8
count by a high RESET signal. The counter CLOCK-INPUT cycles and is used as 8
is advanced on the positive CLOCK-signal ripple-carry signal to directly clock a suc-
transition provided the CLOCK INHIBIT ceeding counter package in a multi-packege
signal is low. counting system.
Use of the Johnson divide-by-8 counter These types are supplied in 16-lead hermetic
configuration permits high-speed operation, dual-in-line ceramic packages (0 and F
2-input decode gating, and spike-free de- suffixes). 16-lead dual-in-line plastic pack-
coder outputs. Anti-lock gating is providpd, age (E suffix). 16-lead ceramic flat package
thus assuring proper counting sequence. The (K suffix). and in chip form (H suffix).
8 decode gating outputs are normally low
Features:
• Madium speed operation ..•. 5 MHz (typ.) at

MAXIMUM RATINGS, Absolute-Maximum Values: VOO - VSS = 10 V
• Divide by N counting; N =2 to 8 with one
STORAGE·TEMPERATURE RANGE (Tstg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150 oC
C04022A plus one CD4001A package
PACKAGE TYPES D. F. K. H . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .-55 to +125 0 C • Quiescent current specified to 15 V
PACKAGE TYPE E . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . • . . . -40 to +8SoC • Maximum input leakage current of 1 [JA
DC SUPPLY-VOLTAGE RANGE. (VDD) at 15 V (full package-temperature range)
(Voltagesraloronced to VSS Torminol!: . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +15 V • I-V noise margin (full package-temper-
POWER DISSIPATION PER PACKAGE (PO) ature range)
FOR TA= -40 to +60 oC (PACKAGE TYPE E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
FOR TA= +60 to +8SoC (PACKAGE TYPE E' . . . . . . . . . Dorato Linaarly at 12 mW/oC to 200 mW
FOR T A = -55 to +100'C (PACKAGE TYPES D. F. K) . . . . . . . . . . . . . . . . . . . . . 500 mW Applications:
FOR T A = +100 to +125'C (PACKAGE TYPES D. F. K) . . . . • Dorato Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR • Binary counting/decoding
FOR TA= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . . . . . . . . . 100 mW • Binary frequency division
INPUT VOLTAGE RANGE. ALL INPUTS . . . • . • . . • . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5 V • Binary counter control/timers
At distanco 1/16 ± 1132 inch (t .59 ±0.79 mm) Irom case lor 10 s max . . . . . . . . . . . . . . . . +265 0 C
RECOMMENDED OPERATING E:ONDITIONS at T A = 25°C, Except 8S Notad.

LIMITS
VOD D,F,K,H E UNITS
CHARACTERISTIC
(V) Packages Package
Min. Max. Min. Max.
Supply-Voltage Range (For T A = Full
Package-Temperature Range) 3 12 3 12 V

Setup Time, ts 10 75 - 75 -
5 500 - 830 - ns
10 170 - 250 -
5 dc 1 dc 0.6
10 dc 3 dc 2
Clock Rise and Fall Time, trCl, 'tCl 5 - 15 - 15

/-IS
10 - 15 - 15
I Reset Pulse Width

6 300 - 600 - ns
10 150 - 300
Reset Removal Time

5 752 - 1000 - ns
10 225 - 275 -
522
CD4022A Types
CLOCK
RESET .\.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
i~T ____________ -J,---,~ ________
"0" ---o\'--_ _ _ _ _ _..Jm'--_ _ _ _ _ _ _ _ _roL-
"," -fT1 m'-_________-'rr
·2" ---.fT\ r----2\'-_ _ _ _ _ _ __
·3' _ _ _ -Jf31'-________--Jnnl..-_ _ _ _ __
·4' f4I f4l'-_ _ _ _ __
"5' __________ ~nn nn~ _____
"6" ____________ ~nn ~
:::::::::=L======~r7'~7J::::::::::::=L======~~~7
"7"
~~y r--
.SS-4~7R2
Fig. 2 - Timing dlBf/rsm.
r AaeENT T[MPERATURE ITAI. 2~·C

TVPlCAL n:MP[AATUltE COEFFICIENT FOR
} WLUfS CW VDD • O]~;·ln!tfm
-ALL INPUTS ARE PROTECTED BY

COSJMOS PROTECTION NETWORK
Fig. 1 - Logic diBf/rsm.

I
20 '0 60 .0
LOAD CAPACITANCE eel 1- ,F
Fig. 3 - Typical pro_tJon dB/ay rimB .,.

STATIC ELECTRICAL CHARACTERtSTICS load capacitance for d.codsd outputr.
Limits. Indla8tM TIIIIIIIN\II. . (oC)

Conditt..
a...-rlode
Vo VIN VDD
(V) IVi (VI -&&
D, F, K, H Packages
+21
Typ. Umlt
+121 -40
E Pck.,.
+21
Typ. Umlt
...
Units
- - & & 0.3 & 300 60 0.& &0 700

QulalCOnt Device
Currant Ii. Max. -- -- 10 10
1& &0
0.&
1
10 800
&0 2000 &00
100 1
&
100 1400 pA
600 &000
Output Voltage:
Low Level - 6 & oTyp.; 0.0& MIX.
VOL - 10 10 oTyp.; 0.0& MIX.
V
High Level - 0 & 4.96 Min.; &Typ.
VOH - 0 10 9.9& Min.; 10 Typ.
Noise Immunity:
Inputl Low,
4.2 - & 1.5 Min.; 2.25 Typ.
Fig. 4 - Typicel pr_etlon delay time ...
VNL 9 - 10 3 Min.; 4.5 Typ.
V load capacitance for carry output.
InputlHlgh 0.8 - 5 1.5 Min.; 2.26 Typ.
VNH 1 - 10 3 Min.; 4.5 Typ.
Noise Mlrgin:
Inputs Low,
4.5 - 5 1 Min.
VNML 9 - 10 1 Min.
\}
Inputs High, 0.& - & 1 Min.
VNMH 1 - 10 1 Min.
Output Drive Decoded 0.& - 5 0.082 0.1& 0.0& 0.03& 0.03 0.1& 0.02& 0.02
Current:
...Chlnnel
OUtputl 0.5 - 10 0.12 0.3 0.1 0.07. 0.08 0.3 0.115 G.04
(Sink) Carry 0.5 - 5 0.186 0.5 0.1& 0.10& 0.119& 0.& 0.08 O.llB&
ION Min. Output 0.5 - 10 0.37& 1 0.3 0.21 0.1&& 1 0.13 0.10&
I
mA
Decoded 4.& - 5 -O.03B ·0.07& -0.03 -0.021 -0.018 -0.075 -0.01& -0.012
p-Chlnnol Outputs 9.& - 10 -0.12 -0.15 -0.1 -0.07 ·0.08 -0.15 -0.0& -0.04
(Source):
lOP Min.
Corry 4.5 - 6 ·0.186 -0.4 -0.15 ·0.10& -0.096 ·0.4 ·0.08 ·0.086
OUtput 9.& - 10 -0.375 -0.8 -0.3 ·0.21 -0.1&& ·0.8 -0.13 -0.10&
~T ~rl&
Input LeakBf/l
Current, ±IO-& Typ., ±1 Max. pA Fig. 6 - Typical trBnlltlon tim• ... load
IIL,IIH capacitanea for dacodBd outputr.
523
CD4022A Types
DYNAMIC ELECTRICAL CHARACTERISTICS lit TA - aOc, Input Ir ,It - 20 n.,
CL -15pF,RL -2ookn
LIMITS
TEST D,F,K,H E
CHARACTERISTIC CONDITIONS Packages Psckllflll UNITS
Voo Min. Typ. Mu. Min. Typ. Mu.
M
CLOCKED OPERATION
Propagation Delay Time: 5 - 325 1000 - 325 1:m ns
arry·~LH
tpJlL' ut Line 10 - 125 250 - 125 500
Fig. 6 - Typical tran.itlon time n. load
Decode Out Lines 5 - 400 1200 - 400 1600
ns
capacitllnCII for carry output.
10 - 200 400 - 200 800
Transition Time:
trHL, trLH
5 - 85 300 - 85 340
ns
Carry·Out Line 10 - 50 100 - 50 200
Decode·Out Lines 5
10
-- 300
125
900
250
-
-
300 1200
125 500
ns
Min. Clock 5 - 250 500 - 250 830

ns
Pulse Width, tw 10 - 85 171) - 85 250
Clock Rise and
Fall Time, 5 - - 15 - - 15
/J.S
trCL ,'tCL 10 - - 15 - - 15
Min. Clock Inhibit 5 175 350 175 700
Set·Up Time, ns
ts 10 75 150 75 300 Fig. 7 - Typical clock input frsqu.ncy VI.
Max. Clock Input 5 1 2.5 - 0.6 2.5 - MHz
,upply voltage.
Frequency, fCL' 10 3 5 - 2 5 -
Input Capacitance, CI Any Input - 5 - - 5 - pF 10 ....IIIENT TEMPERATURE tT"I'25'C
RESET OPERATION • INPUT t,'lt~201l'
i 00'
Propagation Delay Time: 5 - 300 900 - 300 1200 ;p
tPHL, tPLH
Carry·Out Line 10 - 125 250 - 125 500
ns i 10·
~
Decode·Out Line 5 - 500 1250 - 500 2500
ns
D'
10 - 200 400 - 200 800

Min. Reset Pulse 5 - 150 300 - 150 600
ns
Width,tw 10 - 75 150 -. 75 300 LOAD CAMeITANCE tCl"15pF
- - - - CL '50pF
Min. Reset 5 - 300 752 - 300 1000 ns 102

Removal Time 10 - 100 225 - 100 275
10 lOS
INPUT CLOCK FI'IEOUEfrtCy IICLI- ktb
10·
... Measured with respect to carry output line Fig. 8 - Typical dissipstion characteristics.
VDD
INPUTS
V~ ~NP(Jus
VDO :~:~URE INPUTS
o
Vss
10PUTOVII> OUTPUTS
vDO-:::'" -!@
V.:'L I:" o ~
Vss
S£QUENTIALLY,
TO BOTH Voo AND Yss'
CONNECT ALL UNUSED
INPUTS TO EITHER
NOTE:
"00 OR Yss·
Yss ~N.,~~c.l".TION
Vss V5S
tzCS-ZT441
Fig. 9 - Qui,scent-d,t/;ceacurrsnt re.t circuit. Fi9. to - Noilll-immunity test circuit. Fig_ 11 - Input-leakage-current telt circuit
524
CD4024A Types
CMOS 7-Stage Binary Counter "00

14
With Buffered Reset

INPUT I
PULlI!I
The RCA-CD4024A consists of an INPUT
PULSE shaping circuit, RESET line driver
.. !S[T
circuitry, and seven binary counter stages_
The counter is reset to "zero" by a high level
on the RESET input_ Each counter stage is a
static master-slave flip-flop_ The counter
state is advanced one count on the negative- *ALL INPUTS ARE
PROTECTED ey
going transition of each INPUT PUlSE_ CDSI MOS PROTEe nON
NETWORK
VII '.tel-2150GIRI
These types are supplied in 14-lead hermetic Fig. 1 - Functiona'diag,am fo, C04024AO,
dual-in-line ceramic packages (D and F AE,AF,
age (E suffix), 12-lead hermetic TO-5-style
package (T suffix) 14-lead ceramic flat pack-
ages (K suffix). and in chip form (H suffix)_
Applications: INPUT I
4
PlILSES
• Frequency-dividing circuits
RESET:S .,.,
Q,
• Time-delay circuiu
• Counter control 00
Q,
• D/A counter and switch on one chip RESET
*AL.L INPUTS ARE -- Fig. 2 - Functional diagram
PROTECTED BY
COS I MOS PROTEC TION
NETWORK
fa, CD4024A T. '"
1l2CS-2!)OS2
MAXIMUM RATINGS,AbsoluIl1-MBximum VBlues: vss

STORAGE-TEMPERATURE RANGE ITstgl . __ ... __ • . . . . . . . • • . • _ . . . . . . • . -65 to +150 oC
OPERATING-TEMPERATURE RANGE {TAl:
PACKAGE TYPES (0, F, K, T, H) . . • . . • . _ ..• _ . . • . . . . . • . • . . . . . . _ .• -55 to + 125°C
PACKAGE TYPE E .
.. _ . . • . • . . . _ . • • • . . • . . __ ••••....•• _ ••.•. -40 to +85 C °
DC SUPPLY-VOLTAGE RANGE. {VDDI Features:
(Voltages ,efa,enced to Vss Ta,minat): . . . . . . . . • . • . . . . . • . . . . . . . • . . • . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (PO) D Medium-speed operation ....
FOR TA=-4Oto+60oC {PACKAGE TYPE EI . . • • . . • . . . . • • . . . . . . . • . . . • . . • 5OOmW .. 7-MHz (typ.) input pulsa rate at
FOR TA= +60 to +85 0 C {PACKAGE TYPE E I . . • . • . . . . De,a.. Linaa,ly at 12 mW/oC to 200 mW
VOD - VSS = 10 V
FOR TA = -55 to +100·C (PACKAGE TYPES 0, F, ;T) K . • . . . . . . . • • . • • • . . . . • . • 500 mW
• low high-and-Iow level output impedance
FOR TA = +100 to +125·C (PACKAGE TYPES 0, F, K,T) •... De,ate,Linea,lyat 12 mW/oC to 200 mW __ 700n and 500n (typ.), respectively at
VOO-VSS=10V
FOR TA= FULL PACKAGE-TEMPERATURE RANGE IALL PACKAGE TYPESI . . . . . . . • • 100 mW
INPUT VOLTAGE RANGE. ALL INPUTS . . . . • • • • • . . . . • . . • . . . • . . • . . -0.5 to VDD +0.5 V • Fully static operation
LEAD TEMPERATURE {DURING SOLDERINGI: • Common reset
At distanca 1/16 ±1/32 inch (1.59 ±0.79 mm) from case 1o, 10. max . . . • . • . . . . . . • . • . +265 0 C • Quiescent current specified to 15 V
• Maximum input leakage current of 1 p.A
RECOMMENDED OPERATING CONOITIONS at TA = 25°C, Except as Noted. • 1-V noise margin (full package-temper-
For maximum reliability, nominal operating conditions should be salected so that ature range I
operation is always within the following ranges.
liMITS
CHARACTE R ISTIC VOO D,F,K, T,H E UNITS
(V) Packages Package
Min. Max. Min, Max.
Supply-Voltage Range (For T A = Full
Package-Temperature Range) 3 12 3 12 V
Clock Pulse Width, tw 5 330 - 500 - ns

10 125 - 165 -
Clock Input Frequency, fCl 5
10
dc
dc
1.5
4
dc
dc
1
3
MHz .
DR....N-TO-SOURCE VOLTS (VDsl
Clock Rise or Fall Time, trCl, tfCl 5 15 - 15 - j.IS Fig. 3 - Typical output n-channel drain
10 15 - 15 - characteristics.
Reset Pulse Width, tw 5 500 - 600 -
ns
10 300 - 350 -
525
CD4024A Types
Llmltlllt IndlCllted T.mpel'll...... (DC)

Conditions
D, F, K, ~, H Packages E PlICkllflll
Ch.racterlstlc Unltl
Vo VIN VOO -6& +25 +125 -40 +25
+86
CVI CVI (V) Typ. Limit Typ. Limit
Quiescent Device 6 - -6 0.3 6 300 60 0.6 60 700
Current ,IL Max 10- -
10 0.6 10 600 100 1 100 1400 pA
16 - -
60 1 60 2000 600 6 600 5000
Output Voltage:
Low·Level,
6 6 - oTyp.; 0.05 Max.
VOL 10 10 - oTyp.; 0.06 Max. V
High Level, 0 6 - 4.96 Min.; 6 Typ. Fig. 4 - Typic" output p_1HI1 drain
VOH 0 10- 9.96 Min.; 10 Typ. chareterl,rIt:&
Noise Immunity:
Inputs Low,
4.2 5 - 1.5 Min.; 2.26 Typ.
VNL 9 10 - 3 Min.; 4.& Typ.
V
Inputs High, 0.8 5 - 1.6 Min.; 2.26 Typ.
VNH 1 10 - 3 Min.; 4.6 Typ.
Noise Margin:
Inputs Low,
4.6 6 - 1 Min.
VNML 9 10 - 1 Min. V
Inputs High, 0.6 6 - 1 Min.
VNMH 1 10 - 1 Min.
Output Drive
Current:
n·Channel
(Sink),
0.6 -
6 0.31 0.5 0.26 0.176 0.16 0.6 0.12 0.096
D
DbIN·TO-~
10 II
VOLTS (Y DI J

ION Min.
0.6 10 0.62 1 - 0.6 0.36 0.31 1 0.26 0.2
mA
chllrtlClllrlltlcs.
p·Channel
(Source)
4.6 - 6 ·0.19 ·0.3. ·0.16 ·0.106 ·0.146 ·0.3 ·0.12 ·0.096
lOP Min. 9.6 - 10 ·0.46 ·0.7 ·0.36 ·0.26 ·0.31 ·0.7 ·0.26 ·0.2
Input Leakage
Current, -Anr -Inr15 ±10-6 Typ.; ±1 Max. pA
IIL,IIH
Q'}lNPl.!ts 10
_ , .. ,'AGE 'ZCI-!907tR'
'-~-~Q,
Fig. 6 - Minimum output p-chllnn" drain
chMIICtrlri,ticr.
••• NIGH DOMINions {lESETS ALL IT"IiEU

-ACTION OCCUltS ON NIEGATIVI GOING ' .... NIITION Of IMPUT PULSE ~ 92(111-19071
f,~~~t:=~=:~'r'" COUNT ON EACH NfGATIVE • 'R"NSITION
EQUA TlOIIS FOR STAGES Z TO 7

0ZOUT' (OZKOI)(iKII) 05Ol.lT· (QSKOIHOZM01IIO,Ki)(lh
! •
0lOUT = (O)MOIKOZK.)(II) 060UT' (0,)(0IKOZK01KO,KOSKiKIII
0IOUT • (a,)(01)(OZK01K~(iil 0IOUT • (Q7KOIKOZK01KO.KOsK06K:)(Ii)
Fig. 7 - Logic block dillflTBm Ipul.,h_r LOAD CAMCITANCE leL.-.... nCS-11IIO
and 1 binary It/J(/fl). Fig. 8 - Typic" proPlIIJlltion dilley timtl ... CL•
526
CD4024A Types
DYNAMIC ELECTRICAL CHARACTERISTICS 8t TA = 25°C, Input t" tt = 20 nl,
CL =15pF,RL =200kSl
LIMITS
TEST D,F,K, T,H E
CONDITIONS Packages Package UNITS
CHARACTERISTIC
VDD
Min. Typ. Max. Min. Typ. Max.
(V)
If> INPUT OPERATION
Propagation Delay Time;· 5 - 175 350 - 175 400
ns LOAD CAPACITANCI (eli-pi"
tpLH, tpHL
10 - 80 125 - 80 150 Fig. 9 - Typic.1 trsnsition time ... CL •
Transition Time; 5 - 175 225 - 175 250
ns
tTHL,tyLH 10 - 80 125 - 80 150
Maximum Pulse Input 5 1.5 2.5 - 1 2.5 - MHz
Frequency, fif/ 10 4 7 - 3 7 -
ns
Width,tW 10 - 140 125 - 140 165
Input Pulse Rise & 5 - - 15 - -- 15
- - - lAS
•
Fail Time, trif/,tfif/ 10 10 10
Average Input
Capacitance, CI
LOAD CAPACITANCE ICLlo"pf
RESET OPERATION ----cL·~QpF'
TnfTTTT
ns
",' 10" IO~
'NPUT rAEQU£NCT I'.I-HI
10' 'o'
TpLH,TpHL 10 - 250 350 - 250 400
ns
Fig. 10 - Typical diuipation charscteristics,
Width;tw 10 - 200 300 - 200 350
• Propagation delay time is from input pulse to Q 1 output.

.. T Wl:ItATUM: Ta -II-C
LOAD CAMe'TAlICI (C I- II "
·i.
;!.!!
~~ 10
Voo
~
INPUTS
··~ .
,. 10
""",y VOlTSIVcoI
Fig. 11 - Typical input pulse f",quency ... VDO'
NCS-2M4'
Vss
.tc:S-I7401
Fig. 12 - Qui.lCtJnt-d••ice-current hilt

circuit. Fig. 13 - Noise-immunity test circuit.
V~NPU(JS
o ~
vDO :~:~U.£ INPUTS
SEOUENTIA"tt't,
Vss TO BOTH Voo AND Vss
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS·
V'S
Fig. 14 - Input.f••kags-current hilt circuit.
527
Voo
CMOS Decade Counters/Dividers , II
'DO
CLOCK ' ~
With Decoded 7-Segmllnt Display Outputs and: 12 II ~ CLOCK
'2 •
Display Enable - CD4026A
"r
13 c ~
Ripple Blanking - CD4033A CL.OCK
INHIBIT t d g CLOCK ",
AUU " II •
I ,
~
~
INHIBIT
,.
The RCA-CD4026A and CD4033A each
consist of a 5-stage Johnson decade counter
and an output decoder which converts
mUlti-digit decimal number which results in
an easily readable display consistent with
normal writing practice. For example, the
,.
DISPLAY
7.
5 CARRY OUT
•
DISPLAY
RESET
LAMP
.
,
the Johnson code to a 7·segment decoded
output for driving each stage in a numerical
number 0050.07000 in an eight digit display
would be displayed as 50.07. Zero suppres-
ENABLE
,.
ENABLE
OUT
TEST CARRY
!II OUT
display.
These devices are particularly advantageous
sion on the integer side is obtained by con-
necting the RBI terminal of the CD4033A
'"
UNGATEOwC·
5£0"[NT
1t2C"2!1078RI
,.
RIPPLE
BlK.
V55
RIPPL.E
Bll<.
OUT.
in display applications where low power associated with the most significant digit in CD4026A
dissipation and/or low package count are the display to a low-level voltage and con- CD4033A
important. necting the RBO terminal of that stage to FUNCTIONAL DIAGRAMS
Inputs common to both types are CLOCK, the RBI terminal of the CD4033A in the
RESET, & CLOCK INHIBIT; common next-lower significant position in the dis-
outputs are CAR RY OUT and the seven play. This procedure is continued for each Features:
decoded outputs (a, b, c, d, e, f, g). Addi- succeeding CD4033A on the integer side of • Counter and 7-segment decoding in one package
tional inputs and outputs for the CD4026A the display. • Easily interfaced with 7-segment display typas
include DISPLAY ENABLE input and On the fraction side of the display the RBI • Fully stetic counter operation: DC to 2.5 MHz
DISPLAY ENABLE and UNGATED "C- of the CD4033A associated with the least (typ.)
SEGM ENT" outputs. Signals peculiar to the significant bit is connected to a low level • Ideal fOr low·power displays
CD4033 are RIPPLE-BLANKING INPUT voltage and the RBO of that CD4033A is • Display Enable Output (CD4026A)
and LAMP TEST INPUT and a RIPPLE· connected to the RBI terminal of the • "Ripple Blanking" and Lamp Test (CD4033A)
BLANKING OUTPUT. CD4033A in the next more-significant-bit
• Quiescent current spacified to 15 V
A high RESET signal clears the decade position. Again, this procedure is continued
• Maximum input leakage current of
counter to its zero count. The counter is for all CD4033A's on the fraction side of the 1/lA at 15 V (full package-temparature
advanced one count at the positive clock display. range)
signal transistion if the CLOCK INHIBIT In a purely fractional number the zero
signal is low. Counter advancement via the • 1-V noise margin (full package-temper-
immediately preceding the decimal point can ature range)
clock line is inhibited when the CLOCK IN- be displayed by connecting the RBI of that
HIBIT signal is high. The CLOCK INHIBIT stage to a high level voltage (instead of to the
signal can be used as a negative·edge clock RBO of the next more-significant-stage).
Applications:
if the clock line is held high. Antilock gating For Example: optional zero -+0.7346.
is provided on the Johnson counter, thus • Decade countingn·segment decimal
assuring proper counting sequence. The CAR- tikewise, the zero in a number such as 763.0 display
RY-OUT '(Cout ) signal completes one cycle can be displayed by connecting the RBI of • Frequency divisionn-segment decimal
every ten CLOCK INPUT cycles and is used the CD4033A associated with it to a high- displays
to clock the succeeding decade· directly in a level voltage. • Clock/watches/timers
multi-decade counting chain. Ripple blanking of non-significant zeros (e.g. -:- 60,-:- 60, -:-12 counter/display)
The seven decoded outputs (a, b, c, d, e, f, g) provides an appreciable savings in display • CounterIdisplay driver for meter
illuminate the proper segments in a seven power. applications
segment display device used for representing The CD4033A has a LAMP TEST input
the decimal numbers 0 to 9. The 7-segment which, when connected to a high-level volt· These types are supplied in 16-lead hermetic
outputs go high on selection in the age, overrides normal decoder operation and dual-in-line ceramic packages (0 and F
CD4033A; in the CD4026A theses outputs enables a check to be made on possible suffixes), 16-lead dual-in-line plastic pack-
go high only when the DISPLAY ENABLE display malfunctions by putting the seven age (E suffix): 16-lead ceramic flat packages
IN is high. outputs in the high state. (K suffix), and in chip form (H suffix).
CD4026A
When the DISPLAY ENABLE IN is low the MAXIMUM RATINGS, Absolute-Maximum Values:
seven decoded· outputs are forced low re-
gardless of the state of the counter. Acti- STORAGE·TEMPERATURE RANGE (Tstg ) . • • . . . • • • • • • • • • . . . • • • . . . • . . . •-65 to +150 oC
vation of the display only when required OPERATlNG·TEMPERATURE RANGE (TA): °
results in significant power savings. This PACKAGE TYPES D, F, K, H •.••••..•••••••...••.•.•.•.•••-55 to +125 C
system also facilitates implementation of PACKAGE TYPE E .••.•..••.•.•••.•.•••••••..••••••.•.•••. -40 to +850 c
display·character multiplexing. DC SUPPLY-VOLTAGE RANGE, (VDD)
The CARRY OUT and UNGATED"C·SEG· (Voltage. referenced to VSS Terminel): • • . . • • • . • . • . . • . • . . • • . . • . . . . . . • -0.5 to +15 V
MENT" signals are not gated by the 015- POWER DISSIPATION PER PACKAGE (PD)
PLAY ENAB LE and therefore are available FOR TA~ -40 to +5OoC (PACKAGE TYPE E I .••••••.••.•••••.••••••.•••• 500 mW
continuously. This feature is a requireme{lt FOR TA~ +50 to +65°C IPACKAGE TYPE E I • . . . . . • . . Derate Linearly at 12 mW/oC to 200 mW
in implementation of certain divider func- For TA = -55 to +100'C (PACKAGE TYPES D, F. K) ....•••.•.•..••.....••.•••.....••.....• 500 mW
For TA = +100 to +125'C (PACKAGE TYPES D. F, K) ••...•. Derate Linearly at 12 mW/'C to 200 mW
tions such as divide-by-60 and divide-by-12.
FOR T A- FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) ••••••••• 100 mW
CD4033A INPUT VOLTAGE RANGE, ALL INPUTS •.••••••..••••••..••.••••• -0.5 to VDD +0.5 V
The CD4033A has provisions for automatic LEAD TEMPERATURE (DURING SOLDERING):
blanking of the non-significant zeros in a At dillance 1116 ± 1/32 inch (1.59 ±0.79 mml from ca.. for 10. max ••.••••••••••••• +265oC
528
COUT COUNT 010121' 01'101' 01 0'"is
r;:::::--;::::::r=;::=;=~::;===;::::;;8:1::!:::r~--------t>20 (CLOCK + 10) Cl
RESET
4'"
CLOCK
DISPLAY
INHIBIT I-~===~~==:t:===::t-;:==::j
b
UNGATED"C"
~>-----''''-o SEGMENT
ENABLE IN
ENA~r~:hO~
. f----+---+----i
CL~Kl
CLOCK ~2 "IL==~L)-rffi~)--i>
*INHIBIT •
IS UNDATED ~ r:::=;-::t==~:!:===:!=:::_:~
*
CARRYOUT
·C·SEG.
RESET
£t;V
*DISPLAY3 DISPLAY
f~ABLEOI-6-----------------------i·~----~-----a-------4
ENABLE Fig. 2 - C04026A timing disgrsm.
::~~8
OUT
fl..!..lb SEGMENT
• COSt
,"- '""''' ME "'"''''''''
MaS PROTECTION NETWORK ._- "ss
Y'
eldl C DE.,S,.I_G,~,A.,TIONS
_
RESET-,'-----------------________________
CLOCK INHIBIT "L__________
L~P~TE~ST~ ________________'~~_____________
RBO
+ 10J
I
COUT (CLOCK
Fig. 1 - C04026A IOfIic di.gram.
SEGMENT r------------LrL-
DESIGNATIONS
92SM-44111U
Fig. 4 - C04033A timing disgrsm.
DRAIN -TO-IOURCE VOLTS tVDO-VOH)
o
'-----j-~--
-4 -3 -2 -I
o
~~::~:[ -o.,,,,",-c
'OR %0-
~=~=:~=I ~;F~~;~T
*
CLOCK~"
1 ~~:t 5.S S
.z
~~I~W
-0.4;:
2
15
*RESET fTO
* 3
RBIO-----------~L....I ~~----1~~R~
VDD~ *ALL INPUTS ARE PROTECTED~D
BY COS/MOS PROTECTION __ _
GNDO 8
NETWORK.
Vss Fig. 5 - Minimum and typiC" output p-chsnnsl

Fig. 3 - C04033A logic. .dlsgrsm.
dtlcodsd drain charactllri.tic. 1# VOo-3.5
DltAIN-TO-IO.IRCIE VCLTl1Vao-VoMI &5V.
Fig. 6 - Minimum and typic" output p-chsnn.' FIg. 7 - Typlc.' output p-chsnn.' dtlcodtld
""coded dreln ch'rsctlll".tic. III Voo-10 dl1lln chlll7lCttlrI,t/c, lIS II function Fig. 8 - Typical propagation diliay time w.
& 15V. of temperature. CL for decod.d outpU".
529
RECOMMENDED OPERATING CONDITIONS at TA· 25°C, Except .. Noted.
For maximum .... I.blllty, nomln.1 operating condltionl should be
operation II alwayl within the following r'lIIIIl:
10 that _acted
LIMITS
Voo D,F,K,H E
IVI Packaf/es Pack.,.
Min. Max. Min. MIX.
Supply·Voltage RanllllFor TA - Full
Package-Temperature Renllll 3 12 3 12 V
LOAD CAPACITANCE ceL) - p' ucs- ..,,17
Setup Time, ts 10 200 - 300 - Fig. 9 - Typical propagation dBlay rim. v..
Clock Pulll Width, tw 5 330 - 500 - ns

CL for Cllrry output'-
10 170 - 260 -
Clock Input Frequency, fCl 5 de 1.5 de 1
MHz AMBIENT TEMPfRATURE 1T",.a·c
10 de 3 de 2 TYPICAL TEMPERATUItE COEFFICIENT '011
ALL VALUES OF Yoo .O.311o'·C
Clock Rill or Fall Time, trCl, lfCl

5 - 15 - 16
/J.S
10 - 15 - 15
Relit Pulll Width, tw 5 330 - 550 -- ns

10 165 - 250
Relit Removal Time 5 760 - 1000 - ns
10 225 - 276 - I. I.
STATIC ELECTRICAL CHARACTERISTICS 1020 5040!10 607010
LOAD CAPACITANCE {CLI-pF
Limits at Indlcetlld TemperaturelloCI
Conditionl Fig. 70 - Typical trBn.irion tim. v.. CL for
D, 1=, K, H Packages E Packllflll decoded outputs.
Ch_.rlltic Units
Vo VIN Voo +25 +25
-55 +125 -40 +86
IV) IV) IV) Typ. Limit Typ. Limit
Caliescent Device - - 5 5 0.3 5 300 50 0.5 60 700
Current IL Max. - - 10 10 0.5 10 600 100 1 100 1400 /AA
- - 15 50 1 50 2000 600 5 500 5000
Output Voltage:
Low·Leval, - 5 6 oTvp.; 0.06 Max.
VOL - 10 10 oTvp.; 0.05 Max. V
High Level, - 0 6 4.95 Min.; 5 Tvp.
VOH - 0 10 9.95 Min.; 10 Tvp.
Noise Immunity:
Inputs Low,
- 5 1.5 Min.; 2.25 TVp.
VNl - 10 3 Min.; 4.5 TVp.
V
Inputs High, - 5 1.5 Min.; 2.25 TVp.
VNH 10 3 Min.; 4.5 Typ.
Noise Margin:
Inputs low.
4.5 - 5 1 Min.
VNMl 9 - 10 1 Min.
V
VNMH 1 - 10 1 Min.
Output Drive Decoded 0.5 - 5 0.15 0.24 0.12 0.09 0.08 0.24 0.06 0.05
Current
n·Channel
Outputs 0.5 - 10 0.32 0.5 0.25 0.18 0.15 0.5 0.12 0.1
(Sinkl.
Carry 0.5 - 5 0.12 0.4 0.15 0.1 0.095 0.4 0.08 0.06
IDNMin. Output 0.5 - 10 0.45 1 0.35 0.25 0.3 1 0.25 0.2 mA
p·Channel Decoded 4.5 - 5 ·0.21 -0.28 ·0.14 ·0.1 ·0.09 ·0.28 ·0.07 ·0.06
(Sourcel. OutpUts 9.5 - 10 ·0.45 ·0.6 ·0.3 ·0.22 ·0.2 ·0.6 ·0.15 ·0.13
lOP
Min.
Carry 4.5 - 5 ·0.12 ·0.4 ·0.15 ·0.1 ·0.095 ·0.4 ·0.08 ·0.06
Output 9.5 - 10 ·0.45 ·1 ·0.35 ·0.25 ·0.3 ·1 ·0.24 ·0.2
Input Leakage
Current. -AT~nr~5 ±1o-5 Tvp .• ± 1 Max. /AA
iIL.IIH
530
DYNAMIC ELECTRICAL CHARACTERISTICS at TA .. 25°C, Input t, 'It - 20 ns, CL = 15 pF, I[NT T!IIIP!RATUR! IT A'- ZS-C
PlCAI. TEMPERATUIIf CCEfflC:1EN
RL ~2ookSl 500 FOR AL.L VALUES Of v -0.3"11o'·C
TEST
CONDITIONS D,F,-K,H
LIMITS
E
~
-i zoo
CHARACTERISTIC Packages ,r
PackBflB UNITS
Voo Min. Typ. Max. Min. Typ. Max.
M
CLOCKED OPERATION
"
10 20 30 40 !l0 60
70 80
tPLH, tPHL ns
Fig. 11 - Typical transition time VI. CL fOf
Carry Out Line 10 - 125 250 - 125 300 carry output.
Decode Out Lines

5 - 600 1700 - 600 2200 ns
10 - 250 500 - 250 700
Transition Time; 5 - 100 300 - 100 350
ns
tTHL, tTLH
Carry Out Line 10 - 50 150 - 50 200
Decode Out Lines S 300 900 :lOn 11?nn ns

10 - 125 350 - 125 450
Maximum Clock Input
Frequency, fCl •
5
10
1.5
3
2.5
5
-
-
1
2
2.5
5
-
-
MHz
I
Min. Clock Pulse Width, 5 - 200 330 - 200 500
tw ns
10 - 100 170 - 100 250
10 "
p.s
SUPPLY VOI.T5 1'1001
'2es-18Oa1
trCl, tfCL 10 - - 15 - - 15
Fig. 12 - Maximum input clock frsquency vs.
VDD·
Min. Clock Inhibit Set 5 - 175 500 - 175 700
ns
Up Time, ts 10 - 75 200 - 75 300
Average Input
Capacitance, CI
RESET OPERATION
tplH, tpHl
5 - 350 1000 - 360 1300
ns
To Carry Out Line 10 - 125 250 - 125 300
To Decode Out Lines

5 - 550 1400 - 550 1900
ns
10 - 240 500 - 240 600
Min. Reset Pulse Width 5 - 200 330 - 200 500
ns
tw 10 - 100 165 - 100 250
Min. Reset Removal 5 - 300 750 - 300 1000
ns
Time 10 - 100 225 - 100 275
Fig. 13 - Typical dissipation ch8l7lCtBristics.
• Measured with respect to carry out line.
5, 52 5S 54 5S
I
I
0
0
000
I 0 0
V~NPU(J'
Vss
... :,,;:.-::-
TO BOTH Yoo AND Yss'
o 0 I 0 I CCNlECT ALL LWUSID
o I I I I ...uTS TO EITHER
* 015CONN(Cf
FOR CD40HA
PIN 14
Vss
VDDOftySS'
UCI-''ON'"
Fig. 14 - No;SII immunity .'t

92(3-2744'
circuit. Fig. 15 - Qu;escsnt-device-curnmt test circuit. Fig. 16 - ·/nput-!eBkalJll-CUrrent trllt circuit.
531
CD4027 A Types
CMOS Dual J-K Master-Slave Flip-Flop

The RCA-CD4027A is a single monolithic The CD4027 A is useful in performing con-
chip integrated circuit containing two iden- trol, register, and toggle functions. logic
tical cO,mplementary-symmetrv J-K master- levels present at the J and K inputs along
slave flip-flops_ Each flip-flop has provisions with internal self-steering control the state
for individual J, K, Set, Reset, and Clock in- of each flip-flop; changes in the flip-flop
put signals. Buffered Q and a signals are state are synchronous with the positive-going
provided as outputs. This input-output ar- transition of the clock pulse_ Set and reset
rangement provides for compatible opera- functions are independent of the clock and
tion with the RCA-CD4013A dual D-type are initiated when a high level signal is pres-
flip-flop. ent at either the Set or Reset input_
CD4027A
FUNCTIONAL DIAGRAM
STORAGE-TEMPERATURE RANGE {Tstgl . . . . . . . _ . . . . . . . . . . • . . • . . . . .. -65 to +15o"C
OPERATING-TEMPERATURE RANGE {TAl: These types are supplied in 16-lead hermetic
PACKAGE TYPES 0, F, K, H . • . . . . . • . . . . . . . . . . . . . _ . . . . . . . . • . .. -55 to +125·C dual-in-line ceramic packages (0 and F
PACKAGE TYPE E .......••.••.... _ ...•.•..•.•... _ . . . . . . • -40 to +85·C suffixesl. 16-lead dual-in-line plastic pack-
DC SUPPLY-VOLTAGE RANGE, {VDDI age (E suffix), 16-lead ceramic flat packages
(Voltages referenced to VSS Terminal): ....... _ ...•..•.• ' •.•..•... _ ..• -0.5 to +15 V (K suffix), and in chip form (H suffix).
POWER DISSIPATION PER PACKAGE {POl:
FOR T A = -40 to +60·C {PACKAGE TYPE' E'I ...•..•....• _ . . • . . . • • • . . 500 mW
FOR TA = +60 to +85·C (PACKAGE TYPEi E I •.....• Derate Linearlvat 12 mWfC to 200 mW
For T A = -55 to +100·C (PACKAGE TYPES D. F, KI ....................... _............... 500 mW Features:
For TA = +100 to +125·C (PACKAGE TYPES 0, F, KI ........ Derate Linearly at 12 mWI"C to 200 mW
• Set-Reset capability
DEVICE DISSIPATION PER OUTPUTTRIINSISTOR
• Static flip·flop operation-retains state
FORTA =FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) • . • . . . 100 mW
indefinitely with clock level either
INPUT VOLTAGE RANGE. ALL INPUTS ...•...•.••.•.....•.. _ .... -0.5 toV DD +0.5 V
"high" or "low"
• Medium-speed operation-l0 MHz (typ.)
At distance 1/16. 1/32 Inch {1.59' 0.79mm) from case for lOs max•.. _ ..••.. _ .• _ +265"C
clock toggle rate at 10V
RECOMMENDED OPERATING CONDITIONS at TA = 25' C, Except as Noted. • Quiescent current specified to 15 V
For maximum reliability, nominal operating conditions should be selected so that • Maximum input leakage of 1 IlA at 15 V
operation is always within the following ranges. (full package·temperature range)
LIMITS • I-V noise margin (full package-tempera-

ture range)
CHARACTERISTIC V DD D,F,K,H E UNITS Applications
PACKAGES PACKAGE • Registers, counters, control circuits
(VI
MIN. MAX. MIN. MAX.

3 12 3 12 V
Package-Temperature Rangel AMBIENT TEMPERATURE ITA)" Z!5'C
TYPICAL TEMPERATURE COEffICIENT
30 FOR loo-o.3'I"'C
5 150 - 200 -
Data Setu p Ti me, ts ns
10 50 - 75 - ATE - TO- SOURCE VOLTS IVeS) " I

5 330 - 500 - ns i
10 110 - 165 - z
15
! 10
Clock Input Frequency (Toggle 5 1.5 1

de dc MHz
Model fCl 10 4.5 3
DRAIN-TO-SOURCE 'VOlTS 1VOSl

5 - 15 - 15 92CS-I7Ioo
Clock Rise or Fall Time, trCl,' tfCl IlS
10 - 5 - 5
Fig. 1 - Typical n-channel drain characteristics.
5 200 - 300 -
Set or Reset Pulse Width. tw ns
10 80 - 120 -
*If more than one unit is cascaded in a parallel clocked operation, t,cL should be made less than or equal to
the sum of the fixed propagation delay time at 15 pF and the transition time of the output driving stage
for the estimated capacitive load.
532
CD4027 A Types
DRAIN - TO - SOURCE VOlTS lYos'
-15 -10 -5
LIMITS AT INDICATED TEMPERATURES 1°C)
CONDITIONS D, F, K, H PAC!<AGES E PACKAGE
CHARACTERISTICS UNITS -10 i
Vo V IN VDD +25 +25
-55 +125 -40 +85
IV) IV) IV) TYP. LIMIT TYP. LIMIT
GATE-TO-SOURCEVOLTStVGS' __ '~ -20~
~
5 1 0.005 1 60 10 0.01 10 140
Quiescent Device
10 2 0.005 2 120 20 0.05 20 280 "A
Current. 1L Max.
15 25 0.5 25 1000 250 2.5 250 2500 AMBIENT TEMPERATURE ITAI' 25"'C
TYPiCAL TEMPERATURE COEFFICIENT FOR 1 0 '-0.3 To I'C
Output Voltage: - 0.5 5 o Typ.; 0.05 Max
Low Level,
VOL - O.H 10 oTyp.; 0.05 Max
Fig. 3 - Typical p-channel drain
characteristics_
High Level - 0.5 5 5 Typ.; 4.95 Min. V
VOH - O.H 10 10 Typ.; 9.95 Min.
Noise Immunity:
Inputs Low. 4.2 - 5 2.25 Typ.; 1.5 Min.
VNL 9 - 10 4.5 Typ.; 3 Min. AMBIENT TEMPERATURE. (TAl - z,-c
TYPICAL TEMPERATURE COEFFICIENT FOR 10--0.3'11./-C
Inputs High 0.8 - 5 2.25 Typ.; 1.5 Min. V

GATE - TO -SOURCE VOLTS IVOS)- I~
V NH 1 - 10 4.5 Typ.; 3 Min. ~'2.5
•
Noise Margin:
Inputs Low,
4.5 - 5 1 Min.
V NML 9 - 10 1 Min.
Inputs High, 0.5 - 5 1 Min. V ,av

V NMH
1 - 10 1 Min.
Output Drive
Current: '-, 12.5
DRAIN-lO-SOURCE VOLTS (VOS'
N Channel 0.5 - 5 O.SE 1 0.5 0.35 0.35 1 0.3 0.24
(Sink). 0.5 - 10 1.2E 2.5 1 0.75 0.72 2.5 0.6 0.5 Fig. 4 - Minimum n-channel drain
ION Min. characteristics.
rnA
P·Channel 4.5 - 5 -0.31 -0.5 -0.25 -0.17f -0.17 ·0.5 -0.14 -0.12
(Source):
r------- -I~ -IZ.5 -10 -7.5 -~ -Z.5
lOP Min. 9.5 - 10 -0.8 -1.3 -0.S5 -0.45 -0.4 -1.3 -0.33 -0.27 CERAMIC PACKAGES
PLASTIC PACKAGES--- flU -~
Input Leakage
Current, Any
Input
IIL·IIH 15 ±10- 5 Typ .• ±1 Max. "A
I -"
GATE-TO-SOURCE VOLTS! 1--11
orr r-------------------------------------------------
71~_+--------------------~--------------------------_t----- AMBIENT TEMPERATUREITAI_Z5-C
1(151 FDA I --0.3 'II./"'C
·
a -7.5
6"''''''.....,.~ __/
2 (141
1i
DRAIN - TO - SOURCE VOLTS IVoS'
·",'V----<L_~
Fig. 5 - Minimum p-channel drain
characteristics_
CL. CL
• T """- T
CLaCk
3(13)~
"""- INPUTS
.""''''
PRESENT STATE
CL
o ..
NEXT STATE
OUTPUTS
ADD
J k S 0
,, 0 a , a
, a a a L , a
J
, , a a
,a
J
"-
0
,
,
_HOCHANGE
,.
*ALL I.:::I.
PROTECTED BY
COS/MOS PROTECTION
NETWORK
, , a ,
LOGIC '-HIGHLEV[l.
LOIIC C'lOW LEVEL
a
a
I
92CM·'718BR4 IOZ0304oiSOlD
"
10 '0 100
X -OOJol'tCIolif LOAD CAPACITANCE (CL)-pF
Fig. 2 -Logic diagram & truth table for CD4027A Fig. 6 - Typical propagation delay
lone of two identical J·K flip flops!. time vs. CL'
533
CD4027A Types
at7A=25'C,lnputt"t,=20ns,CL = 15pF, RL=200kSl
LIMITS
CHARACTERISTIC V DD D,F,K,H E UNITS
,PACKAGES PACKAGE
(V)
Propagation Delay
Time: Clock to a 5 - 200 400 - 150 400
or Q Outputs ns
tPHL. tPLH
10 - 100 200 - 75 150 Fig.7 - Typical transition time VI. CL.
Set to a or Reset to a, 5 - 175 225 - 175 350

tpLH ns
10 - 75 110 - 75 150
Set to a or Reset to 0, 5 - 175 225 - 175 350
ns
tpHl 10 - 75 110 - 75 150
Transition Time 5 75 125 - 75 250
ns
tTHL. trlH 10 - 50 70 - 50 140
Maximum Clock Input 5 1.5 3 - 1 3 -
MHz
Frequency (Toggle 10 4.5 8 - 3 8 -
Modelf Cl SUPPLY vot.TS IVDoI
Minimum Clock Pulse 5 - 165 330 - 165 500 Fig.S - Typical maximum clock input frequency
Width,tW ns
10 - 65 110 - 65 165 VI. supply voltage.
Minimum Set or 5 - 125 200 - 125 300

Reset Pulse Width, ns
10 - 50 80 - 50 120
tw
Minimum Data Setup 5 - 70 150 - 70 200
Time, ts ns
10 - 25 50 - 25 75
Clock Rise or Fall 5 - - 15 - - 15
Time, t rCl - t fCl us
10 - - 5 - - 5
Average Input Any
Capacitance, C I Input - 5 - - 5 - pF
VDO.~UTO'·'-:"1
102 2 .. SlK)31 . . . 8'042 . . . "051 . . . .10. 1 ....
CLOCK FREQUENCY (tCLJ-Hz 9I:CS-,.OS6
Fig.9 - Typicsl dissipation chsrscterinics.
VNL
NOTE
TEST ANY ONl: INPUT, 'Iss
WITH OTHER ItrrUT5 AT
'loaORVss
VDO
50 pF
~50PF
16
Fig. 10 - Noiss immunity telt circuit. vDO 2 15 (5°i
INPUTS
3 14
.:.. 1 4 13 50 PF
1=
12
Yeo !NPUOS
VDO NOTE' 6 II
'-- ~ MEASURE INPUTS 7 10

o ~ SEQUENTIALLY, 8 9
"'ss TO allM YDO AND Yss·
CONNECT ALL UNUSED
"',"5 TO EITHER
YDOOftYss·
Vss
Vss
92CS-36061
Fig. 11 -Input lesksge current test circuit. Fig. 12 - OUiBICtlnt devlCtl currsnt rest circuit. Fig. 13-Dynamic power dissipation test
circuit.
534
CD4028A Types
CMOS YDD
BCD-Io-Decimal Decoder "o,
. , "~
.U"'.'D
b~~~;~'..
OCTAL
'4 DECOO£O
; Z ~J~1S
The RCA-C04028A types are BCO-to- o through 7 to go low_ If unused, the 0 "
decimal or binary-to-octal decoders consist- input must be connected to VSS_ High drive BCD 4 ~ BU"ERED
t~PUT5 t2 C S DEC .....\.
, 7 DECDDED
ing of pulse-shaping circuits on all 4 inputs, capability is provided at all outputs to en-
;: ~ci~J~
decoding-logic gates, and 10 output buffers_ hance dc and dynamic performance in high " D
A BCD code applied to the four inputs, A to fan-out applications_

••
0, results in a high level at the selected one '55
These types are supplied in IS-lead hermetic
of 10 decimal decoded outputs_ Similarly, a dual-in-line ceramic packages (0 and F
3-bit binary code applied to inputs A suffixes), IS-lead dual-in-line plastic pack-
through C is decoded in octal code at output age (E suffix), IS-lead ceramic flat package
o to 7_ A high-level signal at the 0 input (K suffix), and in chip form (H suffix)_ CD4028A
inhibits octal decoding and causes outputs FUNCTIONAL DIAGRAM
STORAGE-TEMPERATURE RANGE (Tstgl ___ ........ _ ........ _ .... _. -as 10 +150'C

Features:
PACKAGE TYPES D, F•. K•. H ....•..•....•.. _ .....•..... _ . •. --OS 10 +125'C • BCD-to-decimal decoding or binary-to-octal
decoding
PACKAGE TYPE E -4010 +85'C
• High decoded output drive capability. __
•• _8 rnA !typ.) sink or source
(Vollagesreferenc,s 10 VSS Terminal) ....... _ ..... _ ........ _ .. _ .... -0.5 10 +15 V
POWER DISSIPATION PER PACKAGE (PDI: • "Positive logic" inputs and outputs •• _
FOR TA =-40 to +60'C (PACKAGE TYPE E) _. _ ........ _. _ .•.....•.. _ 500mW .• _decoded outputs go high on selection
• Medium-speed operation _••
FOR T A = +60 10 +85'C (PACKAGE TYPE E I Derate Linearly al 12 mW/'C 10 200 mW
___ tTHL. tTLH = 30 ns (typ.) @ VDD = 10 V
For TA = -55 to +100'C (PACKAGE TYPES D. F, K) . . . . . . . . . . . ___ . . . . .. 500 mW
For TA = +100 to +125'C (PACKAGE TYPES 0, F, K). . .. Derate Linearly at 12 mW/'C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR • Maximum input leakage current of 1 pA
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) _ ..... _ 100 mW at 15 V (full package-temperature range)
INPUT VOLTAGE RANGE, ALL INPUTS .... _ ..... _ . . . . . . . . . ' ..... -0.5 to VDD +0.5 V • 1-V noise margin (full package-temper-
LEAD TEMPERATURE (DURING SOLDERING): ature range)
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 105 max. . . . . • . . . . . . . .. +265'C
Applications:
For maximum reliability, nominal operating conditions should be selected so that • Code conversion
operation is always within the following ranges: • Address decoding-memory selection
control
LIMITS • Indicator-tube decoder
CHARACTE R ISTIC VDD D,F,K,H E UNITS

(VI PACKAGES PACKAGE
MIN_ MAX_ MIN. MAX_
Supply-Voltage Range (For T A=Full

3 12 3 12 V
DRAIN-lO-SOURCiE VOlTS1VOSI
-20 -IS -~ -s
~~:I~EA~l T~~~!:~~~:lcIOT::;~C~;;T
FOR ALL VALUES 0' ""GS' -0 ''Io'*(
::: s
~ GATE -TO-sOURCE YOLTS IVasl."
: 20
i
.o !5 10 IS
DRA'N-TO-SOURCE VOLTS 111001
2.
-lD
.aC'-I'Olllll
Fig_ 1 - Typical output n-channel drain 'Fig. 2 - Typical output p-chsnnel drain "Fig. 3 - Typical propagation de/ay time
characteristics. characteristics. .s. CL_
535
CD4028A Types
TABLE I - TRUTH TABLE
DCBA o 1 2 3 4 5 6 7 8 9
o0 0
0 1 o 0 0 0 0 o 0 0 0
o 0 1
0 0 1 o 0 0 0 0 o 0 0
o 0 1
0 o0 1 o0 0 0 o 0 0
o 0 1
1 0 o 0 1 o 0 0 0 0 0
, o 1 0
0 0 000100 o0 0
"
0 1 o 1 0 0 0 o 0 1 0 o0 0 *
I 0 1 1 0 o0 0 0 o0 1 0 o 0
• 0 111 0 o 0 0 0 0 0 1 0 0
1 0 0 0 0 o 0 0 0 0 0 0 1 0
12* 1 0 0 1 0 o 0 0 0 0 0 0 0 1
00--+--\ o
1 1 o 0 0 o 0 0 0 0 0 1 0
1 o 1 1 0 0 o 0 o 0 0 0 0 1
1 1 0 o 0 0 o 0 o 0 0 0 1 0
1
1
1 o 1 o
1 1 o 0
0 0 o 0 0 0 o 0 1
0 0 o 0 0 0 o 1 0
**
1 1 1 1 0 0 0 o 0 0 0 o 0 1
~ _ /O--.~--v8
• * WHERE I • HIGH LEVEL
"00 *AU. INPUTS ARE O· LOW LEVEL
PROTECTED BY
CDS/MOS PROTECTION
L-~======t=r--{>--4>---O'9 ** EXTRAORDINARY
NETWORK STATES
Vss

LIMITS AT INDICATED TEMPERATURES (DCI
CONDITIONS ~.
D, F, K, H PACKAGES I E PACKAGE UNITS ~ 100
i
,0
CHARACTERISTIC +25 +25

Vo VIN VDD -55 125 -40 +85
(VI (VI (Vi TYP. LIMIT TYP. LIMIT
1040.0.0100110140110
Quiescent Device
- - 5 5 0.5 5 300 50 5 50 700 UW) CANCIT"HCIIC"I-"
Current. I L M... - - 10 10 1 10 600 100 10 100 1400 IlA Fig. 5 - Typical transition time vs. CL.
- - 15 50 1 50 2000 500 10 500 5000
Output Voltage: - 5 5 o Typ.;·0.05 Max.
Low·Level,
VOL - 10 10 oTyp.; 0.05 Max.
V
High Level - 0 5 4.95 Min.; 5 Typ.
VOH - 0 10 9.95 Min.; 10 Typ.
Noi.. lmmunity:
Inputs Low.
4.2 - 5 1.5 Min.; 2.25 Typ.
VNL 9 - 10 3 Min.:4.6 Typ.

V
VNH 1 - 10 3 Min.;4.5 Typ. SUPPLY VOLTSCVDDI
Noi.. Margin:
Inputs Low.
4.5 - 5 1 Min.
Fig. 6 - Maximum propagation delay time ....
VNML 9 - 10 1 Min. VDD·
V
Inputs High. 0.5 - 5 1 Min. 10'; "'OO'IOV
VNMH 1 - 10 1 Min.
Output Drive
Current
N-Channel
(Sinkl.
0.5 - 5 0.75 1.2 0.6 0.45 0.35 1.2 0.3 0.25
ION Min. 0.5 - 10 1.5 2.4 1.2 0.9 0.7 2.4 0.6 0.5
mA
P·Channel 4.5 - 5 -0.7 -0.9 -0.45 -0.32 -0.32 -0.9 \-0.22 -0.18
(Sourcel.
IDPMin. 9 - 10 -1.4 -1.9 -0.95 -0.65 -0.65 -1.9 -0.48 -0.4
I nput Leakage ,.' rD' 10"

FREQUENCY Ill-HI
Current, - T l- n r15 ±10-' Typ .• ±1 Max. IlA
IIL.IIH Fig. 7 - Dissipation VI. input frequency.
536
CD4028A Types
S
DYNAMIC ELECTRICAL CHARACTERISTICS VT
at TA =2ff1C, Input tr, tf= 20ns, CL = 15pF, RL =200kfl.
.~. 19}
o •
7
LIMITS BCD C 6
CHARACTER ISTIC
TEST
CONDITIONS O,F,K,H E UNITS
-.{
r--- PACKAGES PACKAGE
VDO
(VI MIN. TYP. MAX. MIN. TYP. MAX. • (Trademark) Burroughs Corp. 92tS ·17i!9~FI'
Propagation Delay
Time; 5 - 250 480 - 250 700
ns
tPLH, tPHL 10 - 100 180 - 100 290
Transition Time; 5 - 60 150 - 60 300 LAk... wllh v_nor (UIOt! So 0 OSmA

ns VIIAICIEO ~ 10Y
trHL. trLH 10 - 30 75 - 30 150
Fig. 9 - Neon readout (Nixie Tub.")
Average Input display application.
Capacitance, CI
INPUTS
The circuit shown in Fig. 9 converts any 4· VDO
1/6 CD40698
bit code to a decimal or hexadecimal code.
Table 2 shows a number of codes and the
decimal or hexadecimal number in these
.
VDO
VSS
INPUTS
codes which must be applied to the input

terminals of the CD4028A to select a partie·
ular output. For example: in order to get a
high on output No. 8 the input must be
either an 8 expressed in 4-Bit Binary code, a
15 expressed in 4-BitGray code, or a 5 ex- Vss
pressed in Excess-3 code.

Fig. 8 - Code conl(8rsion circuit.
Fig. 10 - Quiescent·dev;ce-current
test circuit.
TABLE II - CODE CONVERSION CHART
INPUT CODES INPUTOVDO

OUTPuTS
VOO-VNH
Hexa_ Decimal
Decimal 'o -
vN!..
~-=-
_
M ":'
INPUTS OUTPUT NUMBER
>- <h
a:
f->-
f-« -«
-z '"wuX '"~~ ~r:.
z~
\Iss
Non
TEST ANY COMaINATI""
000
DeB A
0
""- ""a:
.... <Xl
0
.... Cl w
0
xa:
wCl <~ 0 1 2 345 6 7 89101112131415
0 o 1 o 0 0 0 0 0 0 o 0 000 000
Of INPUTS
9ZCS-l 1"4'
000 1 1 1 1 1 0 1 o 0 0 0 0 0 o 0 000 000

0 0 1 0 2 3 0 2 2 o 0 1 0 0 0 0 0 o 0 0 o 0 0 0 0 Fig. 11 - Noise-immunity test circuit.
o0 1 1 3 2 0 3 3 000 1 000 0 0 0 000 0 o 0
0 1 0 0 4 7 1 4 4 0 0 o 0 1 o 0 0 0 o 0 0 000 0
0 1 0 1 5 6 2 300 o 0 0 1 0 0 0 o 0 0 o 0 o 0
0 1 1 0 6 4 3 1 4 o 0 o 0 0 0 1 0 0 0 000 000
0 1 1 1 7 5 4 2 0 0 0 0 0 0 0 1 o 0 0 000 o 0
1 0 0 0 8 15 5 0 0 0 o 0 o 0 o 1 0 0 0 0 0 0 0 Voo 1NPUOS
VDO NOTE
1 o 0 1 9 14 6 5 0 o 0 o 0 0 0 0 0 1 0 0 o 0 o 0 ~ MEASURE INPUTS
o ~ SEOUEN"ALLV.
1 0 1 0 10 12 7 9 6 0 o 0 o 0 0 0 0 0 0 1 0 o 0 o 0 Vss TO BOTH Voo AND Yss·
CONNECT ALL UNUSED
1 0 1 1 11 13 8 5 0 o 0 000 0 0 0 0 0 1 0 0 o 0 INPU1'S TO EITHER
liDO OR Vss
1 1 0 0 12 8 9 5 6 0 o 0 o 0 0 0 0 0 0 0 010 0 0 V.S
1 1 0 1 13 9 6 7 7 0 0 0 o 0 0 0 000 0 001 o 0
1 1 1 0 14 11 8 8 8 o 0 000 000 0 0 0 o 0 0 1 0
1 1'1 1 15 10 7 9 9 o 0 0 0 0 0 0 0 0 0 o 000 o 1 Fig. 12 - Input-leakage-current test circuit.
537
CD4029A Types
CMOS Presettable Up/Down Counter PRESET

ENABLE
Binary or BCD-Decade Features:
• Medium speed operation ••• 5 MHz (typ.) CARRY IN
(CLOCK
@ Cl=15 pF and VDD-VSS=10 V INHIBIT) 5
• Multi·package parallel clocking for synchronous BINARY I

The RCA-CD4029A consists of a four-stage
~
DECADE
high speed output response or ripple clocking
binary or BCD-decade up/down counter with
provisions for look-ahead carry in both for slow clock input rise and fall times UP/DOWN 10
, is
counting modes. The inputs consist of a • "Preset Enable" and individual "Jam" irlputs provided
CLOCK 15
single CLOCK, CARRY-IN (CLOCK INHI- • Binary or decade up/down counting
BIT), BINARY/DECADE, UP/DOWN, PRE- • BCD outputs in decade mode
SET ENABLE, and four individual JAM sig- • Quiescent current specified to 15 V
nals and a CAR RY OUT signal are provided • Maximum input leakage current of 1 IJ.A Vss
as outputs. at 15 V (full package-temperature range) 92CS·I7'190R2
CD4029A
A high PRESET ENABLE signal allows • 1·V noise margin (full package-
temperature range) Functional Diagram
information on the JAM INPUTS to preset .,.~-
the counter to any state'asynchronously with
the clock. A Iowan each JAM line, when the Applications:
PRESET-ENABLE signal is high, resets the • Programmable binary and decade
counter to its zero count. The counter is counting/frequency synthesizers·BCD output
advanced one count at the positive transition • Analog to digital and'digital to
of the clock when the CARRY-IN and PRE- analog conversion
SET ENABLE signals are low. Advancement • Up/Down binary counting
is inhibited when the CARRY-IN or PRESET • Magnitude and sign generation
ENABLE signals are high. The CARRY-OUT • Up/Down decade counting
signal is normally high and goes low when • Difference counting
the counter reaches its maximum count in
the UP mode or the minimum count in the
DOWN mode provided the CARRY-IN sig- is low. Multiple packages can be connected
nal is low. The CARRY·IN signal in the high in either a parallel-clocking or a ripple·
state can thus be considered a CLOCK clocking arrangement.
INHIBIT. The CARRY-IN terminal must be
Parallel clocking provides synchronous con-
connected to VSS when not in use.
trol and hence faster response from all
. Binary counting is accomplished when the counting outputs. Ripple·clocking allows for Fig. 1- Typical propagation delay time vs.
BINARy/DECADE input ishigh;the counter longer clock input rise' and fall times. CL for Q outputs.
counts in the decade mode '.'Vhen the BI-
NARY /DECADE input is low. The counter These types are supplied in 16-lead hermetic
counts Up when the UP/DOWN INPUT is dual-in-line ceramic packages (D and F
high, and Down when the UP/DOWN INPUT suffixes), 16-lead dual-in-line plastic pack-
age (E suffix). 16-lead ceramic flat packages
RECOMMENDED OPERATING CONDITIONS at TA=25 0 C, Except as Noted.

LIMITS
D,F,K,H E
VOO Packages Package LOAD CAPACITANCE ICLI-~
(V) Min. Max. Min. Max.

Fig. 2- Typical propagation delay time vs.
Supply-Voltage Range (For T A=Full
3 12 3 12 V CL for carry output.
Package· Temperature Range)
5 650 - 1300 -
Setup Time, tS' ns
10 230 - 460 -
5 340 - 500 -
Clock Pulse Width. tw ns
10 170 - 250 -
5 dc 1.5 dc 1
Clock Input Frequency. fCl MHz
10 dc 3 de 2
5 - 15 - 15
Clock Rise or Fall Time, trCl.tfCl·· IJ.s
10 - 15 - 15
5 330 ,- 660 -
Preset Enable Pulse Width, tw ns
10 160 - 320 -
LOAD CAPACITANCE tCL t - pF
-From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge.
*·If more than one unit is cascaded in the parallel clocked application, trCL should he made
less than or equal to the sum of the fixed propagation delay at ,15 pF and the transition Fig. 3-· Typical transition time vs. CL
time of the carry output drivmg stage for the estimated capacitive load. for Q outputs.
538
CD4029A Types
MAXIMUM RATINGS. Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE (T"g) ................................... .
OPERATING·TEMPERATURE RANGE (T A):
PACKAGE TYPES 0, F, K, H ............................................ . ·-55 to ; 125°C
PACKAGE TYPE E ................................................. . ·-40 to +85 0 C
DC SUPPLY·VOLTAGE RANGE, (V DD )
IVoltages referenced to VSS Terminal! ...................................... --0.5 to +15 V
POWER DISSIPATION PER PACKAGE (P D):
FOR T A=-40 to +600 C (PACKAGE TYPE E) ............... ............. 500 mW
FOR T A=+60 to +85 0 C (PACKAGE TYPE E) .......... Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100'C (PACKAGE TYPES 0, F, K) ........................................ 500 mW
For TA = +100 to +l25'C (PACKAGE TYPES 0, F, K) ........ Derate Linearly at 12 mW/'C to 200 mW
FOR TA=FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TyPES).......... 100 mW Fig. 4-Typical transition time VS. CL
INPUT VOLTAGE RANGE, ALL INPUTS ................................ . 0.5 to V DD '0.5 V for carlY output.
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm) from case for 10 s max. ............... t2650C
DVNAMIC ELECTRICAL CHARACTERISTICS at T A=25 0 C. Input t,.ft=20 ns.

CL=15 pF. RL =200 k!2
•
TEST LIMITS
CONDITIONS D,F,K,H E
~
Packages Package
(VI Min.' Typ. Max.'Min.' Typ. Max.
Clocked Operation
tpHL. tpLH 5 - 325 650 - 325 1300 Fig. 5- ~ax;mum clock input frequency
Q Outputs 10 - 115 230 - 115 460
ns
vs. VDD-
Carry Output
5 - 425 850 - 425 1700
"DO
10 - 150 300 - 150 600
"DO
Transition Time: INPUTS
tTHL. tTLH 5 - 100 200 - 100 400

Q Outputs 10 - 50 100 - 50 200
ns
Carry Output
5 - 200 400 - 200 800
10 - 100 200 - 100 400
ns
Width, tw 10 - 100 170 - 100 250
Clock Rise & Fall Time, 5 - - 15 - - 15
I1S
trCL. tfCL" 10 - - 15 - - 15
Fig. 6 - Ouiescent-device-current
Minimum Setup Times, 5 - 325 650 - 325 1300 test circuit.
-;
ns
tS' 10 - 115 230 - 115 460
"~~~O'"
Maximum Clock Input 5 1.5 2.5 - 1 2.5 -
MHz
Frequency. fCL 10 3 5 - 2 5 -
Input Capacitance, CI Any Input - 5 - - 5 - pF
Preset Enable
NOTE:
tpHL. tPLH 5 - 325 650 - 325 1300 TEST ANY ON[ INPUT.
WITH 01'H[R INPUTS AT
Yss
Q Outputs 10 - 115 230 - 115 460

ns
Voo ORVss·
5 - 425 850 - 425 1700 Fig. 7- Noise-immunity test circuit.

Carry Output
10 - 150 300 - 150 600
Minimum Preset Enable 5 - 115 330 - 115 660
ns
Pulse Width. tw 10 - 80 160 - 80 320 INPUO'
"co
Minimum Preset Enable 5 - 325 650 - 325 1300 V~
ns
Removal Time 10 - 115 230 - 115 460 "ss
Carry Input NOTE:
M[ASURE INPUTS
Propagation Delay Time: SEQUENTlAl.l.Y. Vss
TO BOTH VDD AND Vss·
tpHL. tpLH 5 - 175 350 - 175 700
ns CONNECT ALL UNUSED
Carry Output 10 - 50 100 - 50 200 I~S 10 EITHER
VDD OR Vss·
For footnotes, see Recommended Operating Conditions.

Fig. 8- Input.Jeakage-current rest circuit.
539
CD4029A Types
STATIC ELECTRICAL CHARACTERISTICS , I.
Limits .t Indic.ted Temperatures (OCI
Conditions
Ch.r.cteristicl-:-:,--,..-,,:--r:-:---+_ __.-D.;...-",;..._K,;..'H--::-:P_B_C_k...;B9:;.9_S_=-t-_=,...:Ec-_P.,.",,=kage-=-_r-=:-i Unit.
Vo VIN VOO -55 +25 +125 -40 +25 +85
(VI (VI (VI Typ. Limit Typ. Limit
Quiescent
5 5 0.3 5 300 50 0.5 50 700
Device
10 10 0.5 10 600 100 100 1400 p.A
Current,
15 50 50 2000 500 5 500 sooo
IL Max.
Output I 10 102 10'
INPUT CLOCK FREQUENCY UCL!- ~HI
Voltage:
Low-Level, - 5 5 0 Typ.; 0.05 Max.
Fig. 9- Typical dissipation characteristics.
VOL - 10 10 0 Typ.; O;OS Max.
V
High·Level. 1--_+-.;;0:-+-~S;;-j:-_ _ _ _ _ _ _..,;.4~.9;:S:.;M;:.::in~.,-;;;:;S.-:T~y:!:p:-._ _ _ _ _ _ _ _.,
VOH - 0 10 9.95 Min.; 10 Typ.
Noise
Immunity:
"ClDCK up"
I
---~
1j"~Mrl------+-""
I "UP/DOWN"
InputsLow.~4..:.;2~_-_~~5~_ _ _ _ _ _ _ _..:1~.S~M~in..:.~;~2~.2~S=T..:y~p~.,-_ _ _ _ _ _ _,
VNL 9 - 10 3 Min.; 4.S Typ. "ClDCK DOWN··.. I I
InputsHigh,~0~.~8~_-~~~S~_ _ _ _ _ _ _ _...;I~.S~M~i~n~.;~2~.2~5~T~Y~p,;..._ _ _ _ _ _ _~
V
---r: I
VNH 1 - 10 3 Min.; 4.5 Typ.
Noise I I CD401lA I
Margin:
L ~A'::.I~T~N~A~-.J 92CS-17'95AI
InputsLow.~..:4~.S~_-_~~5~_ _ _ _ _ _ _ _ _ _ _~lMii..:n..:._ _ _ _ _ _ _ _ _ _, Fig. to-Conversion 01 clock up, clock down

input signals to clock and up/down
VNML 9 - 10 1 Min.
V input signals.
Inputs High. f-"0:::-.5~_-_~~S~_ _ _ _ _ _ _ _ _ _--:-17Mii..:n..:._ _ _ _ _ _ _ _ _ _,
VNMH 1 - 10 1 Min.
Output
Drive Cur- The CD4029A CLOCK and UP/DOWN inputs
rent: are used directly in most applications. In
applications where CLOCK UP and CLOCK
N·Channel
DOWN inputs are provided. conversion to
(Sink). ION the CD4029A CLOCK and UP/DOWN inputs
Min. can easily be realized by use of the circuit
0.5 5 0.5 0.8 0.4 0.28 0.24 0.8 0.2 0.16 shown below.
Q Outputs
0.5 10 0.74 1.2 0.6 0.42 0.36 1.2 0.3 0.24 CD4029A changes count on positive transi·
Carry Out· 0.5 5 0.1 0.16 0.08 0.06 0.05 0.16 0.04 0.03 tions of CLOCK UP or CLOCK DOWN
put 0.5 10 0.4 0.64 0.32 0.22 0.19 0.64 0.16 0.13 inputs. For the gate configuration shown
rnA
P·Channel below. when counting up the CLOCK DOWN
(Source). input must be maintained high and conversely
when counting down the CLOCK UP input
lOP Min.
must be maintained high.
4.5 5 -0.18 -0.24 -0.12 -0.08 -0.07 -0.24 -0.06 -0.05
QOutputs
9.5 10 -0.3 -0.4 -0.2 -0.14 -0.14 0.4 0.1 0.08
L.1~
CLOCKTEPEJ Q •
Carry Out· 4.5 5 -0.09 -0.12 -0.06 -0.04 -0.04 -0.12 -0.03 -0.02 ::-:-~PE J X X 0 0
put 9.5 - 10 -0.15 -0.2 -0.1 -0.07 -0.07 -0.2 -0.05 -0.04 C TE 0.,, ~ Q Q
Input
Leakage
Current.
- -
I
An Y Inpult
15 ±10- 5 Typ .. ±1 Max. p.A NC-NOCHANGE
l.-t-:Co+-HIc~*~
-cr x
TE-TOGGLE ENABlE
Q ONe
NC
IIL.IIH
BINARYI
DECAOE
9
PRESET
ENABLE
"*
*
r-..
v
. I"-
v
4 J,
r -_ _ _ _ _ _ ~.._t~~===j::;===,------hVDD=16
'---"-l
vss·e fi
CL
'J
TE Q
• I X
o •
o 0 ,
x • Q
I
0
Q
0
Q Ne
Q Ne
X-DON'T CARE
CONTROL LOGIC
INPUT LEVEL
BIN/DEC BINARY COUNT

IBIDI DECADE COUNT
I UP COUNT
(lI/D) 0 DOWN COUNT
~ENABLE~---t-:cJA:::M-::'NC----t
(PEl 0 NO JAM
c-----. NO COUNTER
ADVANCE AT POS
CLOCI( TRANSITION
CARRY INleI)
(CLOCK INHIBIT! ADVANCE COUNTER
AT POS CLOCK
TRANSITION
• TRUTM TABLE FOR F-F No I •• TRUTH TABLE FOR F-F 5 2,3,4
Fig. II-Logic diagram.
540
CD4030A Types
CMOS
voo
Quad Exclusive-OR Gate "
" H
12 G
The RCA-CD4030A types consist of four in- These types are supplied in 14-lead hermetic
""
vs
10 L
dependent Exclusive-OR gates integrated on dual-in-line ceramic packages (D and F
9 F
a single monolithic silicon chip_ Each Ex- suffixes). 14-lead dual-in-line plastic pack-
clusive-OR gate consists of four n-channel and age (Esuffix). 14-lead ceramic flat package • E
four p-channel enhancement-type transistors_ (K suffix). and in chip form (H suffix)_
All inputs and outputs are protected against J"A@B L- E@F
K~C@O M= G@H
electrostatic effects_
MAXIMUM RATINGS, Absolute-Maximum Values

STORAGE TEMPERATURE RANGE (Tstg ) ____ .. _................. _....... __ .. _... -65to +150·C FUNCTIONAL DIAGRAM
OPERATING TEMPERATURE RANGE (T A)
PACKAGE TYPES D. F. K. H _••.••..••.••••••. _•••••.•.•••..• _. _._ .• _.•• _...... -55 to +125·C Features:
PACKAGE TYPE E ......... _............... _........ _....... _... __ ._ ... _. ___ ._ - 40 to +85·C • Medium speed operation_
DC SUPPLY VOLTAGE RANGE (V OO ) - - -tPHL = tPLH = 40 ns (tyP.) @ CL = 15 pF
(Voltages referenced to VSS Terminal ............... _....... _................ _.... -0.5 to +15V
and VDD-VSS = 10 V
POWER DISSIPATION PER PACKAGE (PO) • Low output impedance __ _
FOR TA =-40 to+60'C (PACKAGE TYPE E) ......... _. _._ ........ _... _..... _._ ....... _.500 mW
- - _500.n (typ_) @ VDD-VSS = 10 V
FOR TA = +60 to +85'C (PACKAGE TYPE E) ......... _. _. _ Derate Linearly at 12 mW'/C to 200 mW
FOR TA = -55 to+l00·C (PACKAGE TYPES O. F. K) . _.... _. _._ ... _... _..... _. ___ ....... 500 mW
FOR TA = +100 to +125'C (PACKAGE TYPES D. F. K) ... _. Derate Linearly at 12 mW/·C to 200 mW
FOR T A = FULL PACKAGE TEMPERATURE RANGE (ALL PACKAGE TYPES) . _. ___ . _. _. _100 mW
•
•
Maximum input leakage current of 1 I1A
at 15 V (Full package-temperature range)
1-V noise margin (full package-temper-
ature range)
I
INPUT VOLTAGE RANGE. ALL INPUTS ........ __ ..... _. _.............. _... _. _. -0.5 to VDO +0.5
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1/16 ± 1/32 inch (159 ± 0.79 mm) from case for lOs max.... _. _. _. _.... _....... +265'C Applications:
• Even and odd-parity generators
RECOMMENDED OPERATING CONDITIONS at TA = 25 0 C. and checkers
For maximum reliability, nominal operating conditions should be selecteel so that • Logical comparators
operation is always within the following ranges: • Adderslsubtractors
• General logic functions
LIMITS
A.,BIENT TEIiPERATUREITA'oU-C
D.F,K.H E
UNITS
30 FOR I 0-0.3 "",oC
CHARACTERISTIC Packages Package
~ GATE-TO-SOURCE VOLTSevGS'o,'
Min_ Max. Min_ Max.
~~20
Supply Voltage Range (For T A = Full
~
Package Temperature Range) 3 12 3 12 V
3
i
z
*PROTECTEO
ALL INPUTS ARE
BY
! 10
COS/MOS PROTECTION
NETWORK
f=i00 •• 5 10 15
CRAIN-TO-SOURCE VOLTS IVCS'
2.
Fig.2 - Typical output n-channel

*
tss
TRUTH TABLE FOR ONE OF 1(6 .•. ,,)
8 O,E,H
-15
drain characteristics.
CRAIN-TO-SOURCE VOLTSIVDS'
-10 -5
•.
FOUR IDENTICAL GATES
A
a
B
0
J
0
-'0 -IO~
1
0
0
1
1
1 ALL P-CHANNEL SUBSTRATES
ATE-rO.;WURCE VOLTStVGS,0.15V i
1 1 0 ARE INTERNALLY CONNECTED TO VOO
ALL N- CHANNEL SUBSTRATES
WHERE "I" = HIGH LEVEL ARE INTERNAllY CONNECTED TO Vss
"0" = LOW LEVEL -30

AMBIENT TEMPERATURE e TAlol5-C
fOR ALL VALUES OF VCCo·03%I·C
Fig. 1 - Schematic diagram for 1 of 4 identical exclusive-OR gates.
Fig.3 - Typical output p-channel

For quiscent device current, noise immunity. and input leakage current test circuits see "Rating and
Characlerislics" al the beginning of the CMOS section.
541
CD4030A Types
Limit. at Indicated Temperature. (OC)

Conditions
D,. F, K, H Packages E Package
Vo VIN VDD
(V) (V) (V)
-55
Typ.
+25
Limit
+125 -40
Typ.
+25
Limit
+85
,. :::: ::;: ::::
---:~
Is~~g ~~;~
Current I L Max. - - 10 1 0.01 1 60 10 0.1 10 140 /lA ·:l iE~
• .. t·
- - 15 25 0.5 25 1000 250 2.5 250 2500 20 40 10 80 100 120 140 160
LOAO CAPACITANCE lell - pF
Output Voltage:
Low Level.
- 5 5 o Typ.; 0.05 Max.
10 10 o Typ.; 0.05 Max. Fig.4 - Typical propagarion~elay
VOL rime vs. load capacitance.
V
VOH 0 10 9.95 Min.; 10 Typ.
:;1 t::1AMI'UlT TEMP£RATUREITAloUOC
Noise Immunity:
Inputs Low, .... ........... .
r!: :LOIO CAPACITANCE ICL'. 1'&lF
" " ....... .
VNL
3.6
7.2
- 5
10
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
!: :ii: ;::: .... :::: :::i
Inputs High 1.4 5 1.5 Min.; 2.25 Typ.
V
il 'N .... .... .... ... , ....
. .. ri.n~ .... .... .... ....
-
VNH
Noise Margin:
2.8 10 3 Min.; 4.5 Typ.
.. X" ....
VNML 9 - 10 1 Min.
V
VNMH 1 - 10 1 Min.
Output Drive
Current:
N Channel Fig.5 - Maximum propagation-delay
(Sink) 0.5 - 5 0.75 1.2 0.6 0.45 0.35 1.2 0.3 0.25 time vs. supply voltage.
ION Min. 0.5 10 1.5 2.4 1.2 0.9 0.7 2.4 0.6 0.5
mA
PChannel
(Source): 4.5 - 5 -0.45 -0.6 -0.3 -0.21 -0.21 -0.6 -0.15 -0.12
:r~nrl5
lOP Min. 9.5 - 10 0.95 1.3 0.65 0.45 -0.45 -1.3 -0.32 -0.25
I nput Leakage
Current
IIL,IIH ± 10-5 Typ., ± 1 Max. IJA
i 1'03 t I i"~ I
INPUTFIiIEQUENCY(fj!-H.
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r • tf = 20 ns.

CL = 1SpF, RL =200kH Fig. 6 - Typical dynamic power dis-
sipation characteristics.
LIMITS
Characteristic Test Conditions D,F,K,H E Units
'VOD Packages Package
Propagation Delay
5 - 100 200 - 100 300
Time: ns
tPLH, tPHL
10 - 40 100 - 40 150
1 fHHH8ii-!T!it!t::b.-:-:+
200
Transition Time:
5 - 70 150 - 70 300 ~ ,ooH,fH~~~~~~~~"
High·to·Low
-
~ rrtttffi:l~~f?17:¥*#~±
10 25 75 - 25 150
Level, tTHL
ns
Low·to·H igh 5 - 80 150 - 80 300
Level, ITLH 10 - 30 75 - 30 150
Average Input Fig.7 - Typical transition time
Capacitance, CI Any Input - 5 - - 5 - pF VS. load capacitance.
542
CD4031A Types
CMOS 64-Stage Static Shift Register
The RCA·CD4031A is a 64·stage static shift Data (0) and Data (0) outputs are provided
register in which each stage is a D·type, from the 64th register stage. The Data (0)
master·slave flip·flop. output is capable of drving one TTL or DTl
load.
The logic level present at the DATA input is
transferred into the first stage and shifted These types are supplied in 16-lead hermetic
dual-in-line ceramic packages (D and F
one stage at each positive·going clock transi·
tion. Maximum clock frequencies up to age (E suffix), 16-lead ceramic flat packages CLOtK2
4 Megahertz (typical) can be obtained. Be· (K suffix), and in chip form (H suffix). 1M L..,.;;r-'-'-LA-YE-'-r.!
CLOCK
cause fully static operation is allowed, OUT IISS
information can be permanently stored with Nt; 3, 4, 5,11,12,13.14

92:CS- 2:'50'50RI
the clock line in either the low or high state.
Features: CD4031A
The CD4031A has a MODE CONTROL in· FUNCTIONAL DIAGRAM
put that, when in the high state, allows • Fully static operation: DC to 4 MHz typo
operation in the recirculating mode. Register @VDD-VSS=10V • Single phase clocking requirements
packages can be cascaded and the clock lines • Operation from a single 3 to 15 V positive • Recirculation capability
driven directly for high speed operation. or negative power supply • Data compatible with TTL-DTL
Alternatively, a delayed clock output (ClD) • High noise immunity • Two cascading modes:
is provided that enables cascading register • Microwatt quiescent power dissipation: Direct clocking for high-speed opera·
•
packages while allowing reduced clock drive 10llW (typ.) for ceramic packages; 100 IlW tion
fan·out and rise· and fall·time requirements. (typ.) for plastic packages Delayed clocking for reduced clock
drive requirements
MAXIMUM RATINGS,Absolute·Maximum Values: • Quiescent current specified to 15 V
STORAGE·TEMPERATURE RANGE (Tstgl . . . . . . . . • . . . . . . . . . . . -65to+1500C • Maximum input leakage current of 1 IlA
OPERATING·TEMPERATURE RANGE (TAl: at 15 V (full package·temperature range)
PACKAGE TYPES 0, F, K, H ......................... . -55 to +125° C • 1·V noise margin (full package·tempera·
PACKAGE TYPE E .............................. . -40 to +85°C ture range)
DCSUPPLY·VOLTAGE RANGE, (VDDI
Voltages referenced to VSS Terminal): . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +15 V
POWER DISSIPATION PER PACKAGE (Pol Applications:
FOR T A = -40 to +60° C (PACKAGE TYPE E I . . . . . . .. . . . . . . . . . . . . . . . 500mW
FOR T A = +60 to +85° f (PACKAGE TYPE E I Derate Linearlv at 12 mW/C to 200 mW
• Serial shift registers
FOR TA = -55 to +100'C (PACKAGE TYPES 0, F, K) .. . .. .. .. " .. " .. .. .. 500 mW • Time delay circuits
FOR TA = +100 to +125'C (PACKAGE TYPES 0, F, K) Derate Linearly at 12 mW/o C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR AMBIENT TEMPERATuRE ITA ,- 25"C
TYPICAL TEMPERATuRE COEFFIC[NT FOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPESI 100mW ALL VALUES 01' "'00'-0 , ... '''(
INPUT VOLTAGE RANGE, ALL INPUTS . . . . . . . . . . . . . . . . . . . -0.5 to VOD +0.5 V '0 r t~J-l ~~~~
LEAD TEMPERATURE (DURING SOLOERINGI: ~
At di'tanee 1/16 ± 1132 inch (1.59 ± 0.79 mml from ea,. for 10 , max. +26S0C
RECOMMENDED OPERATING CONDITIONS at TA = 25' C, Except as Noted.

liMITS
,
1..
CHARACTERISTIC
D,F,K,H E
, MINIMUM"lt:m.m:f!lff.!
PACKAGES PACKAGE
UNITS ° ORAIN-TO-SOURCE VOLTS lV OS '
VDD
(V) MIN. MAX. MIN. MAX. Fig. 1 - Typical an~ minimum output n-channel
drain characteristics for Q output.
Package·Temperature Range) 3 12 3 12 V DRAIN-TO-SOURCE VOLTSIVOSI
-I§ -10 -§ 0
5 100 - 100 -
Data Hold Time, tH ns
10 200 - 200 -
5 2.5 - 2.6 -
Clock Pulse Width, tw IlS
10 1 - 1.3 -
5 dc 0.8 dc 0.4
10 dc 2 dc 1 :::: :::: ::::
10
5 -
-
2
1
-
-
2
1
IlS U;L~) lLLLU .tutij.:~:. r.;.~:.:~.:.~
TYPICAL TEMP[RATURE COEFFICIENT
FOR ALL VALUES OF" Vo '-O''''''C I~
rj 1:::
....
1-:;':':
It"
: . : +~:'j'. lin:lI1!+'1-I .,.
H
* If more than one unit is cascaded in the parallel clocked application. treL should be made less than or equal Fig. 2 - Typical output p·channel drain character-
to the sum of the propagation delay at 15 pF and the transition time of the output driving stage. istics for a output,
543
CD4031 A Types
AMBIENT TEMPERATURE tTAI'2~'C
TYPICAL TEMPERATURE CQ[FFICENT FOR
LIMITS AT INDICATED TEMPERATURES (OC) ALL VALUES OF Voo' 0 3".. f*C
CONDITIONS IVcol'~ ~
D, F, K, H PACKAGES E PACKAGE SUPPLY VOLTS
Vo V IN VDD
(VI (VI (VI
-55
+25
+125 -40
+25
TYP. LIMIT
+85
0"
n!
TYP. LIMIT
- - 5 10 0.5 10 600 50 1 50 700 0" 0"

,. t,· .1
Quiescent Device "it u.i

Current, I L Max.
- - 10 25 1 25 1500 100 2 100 1400 Jl.A 0"
It:
- - 15 50 1 50 2000 500 5 500 5000 ·LOAO CA~ACITANCE OF 0'15pF
Output Voltage:
t:tHtii:!
- 5 5 oTyp.; 0.05 Mal< IrlliJi ...
Low Level, '" '0 60 70 80 90 100
VOL - 10 10 oTyp.; 0.05 Max , LOAD CAPACITANCE tCLI-pF

_LGlO CAPACITAIfCE OF 1'J~15pF
V
- 5 Fig. 3 - Typical propagation delay time VI. load
High Level 0 4.95 Min.; 5 Typ. capacitance for data outputs.
VOH - 0 10 9.95 Min.; 10Typ.
Noise Immunity:
4.2 - 5 1.5 Min.; 2.25 Typ.
Inputs Low,
V NL 9 - 10 3 Min.; 4.5 Typ.
V
V NH 1 - 10 3 Min.; 4.5 Typ.
Noise Margi n:
4.5 - 5 1 Min.
Inputs Low,
V NML 9 - 10 1 Min.
V
V NMH 1 - 10 1 Min.
Output Drive 0.4 - 4.5 1.6 2.6 1.3 0.91 1.6 2.6 1.3 1.05
Current: a 10 30 50
N·Channel
0.5 - 10 5 8 4 3.2 5 8 4 3.2 LOAD CAPACIYANCr ICtl-pF
(Sink), 0.5 5 0.11 0.18 0.09 0.06 0.05 0.18 0.045 0.037 Fig. 4 - Typical propagation delay vs. load capaci·
Q tance for delayed clock output.
ION Min. 0.5 - 10 0.24 0.4 0.2 0.14 0.12 0.4 0.1 0.08
p. Channel
I CLO
0.5
0.5
4.5
-
-
-
5
10
5
0.48
1.5
-0.4
0.8
2.4
0.4
1.2
0.28
0.84
0.24
0.75
-0.64 -0.32 -0.22 -0.20 -0.64 -0.16 -0.13
0.8
2.4
0.2
0.6
0.16
0.5
rnA
(Source): Q
9.5 - 10 -0.85 -1.4 -0.70 -0.49 -0.42 -1.4 -0.35 -0.29
lOP Min. 4.5 - 5 -0.11 -0.18 -0.09 -0.06 -0.05 -0.18 -0.045 f-o.037
a 9.5
4.5
-- 10
5
-0.24
-0.48
-0.4 .0.20 -0.14 -0.12 -0.4 -0.10 f-o.08
-0.8 -0.40 -0.28 -0.24 -0.8 -0.20 -0.16
CLO ~
9.5 - 10 -1 -1.6 -0.80 -0.56 -0.5 -1.6 -0.40 -0.32 1/1 100
Input Leakage
Ar Input
~
Current,
IIL,IIH - -115 ±10- 5 Typ., ± 1 Max. Jl.A ,.
NOTt: ITtLFOR
..
LOAO CAPACITANCE tCLI- pF
a OU'n'UT rs SIGNIFICANTLY LESS THAN ITLH
"C$-I,r4'
Fig. 5 - Typical transition time VI. load capaci~

ranee for data outputs.
MODE
CONTROL;
E
AECIRCUL"A:.:.T",IO"N_-I.....-'
BIT INTO
DATA RECIRe. MODE STAGE I
L
CL
CL t fi
TYPICAL STAGE TRUTH TAeL[
£\
0 ec 0.,
CLo
0 ...r 0 Input to Output is:
X' DON'T CARE
~ ALL INPUTS ARE

DD I
...r I (a) A Bidirectional Short Circuit when Control
PROTECTED BY K \... Ne Input 1 is "Low" and Control Input 2 is
COS/MOS PROTECTION --
N:' NO CHANGE
"High"
NETWORK
X'DON'T CARE
(b) An Open Circuit when Control Input 1 is LOAO CAPACITANCE leL 1- pF
"High" and Control Input 2 is "Low"
92CS19019R2
Fig. 6 - Typical transition time vs. load capaci·
vSS Fig. 7 - Logic diagram and truth tables. tance for delayed clock output.
544
CD4031A Types
DYNAMIC ELECTRICAL CHARACTERISTICS A"SIENT TEMPERATURE ITA"iS'C
TYPICAL TEMPERATURE COE:FFICENT FOR
EEffi ...
I . , ... , •.•
at TA=25 0 C. Input t r.t,=20 ns. CL =15 pF (unless otherwise specified I. RL =200 kU ALL VALUES OF VOO.Ol,..,-C • .:!:
!.; ::~! ....
liMITS
TEST
CHARACTERISTIC CONDI~ D,F,K,H E UNITS.
VDD
Ivl MIN. TYP. MAX. MIN. TYP. MAX. C04031AE

tplH' tpHl 5 - 400 800 - 400 1600
ns
Clock to Data
Output Q& Q*
10 - 200 400 - 200 800 10
SUPPLY VOLTS eVool
15
RCS-II751
Fig. 8 - Maximum clock input frequency

5 - 400 800 - 400 1600
supply voltage.
V.I.
Clock to ClD Cl = 60pF 10

- 200 400 - 200 800
Transition Time;
tTHL' tTLH 5 - 75 150 - 75 300
QOutput
10 - 30 60 - 30 120
aOutput 5 - 300 600 - 300 1200

ns
10 - 150 300 - 150 600
5 - 200 400 - 200 800
•
CLD Output CL = 60pF 10
- 100 200 - 100 400
Clock Rise and Fall Time; 5 - - 2 - - 2
j.!s
trCl. tfCl" 10 - - 1 - - 1
Minimum Data Set·Up 5 - 200 400 - 200 800
Time. ts ns
10 - 50 100 - 50 200 Fig. 9 - Typical power dissipation vs. frequency.
Maximum Clock Input 5 0.8 2 - 0.4 2 -
MHz
Frequency,lcl 10 2 4 - 1 4 - .NPUTOVDOouTPUTS
Minimum Data Hold 5 - 50 100 - 50 100
n.
VOO-VNH
Time,tH -. - '- ~
Minimum Clock Pulse
10
5 -
100
1.25
200
2.5 -
100
1.3
250
2.6
V':L :t
j.!s NOTE:
Width,tW 10 - 0.5 1 - 0.62 1.3
Vss
TEST ANY ONE INPUT,
WITH 0T14ER INPUTS AT
Average Input Capaci· 92CS-27400 Voa ORVss'
tance, Cl Clock - 60 - - 60 - pF
All Others - 5 - - 5 - Fig. 10 - Noise-immunity test circuit.
V~NPU(JS :~:~u.[
a:
... Capacitive loading on output affects propagation delay of Q output. These limits apply for C load
CL"15 pF.
** If more than one unit is cascaded in the parallel clocked application, t,CL should be made less than or VDO 'HPUTS
equal to the sum of the propagation delay at 15 pF and the transition time of the output driving stage. o ~ SEQU[NflALL,Y,
*** Maximum Clock Frequency for Cascaded Units; \Iss TO BOTH Yoo AND IIss
CONNECT ALL. UNUSED
'HPlITS TO [ITNER
a) Using Delayed Clock Feature - Yoo OA Vss
v55
f max = In-I) Cl D prop. delay + Q prop. delay + set.up time where n = number 01 package.
Fig. 11- Input-Ieakage-current test circuit.
b) Not Using Delayed Clock _ 1 = 1
max propa9,ation delay + set-up time VDD
~
*AU. INPUTS ARE
PROTECTED BY
CDS/MDS PROTECTION
NETWORK
VSS
*1
RECIRCULATION
.N
92CS-191"SR2
WITHs, AT GROUND,CLOCI< UNIT 64 TIMES
BY CONNECTING S2 TO PULSE GENERATOR.
RETURN 52 TO GND AND MEASURE LEAKAGE
CURRENT. REPEAT WITH 5, AT Voo.
Fig. 12 - Functional diagram. Fig. 13 - Quiescent·device-current test circuit.
545
CMOS Triple Serial Adders

Features:
Positive Logic Adder - CD4032A
Negative Logic Adder - CD4038A • Invert inputs on all adders for sum complementing
applications • 2 ......--J..u---,
• Fully static operation . . . . . . dc to 5 MHz hyp.) INVER:~ ,
The RCA-CD4032A and C04038A types • Buffered outputs

consist of three serial adder circuits with • Single-phase clocking
common CLOCK and CARRY-RESET in- • Microwatt quiescent power dissipation. . . . 5 /lW hyp.) I SUM 3
puts. Each adder has two provisions for two

serial DATA INPUT signals and an INVERT
command signal. When the command signal • Maximum input leakage current of 1 /lA VSS"e
is a logical "1 ", the sum is complemented. at 15 V (full package-temperature range) VOO·16
'2CS·17M'
Data words enter the adder with the least • 1-V noise margin (full package-temper- FUNCTIONAL DIAGRAM
significant bit first; the sign bit trails. The ature range)
output is the MOD 2 sum of the input bits signal to a CARRY-RESET input one bit·
plus the carry from the previous bit position. position before the application of the first
The carry is only added at the positive-going bit of the next word. Figs. 2 and 4 show
clock transition for the CD4032A or at the definitive waveforms for all input and output
negative-going clock for the CD4038A, thus, signals. Applications:
for spike free operation the input data trans- These types are supplied in 16-lead hermetic • Serial arithmetic units
itions should occur as soon as possible after dual-in-line ceramic packages (0 and F • Digital correlators
the triggering edge. suffixes), 16-lead dual-in-line plastic pack-
The CAR RY is reset to a logical "0" at the age (E suffix), 16-lead ceramic flat packages • Digital datalink computers
end of each word by applying a logical "1" (K suffix), and in chip form (H suffix). • Flight control computers
MAXIMUM RATINGS, Absolute-Maximum Values: • Digital servo control systems
STORAGE-TEMPERATURE RANGE ITstgl . -65 to +1500 C
OPERATINT GEMPERATURE RANGE ITA):
PACKAGE TYPES D. F. K, H -55 to +125°C
PACKAGE TYPE E -40 to +8SoC
DC SUPPLY-VOLTAGE RANGE. IV DD)
POWER DISSIPATION PER PACKAGE IP D )
FOR T A = -40 to +600 C IPACKAGE TYPE E I 500 rrNV
FOR T A = +60 to +85°C IPACKAGE TYPE E) Derate Linearlv at 12 mW/oC to 200 mW
FOR T A = -55 to +100"C (PACKAGE TYPES D. F, K) 500r'nW
FOR T A = +100 to +125"C (PACKAGE TYPES D, F. K) Derate Linearly at 12 mwtC to 200 mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE IALL PACKAGE TYPESI 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS. ·0.510 V DD +0.5 V
LOAD CAPACITANCE:ICLI - pF
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. +265°C Fig. 1 - Typical propagation delay time vs. load
capacitance for A. 8, or INVERT inputs
to sum outputs.
LIMITS
CHARACTERISTIC D,F,K,H E UNITS
(VI Min. Max. Min. Max.
Supply-Voltage Range (For TA =
Full Package· Temperature Rangel 3 12 3 12 V
5
Input Setup Time, ts
10
trCl - trCl - ns
5 de 1.5 de 2.5
10 dc 3 de 5
Clock Rise or Fall Time, trCl. tfCl

5 - 15 - 15
Fig. 2 - Typical transition time vs.load capacitance
/lS
10 - 15 - 15 for sum outputs.
546
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C. Input t r• tt = 20 ns.
CL ~ 15 pF. RL =200 kG
LIMITS
CHARACTERISTIC TEST CONDITIONS D,F,K,H E UNITS
Propagation Delay
Time;
tpLH' tpHL
,I-I--
. ItCL)-~H.
A. B. or Invert CLOCk FREQuENCY
Inputs to Sum 5 - 400 1100 - 400 1400 ns Fig. 3 - Typical dissipation characteristics.
Outputs 10 - 125 250 - 125 300
Clock Input 5 - BOO 2200 - BOO 2400
to Sum Outputs 10 - 250 500 - 250 600
Transition Time;
tTHL' tTLH
5 - 125 375 - 125 425 ns CL
(Sum Outputs) 10 - 50 150 - 50 200
INVERT ~H-l-l--+--+-+-J....fi"i"i"TTI11
Maximum Clock Input 5 1.5 2.5 - 1 2.5 - MHz
CAIIIY
RESET
•
SUM
Frequency. fCl 10 3 5 - 2 5 -
Clock Rise & Fall
TIme; 5 - - 15 - - 15 jLS
WORD I 0.0111100. +6Q
WORDZ 0.0110010 •• 50
0.1101110 ""0
WORD 3 1.10110 II_ -37
WORD.~.-50
1.0101001--87
trCl. tfCl-- 10 - - 15 - - 15
Fig. 4 - CD4032A timing diagram.
Minimum Input Set Up 5
Time. tS· 10
- - trCl - - trCl ns
WORD I+WORD2- WORD 3 + WORD 4
Average Input
Capacitance. CI - 5 - - 5 - pF
*This characteristic refers to the minimum time required for the A, B. or Reset Inputs to change state CL
following a positive clock transition (CD4032AJ or negative transition (CD4038A). INVERT -t-t-t-+-+-+-+-
CARRY
"If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition RESET
time and the fixed propagation delay of the output of the driving stage for the estimated capacitive SUM
load.
~TRUESUM- COMPl.EMENTED SUM
WORD I LlOOOOII =-61 WORD 3 0.0100100 -+38
WORD 2 1.100 II 01 =-51 WORD 4 0.0110001 .. +49
1.0010000 .. -112 0.1010101 .. +85
92CS-19121R1
Fig. 5 - CD4038A timing diagram.
:3-
I
I
l~~oE.S
I
_. _____ J
* VDO
.Bf
ClOC"l~_H>-"""'_ _ -II-_ 2 as
*Al.L INPUTS ARE PROTECTED
BY COS/NOS PROTECTION VSS
NETWORK
V55
*All.INPUTS ARE PROTECTED
NETWORK 92CS-l7fifi1R2
Fig. 7 - CD4038A logiC diagram of one of three
Fig. 6 - CD4032A logic diagram of one of three serial adders_ ser;al adders.
547
Limits at Indicated Temperatures (oC)

Conditions
Vo VIN VOO -55 +25 +125 -40 +25 +85
- - 5 5 0.3 5 300 50 0.5 50 700

Ouiescent Device
Current I L Max. - - 10 10 0.5 10 600 100 1 100 1400 /JA
- - 15 50 1 50 2000 500 5 500 5000
Output Voltage: - 5 5 o Typ.; 0.05 Max.
Low· Level
- 10 10 o Typ.; 0.05 Max.
VOL
V
VOH - 0 10 9.95 Min.; 10 Typ.
Noise Immunity:
Inputs Low. 4.2 - 5 1.5 Min.; 2.25 Typ.
VNL 9 - 10 3 Min.; 4.5 Typ. V
VNH 1 - 10 3 Min.; 4.5 Typ.
Noise Margin:
Inputs Low. 4.5 - 5 1 Min.
VNML 9 - 10 1 Min. V
VNMH 1 - 10 1 Min.
Output Drive
Current
N·Channel
(Sink), 0.5 - 5 0.6 0.9 0.5 0.3 0.25 0.9 0.2 0.14
ION Min. 0.5 - 10 0.75 2.4 0.7 0.6 0.6 2.4 0.5 0.4
rnA
P·Channel
(Source), 4.5 - 5 -0.21 -0.4 -0.15 -0.075 -0.14 -0.4 -0.1 -0.095
lOP Min. 9.5 - 10 -0.7 -7.2 -0.55 -0.35 -0.3 -1.2 -0.27 -0.22
Input Leakage
Any Input
Current,
±10-5 Typ., ±1 Max. /J A
IIL,IIH - - 15
Voo
INPUTS
°
Vss
voo.::::UTO".~:. V~ ~NPu(Js
o ~
Voo :~:~URE IN,PUTS SEQUENTIALLY.
v~ ~ Yss TO BOTH Yoo AND Vss
CONNECT ALL UNUSED
INPUTS TO EITHER
NOTE: VDO OR Vss
92CS-2'1"441 vss ~N~~~ONBINATICN Vss ,2C5-21402
Fig. 8 - Quiescent-device-current test circuit. Fig. 9 - Noise-immunity test circuit. Fig. 10 - InpuNeakage-current test circuit.
548
CD4034A Types
CMOS a-Stage Static Bidirectional

Paraliel/Seriallnput/Output Bus Register * ENABLE
-A·
The RCA·CD4034A is a static eight·stage The serial data appears as output data on
* AlB
parallel·or serial·input parallel·output regis'
* AIS
either the B lines (when AlB is high) or the .. PIS
ter. It can be used to: A lines (when AlB is low and the AE signal
* CLOCK
1) bidirectionally transfer parallel informa· is high).
tion between two buses, 2) convert serial Register expansion can be accomplished by 92CS-1920ZRl
data to parallel form and direct the parallel simply cascading CD4034A packages. Fig. 1 - Functional diagram.
data to either of two buses, 3) store (recircu,
n
late) parallel data, or 4) accept parallel data The CD4034A-Series types are supplied in
from either of two buses and convert that 24-lead hermetic dual-in-line ceramic pack-
DD
data to serial form. Inputs that control the ages (0 and F suffixes), 24-lead dual-in-line
operations include a single·phase CLOCK plaslic packages (E suffix), 24-lead ceramic *PROTECTED
tss
ALL INPUTS ARE
(CL), A DATA ENABLE (AE), ASYNCHRO· flal packages (K suffix), and in chip form (H BY
COSIMOS PROTECTION
NOUS/SYNCHRONOUS (A/S), A·BUS·TO· suffix). NETWORK
B·BUS/2B·BUS·TO·A·BUS (A/B), and PAR·

ALLEL/SERIAL (P/S).
Data inputs include 16 bidirectional parallel
STORAGE·TEMPERATURE RANGE (Tstgl . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to + 150"C
•
data lines of which the eight A data lines are OPERATING· TEMPERATURE RANGE (TAl:
inputs (outputs) and the B data lines are out·
PACKAGE TYPES 0, F, K, H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125"C
puts (inputs) depending on the signal level
PACKAGE TYPE E. . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85°C
on the A/Binput. In addition, an input for DC SUPPLY·VOLTAGE RANGE, (V DD )
SERIAL DATA is also provided.
(Voltages referenced to VSS Terminal) . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . -0.5 to +15 V
All register stages are D·type master·slave POWER DISSIPATION PER PACKAGE (POl
flip· flops with separate master and slave FOR T A = -40 to +60'C (PACKAGE TYPE EI. • . . . . . . . , . . . . . . , , . , . . . . . . , 500 mW
clock inputs generated internally to allow FOR T A = +60 to +85'C (PACKAGE TYPE EI. • . . . . . . . . . Derate Linearly at 12 mWI'C to 200 mW
synchronous or asynchronous data transfer FOR T A = -55 to +100'C (PACKAGE TYPES 0, F~ K) ............ , ..... , . . . 500 mW
from master to slave. Isolation from external FOR T A = +100 to +125'C (PACKAGE TYPES 0, F, K) . . . . . ,Derate Linearly at 12 mWI'C to 200 mW
noise and the effects of loading is provided DEVICE DISSIPATION PER OUTPUT TRANSISTOR
by output buffering. FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPESI. . . . . . 100 mW
INPUT VOLTAGE RANGE, ALLINPUTS , . . • . . . . . . . . . , . . . . . . . , . . . . . -0,5 to V OD +0.5 V
PARALLEL OPERATION LEAD TEMPERATURE (DURING SOLDERING):
A high PIS input signal allows data transfer At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from ca .. for 105 max . . . . . , .. , .. , ,. +265'C
into the register via the parallel data lines RECOMMENDED OPERATING CONDITIONS at TA = 25°C, Except as Noted.
synchronously with the positive transition For maximum reliability, nominal operating conditions should be selected so that
of the clock provided the A/S input is low. operation is always within the following ranges:
If the A/S input is high the transfer is in·
dependent of the clock. The direction of LIMITS
data flow is controlled by the A/B input.
When this signal is high the A data lines are CHARACTERISTIC VDD D,F,K,H E UNITS
inputs (and B data lines are outputs); a low (V) PACKAGES PACKAGE
AlB signal reverses the direction of data flow.
MIN. MAX. MIN. MAX.
The AE input is an additional feature which
allows many registers to feed data to a
Supply.voltage Range (For T A = Full
common bus. The A DATA lines are enabled 3 12 3 12 V
only when this signal is high.
Data storage through recirculation of data in
Data Setup Ti me, ts
5 500 - 500 - ns
each register stage is accomplished by mak· 10 200 - 200 -
ing the AlB signal high and the AE signal
low.
5 400 - 400 - ns
SERIAL OPERATION 10 175 - 175 -
A low PIS signal allows serial data to transfer
5 dc 1.5 dc 1.5
into the register synchronously with the Clock Input Frequency, fCl MHz
10 dc J dc 3
positive transition of the clock. The A/S in·
put is internally disabled when the register is
in the serial mode (asynchronous serial opera·
Clock Rise and Fall Time, trCL, tfCl' 5,10 - 15 - 15 jlS
tion is not allowed). ..

"'If more than one Unit IS cascaded trCl should be made less than or equal to the sum of the tranSition time
549
CD4034A Types
Features:
Table I - Truth Table for Register Input-Levels and the Resulting Register Operation (La Low
Level, H = High Level, X =Don't Carel • Bidirectional parallel data input
"A" • Parallel or serial inputslparallel outputs
Enable PIs • Asynchronous or synchronous
AlB AIS Operation*
parallel data loading
Serial Mode; Synch. Serial Data Input, "A" Parallel Data Outputs • Parallel data-Input enable on
L L L X
Disabled "A" data lines
L L H X Serial Mode; Synch. Serial Data Input, "B" Parallel Data Output • Data recirculation for re·gister expansion
Parallel Mode; "B" Synch. Parallel Data Inputs, "A" Parallel Data • Multipackage register expansion
L H L L
Outputs Disabled
• Fully static operation DC-to-5 MHz (typ.1
Parallel Mode; "B" Asynch. Parallel Data Inputs, "A" Parallel Data
L H L H Outputs Disabled At VDD-VSS =10 V
Parallel Mode; "A" Parallel Data Inputs Disabled, "B" Parallel Data • Quiescent current specified to 15 V
L H H L Outputs, Synch. Data Recirculation • Maximum input leakage current of 1 /lA
Parallel Mode; "A" Parallel uata Inputs Disabled, "B" Parallel Data at 15 V (full package-temperature
L H H H range I
Outputs, Asynch. Data Recirculation
• 1-V noise margin (full package-temper-
H L L X Serial Mode; Synch. Serial Data Input, "A" Parallel Data Output
ature rangel
H L H X Serial Mode; Synch: Serial Data Input, "B" Parallel Data Output
Parallel Mode; "B" Synch. Parallel Data Input, "A" Parallel Data Applications:
H H L L
Output
• Parallel Input/Parallel Output,
Parallel Mode; "B" Asynch. Parallel Data Input, "A" Parallel Data
H H L H Parallel Input/Serial Output,
Output
Serial Input/Parallel Output,
Parallel Mode; "A" Synch. Parallel Data Input, "B" Parallel Data Serial InputlSerial Output Register
H H H L Output
• Shift right/shift left register
Parallel Mode; "A" Asynch. Parallel Data Input, "B" Parallel Data • Shift right/shift left with parallel loading
H H H H
Output
.. • Address register
·Outputs change at positive transition of clock In the serial mode and when the AIS control Input IS "low"
• Buffer register
in the par~lIel mode.
• Bus system register with enable parallel
lines at bus side
• Double bus register system
• Up-Down Johnson or ring counter
• Pseudo-random code generaton
• Sample and hold register (storage, count-
" '8 ing, display I
• Frequency and phase comparator
AE
(A ENABLE
6 STAGES a.0CIi~
SAME AS SToIIGE r
~~
'"
( PARALLEL
SERIAL ". rn:=======~==~---
"'Ii" L--
Alan n r-
S~:L ~
,,~
.. _ _ _ _ _ _ _ _ _ _r-unL
..
~~
~
... ~ r-unL
... ~
.. ~ r-unL
.... TC·TRANS.ISSIOMCAn
;--rrs-&l
82 83 !4 B!j 86 87
,,~
.. ~ r-unL
~·'--~----t-.O tiM CL 5 0 Q
INPUT TO OUTPUT IS "\. '\. 00
.)"IIDlJlECTIOIIALLOWIIiPEOANCE J '\. 00
IIMENCONlWOLINPUtIIS"LD'··
ANOCONTROLIJIPUTllS"HICH" '\. J 0" II: DON'T CARE -------,L_____r-V"L
.
f J II: Q .. r,
.)AM Of'ENCIRCUIT IIHEN CONTROL V
INf'UTIIS""Gt4"AHDCONTIlOLINPUT~""''''~_ '\. '\. I I .. INVALID CONDITION
DD ~
f '\. I I
'\. J ," -I IL1lJ
*PROTECTED
ALL INPUTS ARE
BY
92CM·,92QOR2
..
,,~
~
COS/MOS PROTECTION
NETWORK V'S L- 8 DATA LiNtS lJI[ OUTPUTS ~LI~O:~E"
OUTPUTS
Fig. 2 - LogiC diagl'8m. Fig. 3 - nming diagram.
550
CD4034A Types
LIMITS AT INDICATED TEMPERATURES IDC)
CONDITIONS
0, F, K, H PACKAGES EPACKAGE
Vo VIN VDD +25 +25
-55 +125 -40 +85
IV) IV) (V) TYP. LIMIT TYP. LIMIT
- - 5 5 0.3 5 300 50 0.5 50 700

Quiescent Device
Current. I L Max. - - 10 10 0.5 10 600 100 1 100 1400 IlA
- - 15 50 1 50 2000 500 5 500 5000
Output Voltage:
Low Level. - 5 5 o Typ.; 0.05 Max
'00
VOL - 10 10 oTyp.; 0.05 Max LOAD CAPACITANCE LCLI- ~f
V
High Level - 0 5 4.95 Min.; 5 Typ. Fig. 4 - Typical propagation delay time
VOH vs. load capacitance.
- 0 10 9.95 Min.; 10 Typ.
Noise Immunity:
Inputs Low.
4.2 - 5 1.5 Min.; 2.25 Typ.
V NL 9 - 10 3 Min.; 4.5 Typ.
V
VNH 1 - 10 3 Min.; 4.5 Typ.
Noise Margin:
Inputs Low,
4.5 - 5 1 Min.
I
V NML 9 - 10 1 Min.
V
VNMH
1 - 10 1 Min.
Output Drive
Current:
LOAD CAPACITANCE ICLI-pf
N-Channel
(Sink), 0.5 - 5 0.124 0.2 0.1 0.07 0.124 0.2 0.1 0.07
Fig. 5 - Typical transition time vs. load
ION Min. 0.5 - 10 0.31 0.5 0.25 0.175 0.31 0.5 0.25 0.175 capacitance.
rnA
P-Channel
(Sou;ce): 4.5 - 5 -0.075 -0.1 -0.05 -0.035 0.075 -0.1 -0.05 0.1l15
lOP Min. 9.5 - 10 -0.188 -0.25 -0.125 0.088 0.188 -0.25 -0.125 0.088
Input Leakage
Current,
IIL,IIH _A"( :T15 ±10- 5 Typ., ±1 Max. IlA
""'OR'B"
10' AWeOtT TEMPERATURE tTA1'Z~'C I~=~~S

. At.TEAfrlATlNG '0'
t ro~t-~-'---rrT-'
iI "''''0 '1" PATTER".
'B~;;A'
Ioe-'THL
"""==,j:-,="--t-_-=-:==~~L
-"'OC
SUPPLY VOLTS 1VooI
J> ":"":':'':';PU;:;'''--+_-'''t -- - - 10'110 0

;: lo-I--r--+H-I---1,...-H Fig. 6 - Typical clock input frequency VS.
a 10 1
supply voltage.
-..
:
i• IOlb~o1"'H;I"",,""'-I4tt-+-+-ttt--t--~H-l Fig. 8 - Asvnchronous operation propagation delay

time and transition time.
,"'00
----=-9<).".
- - ___ ':iO.".
i~~~Tt~~~~
10 10' 10J 10·
INPUT (lOCM fREQUENCY tlCL)-kH, 12C5-"101_5
OUTPUT
Fig, 7 - Typical dissipation characteristics.
*INPUT AErEAS TO ANY Of THE "A"Qft'S' OAT4 INPuTS,"A"ENABLE,

SEAIALINPUT,A/B,P/S,OAA/SINPUTS
•• ISLH ANO 'SHL AIlE SET-UP TIMES
Fig. 9 - Clock pulse rise and fall timBS, Fig. 10 - Synchronous operation propagation
delay times, transition times, and set,up
times.
551
CD4034A Types
At TA = 2!fC, Input tr , tf= 20ns, CL = 15 pF, RL = 200oH2
TEST LIMITS
INPUTOVCOOUTPUTS
CHARACTERISTIC CONDITIONS D,F,K,H E UNIT VDC-VNH
.-----
V
PACKAGES PACKAGE '-- ~
DD
v~ ~
(VI MIN. TYP. MAX. MIN. TYP. MAX.
NOTE:
TEST AM" ONE INPUT,
ns
;vss WI,... OTHER IWUTSAT
92C5'27400 "00 ORVss·
Time; tPlH, tPHl 10 - 240 480 - 240 480
Transition Time; 5 - 250 750 - 250 750
ns Fig. 11 - Noise-immunity test circuit.
t THl, tTlH 10 - 100 300 - 100 300
Maximum Clock Input 5 1.5 2.5 - 1.5 2.5 - MHz
Frequency, fCl 10 3 5 - 3 5 -
Clock Pulse Width, 5 - 200 400 - 200 400
ns
tw 10 - 100 175 - 100 175
Min. High·Level
AE, P/S,A/S
5 - 240 480 - 240 480
ns
Pulse Width 10 - 85 195 - 85 195
INPUTS
Clock Rise& Fail Time 5 - - 15 - - 15

/-IS
trCL, tfCL * 10 - - 15 - - 15
Data Set·Up Time, 5 - 250 500 - 250 500
ns
ts 10 - 100 200 - 100 200
Average Input
Capacitance, C I Any Input - 5 - - 5 - pF Vss
*If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time Fig. 12 - Ouiescent4ev;ce*current test circuit.
APPLICATIONS
'"
.,
"00 INPUC'
Vco NOT[
'-----"t'--- M(ASURE INPUTS
o ~ SEQUENTIALLY,
Yss TO eoTM "DO AND Vss
CONNICT ALL UNUSED
INPUt'S 10 (ITH["
VDD DfIVss·
V55
Fig. 14 - 16·Bit parallelin/parallel out, parallel Fig. 15 - 16-Bit serial in/gated parallel out register. Fig. 13 - Input·l..kage.current tert circuit.
in/serial out, serial in/parallel out, serial
in/seriill out register.
552
CD4035A Types
CMOS 4-Stage PARALLEL IN
Parallel In/Parallel Out :I' 1012

"I' 1214 \,
Shift Register
f.L
Sf~' RL
cLlcL CD403~A
App/ications p/sL 4-STAGE REGISTER
with J-K Serial Inputs and True/ TIeL
• Counters, Registers
Complement Outputs RESET L
Arithmetic-unit registers
I'" Qyr T'
VOO-16 ,
Shift left - shift right registers Vss z8
Features:
Serial-to-parallel/parallel-to-serial conversions , 01/0, 0tQz Q3 Q4/04
• 4-Stage clocked shift operation • Sequence generation TIC' OUT I
• Synchronous parallel entry on all 4 stages • Control circuits 92CS-19966A'
• JR inputs on first stage • Code conversion CD4035A

• Asynchronous True/Complement control FUNCTIONAL DIAGRAM
on all outputs
• Static flip-flop operation; Master-slave MAXIMUM RATINGS, Absolute-Maximum Values:
configuration STORAGE-TEMPERATURE RANGE (Tstgl . . . . . • . • . . . • . • • . • . . • • • • . . . . . -66 to +150oC
OPERATING-TEMPERATURE RANGE (T A ):
• Resat control
PACKAGE TYPES D. F. K. H • . . • . . • . . . . . . . . • . . . • . . . . . . . . • . . . . . -55 to +125°C
• Buffered outputs
• Low power dissipation - 51lW typ_ (ceramic) PACKAGE TYPE E . . . . . . • . . . . • • . . • . . • . . • . • . . . . . . • • • • . . . ,. -40 to +85°C
• High speed - to 5 MHz DC SUPPLY-VOLTAGE RANGE. (V DD )

• Quiescent current specified to 15 V (Voltages referenced to V SS Terminal): • • . . . . • . • • • . . • . . . • • • • . • • . . . • . . -0.5 to +15V
• Maximum input leakage current of lilA
• l-V noisa margin (full package-temper-
FOR T A = -40 to +60oC (PACKAGE TYPE E )
FOR T A = +60 to +850 C (PACKAGE TYPE E)
• • • • • . • • • • . . . . . • • • . . . . • • • . 500 mW
.•.. , ...•• Derate Linearly at 12mWfC to 200 mW
I
ature range) FOR T A = -55 to +100·C (PACKAGE TYPES 0, F, K) , . . . . • . . . . • . • . • . . . . . • • . . 500 mW
FOR T A = +100 to +12S·C (PACKAGE TYPES 0, F, K). . . .• Derate Linearly at 12mWfC to 200 mW
The RCA-CD4035A is a four-stage clocked DEVICE DISSIPATION PER OUTPUT TRANSISTOR
signal serial register with provision for FOR T A = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES). . • • • . •. 100mW
SYNCHRONOUS PARALLEL inputs to INPUT VOLTAGE RANGE, ALL INPUTS . • . • • • . . • • • • • . . . • • • • • • . • . . -0.5 to V DD +0.5V
each stage and SER IAL inputs to the first LEAD TEMPERATURE (DURING SOLDERING):
stage via JK logic. Register stages 2, 3. and At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. . • • • • . . • . . • • .. +2SSoC
4 are coupled in a serial D flip-flop config-
RECOMMENDED OPERATING CONDITIONS at TA=250 C. except as noted.
uration when the register is in the serial
mode (PARALLEL/SERIAL control low).
Parallel entry via the D line of each reg-
ister stage is permitted on Iy when the
LIMITS
PARALLEL/SERIAL control is high.
In the parallel or serial mode information CHARACTERISTIC VDD D,F,.K,H E UNITS
is transferred on positive clock transitions. (VI PACKAGES PACKAGE
When the TRUE/COMPLEMENT control is
high. the TRUE contents of the register are MIN. MAX. MIN. MAX.
available at the output terminals. When the
SupplV Voltage Range (For T A = Full
TRUE/COMPLEMENT control is low. the 3 12 3 12 V
outputs are the complements of the data in Package-Temperature Range
the register. The TRU~/COMPLEMENT
Data Setup Time, tS:
control functions asynchronously with re-
pect to the CLOCK signal. J/K Lines
5 500 - 750 -
10 200 - 250 -
ns
JK input logic is provided on the first stage
SERIAL input to minimize logic require- Parallel·ln Lines
5 350 - 500 -
ments particularly in counting and sequence-
10 80 - 100 -
generation applications. With JK inputs
connected together. the first stage becomes Clock Pulse Width. tw 5 335 - 500 - ns
a D flip-flop. An asynchronous common 10 165 - 250 -
RESET is also provided.
I
Clock Rise and Fall'Time, trCL.tfCL
5 - 15 - 15
Ils
These types are supplied in 16-lead hermetic 10 - 5 - 5
dual-in-line ceramic packages (0 and F
suffixes). 16-lead dual-in-line plastic pack-
age (E suffix). 16-lead ceramic'flat gackag~s Reset Pulse Duration. tw
5 400 - 500 - ns
(K suffix). and in chip form (H suffix). 10 175 - 200 -
553
CD4035A Types
PARALLEL PARALLEL
SERIAL
CONTROllptS)
INPUT-I
,
.7o-------~~--~~-.--~~----~~--~~--~~--~+_--~.___,
f
1
~
=400
~a 300
•• 0:-:':'::"--., :;>o---------+-+----+---+.-+----+--____-+----+----' !
~ 200
:f ,0
&s RESET
100 "
TRUE/tOMPL.
10 20 ~ ~ 50 ~ ~ ~ ~
62 !Tltl lOAD CAPACITANCE 1Cll-pf'
P/S'O'SERIAl MODE
TIC' ,. TRuE OUTPUTS
FIRST STAGE TRUTH TABLE Fig. 2 - Typical propagation delay time vs.
I_,UNPUTS} 'ntOUTPUTS) load capacitance.
J 0,
CL
...r 0 ,
On-I
o· 0, 0, 0, 04
...r ' , TERMINAL No.16·YOO

TERMINAL No. e -GND
AM81ENT TEMPERATURE (TA'"2'-C
...r ' 0
TYPICAL TEMPERATURE COEf'f'ICIENT FOR All VALUES
Of' VDO "0. 3.,.' "C
CLOCKlt! OPERATION
On-I
...r ' V55

Q~-I On-I
INPUT TO OUTPUT IS:
ALL INPUTS PROTECTED BY olA BIDIRECTIONAL LOW '''PEDANCE
COS/MDS PROTECTION NETWORK WHEN COftTROI.. INPUT liS LOW
AND CONTROL. INPUT 2 IS HIGH
til AN OPEN CIRCUIT WHEN COftTROL
INPUT I IS HIGH AND CONTROL
'NPUT Z IS lOW
Fig. 1 - Logic block diagram.

LIMITS AT INDICATED TEMPERATURES 1°C) w ~ ~ ~ ~ ~ w ~ ~
CONDITIONS D, F, K, H PACKAGES
LOAD CAPACITANCE (Cll-pF
E PACKAGE
Vo VIN VDD +25 +25 Fig. 3 - Typical transition time vs. load
-55 +125 -40 +85
IV) IV) IV) TYP. LIMIT TYP. LIMIT capacitance.
Quiescent Device
- - 5 5 0.3 5 300 50 0.5 50 700
Current, I L Max.
- - 10 10 0.5 10 600 100 1 100 1400 /J.A
- - 15 50 1 50 2000 500 5 500 5000
Output Voltage:
Low Level.
- 5 5 oTyp.; 0.05 Max
VOL - 10 10 oTyp.; 0.05 Max
V
VOH - 0 10 9.95 Min.; 10 Typ.
Noise Immunity:
Inputs Low,
4.2 - 5 1.5 Min.; 2.25 Typ.
V NL 9 - 10 3 Min.; 4.5 Typ.
V SUPPLY VOLTS IVooI
V NH 1 - 10 3 Min.; 4.5 Typ.
Fig. 4 - Typical clock input frequency vs.
Noise Margin:
Inputs Low,
4.5 - 5 1 Min.
supply voltage.
V NML 9 - 10 1 Min.
V
V NMH 1 - 10 1 Min.
Output Drive
Current:
N-Channel
ISink), 0.5 - 5 0.62 1 0.5 0.35 0,43 1 0.35 0.24
ION Min. 0.5 - 10 1.55 2.5 1.25 0.87 1.05 2.5 0.85 0.59
mA
P-Channel LOAD CAPACITlIoNCE (CLI""pf'
--Cl"50pf'
(Source): 4.5 - 5 -0.31 -0.5 -0.25 -0.17 -0.2 -0.5 -0.18 -0.12
102 104
lOP Min. 9.5 - 10 -0.81 -1.3 -0.65 -0,45 -0.56 -0.31 -0,45 -0.31 10 Ie!
INPUT CLOCK f'REQUENCY (fCll-kHZ
nCS·17111oeA3
Input Leakage
Current,
IIL,IIH :T ~nr5 ±10- 5 Typ., ±1 Max.
/J.A Fig. 5 - Typical dynamic power dissipation
charac teristics.
554
CD4035A Types
At TA =25 0 C, Input tr,tt =20 ns, CL = 15 pF, RL =200 kG
LIMITS
TEST D,F,K,H E
CONDITIONS PACKAGES PACKAGE
V DD
CLOCKED OPERATION
Propagation Delay
Time:
5 - 250 500 - 250 700
ns
t pLH , tpHL 10 - 100 200 - 100 300
Transition Time: 5 - 100 200 - 100 300

ns
t THL , tTLH 10 - 50 100 - 50 150
Minimum Clock 5 - 200 335 - 200 500
tw ns
•
Pulse Width, 10 - 100 165 - 100 250
Maximum Clock
Rise & Fall Time
5 - - 15 - - 15
ps
trCL' t fCL *
10 - - 5 - - 5
Minimum SetupTime:
-
5 - 250 500 - 250 750
ns
J/K Lines 10 - 100 200 - 100 250
5 - 100 350 - 100 500
Parallel-In Lines
10 - 50 80 - 50 100
Maximum Clock 5 1.5 2.5 - 1 2.5 -
MHz
Frequency, tCl 10 3 5 - 2 5 -
Input Capacitance, CI Any Input - 5 - - 5 - pF
RESET OPERATION
Propagation Delay
Time:
5 - 250 500 - 250 700
ns
t pHL , tpLH 10 - 100 200 - 100 300

Width, \v 10 - 100 175 - 100 200
ns
*If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time
VDD-~UTO"'-:"1 .
'DO
INPUTS
'DO
INPUO'
'DO
~
Vss
'55
V,:'L
NOTE
NEAS~R£ INPUTS
SEQUENTlAL.LY, vss
NOTE: Vss TO aoTH Voo AND 'Iss·
TEST ANY COMBINATION CONNECT AL.L UNUSED
OF INPUTS 92CS-27441 INPUTS 10 [ITHEA
Veo OR Vss
'55
Fig. 6 - Noise-immunitv test circuit. Fig. 7 - Ouiescent·device-current Fig. 8 -Input-leakage-current

test circuit. test circuit.
555
CD4037 A Types
CMOS Triple ANDIOR Bi-Phase Pairs

The RCA·CD4037A consists of three AND/
OR pairs driven by common control signals
HRZ DATA
A and B.
CONTROL
Each circuit has adata input (C), and two out· SIGNALS
put terminals (D and E) that provide outputs
in accordance with the truth table shown in D~~PHASE
MOOULATED
Fig. 1. The circuit is useful for coding or de· OUTPUTS 5 r ---- --------,jfD2
coding signals for split·phase (Bi·phase) com· ci"i AND/OR PAIR 'II
CODING WAVEFORMS
PHASE
c ----I r --------J"'E2
munication systems, magnetic recording, and MOCULATED 6 r - - - - .L--------,.!03
DATA -I _ _ _ _AND/OR
plated wire and core memory systems. A sep- 3'- _ _ _PAIR 19
_ _ _ _ .....r-E3
CONTROL
arate VCC terminal is provided to allow level SIGNALS
CD 4037A
conversion to any voltage from 3volts to VDD.
FUNCTIONAL DIAGRAM
These types are flupplled In 14-lead hermetic O~~PL~:~NTARY TRUTH TABLE
E OUTPUTS
dual-in-line ceramic packages (0 and F INPUT OUTPUT
suffixes). 14-lead dual-in-line plastic pack- DECODING WAVEFORMS A B 0 E
Fig. 1 - Coding and decoding walleforms. 0 0
o-......"'fI-....,~GATES
age (E suffix). 14-lead ceramic flat package I I
0'
I 0 C C
(K suffix). and In chip form (H suffix). Vss
0 I C C ALL INPUTS ARE PROTECTED BY
RECOMMENDED OPERATING CONDITIONS. For maximum reliability. nominal operating I I 0 0
conditions· should be selected to that operation is always within the following ranges:
Features:
LIMITS
• Outputs compatible with low-power TTL
systems.
CHARACTE RISTIC VDD D,F,K,H E UNITS • High sink and source current (1.6 mA typ.)
(V) PACKAGES PACKAGE capability at V DO = Vce= 10V and
V DS =0.5V.
MIN. MAX. MIN. MAX.
• Microwatt quiescent power dissipation:
Po = 0.5 J.lW/ceramic pkg. (typ.), Po =
Supply· Voltage Range (For T A = Full 3 12 3 12 V 2 J.lW/plastic pkg. (typ.) at VOD = 10 V
CAUTION: VCC VOLTAGE LEVEL MUST BE EQUAL TO OR LESS POSITIVE THAN VDD • Maximum input leakage current of 1 J.lA at
15 V (full package·temperature range)
DYNAMIC ELECTRICAL CHARACTERISTICS • l·V noise margin (full package·temperature
at TA = 25·C. Input t r • tf= 20 ns, CL = 15 pF. RL = 200 kn range)
LIMITS
TEST Applications:
CHARACTERISTIC CONDITIONS D,F,K,H E UNITS
.--- PACKAGES PACKAGE
• Split·phase (Si·Phase) communication sys·
tems.
VDD
(V) • Disc, drum, and tape digital recording
systems.
Propagation Delay Time: • Plated wire and core memory systems.
A and B Inputs
5 - 225 450 - 325 650 ns • High-ta-Iow logic level converter.
t pHL• tpLH
10 - 75 150 - 100 200
_ _ _ _ -90% _Voo
A, B,OR C
C Inputs 5 - 250 SOO - 350 700 INPUT
tpHL 10 - 75 150 - 100 200 ns

tpLH 5 - 225 450 - 325 650
INVERTING
10 - 90 180 - 125 250 OUTPUT
o OR E
Transition Time: 5 - 40 80 - 60 120

High·to· Low Level. ns
10 - 15 30 - 20 40 NON-INVERTING
OUTPUT
tTHL o OR E
Low·to·High Level. 5 - 75 150 - 100 200 ns 92C5-20079
tTLH 10 - 60 120 - 90 180

Fig. 2 - Waveforms for measurement of dynamic
I nput Capacitance. CI Any Input 5 5 pF characteristics.
556
CD4037A Types
MAXIMUM RATINGS, Absolute-Maximum Values: AMBIENT TEMPERATUREITA'.25-C
COLLECTOR SUPPLY VDLTS(VCCr-s
TEMPERATURE COEFFICIENT FOR ALL
STORAGE·TEMPERATURE RANGE (T,ty) ..•...•••.•.•..••.......• -65 to +150' C c: VALUES OF VOO-O.3 "I.'-C
OPERATING·TEMPERATURE RANGE (TA): ~200

PACKAGE TYPES D. F, K, H • • • . • • • • • • • • . . • . • • • • • • • • • • • . • •• -55 to +125' C
PACKAGE TYPE E -40 to +85' C'
(Voltages referenced to VSS Terminal) . • . . . . . . . . . . .
FOR T A ~ -40 to +60' C (PACKAGE TYPE E)
-0.5 to +15 V
500 mW
..
FOR TA ~ +60 to +85' C (PACKAGE TYPE E) Derate Linearly at 12 mW/' C to 200 mW
LOAD CAPACITANCECCLI-pF
FOR T A; -55 to +100·C (PACKAGE TYPES D. F. K) • • . ••• . ••• •. • . . 500 mW
FOR T A ; +100 to +125·C (PACKAGE TYPES D, F, K) Derate Linearly at 12 mW/' C to 200 mW Fig. 3 - Typical transition time vs.
DEVICE DISSIPATION PER OUTPUT TRANSISTOR load capacitance.
FOR TA; FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS -0.5 to V DD +0.5 V
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max. • . • • • . . •• +265' C

LIMITS AT INDICATED TEMPERATURES (·C)
•
CONDITIONS
D, F, K, H PACKAGE~ E PACKAGE
Vo VIN V DD +25 +25
-55 +125 -40 +85
(V) (V) IV) TYP. LIMIT TYP. LIMIT
- - 5 5 0.03 5 300 50 0.1 50 700

Quiescent Device ,
Current, I L Max. - - 10 10 0.05 10 600 100 0.2 100 1400 J.l.A LOAD CAPACITANCE (CLI-pF
- - 15 50 1 50 2000 500 5 500 5000

Fig. 4 - Typical transition time vs.
Output Voltage:
Low Level,
- 5 5 oTyp.; 0.05 Max load capacitance.
VOL - 10 10 o Typ.; 0.05 Max

V
V OH 9.95 Min.; 10 Typ.
- 0 10
Noise Immunity:
Inputs Low.
4.2 - 5 1.5 Min.; 2.25 Typ.
V NL 3 Min.; 4.5 Typ.

9 - 10
V
V NH 3 Min.; 4.5 Typ.
1 - 10
Noise Margin:
Inputs Low,
4.5 - 5 1 Min.
V NML 9 - 10 1 Min.
V
V NMH 1 Min. Fig. 5 - Typical propagation delay time vs.
1 - 10
Output Drive load capacitance.
Current:
N·Channel
(Sink), 0.5 - 5 0.85 0.7 1.2 0.45 0.4 0.35 0.7 0.3
~
IDN Min. -
0.5 10 1.3 1.1 2 0.7 0.65 0.55 1.1 0.45
rnA ,~
5
P·Channel ~
(Source): 4.5 - 5 -0.65 -0.55 -1 -0.35 -0.35 -0.3 -0.55 -0.2 U
IDPMin. 9.5 - 10 -0.9 -0.75 -1.6 -0.45 -0.5 -0.4 -0.75 -0.3 I.'
Input Leakage
-T~T:5
Current, ~
IIL,IIH ±1O-5 Typ., ±1 Max. J.l.A
For quiescent device current, noise immunity, and input leakage current test circuits see
"Ratings and Characteristics" at the beginning of the CMOS section.
-
(O-2'-_ _---1'7""_ _--'--,-_ _. L_ _---'
~ ~ ~
INPUT FREQUENCY ttl - HI
..PACtlAGE CONTAINS 6 AND-OR CIRCUITS
~
557
CD4040A Types
CMOS 12-Stage
Ripple-Carry 0'2 I. ,S vDD
Features:
Binary Counter/Divider - Medium-speed operation • 5 MHz (typ.) input pulse
as
05
07
2
3 ,.
'5 all
0'0
'3 08
rate at VDD - VSS = 10 V Q4 '2 09
03
The RCA-C04040A consists of an input-
pulse-shaping circuit and 12 ripple-carry
- Low output impedance •. 750 n (typ.) at VDD - VSS
= 10 V and VDS= 0.5 V
02 "
'0
•
R
Vss a'
binary counter stages_ Resetting the counter - Common reset - Fully static operation
to the all-O's state is accomplished by a
- All 12 buffered outputs available
high-level on the reset line. A master-
slave flip-flop configuration is utilized for - Low-power TTL compatible 92CS-20747RI
each counter stage. The state of the counter - -Quiescent current specified to 15 V
is advanced one step in binary order on the - Maximum input leakage current of 1 p.A CD4040A
negative-going transition of the input pulse. at 15 V (full package-temperature range) TERMINAL DIAGRAM
All inputs and outputs are fully buffered. - 1-V noise margin (full package-temper-
These.types.are supplied in l6-lead hermetic ature range)
dua1-in-ltne ceramic packages (0 and F Applications:
suffixes). le-Iead dual-in-line plastic pack- AMBIENT TEMPERATURE ITAI • 15·C
age (E suffix). l6-lead ceramic flat package - Frequency-clividing circuits TYPICAl.. TEMP. COEFFICIENT AT ALL VAWES OF VGS" -0.3%I·C
(K suffix). and in chip form (H suffix). - Time-clelay circuits - Control counters TE-TO-SOURCE VOLTAGE I '"I!! V
r 12.5
RECOMMENDED OPERATING CONDITONS at TA = 250 C, Except as Noted: 8 10

For maximum reliability, nominal operating conditions should be selected so that operation is ~
~
~ 1.5
always within the following ranges :
LIMITS ,..
CHARACTERISTIC
D,F,K,H E
UNITS 2.!! 5
•• 7.S 10 12.S IS
VDD Packagea Package CRAIN - TO - SOURCE VOLTAGE tVcsl-v
(V) Min. Max. Min. Max.

Fig.2 - Typical output n-channel
Supply Voltage Range (For TA = Full drain characteristics.
3 12 3 12 V
Input Pulse Width, tw 5 400 - 500 - DRAIN-TO-S(X.IIC£ YOLmGE (VosI-V
10 110 - 125 -
ns -.
Input-Pulse Frequency, ftjJ 5 dc 1.5 dc 1.5
MHz
10 dc 4 dc 4
5 15 15
Input-Pulse Rise or Fall Timll, trtjJ,tftjJ p.s
Reset Pulse Width, tw

10
5
10
15
1000
500
-
-
-
15
1250
600
-
-
- ns GATE-TO-SOl.llCE YOLTAGE ( '"ISV
-'0 !
I
~
AMBIENT TEMPERATURE ITAl -2S"C

TYPICAL TEMP. COEFFICiENT ATALL VALUES OF VGS"-o.3"4/",
-"
Fig.3 - Typical output p-channel

Q, OUT- (QIH6:.)(ih
ROD ;>0----09
tss
*PROTECTED
AU. INPUTS ARE
BY • R-HiGH DOMINATES (RESETS ALL STAGES)
COSI MOS PROTECTION AACTION OCCURS ON NEGATIVE GOING
NETWORK TRANSITION OF INPUT PULSE. COUNTER
_
'}'NTOPUTS
STAGE
2nd
92CS-Z0522
ADVANCES ONE BfNARY COl.WT ON EACH
NEGATIVE f TRANSITION 14096 TOTAL
BINARY COUNTS).
92CM-2074BR3
Fig.4 _. Functional diagram.
Fig. I - Logic diagram of CD4040A input pulse shaptlr and t of 12 srages.
558
CD4040A Types
MAXIMUM RATINGS, Absolute·Maximum Values: AMBIENT TEMPERATURE (T"I. i;O"C
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF vGS' -O'%I"C
STORAGE·TEMPERATURE RANGE ITstgl
1.'
OPERATING·TEMPERATURE RANGE ITAI: TE-TO-SOURCE VOLTAGE l'tOV
PACKAGE TYPES 0, F, K, H -55 to +125 0 C

PACKAGE TYPE E -40 to +8so C
OCSUPPLY·VOLTAGE RANGE, IVOOI
(Voltages referenced to VSS Terminal!...................................... -0.5 to +15 V 133.75
POWER DISSIPATION PER PACKAGE IPOI: Z JOV
FOR T A = -40 to +60 0 C IPACKAGE TYPE E) 500mW ~ 2.5
FOR T A = +60 to +85 0 C IPACKAGE TYPE Ell Derate Linearly at 12 mW/oC to 200 mW I."
FOR TA = -55 to +loo·C (PACKAGE TYPES 0, F, K) ................ 500 mW
Z:I :I
.v 1.5 10 12.5 .:1
FOR TA = +100 to +125·C (PACKAGE TYPES 0, F, K) , . Derate Linearly at 12 mW/oC to 200 mW
DRAIN - TO - SOURCE VOLTAGE 'Vosl-9~CS'21~12
FOR TA = FULL PACKAGE·TEMPERATURE RANGE IALL PACKAGE TYPESI. ...... 100 mW Fig.S - Minimum output n-channel
INPUT VOLTAGE RANGE. ALL INPUTS............. ................. ... -0.5 to V DO +0.5 V drain characteristics.
LEAD TEMPERATURE lOURING .~OLDERINGI:
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ............. . DRAIN-lO-SOlACE VOLTAGE 'VDsI-V
-IS
STATIC ELECTRICAL CHARACTERISTICS GAlE-TO-SOURCE VOLTAGE' I.I~V

I
Limits at Indicated Temperatures (OC) AMaENT TEMPERATURE 'TA J • 25·C
Conditions TYPICAL TEMR COEFFICIENT AT ALL VALUES OF VGS. -0.3%/'"(
Characteristic 0, F, K, H Packages E Package Units
Vo VIN VOO -55 +25 +125 -40 +25 +85
(V) (V) (V) Typ. Limit Typ. Limit Fig.6 - Minimpm output p·channel
Quiescent Device - - 5 15 0.5 15 900 50 1 50 700
Current, - - 10 25 1 25 1500 100 2 100 1400 I1A
IL Max. - - 15 50 2.5 50 2000 500 5 500 5000
Output Voltage:
Low·Level, - 5 5 a Typ.; 0.05 Max.
VOL - 10 10 a Typ.; 0.05 Max.
V
High·Level - a 5 4.95 Min.; 5 Typ.
VOH - a 10 9.95 Min:; 10 Typ.
Noise Immunity:
VNl 9 - 10 3 Min.; 4.5 Typ.
V
LOAD CAPACITANCE 'CLI-pF
VNH 1 - 10 3 Min.; 4.5 Typ.
Noise Margin: Fig] - Typical propagation delay time vs.
4.5 - 5 1 Min.
load capacitance (per stage).
Inputs low,
9 - 10 1 Min.
VNMl
V
VNMH 1 - 10 1 Min.
Output Drive
Current:
N·Channel
(Sink). 0.5 - 5 0.22 0.36 0.145 0.102 0.21 0.36 0.08 0.056
ION Min. 0.5 - 10 0.44 0.75 0.4 0.250 0.42 0.75 0.2 0.14
mA
P·Channel
(Source): 4.5 - 5 -0.15 -0.25 -0.1 -0.07 -0.15 -0.25 -0.06 -0.04
lOP Min. 9.5 - 10 -0.03 -0.5 -0.25 -0.175 -0.29 -0.5 -0.15 -0.1
Input Leakage
Current, Any Input
IIL.IIH - - 15 ±10- 5 Typ., ±1 Max. p.A Fig.S _ Typical transition time vs. load
capacitance.
559
CD4040A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =25°C, Input tr, tt =20 ns, 10 AMBIENT TEMPERATURE ITAJ·2~·C:
CL = 15 pF, RL = 200 k!2
LIMITS
Test Conditions D,F,K,H E
~
Packages Package
Input·Pulse Operation LOAD CAPACITANCE ICL1-I!!ipF
--CL-50pF
Propagation Delay
Time, 5 - 450 900 - 450 950
ns 10 10 2 103 10'
tPLH, tPHL· 10 - 225 450 - 225 475 INPUT FREQUENCY (f.t-kHz

9ZCS-2i5I!1RI
Fig.9 - Typical dissipation characteristics.

Transition Time, 5 - 150 300 - 150 350
ns
tTHL, tTLH· 10 - 75 150 - 75 175
Maximum Input·Pulse 5 1.5 2.5 - 1.5 2.5 -
MHz
Frequency, frp 10 4 6 - 4 6 -
Minimum Input·Pulse 5 - 200 400 - 200 500
f=100 kHZ ns
Width, tw 10 - 75 110 - 75 125 AMIIENT TEMPERATURE ITA I-n·e
LOAO CAPACITANCE Ie I. I!I pF
Input·Pulse Rise & 5 - - 15 - - 15

liS
Fall Time, trrp, tfl' 10 - - 7.5 - - 7.5
Average Input
Capacitance, CI
Reset Operation
ns
Time, tPHL' 10 - 250 500 - 250 600
Minimum Reset 5 - 500 1000 - 500 1250
ns 10 15
Pulse Width, tw 10 - 250 500 - 250 600 SUPPLY VOlTStVDDI

9ZCS'Z~"4RI
Fig. 10 - Typical input-pulse frequency

VI. supply voltage.
• Measured from the 50% level of the negative .. Maximum input rise or fall time for func·
input pulse edge to the 50% level of either tional operation.
the positive or negative edge of the 01 out· • Measured from the positive edge of the re,
put (pin 9); or measured from the nega· set pulse to the negative edge of any output
tive edge of 01 through all outputs to '(01 to 012).
the positive or negative edge of the next
higher output.
VDO
.
VDO
VIS
INPUTS
Y 1NPUOS
VDO NOTE
INPUTOVDO
OUTPurs oo
voo'.:::'" ~
.
.
~
Yss
~
MEASURE INPUTS
SEOUlNTiALLY.
TO BOTH Yoo ANDVss
YNL _ CONNECT ALL UfilUSm
l. .lITS 10 EITH[R
NOTE: Voo OR VSS·
TEST ANY ONE INPUT, VSS
Yss WITH OTHER INPUTS AT Vss
92CS-27~OO Veo ORYSS·
Fig. 12 - Quiescent-device-current test circuit. Fig. 13 - Input-Ieakage-current test circuit.

Fig. 11- Noise-immunity test circuit.
560
CD4041 A Types
resistor·network driver for AID and D/A
CMOS Quad conversion, as a transmission·line driver, and
True/Complement in other applications where high noise im·
munity and low·power dissipation are pri·
Buffer ··mary design requirements.
These types are supplied in 14-lead hermetic

The RCA·CD4041 A types are quad truel dual-in-line ceramic packages (D and F
complement buffers consisting of n· and suffixes). 14-lead dual-in~line plastic pack-
p·channel units having low channel resistance age (E suffix), 14-lead ceramic flat packages
and hiQh current (sourcinQ and sinking)capa· (K suffix), and in chip form (H suffix).
bility. The CD4041A is intended for use as
a buffer, line driver, or COS/MOS·to·TTL
driver. It can be used as an ultra·low power

STORAGE·TEMPERATURE RANGE (T stg ) -66 to +lS00C
OPERATING·TEMPERATURE RANGE (T A ):
PACKAGE TYPES 0, F, K, H -SS to +12SoC
DC SUPPLY·VOL TAGE RANGE. (VDD).
(Voltages referenced to VSS Terminal)................... ................... -O.S to +15 V
•
FOR T A = -40 to +SOoC (PACKAGE TYPE E) SOOmW
FOR T A = +60 to +8SoC (PACKAGE TYPE EI) Derate Linearly at 12 mW/oC to 200 mW
FOR T A = -55 to +l00'C (PACKAGE TYPES 0, F, K) .................. SOOmW Features:
FOR T A = +100 to +125'C (PACKAGE TYPES 0, F, K) ..... Derate Linearly at 12 mW/oC to 200 mW True Output
DEVICE DISSIPATION PER OUTPUT TRANSISTOR • High current source and sink capability
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TyPES)....... 100 mW
8 mA (typ.) @ VOS =0.5 V, VOO = 10 V
INPUT VOL TAGE RANGE. ALL INPUTS. .. .... ....... -0.5 to V DD +0.5 V
LEAD TEMPERATURE (DURING SOLDERING): .
3.2 mA (typ.) @ VOS = 0.4 V, VOO = 5 V
At distance 1/16 ± 1/32 Inch 11.59 ± 0.79 mml from case for 10 s max. +266 o C (two TTL loads)
Complement Output
• Medium current source and sink capability
3.6 mA (typ.) @ VOS = 0.5 V, VOO = 10 V
1.6 mA (typ.) @ VOS = 0.5 V, VOO = 5 V
RECOMMENDEO OPERATING CC,lNOITIONS • Quiescent current specified to 15 V
For maximum reliability, nominal operating conditions should be selected so that • Maximum input peakage of 1 IJ.A at 15 V
operation is always within the following range: (full package·temperature range)
• l·V noise margin (full package temperature
LIMITS
CHARACTERISTIC UNITS range)
Min. Max.
Supply Voltage Range (For TA = Full Package Applications:
Temperature Range) 3 12 V • High current source/sink driver
• CMOS-to-DTL/TTL Converter
• Oisplay driver
VDD
JD JD •
•
MOS clock driver
Resistor network driver
(Ladder or weighted R)
~L~TRUE
~S--0UTPUT
• Buffer
• Transmission line driver
Vss 1 , Vss Vss

* ALL. INPUTS PROTECTED
BY COS/MOSPROTECTlQN
NETWORK VDD
d
-------OOCOMPLEMENT
} OUTPUT
! Vss 92CS-2003!!RI
Fig.1- CD4041A schematic diagram.
561
CD4041A Types
DVNAMIC ELECTRICAL CHARACTERISTICS at TA = 2SOC and CL = 15 pF. RL = 200 kSl
TEST LIMITS
CONDITIONS D.F,K,H E
(VoIU) TVP. MAX. TVP. MAX.
Propagation Delay Time: True 5 65 115 65 140
ns
High·to-Low Level Output 10 40 75 40 100
tpHL Compo 5 55 100 55 125
ns
Output 10 30 45 30 65
True 5 75 125 75 150
ns
Low-to-High Level Output 10 45 75 45 100
Hes-2Q042
tpLH Compo 5 45 100 45 125 Fig.S - Minimum output n-channel drain charac-
ns teristics -complement output.
Output 10 25 50 25 60
Transition Time: True 5 20 40 20 60
ns
High-to-Low Level Output 10 13 25 13 40
tTHL Compo 5 40 60 40 80
ns
Output 10 25 40 25 50
True 5 20 40 20 60 ns
Low-to-High Level Output 10 13 25 13 40
Compo 5 35 55 35 75
tTLH ns
Output 10 25 40 25 50
Input Capacitance CI Any Input 5 - 5 - pF
DRAI't'TO-$OURCE VCM,.TAGl:1YOSI-V
Flg.S - Minimum output p-chsnnel drain charac-
.. reristics - complement output•
>
.• ~o
'V "lOY
~ ''':''ENT I.TEM..kRAnlRE
11 1c I
10 AMBIENT TEMPERATURE:
!
IT"l-Z"e
o
~.~"
1• 2 .1_ ;,./
or--- ----h 1 ••~;:ft/
o
...
..
Yoo· 0
0
~
J
-Jfio-'
1" l'Illn""'"J,
NOO,·\5"
I I
I--
- ~
10 12 14 18 II '0 2ll 50 40 SO 60 70
L.OAD CAPACITANCE (CL.I-PF
80 90
92CS-20044
92CS-20046
Fig. to - Minimum and maximum transfer charac- Fig. t, - Minimum and maximum transfer charac-
teristics - true output. teristics - complement output. Fig. 12 - Typical transition time VI.
CL - true output.
AMBIENT TEMPERATURE
IT.1·2.·C
J. I, ,.~
l"llll""-- I::::::: AMBIENT TEM~R'T0RE I. V
• "",",.G;';"';- r- ITj' .... c. ,.~;'"
suPP~
0 I...~,.~
f-"
0
0
-- J4:-- -L
IVnn"I'"'
~
f--
roo- r--;.--).fr"J
lJ""':..J.,-.-
_ -:::! ·""'. . . . -
WOO,s\fiN -
f.- i-" ~
•o ~ ~ ~
J
~ ~ ro ~ ~
.0 20 ~
I
40 so
J 60 70 80 90
LOAD CAPACITANCE ICLl-PF LOAD CAPACITANCE {CLI-PF
92CS-20048 L.OAD CAPACITANCE (CLl-PF
92CS-20041 92CS-20049
Fig. 73 - Typical high-to-Iow level transition Fig. 74 - Typicallow-to-high level propagation Fig. 15 - Typicallow-to-high level propagation
time VS', CL - complement output. delay time .... CL - true output_ delay time vs. CL - complement output.
562
CD4041 A Types

Conditions
Characteristic
D, F, K, H Packages E; Package.
Units
Vo VIN VDD -55 +25 +125 -40 +25 +85
Current, I L - - 10 2 0.005 2 120 20 0.02 20 280 p.A
Max. - - 15 25 0.25 25 1000 250 2.5 250 2500
Output Voltage:
Low·Level,
- 0.5 5 oTyp.; 0.05 Max.
0.10 10 oTyp.; 0.05 Max. * nETIME
FIG.17 FOR INPUT RISE ANO FALL
VOL UMITATIONS
V
H igh·Level, - 0.5 5 4.95 Min.; 5 Typ. Fig.2 - Typical output n-channel drain charac-
VOH - 0.10 10 9.95 Min.; 10 Typ. teristics - true output.
Noise Immunity:
Inputs Low,
3.6 - 5 1.5 Min.; 2.25 Typ.
7.2 - 10 3 Min.; 4.5 Typ.
VNL
V
VNH 2.8 - 10 3 Min.; 4.5 Typ.
•
Noise Margin:
Inputs Low,
4.5 - 5 1 Min.
VNML
9 - 10 1 Min.
V
VNMH 1 - 10 1 Min.
Output Drive
0.7
Current: ~
0.5
True
5
10
2.1
6.25
3.2
10
1.6
5
1.2
3.5
1
3
3.2
10
0.8
2.5 2.2
ORAIN-TD-SOURCE \oOI...TAGE !Vosl-V
N·Channel
(Sink), ~ Compo 5 1
2.5
1.6
4
0.8
2
0.55 0.5
1.2
1.6 0.4
1
0.35
0.9 Fig.3 - Typical output p--channel drain cherac-
ION Min. 0.5 10 1.4 4
rnA reristies - true output.
-2- ~
5 -1.75 -2.8 -1.4 -1 -0.85 -2.8 -0.7
P-Channel
(Source) 9.5
#
True
10 -5 -8 -4 -2.8 -2.4 -8 -1.8 MAX. AVERAGE DISSIPATION
5 -0.75 -1.2 -0.6 -0.4 -0.35 -1.2 -0.3 -0.27 *
lOP Min. #9.5
Compo
10 -2.25 -3.6 -1.8 -1.25 -1.1 -3.6 -0.9 -0.8
PER OUTPUT (lOOmW)
I n put Leakage
Current, Any Input 15 ±10- 5 Typ.; 1 Max. p.A
IIL.IIH
*SEE FIG.17 FOR INPUT RISE AND FALL

TIME LU.ttTATIONS
Fig.4 - Typical output n-channel drain charac-

teristics - complement output.
DRAIN-Ttl-SOURCE VOLTAGEIVDSI-V
O~AlN-TO-SOUACE VOLTAGE tVosH/
UCS-Z0040
Fig.5 - Typical output p-channel drain charac- Fig.6 - Minimum output n-channel drain charac- Fig.7 - Minimum output p--channel drain charac·
ter/sties - complement output. teristics - true output. teristics - true output.
563
CD4041A Types
VOO
.
Vss
INPUTS
,
"
Alllf.IY·"
101 10" 105 10'

INPUT fliSt. , .. ~~ TIIII;- ..
. Vss
Fig. 16 - Typical power dissipation vr. Fig. 77 - Typical power dissipation vs. input Fig. 18 - Quiescent device current test circuit.
frequency per output pair. rise & fall time per output pair.
INPUTOV'"OUTPUTS
YOO-VNH Yeo Voo NOTE'
,NPuDs
"---
V:L
~
J ~ ;::~:I!~~~
Yss TO BOTH Voo AND Vss'
CONNECT ALl. UNUSED
NOTE: INPUTS 10 EITHER
TEST ANY ONE INPUT,
Yss WITH OlHER INPUTS AT Yoo CRYss'
92C$- 21400 Voo DR Yss' Vss
Fig. 19 - Noise immunity test circuit. Fig.20 - Input le~kage current test circuit.
564
CD4042A Types
CMOS Quad Clocked "0" Latch D, 0,

The RCA-CD4042A types contain four latch and POLARITY levels defined above are
circuits, each strobed by a common clock_ present_ When a CLOCK transition occurs
Complementary buffered outputs are availa- (positive for PO LAR ITY = 0 and negative o-D'_-IH r----.:°:.e.'-o 'D
0,
ble from each circuit_ The impedance of the for POLARITY = 1) the information present D,
n- and p-channel output devices is balanced at the input during the CLOCK transition is
an~ all outputs are electrically identical_ retained at the outputs until an opposite D. t-LJI--:-:Q,:.-o "
Information present at the data input is CLOCK transition occurs_ "O---t-fr-----""-Q
transferred to outputs Q and IT during the
•~~~"
These types are supplied in 16-lead hermetic CLOCK
CLOCK level which is programmed by the dual-in-line ceramic packages (D and F
POLARITY input_ For POLARITY = 0 the suffixes). 16-lead dual-in-line plastic pack-
POLARITY
transfer occurs during the 0 CLOCK level age (E suffix), 16-lead ceramic flat package .O-,........'--l..J
and for PO LAR ITY = 1 the transfer occu rs (K suffix), and in chip form (H suffix). VDD~ UCS-ZOItI
V5S~
during the 1 CLOCK level_ The outputs
CD4042A
follow the data input providing the CLOCK
FUNCTIONAL DIAGRAM
STORAGE-TEMPERATURE RANGE (Tstgl ..•••• , •. , •.•.•••.•••. _ •...-65 to +150oC Features:

PACKAGE TYPES D, F, K, H ••••••.•••.•••• ,. _ •.•••••••••••.. -55 to +125 0 C • Clock polarity control
PACKAGE TYPE E .••.•..•.••.•.••..• , ••••.•••••••••.•••• -40 to +85 0 C • Q and IT outputs
•
DC SUPPLY-VOLTAGE RANGE, (VDDI • Common clock
(Voltages referenced to VSS Terminall: .• _ .. _ •••• _ . . . • • • • . • • . . • • • • • -0.5 to +15 V • Low power TTL compatible
POWER DISSIPATION PER PACKAGE (PDI: • Quiescent current specified to 15 V
FOR T A = -40 to +60oC IPACKAGE TYPE E) . • . • . . . . _ ...••••.•••••••• 500 mW • Maximum input leakage of 1 fJA at 15 V
FOR T A = +60 to +85°~ (PACKAGE TYPE E I .••••. Derate Linearly at 12 mW/C to 200 mW {.full package-temperature range)
FOR TA =-55 to +100'C (PACKAGE TYPES D, F, K) .•.•••••.•••••• , , ••••• 500 mW • 1-V noise margin (full package-temperature
FOR TA = +100 to +125'C (pACKAGE TYPES D, F, K) .•• Derate Linearly at 12 mW/oC to 200 mW range)
DEVICE DISSIPATIO!'l PER OUTPUT TRANSISTOR
Applications:
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) .•••••• 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS •.••••.••• .- •.•••.• , ••. , . -0.5 to VDD +0.5 V
• Buffer storage
• Holding register
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max •••.•••.•••••• +265 0 C
• General digital logic
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input t r , If= 20 ns, CL = 15 pF,
RL = 200 Kil
D,
LIMITS
VOO D,F,K,H E
(V) PackaJJ.es Packags
Typ, Max. Typ. Max.
fCONTROi- ---p- - - ----l
Propagation Delay
Time: tPHL, tpLH
Data In to Q
5
10
150
75
300
150
150
75
400
200
ns
"CCK~"
• I CL II
I P
5 250 500 250 600 ns I " " I

Data In to Q 10 100 200 100 250
: ' :
Clock to Q
5 300 600 300 750
ns POLARITV~P I
10 125 250 125 300 6 I v ~_ I
L ________ -"___ -.J
5 400 800 400 1000
Clock to 6 10 175 350 175 400
ns
Transition Time: 5 100 200 100 300 ns

~DD
tTHL, tTLH 10 50 100 50 150
tss
*AIJ. INPV1'S ARE
Minimum Clock 5 175 250 175 350 PROTECTED BY
ns COS/IIOS PADTEC TION
Pulse Width, tw 10 60 120 60 175 NETWORK
Minimum Hold 5 150 300 150 350 ns

Time, tH 10 60 120 60 150 CLOCK POLARITY Q
Minimum Setup 5 0 50 0 50 0 0 D
ns
Time, ts 10 0 30 0 30 ....r 0 LATCH
Minimum Clock Rise 5 1 1 D
Not rise or fall time sensitive. ps
or Fall Time: tr , tf 10 ~ 1 LATCH
Input Capacitance, CI Fig. 1 - Logic block diagram & truth table.
(Any Input)
- 5 - 5 - pF
565
CD4042A Types
=
RECOMMENOEO OPERATING CONOITIONS at TA 25°C. Except as Notad. AMBIENT TEMPERATURE CTA' .215-C
TYPICAL. TEMPERATURE COEFFICIENT FOR Io··o.3"re'·C
CHARACTERISTIC
VOO D.F.K.H
LIMITS
E UNITS
...
~..
115
..TE·'.·'....CE ""'AGE 1'10".,..
(V) Packages Package ,.v

•i ,.
Min. Max. Min. Max.
(For T A = Full Package
Temperature Range)
- 3 12 3 12 V
U
ov
1.5 10 12.5 15
DRAIN-TO-SCUI:l VOLTAGI: (VDSI-V
Clock Pulse 5 350 - 250 ~
ns
Width. tw 10 175 - 120 - Fig. 2 - T"pical output n-chsnn.1 drain
5 50 - 50 - ns
chsractBristics.
Setup Time. ts 10 30 - 30 -
5 350 - 300 - ns
DRAII-TO-SOUU 'IOL1IGE 'Vos'-V
Hold Time. tH
10 150 - 120 - -I -to
Clock Rise or Fall 5

Not rise or fall time sensitive. IJ$
ov
..
Time: t r• tt 10 IOV
u.'E-TO-S~TAGlI ,a""
... :
Limits at Indicatad Temperaturas (oC)
···1
Conditions
D. F. K. H Packages E Package
Vo ~IN VOO -65 +25
+125 -40
+25
+85
IV) (V) (V) Fig. 3 - T"pical output p-chsnn.1 drain
characterisrics,
Current. IL Max. - - 10 2 0.005 2 120 20 0.02 20 280 p.A
- - 15 25 0.25 25 1000 250 2.5 250 2500
Output Voltage:
Low· Level.
- 0.5 5 o Typ.; 0.05 Max. .,
VOL - 0.10 10 oTyp.; 0.0s Max. V
High Level. - 0.5 5 4.95 Min.; 5 Typ.
VOH - 10.10 10 9.95 Min.; 10 Typ.
Noise Immunity:
Inputs Low.
4.2 - 5 1.5 Min.; 2.25 Typ. CD404ZAD.CD4042AIC, ~
CD4042AF
VNL 9 - 10 3 Min.; 4.5 Typ.

V
2.'
Inputs High. 0.8 - 5 1.5 Min.; 2.25 Typ.
'----c ".S
C040" ___} : ' - :
IS
VNH 1 -' 10 3 Min.; 4.5 Typ. DRAIN - TQ - SOURCE YCK.TAGE IVosl
Noise Margin:
Inputs Low.
4.5 - 5 1 Min. Fig. 4 - Minimum n--channel drain characterilties.
VNML 9 - 10 1 Min.
V
DRAIN - TO- SOURCE 'IOLlAGE (Vnsl-V
VNMH 1 - 10 1 Min. -,
Output Drive
Current:
n·Channel
0.5 - 5 0.5 1 0.4 0.27 0.24 1 0.2 0.18
(Sink).
ION Min.
0.5 - 10 1.25 2 1 0.7 0.6 2 0.5 0.45
mA
p·Channel 4.5 - 5 ·0.45 ·1 ·0.35 ·0.25 ·0.2 ·1 0.17~ ·0.15
(Source).
lOP Min. 9.5 - 10 ·1.15 ·2 ·0.9 ·0.6 ·0.34 ·2 ·0.45 ·0.4
Input Leakage
Any
Current. 15 ±1O-5 Typ.; 1 Max. p.A
Input Fig. 5 - Minimum p--channs/ drain charactsrlstics.
IIL.IIH Max.
566
CD4042A Types
1 NOTE I
CLgLCK ~'-----------l'----
NOTE 2 I
DATA
IN~UT t
~I
DATA :I
.1
f-tsttl:l-I
I
I
I
LATCH HIGHI I
~I L -__~_____ _
LOAD CAPACITANCE ttl) - pF
gZCS-2J'&31 92CS-Z7632
{t~~C~~bAi
Fig. 1- Typical propagation delay tima VI. Fig. 8 - Typical propagation dalay tima VI. load
o load capacitance- datB to Q. capacitanes - data to Q.
OUTPUT I
I
HIGH DATA
LATCHED
tpHL' tpLH
CLTOQOR~
•
NOTES:
I. FOR POSInVE CLOCIC EDGE,INPUT DATA IS LATCHED WHEN
POLARITY IS LOW.
2. FOR NEGATIVE CL.OCK EDGE, INPUT DATA IS LATCHED WHEN
POLARITY 19 HIGH.
92CS'Z7630
LOAD CAPACITANC£ ICl) - pF LOAD CAPACITANCE ICl) - pF

92CS-27633 92CS·27.3~
Fig. 9 - Typical propagation delay tima v.. load Fig. 10 - Typical propagation dalay tima VI. load
capac/tanes - clock to Q• capacitance - clock to Q.
•
f
~ 10
a
~
~ 10
LOAD CAPACITANCE CL '15 pF
CL"!50pF---
.
·00
·ss
INPUTS
·ss
9Zt'S-27441
Fig. 12 - Qu/escent device current test circuit. Fig. 13 - Noise immunity tost circuit.
INPU(JS
.",
Voo NOTE:
~ ::~i:;I~~~~~S
Vss TO aoTH Voo ANO VSS'
CONNECT ALL UNUSED
INPUTS TO EITHER
VDO OR Vss'
Vss
Fig. 14 - Input leakage current test circuit.
567
CMOS Quad ------- 3-State
RIS Latches 5,
"I
Quad NOR R/S Latch - CD4043A 52
O.
Quad NAND R/S Latch - CD4044A "2
5,
The RCA-CD4043A types are quad cross- 0,
coupled 3-state CMOS NOR latches and the ".
C04044A types are quad cross-coupled s.
3-state CMOS NAND latches. Each latch
has a separate Q output and individual SET
-. Q.
and RESET inputs. The Q outputs are can· ENABLE Ne ENABLE
trolled by a common ENABLE input. A log- CD4043A Vss 92CS-2022IRI

ic "1" or high on the ENABLE input can· FUNCTIONAL DIAGRAM 12C5·20222
FUNCTIONAL DIAGRAM
nects the latch states to the Q outputs. A
logic "0" or low on the ENABLE input Features:
disconnects the latch states from the Q out- Applications:
puts, resulting in an open circuit condition • 3-Level outputs with common
on the Q outputs. The open circuit feature • Holding register in multi· . output ENABLE
allows common busing of the outputs. The register system
• Separate SET and RESET inputs
logic operation of the latches is summarized • Four bits of independent for each latch
in the truth table shown in Fig. 1. storage with output ENABLE
• NOR and NAND configuretions
These types are supplied in 16-lead hermetic • Strobed register • Quiescent current specified to 15 Y
dual-in-line ceramic packages (0 and F • General digitellogic
suffixes), 16-lead dual-in-line plastic pack- • Maximum input leakage of 11JA at 15 Y
age (E suffix), 16-lead ceramic flat packages (full package-temperature range)
(K suffix), and in chip form (H suffix). • 1·Y noise margin (full peckage-temperature
range I
MAXIMUM RATINGS, AbsolullI·Maximum Valutls: CD4043A- NOR
STORAGE·TEMPERATURE RANGE (Totgl . . . . • . • • • • . . • . . • • • . • . . • • . . .-65 to +150oC

OPERATING·TEMPERATURE RANGE (TAl: °
PACKAGE TYPES D, F, K, H ••••.•..•••..•••••.••..•••.•.-55 to +125 C
PACKAGE TYPE E ..•.•.••••..•.•.••••.•••.•.••...••.•..• -40 to +S50C
(Voltages referenced to Vss TermlnaU: . • . • • . . • • • • . • • . • . • . • • • . . . • . • -0.5 to +15 V
FOR TA = -40 to +sooc (PACKAGE TYPE EI
FOR T A = +60 to +S50C (PACKAGE TYPE E I
.•••..•.••••.•• , •.•••••.• 500 mW
.••••. Der.", Linearlv at 12 mW/oC to 200 mW
EN~~ 5 _ 0
FOR T A = -55 to +100·C· (PACKAGE TYPES D, F, K) .•••.•.••..•••.••••••• 500 mW x x OC·
r
FOR A = +100 to +125·0 (PACKAGE TYPES D. F, K) ... Derate Linearlv at 12 mWlC to 200 mW o a
I 0
NC+
I
DEV ICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) •.••••. 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS .•.••.••••..•••..•..•••• -0.5 to VDD +0.5 V
I
o
·OPEN CIRCUIT
+ NO CHANGE
I
I I>
A DOMINATED By S. IINPUT
0
~:
IN - ·A -f~ Y
.
ALL INPUTS ARE PROTECTED 8Y
At distance 1/16 ±1I32 inch 11.59 ±0.79 mm) from case for 10 sma •.••.••.••.•.•. +2650C COS/MaS PROTECTION NETWORK.
RECOMMENDED OPERATING CONDITIONS at TA 25°C, Except as Noted. = CD4044A-NAND
For maximum reliability, nominal operating conditions should ba selected so that I IiNEo'FOU.LAitH~l
operation is always within the following ranges: I E I
LIMITS
YDD D.F,K.H E
!VI Packages Package
Min. Max. Min. Max.
•
Supply·Voltage Range E~~
(For T A = Full Package - 3 12 3 12 Y S REO
Temperature Range X X DC·
I I NC+
Set or Reset Pulse 5 200 -

-
225 -- ns
o
I
o
I
0 0
I
Width, tw 10 100 110 ·OPEN CIRCUIT

0 ft.!!.
+ NO CHANGE
t:..11 DOMINATED BY RaO INPUT
92CS-20212
Fig. , - Logic diagram. end truth ttlble..
568
Conditions
D, F, K, H Packages E Package «
Characteristic Units i 2!r1
Vo VIN VDD +25 +25
(V) (V) IV) -55 Typ. Limit +125 -40 Typ. Limit +85 P 20
- -5 1 0.005 1 60 10 0.01 10 140 ~

Quiescent Device
- -
10 2 0.005 2 120 20 0.02 20 280 pA
"
Current, I L Max. '0
- -
15 25 0.25 25 1000 250 2.5 250 2500
Output Voltage: - 0,5 5 o Typ.; Q.05 Max. ,<
Low-Level, '0 ,
VOL - 0,10 10 o Typ.; 0.05 Max. V
ORAI"-TO-SOURCE VOLTAGE 1"'051-V
High Level, - 0,5 5 4.95 Min.; 5 Typ.

Fig.2 _ Typical output n-channel drain
VOH - 0,10 10 9.95 Min.; 10 Typ. characteristics.
Noise Immunity:
Inputs Low,
4.2 -
5 1.5 Min.; 2.25 Typ.
DRAIH-TO-SOURCE VOLTAGE 1V051-V
VNL 9 -
10 3 Min.; 4.5 Typ. -15 -10
o.
-5
Inputs High,
VNH
0.8 -
1
5
-
10
1.5 Min.; 2.25 Typ.;
3 Min.; 4.5 Typ.
V
..
Inputs Low, ."
VNML 9 -
10 1 Min.
V
- .,<,.< tt -20
Inputs High, 0.5 5 1 Min. :;--4
VNMH 1 -
10 1 Min. ...
Output Drive
,mrr.
AMBIENT TEMPERATURE (TAl· 25'C
Current: FOR Io,-D.' '"4,"e
n-Channel 0.5 - 5 0.25 0.5 0.2 0.19 0.12 0.5 0.1 0.09
(Sink),
IDNMin. Fig. 3 - Typica' output p-channe/ drain
0.5 - 10 0.61 1 0.5 Cl.35 0.3 1 0.25 0.22
mA
characteristics.
p-Channel
(Source),
4.5 - 5 -0.22 -0.5 -0.175 -0.12 0.11 -0.5 0.09 -0.08
IDPMin. 9.5 - 10 -0.5 -1 -0.4 -0.28 0.24 -1 ·0.2 -0.18
I nput Leakage
Any 15 ±10-5 Typ.; ±1 Max. pA
Current,
Input
IIL,IIH
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C; Input t r , tt = 20 ns, CL -15 pF,

RL=200kO
LIMITS
VDD D,F,K,H E
IYl Package
Typ. Max. Typ. Max. 92CS'ZOZI7
Fig. 4 _ Minimum n-.channel drain characteristics.
Propagation Delay
5 175 350 175 400
Time: tPHL, tpLH ns
10 75 175 75 200
SET or RESET to Q
3-State Propagation Delay
Time: ENABLE to Q 5 100 200 1.00 200 ns
10 50 100 50 100
tpHZ,tPZH
5 80 160 80 160 ns
tpLZ, tpZL 10 40 80 40 80
Transition Time: 5 100 200 100 250 ns
tTHL' tpLH 10 50 100 50 125
Minimum SET or RESET 5 80 200 80 225 ns
Pulse Width, tw 10 40 100 40 110
Average Input Capacitance, CI
(Any Input) - 5 - 5 - pF Fig. 5 - Minimum p-channel drain charllCtrlri,tIc..
569
3~O AMBtE~T TEMPERATURE (1A)-25·C • AMBIENT tEMPERATURE (TA"2S"C
f 300 FOR Io' 03"4 ,"e

TYPICAL TEMPERATURE COEFFICIENT TYPICAL TEMPERATURE COEFFICIENT
FOR 10" 0.3 "4/"C
-:.
•
;
~
2~O
·•
;: 200
~ 150 = 150
~ ~ LOAD CAPACITANC
i§ 100
CL"IS pF
CL·~pF
~
! '0
~
10' 10' 10'
10 W ~ ~ 50 ~ ro ~ 00 10 20 40 50 60 70 INPUT FREQUENCY-Hr
LOAD CAPACITANCE leL.l-pF
LOAD CAPACITANCE (CL.I-pF 92CS-20219
92GS-20220
Fig. 6 - Typical propagation delay time vs. CL . Fig. 7 - Typical transition time vs. CL • Fig. 8 - Typical dissipation characteristics.
INPUTS
o
Vss
VDO-VNH
'--
INPIITOVDO
OUTPUTS
~
V~NPU(J' ::~ ~
o ~
'. ••
SEQUENTIALLY,
V:L 1 Vss TO BOTH YOO AND VSS'
CONNECT ALL UNUSED
INPUTS 10 EITHER
NOTE:
Vss TEST ANY ONE: INPUT, Yoo OR YSS '
Vss WITH OTHER INPUTS AT Vss
92C5-27400 Voo DRYsS'
'J2CS-27402
Fig. 9 - Quiescent device current test circuit. Fig. 10 - Noise immunity test circuit. Fig. 11 - Input leakage current test circuit.
Voo
I.
EST IN
IpHZ VOD Vss VSS
IN
• 3 04043 10
IS 1
I. ~PLZ Vss VDO v DO
13 tpZH VOD Vss Vss
"
ENABLE 12 IN LOi"i)"A
II iN IKn 'PlL Vss VOO VOO
10t--t-<o-'IN\~
Z· HIGH IMPEDANCE
ENABLE A 0---------1-1---'
VSS
BUsJ[1-~--~\ 12
"
3 CD4043
ENABLE 12 I
Vss
"
LOAiiB'
" L _ _ _ _ _ JI
"
IIN~;:'*.VSS) ENABLE 8 0 - - - - - - - - - - 1 - - - - '
POINT A--;-,-"I.- .213 Yeo

IIN-Vss,m.voo'
tpZL ......
2/3 C04009
Fig. 12 - ENABLE propagation delay time test circuit and waveforms.
""
APPLICATIONS 3 C04043 10
V DO "
1/4 CD4043
COAOC
"
ENABLE C 0----------1--
12
14
3 C04043 10
IMQ IMQ I
L"OA01i
"
VOO ENABLE Do-----------1-~
RESET
Fig. 13 - Switch bounce eliminator. Fig. 14 - Multiple bus storage.
570
CD4045A Types
CMOS 21-Stage Counter

These types are supplied in l6-lead hermetic Sp
The RCA-C04045A is a timing circuit con-
sisting of 21 counter stages, two output-
shaping fl ip-flops, two inverter output
suffixes), l6-lead dual-in-line plastic pack- I~~---,:" '--"-
drivers, three 5_5-V zener diodes (providing age (E suffix), l6-lead ceramic flat packages
(K suffix), and in chip form (H suffix)_
,~ SN 1!5
transient protection at 16_5 V), and input
inverters for use in a crystal oscillator_The
C04045A configuration provides 21 flip-
flop counting stages, and two flip-flops for Applications:
shaping the output waveform for a 3_ 125%
duty cycle_ Push-pull operation is provided • Digital equipment in which ultra-low
dissipation andlor operation using a
by the inverter output drivers_
The first inverter is intended for use as a
crystal oscillator/amplifier_ However, it may
battery source are primary design
requirements.
VDDJ 4,5,6,9,10,11,12,13·
NO CONNECTION
92CS-l0943
be used as a normal logic inverter if desired_ • Accurate timing from 8 crystal

A crystal oscillator circuit can be made less oscillator for timing applications Vss " CD4045A
sensitive to voltage-supply variations by the such as wall clocks, table clocks, FUNCTIONAL DIAGRAM
use of source resistors_ In this device, the automobile clocks, and digital
sources of the p and n transistors have been timing references in any circuit
brought out to package terminals_ If external requiring accurately timed outputs
resistors are not required, the sources must at various intervals in the counting
•
be shorted to their respective substrates (Sp sequence_
to VOO' Sn to VSS)- See Fig_ 3_ • Driving miniature synchronous motors, Features:
stepping motors, or external bipolar • Microwatt quiescent dissipation ..... .
transiston in push-pull fashion_ 2.5 j.l.W (typ_) @ VDD = 5 V;
10 IN'I (typ.) @ VDD = 10 V
• Very low operating dissipation .....•
MAXIMUM RATINGS, Absolute-Maximum Values: 1 mW (typ.);@ VDD = 5 V, ft/! = 1 MHz
STORAGE-TEMPERATURE RANGE (Tstg ) __________ . _ • • . • • • . . . • . . . . • . • -6510 +150 oC • Output driven with sink or source
OPERATING-TEMPERATURE RANGE (TA): ° capability •. _...
PACKAGE TYPES D, F, K, H _ •..••••. _ •••• _ . . . • • • . • _ .••••••••.•-55 to +125 C 7 mA !typ.) @VO=0.5 V,
PACKAGE TYPE E ..•. '•.•.• "• • • • . . . • • • • . . • • • • • . . • . • • • • • . . • -40 to +8SoC
VDO = 5 V (sinkl
(Voltages referenced to Vss Terminal): ..•.••• _ ••.• _ ••••• _ • _ .••..•.•• -0.5 to +15 V
5 mA !tYP_)@VO=4.5V,
POWER DISSIPATION PER PACKAGE (PDI:
VDD = 5 V (source)
FOR TA= -40 to +60 oC (PACKAGE TYPE E) . • . . . • _ ••••• _ . . . . . . . . . . . . . . . . 500 mW • Medium speed (typ.) ... _.
FOR TA= +60 to +850 C (PACKAGE TYPE E) ••. _ ••.•• Derate Linearly at 12 mW/oC to 200 mW ft/!= 5 MHz@VDD=5V
FOR T A = -55 to +100·C (PACKAGE TYPES D, F, K) • • . . . . . . _ •••. - .•••.. " •. 500 mW ft/!= 10 MHz@VDO= 10 V
FOR T A = +100 to +125·C (PACKAGE TYPES D, F, K) . . . . . Derate Linearly at 12 mWI C to 200 mW
• 16.5 V zener diode transient protectior.
FOR TA= FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) • _ . . . • • . . 100 mW
on chip for automotive use
INPUT VOLTAGE RANGE, ALL INPUTS .•.••.••.•••••• -• . . • . • . • . . . -0.5 to VDD+0.5 V
• Maximum input leakage current of 1 pA
At dislance 1/16 ± 1/32 inch 11.59 ±0.79 mm)from ca.e for 10 s max • . . . . . . . • . • . . . . • +26SoC
• 1-V noise margin (full package-temper-
ature range)
LIMITS
D, F. K, H E NOTE 1: To minimize power diSSipation in the
Packages Package zener diodes, and to ensure device
IV)
Min. Max. Min. Max. dissipation less than 200 mW, a ISO on
current·llmiting resistor must be placed
Supply-Voltage Range (For T A=Full in series with the power supply for
3 12 3 12 V VOD>13V.
Input-Pulse Width, tw 5 115 - 140 - ns
10 60 - 75 - NOTE 2: Observe power-supply terminal connec-
5 dc 4_4 dc 3.5 tion., VDD is terminal No.3 and Vss I.
Input-Pulse Frequency, ft/! MHz terminal No. 14 (not 16 and 8 respec-
10 dc 8.5 dc 6.5 tively, as in all other CD4000A Sarie.
Input-Pulse Rise or Fall Time, trt/!, ttt/! 5
10
-
-
15
10
-
-
15
10
/IS 16-lead devleas).
571
CD4045A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input tr ,tt = 20 n~,
CL = 15pF, RL = 200 k!2
LIMITS
TEST
D,F,K,H E
CONDITIONS UNITS
CHARACTERISTIC Packages Package
VDD
Min. Typ. Max. Min. Typ. Max.
(V)
q, to y or y+d out
5 - 2.2 4.4 - 2.2 5.5
IJ$
tpLH ,tPHL 10 - 1.2 2.4 - 1.2 3.3
Transition Time:
5 - 450 800 - 450 900
ns DRAIN-TO-50URCE VOL.TAGE Ivcs\-V
92CS·20B96RI
tTHL ,tTLH 10 - 375 650 - 375 750 Fig. I - Typical output n-channel drain
characteristics.
Maximum Input·Pulse 5 4.4 5 - 3.5 5 - MHz
Frequency, fmq,
10 8.5 10 - 6.5 10 -
Minimum Input-Pulse
Width,tW
5 - 100 115 - 100 140
ns
10 - 50 60 - 50 75
Input-P\llse Rile & Fall 5 - - 15 - - 15
IJ$
Time; titfl, tf'/J 10 - - 10 - - 10
Average Input
Capacitance, CI Any Input - 5 - - 5 - pF
REFER TO APPLICATlON r
NOTES ICAN 60B6 I OR
T~~ C~~I~E6~F9 FOR I DRAIN TO SOURCE VOLTAGE IV05I-V
gg~~oLN~1°: VALUES L
92CS-20B97AI
AND T'I'PICAL OSCILLATOR

CURRENTS
characteristcs.
DRAIN TO SOURCE VOLTAGE IVosI-v

2.097152 I
MH,
-,0
L COMPONENTS---.J
EXTERNAL
92CM'208'J~
Fig. 3 - CD4045A and outboard components in a typical 21-,tage counter application_ Fig. 4 - Typical output p-channei drain "'"
characteristics.
DRAIN TO SOURCE VOLTAGE IVDSI-v
AM81ENT TEMPERATURE ITAJ·25·(:
10 4 10 5 10·
INPUT FflEQUENCY U+I-HI
92I;S-201ISII
Fig. 5 - Minimum output p-channel drain Fig. 6 - Typical dissipation VI input frequency Fig. 7 - Typical zener diode characteristics.
characteristics. (21 counting ,tages).
572
CD4045A Types

Conditions
Vo VIN VOO -55 +25 +25
+125 -40 +85
Quiescent Oevice - - 5 15 0.5 15 900 50 1 50 700
Current I L Max. - - 10 25 1 25 1500 100 2 100 1400 pA
- - 15 50 1 50 2000 500 5 500 5000
Low· Level, SUPPL.Y VOLTAGE IV oo l-\1
VOL - 10 10 o Typ.; 0.05 Max. V Fig. 8 - Typical propagation delay

92CS'209~5
(CPt to
High Level - 0 5 4.95 Min.; 5 Typ. y or y+d out) vs V DD •
VOH - 0 10 9.95 Min.; 10 Typ.
Inputs Low,
VNL 9 - 10 3 Min.; 4.5 Typ.
V
VNH 1 - 10 3 Min.; 4.5 Typ.
Inputs Low,
VNML 9 - 10 1 Min.
V
VNMH 1 - 10 1 Min.
Output Orive '0

Current: LOAD CAPACITANCE ICLI-pF
n·Channel Fig. 9 - Typical transition time vs CL-

(Sink) 0.5 - 5 4.4 7 3.5 2.5 2.2 7 1.8 1.3
ION Min.
0.5 - 10 6.9 11 5.5 3.9 3.5 11 2.8 2
mA
p-Channel
(Source):
4.5 - 5 -3.1 -5 -2.5 -1.8 -1.6 -5 -1.3 -0.9
lOP Min. 9.5 -10 -5.6 -9 -4.5 -3.2 -2.8 -9 -2.3 -1.6
I nput Leakage Any Input
Current,
IlL ,IIH
- 1- 15
±10-5 Typ., ±1 Max. pA
Zener Breakdown Min. 13.3 - 13.5 13.7 13.3 - 13.5 13.6

Voltage, V(BR)Z 1-100pA Typ. 16.5 - - - - 16.5 - - V
Max. 17.8 - 18 18.2 17.8 - 18 18.1
I
SUPPL.Y VOLTAGE [Voo J-\1
Fig. 10 - Typical maximum input-pulse

frequency.
INPUTS
o
Vss
Veo INP(JUS
Voo NOTE'
~ ~::~~:;I~~~~
Vss TO BOTH Voo AND Vss'
CONNECT AL.L UNUSED
INPUTS TO EITHER
Voo ORVSS'
VSS
Fig. 11 - Ouiescent-device-current Fig. 12 - Noise-immunity testc;rcuit. Fig. 13 - Input-Ieakage-current test circuit.
test circuit.
573
CD4046A Types
CMOS Micropower Phase-Locked Loop • Choice of two phase comparators:
1. Exclusive-OR network
The RCA-CD4046A CMOS Micropower 2_ Edge-controlled memory network with
Phase-Locked Loop (PLL) consists of a low-
Features:
phase-pulse output for lock indication
power, linear voltage-controlled oscillator • Very low power consumption: • High veo linearity: 1% (typ_)
(VCO) and two different phase comparators 70 JJW (typ.) at veo fa = 10 kHz, VDD = 5 V
having a common signal-input amplifier and • Operating frequency range up to 1_2 MHz (typ.) • veo inhibit control for ON-OFF Ieeying
a common comparator input. A 5.2-V zener and ultra-low standby power consumption
atVDD=10V • Source-follower output of veo control input
diode is provided for supply regulation if
necessary. • Wide supply-voltage range: VDD - VSS = 5 (Demod_ output)
These types are supplied in 16-lead hermetic to 15 V
• Zener diode to assist supply regulation
dual-in-line ceramic packages (D and F • Low frequency drift: 0.06%/O e (typ_) • Quiescent current specified to 15 V
suffixes). 16-lead dual-in-line plastic pack- at VDD = 10V
age (E suffix). 16-lead ceramic flat packages • Maximum input leakage current of 1 JJA
(K suffix), and in chip form (H suffix). at 15 V (full package-temperature range)
veo Section Applications:
The VCO requires one external capacitor Cl • FM demodulator and modulator
and one or two external resistors (R 1 or R 1
and R2). Resistor R 1 and capacitor Cl • Frequency synthesis and multiplication
determine the frequency range of the VCO • Frequency discriminator
and resistor R2 enables the VCO to have a • Data synchronization
frequency offset if required. The high input • Voltage-to-frequency conversion
impedance (1012Q) of the VCO simplifies • Tone decoding
the design of low-pass filters by permitting co
the designer a wide choice of resistor-to- • FSK - Modems
capacitor ratios. In order not to load the • Signal conditioning
low-pass filter, a source-follower output of • (See ICAN-610t) "RCA CMOS
the veo input voltage is provided at terminal Phase-Locked Loop - A Versatile
10 (DEMODULATED OUTPUT). If this Building Block for Micropower
terminal is used, a load resistor (RS) of 10 92CS-2000iRI Digital and Analog Applications"
kQ or more should be connected from this
terminal to VSS. If unused this terminal
should be left open. The VCO can be con- ,-----,-+Voo
nected either directly or through frequency U-+-VY'v-<'":!:_GATES
dividers to the comparator input of the IN 01
phase comparators. A full CMOS logic
swing is available at the output of the VCO ALL INPUTS ARE PROTECTED BY
COS/MOS PROTECTION NETWORK.
and allows direct coupling to CMOS
frequency dividers such as the RCA-CD4024,
CD4018, CD4020, CD4022, CD4029, and Fig_t - COS/MaS phase-locked loop block diagram.
CD4059. One or more CD4018 (Preset-
table Divide:by:N Counter) or CD4029 (Pre- MAXIMUM RATINGS, Absolute-Maximum Values:
settable Up/Down Counter), or CD4059A STORAGE-TEMPERATURE RANGE (Tstgl
(Programmable Divide-by-"N" Counter), to- OPERATING-TEMPERATURE RANGE (T A ):
gether with the CD4046A (Phase-Locked
PACKAGE TYPES D, F. K, H __ -55 to +125°C
Loop) can be used to build a micropower PACKAGE TYPE E -
low-frequency synthesizer_ A logic 0 on the -40 to +850 C
DC SUPPLY-VOLTAGE RANGE. (V OD '
INHIBIT input "enables"the VCO and the
(Voltages referenced to V 55 Termmal) ................. , .......... " ........ . -0.5 to +15 V
source follower, while a logic 1 "turns off"
both to minimize stand-by power consump- POWER DISSIPATION PER PACKAGE (PO':
tion. FOR T A " -40 to +600 C (PACKAGE TYPE El 500mW
Phase Comparators FOR T A" +60 to +85 0 C (PACKAGE TYPE E"I Derate Linearly at 12 mW/oC to 200 mW
The phase-comparator signal input (terminal FOR TA = -55 to +100'C (PACKAGE TYPES D, F, K) 500mW
14) can be direct-coupled provided the signal FOR T A = +100 to +125'C (PACKAGE TYPES D, F, K) '. Derate Linearly at 12 mW/oC to 200 mW
swing is within CMOS "logic levels [logic DEVICE DISSIPATION PER OUTPUT TRANSISTOR
"0" ';;;30% (VDD-VSS), logic "1" ;;;, 70% FOR TA = FUll PACKAGE-TEMPERATURE RANGE (All PACKAGE TYPES)_ l00mW
(VDD-VSS) J. For smaller swings the signal
INPUT VOL TAGE RANGE. All INPUTS -0.5 to V DD +0.5 V
must be capacitively coupled to the self-
lEAD TEMPERATURE lOURING SOLDERING):
biasing amplifier at the signal input. At distance 1116 ± 1/32 Inch 0.59 ± 0.79 mm) from case for 10 s max.
Phase comparator I is an exclusive-OR net-
work; it operates analagously to an over-
driven balanced mixer. To maximize the lock out of lock is defined as the frequency cap- parator I enables a PLL system to remain
range, the signal- and comparator-input fre- ture range (2fd. in lock in spite of high amounts of noise
quencies must have a 50% duty cycle. With The frequency range of input signals on in the input signal.
no signal or noise on the signal input, this which the loop will stay locked if it was One characteristic of this type of phase com-
phase comparator has an average output initially in- lock is defined as the frequency parator is that it may lock onto input fre-
voltage equal to VDD12. The low-pass filter lock range (2fU. The capture range is';;; the quencies that are close to harmonics of the
connected to the output of phase comparator lock range. VCO center-frequency. A second charac-
I supplies the averaged voltage to the VCO With phase comparator I the range of fre- teristic is that the phase angle between the
input. and causes the VCO to oscillate at the quencies over which the PLL can acquire signal and the comparator input varies be-
center frequency (f o )' lock (capture range) is dependent on the tween 0 0 and 1800 , and is 900 at the center
The frequency range of input signals on low-pass-filter characteristics, and can be frequency. Fig_ 2 shows the typical, trian-
which the PLL will lock if it was initially made as large as the lock range_ Phase-com- gular, phase-to-output response characteristic
574
CD4046A Types
LZ
VDD operation is always within the following range:
O~
"'" VOD/Z CHARACTERISTIC
LIMITS
Min. Max.
UNITS
o 90- 80-
Supply Voltage Range (For T A = Full Package
Temperature Range 3 12 V
SIGNAL-TO- COMPARATOR
INPUTS PHASE DFFERENCE
92CS-20009
Fig.2 - Phase-comparator I characteristics ELECTRICAL CHARACTERISTICS at TA = 250 C

at low-pass filter output.
Limits
of phase-comparator I. Typical waveforms
Test Conditions
for a CMOS phase-locked-loop employing Characteristic All Package Types Units
Vo VOO
phase comparator I in locked condition of fo
is shown in Fig. 3. Volts Vails Min. I Typ. I Max.
Phase Comparator Section
SIGNAL INPUT CTERM. 14) IL-rL Operating Supply Voltage. VOO-VSS
VCO Operation - 5 - 15
V
veo OUTPUT ITERM 41.
COMPARATOR INPUT ~
Comoarators on Iv - 3 - 16
(TERM 31 Total Quiescent Device Current, IL: 5 - 25 ~
PHASE COMPARATOR I
OUTPUT ITER". 2)
...............
J'lJL..f1..r-Veo Term. 14 Open Term. 15 open 10 - 200 - JJA
•
veo JNPUT (TERM. 91- Term. 5 at VOO 5 - 5 15
-LOW-PASS FILTER Term. 14 at VSS or VOO
OUTPUT -vss Terms. 3 & 9 at VSS 10 - 25 60
92CS-20010RI
15 - 50 500
Fig. 3 - Typical waveforms for COS/MaS phase·
locked loop employing phase comparator 5 1 2 -
Term. 14 (SIGNAL IN)
I in locked condition of f o'
Input Impedance, Z14
10 0.2 0.4 - Mn
15 - 0.2 -
Phase-comparator II 'is an edge-controlled AC·Coupled Signal Input 5 - 200 400
digital memory network. It consists of four Voltage Sensitivity* See Fig.7 10 - 400 800 mV
flip-flop stages. control gating. and a three- (peak-to·peak) 15 - 700 -
state output circuit comprising p- and n-type
DC·Coupled Signal Input
drivers having a common output node. When
the p-MOS or noMOS drivers are ON they and Comparator Input
5 1.5 2.25 -
pull the output up to VDD or down to Voltage Sensitivity 10 3 4.5 -
VSS. respectively. This type of phase com- Low Level 15 4.5 6.75 - V
parator acts only on the positive edges of
the signal and comparator inputs. The duty High Level
-
Vo
5
10
-
-
2.75
5.5
3.5
7
cycles of the signal and comparator inputs Volts 15 - 8.25 -
are not important since positive transitions
control the PLL system utilizing this type Output Drive Current: Phase Comparator 0.5 5 0.43 0.86 -
of comparator. If the signal-input fre- I & II Term. 2 & 13 0.5 10 1.3 2.5 -
n·Channel (Sink). ION
quency is higher than the comparator-input 0.5 5 0.23 0.47 -
frequency. the p-type output driver 'is maIn- Phase Pulses
0.5 10 0.7 1.4 -
tained ON most of the time. and both the mA
nand p drivers OFF (3 state) the remainder Phase Comparator 4.5 5 -0.3 -0.6 -
of the time. If the signal-input frequency I & II Term. 2 & 13 9.5 10 -0.9 -1.8 -
p·Channel (Source!. lOP
is lower than the comparator-input frequen- 4.5 5 -0.08 -0.16 -
cy. the n-type output driver is maintained Phase Pulses
9.5 10 0.25 0.5
ON most of the time, and both the nand ±10- 5
p drivers OFF (3 state) the remainder of
Input Leakage Current. IIL,IIH Max. Any Input 15 - ±1 IJA
the time. If the signal- and comparator- • For sine wave, the frequency must be greater than 1 kHz for Phase Comparator II.
input frequencies are the same. but the
signal input lags the comparator input in
phase. the n-type output driver is main-
tained ON for a time corresponding to the
SIGNAL INPUT CTERM. 141
phase difference. If the signal- and com-
parator-input frequencies are the same. but veo OUTPUT ITERM 4'.
COMPARATOR INPUT
the comparator input lags the signal in phase. ITER" 31
PHASE COMPARATOR D
the p-type output driver is maintained ON OUTPUT ITERM.I!) •.1- - - +- - - - __ "..~~:
for a time corresponding to the phase dif- • • ..yDD
ference. Subsequently. the capacitor voltage veo INPUT (TERM. 91-
• LOW-'"Ss FILTER -VSS
of the low-pass filter connected to this phase
comparator is adjusted until the signal and
OUTPUT
PHASE PULSE ITERM. I)
11 •
comparator inputs are equal in both phase NOTE: DASHED LINE IS AN OPEN·CIRCUIT CONDITION
and frequency. At this stable point both p-
and n-type output drivers remain OFF and Fig.4 - Typical waveforms for CMOS phase-locked loop
thus the phase comparator output becomes employing phase comparator /lIn locked condition.
an open circuit and holds the voltage on the
capacitor of the low-pass filter constant.
575
CD4046A Types
ELECTRICAL CHARACTER ISTICS at T A = 25°C Moreover the signal at the "phase pu(ses"
output is a high level which can be used for
Limits indicating a locked condition. Thus, for
Test Conditions phase comparator II, no phase difference
Characteristic All Package Types Units exists between signal and comparator input
Vo VOO
Volts Volts Min. I Typ. I Max.
over the full veo frequency range. More·
over, the power dissipation due to the low·
VCO Section pass filter is reduced when this type of phase
Operating Supply Voltage As fixed oscillator only 3 - 15 comparator is used because both the p- and
V n-type output drivers are OFF for most of
VOO-VSS Phase·lock·loop operation 5 - 15
the signal input cycle. (t should be noted
fo=10kHz Rl = 1 MO 5 -[ 70 - thatthe PLL (ock range for this type of phase
Operating Power
Dissipation, Po
R2=- VOO 10 - 606 - /lW comparator is equal to the capture range,
VCOIN=-2- independent of the (ow-pass filter. With no
15 - 2400 -
Rl = 10kO Cl = 100pF 5 0.25 0.5 - signal present at the signal input, the veo
Maximum Operating is adj usted to its lowest frequency for phase
R2=- 10 0.6 1.2 - MHz comparator II. Fig. 4 shows typical wave-
Frequency, f max Cl = 50 pF
VeOIN = VOO 15 - 1.5 - forms for a CMOS PLL employing phase
Center Frequency (f 0) and comparator II in a locked condition.
Frequency Range, Programmable with external components R 1. R2, and Cl
fmax-fmin See Design Information
VCOIN = 2.5 V ± 0.3 V. Rl > 10 kO 5 - 1 -
Linearity = 5 V ± 2.5 V, Rl > 400 kO 10 - 1 - %
=7.5V±5V,Rl =1 MO 15 - 1 -
T emperature-F requency
%/oC<x __ 1_
5 - 0.12-0.24 -
Stability-: f·VOO 10 - 0.04-0.08 -
No Frequency Offset 15 - 0.015-0.0 -
fMIN =0 R2=-
%/oC
Frequency Offset
5 - 0.06-0.12 -
%/oC<x_l_
f.VOO 10 - 0.05-0.1 -
fMIN*O
15 - 0.03-0.06 -
Input Resistance of
5,10,15 - 10 12 - 0
VCOIN (Term g), RI
VCO Output Voltage
(Term 4) 5,10,15 - - 0.01
Low Level, VOL
Oriving CMOS-Type 5 4.99 - - V
High .Level, VOH Load (e.g. Term 3 10 9.99 - -
Phase Comparator Input) 15 14.99 - -
veo Output Outy Cycle 5,10,15 - 50 - %
VCO Output Transition

- Va 5 - 75 150
Times, tTHL,lTLH Volts

10 - 50 100 n,
15 - 40 -
veo Output Drive
Current: 0.5 5 0.43 0.86 -
n·Channel (Sink), ION 0.5 10 1.3 2.6 -
rnA
4.5 5 -0.3 -0.6 -
p·Channel (Source), lOP
9.5 10 -0.9 -1.8 -
Source-Follower Output
(Demodulated Output): 5,10 - 1.5 2.2
RS> 10kO V
Offset Voltage 15 - 1.5 -
(VeOIN-VDEM)
VeOIN = 2.5!0.3 V 5 - 0.1 -
Linearity RS>50kO = 5±2.5 V 10 - 0.6 - %
= 7.5±5 V 15 - 0.8 -
Zener Diode Voltage (V z) IZ = 5O/lA 4.5 5.2 6.1 V
Zener Dynamic
Resistance, RZ
IZ= 1 rnA - 100 - 0
•
.. ..
Positive coeffiCient .
576
CD4046A Types
DESIGN INFORMATION 10 kn ",Rl, R2, RS '" 1 Mn AMalu,T TEMPERATURE (TA j·25·C
• '101"11' WHEN VCOIN"VOD,INHIBITo..,SS
This information is a guide for approximating Cl ",100 pF at VDD '" 5 V; 'IoI'N '!VHEN veolNo..,SS
the values of external components for the Cl",50pFatVDD'" 10V

I
··
TYPICAL
CD4046A in a Phase·Locked·Loop system. In addition to the given design information '00 ' ...... " .. IN
UNIT-TO-UNIT VARIATION
z
The selected external components must be refer to Fig.5for Rl, R2, and Cl component _i
"'00 DyE :K~;S
within the following ranges: selections.
j "
!so.,.
·
lOY :!:I,.,.
'0
Phase 13Y t 10 ..
Characteristics Comparator Design Information

Used
VCO WITHOUT OFFSET VCO WITH OFFSET
R2=oo
·_tzr t:L
Fig.5(c) - Typical 'max/fmin vs R2/RI.
- _ 21L
fO --
VCO Frequency I 12tL I
--
I I
'MIN
"uolZ VOl) oo
V
yeo INPUT VOLTAGE yeo INPUT VOI.TAGE
92eS-ZOOll'"
2 Same as for No.1
•
For No Signal Input 1 VCO will adjust to center frequency, fo
2 VCO will adjust to lowest operating frequency, fmin
2 fL = full VCO frequency range
Frequency Lock 1
2 fL = fmax-fmin AI-KO
Range, 2 fL
2 Same as for No.1 Fig.6(a) - Typical VCO power dissipation at center
frequency vs R 1.
IN
•• OUT
(1), (2)
~
Frequency Capture
Range,2 fC
2 f C "'";
l~L
-;:J
"M8IENT TEMPERATURE (T,,1_2'-C
veO'N""SS
1
IN
•• OUT
Loop Filter
Component
Selection
t *C_
92tS-21901
For 2 fC, see Ref. (2)
\ ,
\
2 fC = fL
Phase Angle Between 900 at center frequency (fo) approximating 00

1
Signal and Comparator and 1800 at ends of lock range (2 fL) 6 'IO Z 2 4 6 'IOl
2 Always 00 in lock R2-KO
TYPICAL CENTER FREOUENC., Fig.6(b) - Typical VCO power dissipation at

UNIT-tO-UNIT VARIATION
061110-"4
'min vsR2.
(61111-%
AMBIENT TEMPERATURE IT"I-25-C

VCOIN -""00/2, RI_R2·CD
'v
VCO TIMING CAPACITOR \CI}-,.F
92CS-218B.!RI
Fig.5(a) - Typical center frequency vs CI for

Fig.5(b) - Typical frequency offset vs CI for .. 6 "0 2 2 .. 6 '103
RI = 10 kr!, and 1 Mr! and fo "'1/RI CI. R2= 10kr!, l00kr!,and 1 Mr!. ',,-KO
NOTE: Lower frequency values are obtainable if larger values of C1 Fig.6(c) - Typical source follower power dissipation
than shown in Figs. 5(a) and 5(b) are used. vsRS·
NOTE: To obtain approximate total power dissipation of PLL system for no-signal input
Po (Totali = Po (fo) + Po (fMIN) + Po (RSl - Phase Comparator I
Po (Totali = Po (fMIN) - Phase Comparator II
577
CD4046A Types
DESIGN INFORMATION (Cont'dl:
Pha..
CharacteristicsComparator Oeiign Information
U..d
Locks On Harmonic 01 I-_....;.I_ _f-_ _ _ _ _ _ _ _ _-'Y..:e.:.s_ _ _ _ _ _ _ _ _ _.,
Center Frequency 2 No
Signal Input I High
Noise Rejection 1---:2--f----------.,-L""0"'w"'----------;
veo WITHOUT OFFSET veo WITH OFFSET
R2=oo
- Given: 10 - Given: 10 and IL
- Use 10 with Fig.5a to - Calculate Imin lrom
determine R I and CI the equation
Imin = fo-IL
- Use Imin with Fig.5b
to determine R2 and CI
Imax
- Calculate Imin
Irom the equation
Imax = 10+IL
Imin 10 - IL
Imax
VCO - Use Imin with
Component Fig.5c to determine
Selection ratio R2/R I to obtain
RI
- Given: Imax - Given: Imin & f max
- Calculate 10 Irom - Use Imin with Fig.5b
the equation to determine R2 and CI
Imax _ Calculate I max
10 =-2-
2 Imin
-Use 10 with Fig.5a to Imax. .
determine R I and C I - Use Imin With Flg.5c
to determine
ratio R 2/R 1 to
obtain Rl
For further information, see
(11 F. Gardner, "Phase-Lock Techniques" John Wiley and Sons, New York, 1966
(21 G. S. Moschytz, "Miniaturized RC Filters Using Phase-Locked Loop", BSTJ, May, 1965.
1. . J.
10: AMe'ENT TEMPERATURE IT,,'025.C
AMaiENT TEMPERATUR~ IT~I.,25·C _.1 oil VDD.,5\1.vIOIN.7.~V!5\1.R2.CD
AMBIENT TEMPERATURE lTA1'25~C
"DO'IOV,VCO'N'!!V:!:2.!!V • R2.a)
SUPPLY VQt.TAGE "00"5\1,'0-250 KHI
~ 2 .,..- CI-SOpF
/ I 10.t:----+---""'~c--+------1
I
g
I.•
I.'
I I'O~.'O·"J
~
~
KH.
.! .1. ·
I
/ 15V,fO"950KHI
I
0
~ 14
~ I..
I
I
I
· I~
.
.=-=,;;-,,=-'-
,O-tl7.5Vl
~ 1.2r---
. I
"'-LINEARITY' - - . - -
'0
I
100 6 8'000
, . ..
P[AK ·TO·,£"I( SIGNAL INPUT VOLTAGE IVI I-IIIV
1
Fig.7 - TVPicallock range vs signal input amplitude. Fig.8Ia) and Ib) - Typical VCO linearity vs R 1 and CT.
578
CD404 7 A Types
CMOS Low-Power These types are supplied in 14-lead hermetic

Monostablel Astable suffixes). 14-lead dual-in-line plastic pack-
ages (E suffix). 14-lead ceramic flat pack- R I
Multivibrator ages (K suffix). and in chip form (H suffix). ....c COMUON ~
The RCA·C04047 A consists of a gatable Features: -TRIGGER

Vss
astable multivibrator with logic techniques
incorporated to perm it positive or negative • Low power consumption: special 9ZCS-ZI"l3IRI
COS/MOS oscillator configuration
edge·triggered monostable multivibrator
action with retriggering and external count· • Monostable (one·shot) or astable
(free·running) operation
ing options.
• True and complemented buffered
Inputs include +TRIGGER, -TRIGGER,
outputs
ASTABLE, ASTABLE, RETRIGGER, and
• Only one external Rand C required CD4047A
EXTERNAL RESET. Buffered outputs are Terminal Diagram
a, a, and OSCILLATOR. In all modes of • Ouiescent current specified to 15 V
• Maximum input leakage current of
operation an external capacitor must be can·
1 !lA at 15 V (full package·temperature
nected between C·Timing and RC·Common Astable Multivibrator Features:
range)
terminals, and an external resistor must be
• 1-V noise margin (full package·temper- • Free·running or gatable operating modes
connected between the R·Timing and RC-
ature range) • 50% duty cycle
Common terminals.
• Oscillator output available
Astable operation is enabled by a high level Monostable Multivibrator Features: • Good astable frequency stability:
•
on the ASTABLE input. The period of the
a
square wave at the a and Outputs in this • Positive- or negative·edge trigger
Frequency deviation:
=±2% + 0.03%loC @ 100 kHz
mode of operation is a fl,lnction of the ex· • Output pulse width independent of
ternal components employed. "True" input trigger pulse duration =±o.5% + 0.015%lo C @ 10 kHz
pulses on the ASTABLE input or "Com· • Retriggerable option for pulse width (circuits "trimmed" to frequency
plement" pulses on the ASTABLE input VDD = 10 V ± 10%)
expansion
allow the circuit to be used as a gatable • Long pulse widths possible using small Applications:
multivibrator. The OSCILLATOR output RC components by means of external Digital equipment where'low·power dissipa-
period will be half of the a terminal output counter provision tion and/or high noise immunity are primary
in the astable mode. However, a 50% duty • Fast recovery time essentially independent design requirements:
cycle is not guaranteed at this output. of pulse width • Envelope detection
• Pulse·width accuracy maintained at duty • Frequency multiplication
In the monostable mode, positive·edge cycles approaching 100% • Frequency division
triggering is accomplished by application of • Frequency discriminators
a leading·edge pulse to the +TRIGGER • Timing circuits
input and a low level to the -TRIGGER • Time-delay applications
input. For negative-edge triggering, a trailing·
edge pulse is applied to the -TRIGGER and
a high level is applied to the +TRIGGER.
Input pulses may be of any duration relative
to the output pulse. The multivibrator can
be retriggered (on the leading edge only) by
applying a common pulse to both the
RETRIGGER and +TRIGGER inputs. In
this mode the output pulse remains high as
long as the RETRIGGER input is high, with or
without transitions.
92CS-20026R2
An external countdown option can be imple· Fig. 1 - C;D4041A logiC block diagram.
mented by coupl ing "a" to an external MAXIMUM RATINGS, Absolute-Maximum Values:
"N" counter and resetting the counter with STORAGE·TEMPERATURE RANGE (Tstgl •••••••••••••••.••••••••••••• -65 to +l50 oC
the trigger pulse. The counter output pulse is OPERATlNG·TEMPERATURE RANGE (TAl:
fed back to the ASTAB LE input and has a PACKAGE TYPES D, F, K, H . • • • . • . • • • . • • . • • • • • •• .. • . • • -55 to +125·C
duration equal to N times the period of the PACKAGE TYPE E • . . • • • • • • • • • • • • . • • . . . . . • • -40 to +85·C
multivibrator. DC SUPPLY·VOLTAGE RANGE, (VDDI
A high level on the EXTERNAL RESET (Voltages referenCed to VSS Termlnail: ••••••••••••••••.•••••••..•.•. -0.5 to +15 V
input assures no output pulse. during an POWER DISSIPATION PER PACKAGE (PDI
"ON" power condition. This input can also FOR TA= -40 to +60 oC (PACKAGE TYPE E I •••••••.••••••••.•.•.••.•••• 500 mW
be activated to terminate the output pulse at FOR T A= +60 to +85 0 C (PACKAGE TYPE E I .•••••••. Derate Linearly at 12 mWloC to 200 mW
any time. In the monostable mode. a high· FOR TA = -55 to +l00·C·(PACKAGE TYPES 0, F, KI • ... • • • . • • • • • • • • • . . . • 500 mW
level or power·on reset pulse. must be FOR TA = +100 to +125·C (PACKAGE TYPES 0, F, KI • . • • . Derate Linearly at 12 mW/·C to 200 mW
applied to the EXTERNAL RESET when· DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ever VOO is applied. FOR TA= FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPESI ..••••••• 100 mW
INPUT VOLTAGE RANGE, ALL INPUTS ••••.••••••••••••.•.•.•..• -0.5 to Vee +0.5 v
At distance 1/16 ±1/32 inch (1.59 ±0.79 mml from case for 10 s max .••..••.•.•••.•• +265 0 C
579
CD404 7 A Types
RECOMMENDED OPERATING CONDITIONS at TA= 25°C, Except as Noted.
For maximum reliability; nominal operating conditions should be selected so that ~
c
8ii:ENT TEMPERATURE IT41-25-C
TYPICAL TEMPERATURE COEFFICIENT AT ALL VALUES

LIMITS
..g ~~O~FYiGls.~-~o.~,~~~,,~c~~~~~~~~~~
~i
~
GATE-fO-SOURCE VOLTAGE tVGSI-,5 v

D,F,K,H ~40
E UNITS az
CHARACTERISTIC VDD Packages Package
~50
Min. Max. Min. Max.
Supply·Voltage Range (For T A=Full
3 12 3 12 V
Package· Temperature Range)
Input Pulse Width, tW 5 1000 - 1300 - ns
(Any Input) 10 400 - 600 - DRAIN-YO-SOURCE VOLTAGE (VDSI-V
Trigger, Retrigger 5 - 15 - 15 ps
Fig. 2 - Typical output n-channel drain
a and '0buffen.
Rise or Fall Time, tr ' tf 10 - 5 - 5 characteristics for

Conditions
E
r
D, F, K, H Packages Package
Characteristics Units
Vo ViN VDD -55 +25 +25
+125 - 40 +85
'Y
- - 5 5 0.03 5 300 50 0.1 50 700 'Y
Ouiescent Oevice '0
DRAIN-fO-SOURCE VOLTAGE 1VOSI-V
Current I L Max. - - 10 10 0.05 10 600 100 0.2 100 1400 IJA
- - 15 50 1 50 2000 500 5 500 5000 Fig. 3 - Minimum output n-channel drain
characteristics for and buffers.a a
Low·Level,
VOL - 10 10 o Typ.; 0.05 Max. DRAIN-TQ-SOURCE VOLTAGE tVDsl-V
V
High Level - 0 5 4.95 Min.; 5 Typ. -15
AMBIENT TEMPERATURE ITAI.·2~-C
-10
VOH - 0 10 9.95 Min., 10 Typ.

AT ALL VALUES 01" YGS·-O.3 " - C

Inputs Low,
VNL
Inputs High 0.8
9 -
-
10
5
3 Min.; 4.5 Typ.
1.5 Min.; 2.25 Typ.
V 'OY
VNH 1 - 10 3 Min.; 4.5 Typ.
Noise Margin: 4.5 5 1 Min.
Inputs Low,
UTf-TO-SOURCE VOLTAGE IVes'> 1'5 V
VNML 9 10 1 Min.
V
Inputs High, 0.5 5 1 Min.
VNMH 1 10 1 Min. Fig. 4. - Typical output p-channel drain
Output Orive characteristics for Q and Q buffers.
Current:
(O,n Outputs) 0.5 - 5 0.5 0.8 0.4 0.28 0.34 0.8 0.28 0.23
n·channel ORAIN-TO-SOURCE VOLTAGE IYDSI-V
~15 ~IO ~5
(Sink), AMBIENT .TEMP~.!f_ATURE ITA '25'C!g 5V
ION Min. mA
-
p·Channel
0.5
4.5 -
10
5
1.25 2 1 0.7 0.85 2 0.7 0'.6
CD4047~:(.t:
.. ~
~
·0.5 ·0.8
ia
\0"
·0.4 ·0.28 ·0.34 ·0.8 -0.28 -0.23 - - - CD .. 04l1" AE
(Source):
lOP Min. 9.5 - 10 1.2E -2 -1 -0.7 -0.85 -2 -0.7 -0.6
I nput Leakage
"y -10 ~
Current,
IIL,IIH
-AT ~nr~5 ±10-5 Typ.', ±1 Max.
IJA .
z
v
-15 I
~ATE-TO-SOURCE VOLTAGE (VGSI. 15 V
Fig. 5 - Minimum output p-channel drain

characteristics for Q and Q buffeTS.
580
CD404 7 A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, Input tr ,tt = 20 ns, CL = 15 pF, AMBIENT TEMPERATURE IT,,'-25·C
TYPICAL TEMP. COEFFICIENT AT ALL VAlUES OF Voo·a.] "I./-C
RL = 200 kn
LIMITS
TEST D,F, K,H
SuPPLY VOLTAGE lVool°sV
E
CONDITIONS Packages Package
CHARACTERISTICS UNITS pc-
~".
VDD .. IOV
Min. TYP. MAX. MIN. TYP. MAX.
(Volts)
'"
tpHL' tpLH 5 - 200 400 - 200 550 20 so 40 50
LOAD CAPACITANCE ICL.J-pf
60 70 80 90
Astable, Astable
Fig. 6 - Tvpicallow-to-high level propagation
to Osc. Out 10 - 100 200 - 100 275
delay time vs load capacitance for Q
Astable, Astable
5 - 550 900 - 550 1200 and Q buffers.
toO,a 10 - 250 500 - 250 650

AMBIENT TEMPERATURE ITA}-Z5'C
TYPICAl TEMP. COEffiCIENT AT ALL VAlUES Of Voo-O,] "1./"C
5 - 700 1200 - 700 1600 :.,::ttlliJ"j' ;:;:

... C.::.. .. ..
r
+0.
+Trigger, -Trigger ns t •• - +-!- -f"~ •
toO,a 10 - 300 600 - 300 800 ~ tti: $t#~:tij:j'j +~

~200
+Trigger, Retrigger 5 - 300 600 - 300 800
!
•
150
toO,a 10 - 175 300 - 175 400
~ 100 IOV
External Reset 5 - 300 600 - 300 800

~ "V
toO,a 10 - 125 250 - 125 350
\0 W ~ ~ ~ ~ • ~ ~
Transition Time:
tTHL ,tTLH
5 - 75 125 - 75 150 LOAD CAPACITANCE ICt.I-pf
Fig. 7 - Typical transition time vs load capa-

o,a 10 - 45 75 - 45 100
ns citance for Q and a buffers.
Osc. Out
5 - 75 150 - 75 180
I. Astable Mode Design Information
10 - 45 100 - 45 130 A_ Unit-to-Unit Transfer-Voltage
Variations.
ns The following analysis presents worst-
Width (any input), tw " 10 - 200 400 - 200 600 case variations from unit to unit as a
function of transfer-voltage (VTR)
+Trigger, Retrigger 5 - - 15 - - 15
ps shift (33%-67% VDO) for free-
running (astable) operation.
Rise & Fall Time, tr , tf 10 - - 5 - - 5
Average Input Any TERMINAL.IS~

Capacitance, CI Input - - 5 - - 5 - pF
TERMINALIO~
" Input pulse widths below the minimum specified may cause malfunction of the Unit.
See Application Note ICAN· 6230
~tA---1
92CS-20027
CD4047A FUNCTIONAL TERMINAL CONNECTIONS Fig. 8 - Astable mode waveforms.

NOTE: IN ALL CASES EXTERNAL RESISTOR BETWEEN TERMINALS 2 AND 3A
EXTERNAL CAPACITOR BETWEEN TERMINALS 1 AND 3A VTR
tl = -RC In - -_ __
TERMINAL CONNECTIONS VDD+VTR

OUTPUT OUTPUT PERIOD
FUNCTION INPUT PULSE OR
TOVDD TOVSS t2 = -RC In V DO - VTR
PULSE FROM PULSE WIDTH
2VDD-VTR
TO
Astable Multivibrator:
Free Running 4,5,6,14 7,8,9,12 - 10,11,13 tA{10,ll)=4.40 RC
True Gating 4,6,14 7,8,9,12 5 10,11,13 tA(13)=2.20 RC
Complement Gating 6,14 5,7,8,9,12 4 10,11,13
Monostable Multivibrator: Typ: VTR=O.5VDO tA =4.40 RC

Positive-Edge Trigger 4,14 5,6,7,9,12 8 10,11 Min: VTR = 0.33 VDD tA = 4.62 RC
Negative-Edge Trigger 4,8,14 5,7,9,12 6 10,11 tM{10,ll)=2.48 RC
Max: VTR = 0.67 VDO tA =4.62 RC
Retriggerable 4,14 5,6,7,9 8,12 10,11
External Countdown" 14 5,6,7,8,9,12 - 10,11 thus if ItA = 4.40 Rci is u~ed,the lTIa~~mum
~ Input Pulse to Reset of External Counting Chip External Counting Chip Output To Terminal 4 ... See Text.
variation will be (+5.0%,-0.0%).
581
CD4047 A Types
ASTABLE (!,j)":.----------,
~(.4~r>-----_,
~~~J-+--~----~12
*
RETR GOER
* INPUTS
COSIMOS
PROTECTED BY SUPPLT VOLTAGE (VOOI-V
RESISTOR- DIODE NETWORK
Fig. 10 - Typical O-and-(j·period accuracy
Bf[
**
Vss
NOD,FIEO INPUT PROTECTION
CAUTION' TERMINAL 31S MORE SENSITIVE
TO STAT Ie ELECTRICAL DISCHARGE;
EXTERNAL
RESET
VB supply voltage (high frequency).
CIRCUIT TOP[RMIT LARGER EXTRA HANDLING PRECAUTIONS

INPUT-VOLTAGE SWINGS
ARE RECOMMENDED
Fig. 9- CD4047A logic diagram.
B. Variations Due to VDD and Temperature Voo and temperature. Typical variations
Changes are presented in graphical form in Figs.
In addition to variations from unit to 10 to 20 with 10 V as reference for SUPPlY II'OLTAGE Wool-V
unit, the astable period may vary as a voltage variation curves and 25°C as
function of frequency with respect to reference for temperature variation curves.
Fig. 11 - Typical O-and·(j·period accuracy
VB supply voltage (medium frequency)
,
z
AMBIENT TEMPERATURE IrA
ASTABLE MOD£
'0 25°C
,
ffi "
i ••
J I
Ig .
~ SUPPLY ~OLTAGEIIVDD I"V!IO% 7J
~
t2
I I
lovt 10% / If
10
! il
l...--" ~",l!IO'
~ r7
0
,
0
., , 10
, ,
10 10 3 104 10' 10&
SUPPLY VOLTAGE (Ygo)-V FREQUENCY ttl-HI
SUPPLY VOLTAGE IVool-V 92CS.21~45 9ZCS-l1390
Fig. 12 - Typical O-and·O-period accuracy Fig. ·13 - Typical O-and-(j. period accuracy Fig. 14 - Typical O-and a·period accuracy
VB supply voltage (low frequency). VB supply voltage (very low frequency). VI frequency for V DO variation
of ± 10% from value indicated.
~ e +4 ASTABLE MOOE
I .,
I .2
!§ .,
~
0
.,
. .,. e
., I YoO
I .. 0 ,F Kn v
A '0 100 47
50 100 47 '0
.> e
~
'0
,
100 220 5
SUPPLY VOLTAGE !Vool-V SUPPLY VOLTAGE 11100)-11 92CS-21446

r .,
-5' -35 -15 +5 +25 +45
D
E
+60
'0
, '0
+85
220
+105
10
220 5,10
+125
Fig. 15 - Typicaloscillator-output-period Fig. 16 - Typicalosclllator-output-period AMBIENT TEMPERATURE ITAI-eC
accuracy VB supply voltage (high accuracy VB supply voltage Fig- '7 - Typical 0- and O-period accu';;;;l!447
frequency). (medium freqUtlncy) • .. tempersture (medium frequency).
582
CD4047 A Types
~§
ASTABLE 1roI00E
1+15
~
§ +10
~ ~
~ ET
~ 0 \O~ B
KrZ"';F :n veo ~B , c ,
~ , , '-IHI pF Kfi
1-'
g -2
A
B
100 100
100
20 100
47
220
10
5 o -10 ~~~~ B 0.2 100
~ 20 :~~O' ~¥o :t. ~

:t -15
"65
A'-IBIENT TE'-IPERATURE (TA1-'C
+85 +105 +125 ." AMBIENT TEIroIPERATURE (TAI-'C
A'-IBIENT TE'-IPERATURE (TA1-'C
Fig. 18 - Typical Q- and a-period accuracy Fig. 19 - Typical oscillator-period accuracy Fig. 20 - Typical oscillator-period accuracy
vs temperature (high frequency). vs temperature (medium frequency). vs temperature (high frequency).
II. Monostable Mode Oesign Information

The following analysis presents worst-
case variations from unit to unit as a
function of transfer-voltage (VTR) shift
(33% - 67% V OO ) for one-shot (mono-
stable) operation.
TERM1NA1.8~ I
TERMINALI3~
TERMINAL 10 JfMLS~
I
nCS-2002B SUPPLY VOLTAGE (\1001-\1 SUPPLY \lOLTAGE NODI-II
Fig. 22 - Typical Q- and O-pulse·width Fig. 23 - Typical Q- and ii·pulse·width

Fig. 21 - Monostable waveforms. accuracy vs supply voltage accuracy vs supply voltage
(tM = 15,60, 120 /lsi. (tM = 0.5, 1, 10 ms).
~-,~,U"'~'~'N~"'~'"""~E"",m,"~,<,",,~,T.I'~2",·~c--T---
'-IONOSTABLE MODE
----
"I----t----t---+--+---t----f----i
(VTR) (VOO - VTR) "r---j----+---+--+---j----f----l
tM = -RC In
(2V OO - V TR ) (2V OO) :!:2 5 V ± 10 'fo --j----+---+---+---+---j
where tM = Monostable mode pulse width.
Values for tM are as follows: "IVt'lo
Typ: VTR = 0.5 VOO tM = 2.48 RC 10 5 10 4 10} 10 2 10 I 100 10 1
Min: VTR = 0.33 VOO tM = 2.71 RC SUPPLY VOLTAGE 1Vool-V
'.I2CS-21430
Q AND ll-PULSE WIDTH- SECONDS
92CS-2n91
Max. VTR = 0.67 VOO tM = 2.48 RC Fig. 24 - Typical Q- and o.pu/se·width Fig. 25 - Typical Q. and lJ pulse· width
accuracy vs supply voltage accuracy vs Q and ii pulse width
(tM~ lOOms).
I
Thus if ItM = 2.48 RC is used, the maximum
for a variation of ± 10% from
value indicated.
variation will be (+9.3%, -0.0%).
IroIONOSTABLE 1roI0DE
l~ iNOSTABLE ~ODE I HI-lH-i
Note: ~~O-~ ++ - ~': *H*r:tmnj~
In the astable mode, the first positive half ~ B. . IAI\O~s S:IM.:!ilm$
cycle has a duration of TM; succeeding ~ 0-2 IBlt~~~O':~IOII
durations are tA/2. :i 1100'5,1011
o
,
>'
In addition to variations from unit to unit, , 60"
o
47
100 220
5.10
5,10
the monostable pulse width may vary as a
function of frequency with respect to VOO +25 +45
and temperature. These variations are AMBIENT TEMPERATURE (TA1-'C
AMBIENT TEIroIPERATURE (TA)-'C
presented in graphical form in Fig. 22 to 27
with 10 V as reference for voltage-variation Fig. 26 - Typical Q and Q pulse-width Fig. 27 - Typical Q and Q pUlse-width
curves and 25°C as reference for temper- accuracy vs temperature accuracy range vs temperature.
ature-variation curves. (high frequency).
583
CD404 7 A Types
III. Retrigger Mode Operation VI. Power Consumption 10 ASTABLE MODE
SUPPLY 'VOLTAGE IYogl-'",
The C04047A can be used in the In the standby mode (Monostable or
retrigger mode to extend. the output- Astable), power dissipation will be a
pulse duration, or to compare the fre- function of leakage current in the
quency of an input signal with that of circuit, as shown in the static electrical
the internal oscillator. In the retrigger characteristics. For dynamic operation,
mode the input pulse is applied to the power needed to charge the external
terminals 8 and 12, and the output is timing capacitor C is given by the
taken from terminal 10 or 11. As shown follOWing formulae:
in Fig. 28, normal monostable action is
obtained when one retrigger pulse is
applied. Extended pulse duration is Astable Mode: P = 2CV 2f. (Output at
terminal No. 13)
10' '0'
obtained when more than one pulse is
applied. For two input pulses, tRE=t1' P = 4CV 2f. (Output at
Fig. 30 - Power di../pation .. output
+ t1 + 2t2' For more than two pulses, terminal Nos. 10 and 11)
frequency (VDO C 5 V).
tRE (a OUTPUT), terminates at some
variable time, to, after the termination Monostable Mode:
of the last retrigger pulse, to is variable (2.9CV2) (Duty Cycle)
because tRE (a OUTPUT) terminates
P=
T to
after the second positive edge of the ASTABLE MOOE
SUPPLY VOLTAGE CVOO'.IOV
oscillator output appears at flip-flop 4
(Output at term inal ~I+---+---+---+---f---+---f---1
(see Fig. 8)_
Nos. 10 and 11)
,o"-e---+---+---+----t----t--
IV. External Counter Option
Time tM can be extended by any a- 10'
mount with the use of external counting
circuitry. Advantages include digitally The circuit is designed so that most of
the total power is consumed in the ,o"-F--f--t-"'::"f--=---I--t--t--!
controlled pulse duration, small timing
capacitors for long time periods, and external components. In pr~ctice, the
lower the values of frequency and '0'
extremely fast recovery time. A typical 104
implementation is shown in Fig. 29. voltage used, the closer the actual power
10 I .00 $01 102 10'
OOR'O FREQUENCY III-Hz
10'
'0'
The pulse duration at the output is dissipation will be to the calculated
Fig. 31 - Power diu/pat/on .. output
text = (N-1)(tA) + (tM + tA/2) value.
Because the power dissipation does not frequency (VDO - 10 V).
where text= pulse duration of the cir-
cuitry, and N is the number of counts depend on R, a design for minimum
used. power dissipation would be a small
value of C~ The value of R would
depend on the desired period (within
V. Timing·Component Limitations
the limitations discussed above). See
The capacitor used in the circuit should ASTAILI MODE
Figs. 30-32 for typical power con- SUPPLY VOLTAGII {Vool-ISV
be non-polarized and have low leakage(i.e.
sumption in astable mode. '0
the parallel resistance of the capacitor
! ,~W
~~'.
should be an order of magnitude greater
than the external resistor used)_ There is '0'
~.\'•
~~ ~'- f
no upper or lower limit for either R or C

value to maintain oscillation.
However, in consideration of accuracy, C
'0' -
must be much larger than the inherent 10'
stray capacitance in the system (unless
this capacitance can be measured and
taken into account). R must be much 'ZCS-Z0030R2
'0
0
10 _10
, 10
,
QDR 0 FREQUENCY IO-H,
.0
..
10 '0
, .
'
'0
larger than the CMOS "ON" resistance in 9ZCS-Z1414
series with it. which typically is hundreds Fig. 28 - Implementation of external Fig. 32 - PoWtlr dillipation .. output
of ohms. In addition, with very large counter option. frequency (V DO = 15 Vi.
values of R, some short-term instability
with respect to time may be noted.
The recommended values for these
components to maintain agreement with
previously calculated formulas without
trimming should be:
1UUl:-:.:.::.-.lL
7~
C;;;'100 pF, up to any practical value, for
astable modes;
C ;;;. 1000 pF, up to any practical value
for monostable modes.
92C:5-20029
10kU';;;R';;;1 MU
Fig. 29 - Retrigger-mode WtI""form••
584
CD4048A Types
Thesetypesaresupplied in 16-lead hermetic
CMOS MUlti-Function dual-in-line ceramic packages (0 and F
Expandable a-Input Gate age (Esuffix), l6-lead ceramic flat package
The RCA- CD4048A is an 8-input gate an open circuit. This feature enables the
having four control inputs. Three binary user to connect this device to a common
control inputs - Ka, Kb, and Kc - provide bus line.
BINARY CON!ROL INPUTS
the implementation of eight· different logic
'FUNCTION CONTROL'
functions. These functions are OR, NOR, In addition to the eight input lines, an ------- 3-STATE
i' "V
AND, NAND, OR/AND, OR/NAND, AND/
OR, and AND/NOR.
A fourth control input -Kd - provides the

user with 3-state outputs. When control
EXPAND input is provided that permits the
user to increase the number of inputs to one
CD4048A, (see Fig. 6). For example, two
CD4048A's can be cascaded to provide a
r-,.
INPUTS B - 13
e-l'
0-11
"I· "
10 7
••
CONTROL
16-input multifunction gate. When the

rau~PUT
EXPAND- 15
r--
input Kd is high the. output is either a logic EXPAND input is not used, it should be I
1 or a logic 0 depending on the input states. connected to VSS_ INPUTS F - 5

When control input Kd is low, the output is 0-'
H-3
vss·a
MAXIMUM RATINGS, Absolute-Maximum Values: VOO·16
92CS-22249
STORAGE-TEMPERATURE RANGE (T.tg) ••••••••••••.••••••••..•••••• -65 to +150oC CD4048A

OPERATING-TEMPERATURE RANGE (TA): ° Functional Diagram
PACKAGE TYPES D, F, K, H ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 to +125 0 C
PACKAGE TYPE E .••.•••••.•••••.••••••••••••.•••••.••••• -40 to +85 C
(Voltage. referenced to VSS Terminal): ••••••••••••••.•.••••••••••.•• -0.5 to +15 V
Features: I
POWER DISSIPATION PER PACKAGE (PD) • Medium-power TTL drive capability
FOR TA=-40to+60oC (PACKAGE TYPE E) .•••••••••••••..•.•.••••.••• 500mW • Three-state output
FOR TA=+60 to +85 0 C (PACKAGE TYPE E) ••••••••• Darate Linearly at 12 mW/oC to 200 mW
• High ·current source and sink capability
FOR T A = -55 to +100·C (PACKAGE TYPES D, F, K) .•.•••••.••••.••••..•.••• 500 mW
FOR TA = +100 to +l25·C (PACKAGE TYPES D, F, K) ••••. Derate Linearly at 12 mW/oC to 200 mW
9 mA (typ.) @VDS=0.5V, VDD = 10 V
DEVICE DISSIPATION PER OUTPUT TRANSISTOR • Many logic functions available in one
FOR TA= FULL PACKAGE-TEMPERATURE RANGE (ALL PACKAGE TYPES) . • . • • • . . . 100 mW package
INPUT VOLTAGE RANGE, ALL INPUTS •••••••••••••••••••••.•••• -0.5 to VDD +0.5 V • Quiescent current specified to 15 V
LEAD TEMPERATURE (DURING SOLDERING): • Maximum input leakage current of 1 pA
At di.tance 1/16 ±1/32 inch (1.59 ±0.79 mm) from ca •• for 10. max • • • . . • • • • . . . . . • • +26SoC
Ay-
NOR OR NAND AND • l-V noise margin (full package-
temperature range)
A~
C D
E
G H
F
e
E
G
D
F
H
.~
C D
E F
• H
EX. EX. EX.
OR/AND OR/HAND ANDIOR ANO/NOR Applications:
iD-ni~~~J~ • Selection of up to 8 logic functions

• Digital control of logic
• General-purpose gating logic
~~ ~~ ~~-.--~ ~~
Decoding
- Encoding
Fig. 1 - Basic logic configurations.

MBIENT TEMPERATURE IT"I-25-C
TYPICAL TEMP. COEFFICIENT AT ALL VAL.UES OF VGS.-Q3.,.ftt:,
LIMITS
10V
CHARACTERISTIC VOO D,F,K,H E UNITS

(VI Packages Package
Min. Max. Min. Max_

!5 10 15
DRAIN-TO~SOURCE VOLTAGE (Vosl-V
Supply-Vo(tage Range (For TA = Full .ZCS-ZOI4SfU
3 12 3 12 V
Package-Temperature Range) Fig. 2- Tvp(cal output·n~channel drain
characteristics.
585
CD4048A Types
AM81ENT TEMPERATURE ITA)-25-C
STATIC ELECTRICAL CHARACTERISTICS TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF 'YGS-·D.3 ..J-c
CD4048AO, Ak
CD404IAE
Conditions GATE-TO-SOURCE VOLTAGE {Vasl-ISV
D. F. K~ H Packages E Package
Va VIN Voo -5 +25 +25 lOY
+125 -40 +85 lOY
(V) IV) (V)
lOY
- - 5 1 p.005 1 60 10 0.01 10 140
Quiescent Device
Current I L Max. - - 10 2 0.01 2 120 20 0.02 20 280 p.A ..
ov
10 IO
- - 15 25 0.5 25 1000 250 2.5 250 2500 MAIN-TO-SOURCE VOLTAGE IVosl-V tzCS-tlilMIn
Fig. 3- Minimum output n-channel drain

Output Voltage: characteristics
Low Level. - 5 5 o Typ.; 0.05 Max.
VOL DRAIN-lO-SOURCE VOLTAGE (yost-v
- 10 10 o Typ.; 0.05 Max. V -15 -10 -So
-'Y
High Level - 0 5 4.95 Min.; 5 Typ. -20
~
VOH - 0 10 9.95 Min.; 10 Typ. -40 I
-IOV 6:
Noise Immunity:
-60 - "
Inputs Low. 4.2 - 5 1.5 Min.; 2.25 Typ. ~
VNL
9 - 10 3 Min.; 4.5 Typ.
V
AMIBIENT TEMPERATURE ITAI'25·C
VNH TYPICAL TEMP. COffFICIfNT AT ALL VALUES OF .- 0.3.,. -C
1 - 10 3 Min.; 4.5 Typ. "CI-101441,
Fig. 4- Typical output p-channe' drain
Noise Margin: characteristics.
Inputs Low. 4.5 - 5 1 Min.
DRAIN-TO-SOURCE \IOLTAGE ,IVo51-V
VNML V -15 -10 -
9 - 10 1 Min. ~~:~:~ ;:MM:~~~~~~!~I.~~5~L ++F-sv
VALUES OF VGS··0,3 %/-C 1
6:
I
VNMH 1 - 10
~OY ~
1 Min.
Output Drive
GATE·TO-SOURCE VOLTAGE l\foslo-ISV
Current:
n·Channel(Sink)
0.4 - 4.5 2 3.2 1.6 1.1 1.9 3.2 1.6 1.3
IDN Min . 0.5 - 10 5.6 9 4.5 3.1 5.4 9 4.5 3.7

mA
CI)4I04BAD,AK
p·channel
(Source).
IDPMin.
4.6 - 5 -2 -3.2 -1.6 -1.1 -1.9 -3.2 -1.6 -1.3
C0404UE
Fig. 5- Minimum outputp-channefdrain

......-
9.5 - 10 -5.6 -9 -4.5 -3.1 -3.8 -9 -3.15 -2.6 characteristics.
Any Input
Input Leakage
Current.
IIL.IIH
- - 15 ± 10-5 Typ .• ± 1 Max. JlA
.
i
?I~~----~-------+
3·State Output Forced

Leakage Current (Output Disabled) JlA ~ I05f------l--.,...~~~~=--+-----____l
!ffi loz'~."..£"...4c,..~~4------.L------I
IOL.IOH
-I - 115 ±10- 4 Typ .• ±2 Max.
~
~.
INPUT FREQUENCY "II-Hz
Fig. 6- Typical power dissipation as a

586
CD4048A Types
DYNAMIC ELECTRICAL CHARACTERISTCS at TA = 25°C and CL = 15 pF·and 50 pF, ..

AMBIENT TEMPERATURE IT""25-C
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF Voo·0.3 %/-c
Typical Temperature Coefficient for all values of VDD = 0.3%fOC RL = 200 kil i 1200
CL=15pF
LIMITS
t"
~800
SuPPLY VOLTAGE lVool-sv
TEST D,F,K,H E
CONDITIONS Package
VDIl TYP. MAX.* TYP. MAX.* ,,.
,Oy
(Vo tsl
Propagation Delay Time 5 750 1300 750 1600 60 80 100 120 160 ISO
ns
tpHL 10 225 400 225 500 LOAD CAPACITANCE ICL'- pF

ns Fig, 7- Typical propagation delay time as a
High-to-Low Level tTHL 10 30 50 30 65
5 130 250 130 300
Low-to-High Level tTLH ns
10 40 60 40 75
Input Capacitance CI Any Input 5 - 5 - pF
AM ...NT
CL = 50pF
•
Propagation Delay Time 5 775 1350 775 1650
ns
tPLH,tpHL 10 240 430 240 530
ns
High-to-Low Level tTHL 10 40 70 40 85
5 145 280 145 330
Low-to-High Level tTLH ns
10 50 80 50 95
Input Capacitance GI
. .
Any Input 5 - 5 - pF
. .
• Max. Limits represent worst-case limits for worst-case modes of operation shown In Figs. 15, 16, and 17 .
LOAD CAPACITANCE ICLI-pf
Fig. 8- Tvpicallow-to-high level transition

time as a function of load capacitance.
AMBIENT TEMPERATURE: ITA'-2S-C

.TYPICAl. TEMP. COEFFICIENT AT ALL YAIJIE5 OF 'IDOoO.l"'l.'-c
INPUTS
o
Vss
~ "0 suPp 1.1 '4'O\.1»E \~0I.''1 INPUTOVCO
OUTPUTS
VOO-VNH
~ 100
~
.0
"--
VNOL
~
I
lOY
NOTE:
TEST ANY ONE INPUT,
Vss
LOAD CAPACITANCE tCll-IlF '2C5- 27400 Voo OR Vss'
Fig. 10- Quiescent-device~urrent Fig. 11- Noi$~immunity

Fig. 9- Tvpical high-to-Iow level transition te't circuit. test circuit.
time as a function of load capacitance.
VOO
INPUT~~'"
16
Voo INPu(Js
VDO NOTE'
IS
"
INPUT O U T P U T H - ---90%
- --
-
--10%
~ MEASURE INPUTS
13
o~ SEQUENTIALLY, tTHL tTLH
"
Yss TO BOTH Voo AND 'Iss'
CONNECT ALL UNUSED "10 92C5-22265
INPUTS TO EITHER
Vss Veo OR Yss'
Vss
Fig. 12- Input-Ieakage-current

test circuit. Fig. 13- tTHL' tTLH - ANO/NOR.
587
CD4048A Types
Voo Voo
NOR
J (OUTPUT)
I.
"~
Voo
13
" IS
"IS INPUT
i
"
13
Ko -Kb-I(c "
0-0-0
"
10
12- INPUT ORlAND GATE 92CS-20240

J. (A+B+C+O)' (E+F+G+H)' (XI +X2+X3+X4)
ANO
Fig. 14(a) . 12·input OR/AND gate.
INPUT 50%
OUTPUT
92CS-2226)
Fig. 15- tpLH - NAND.
OR
IS-INPUT NOR GATE 92CS-20Z'"

Voo
Fig. 14(b) 16·input NOR gate.

OUTPUT I.
IS
INPUT
Applications of Expand Input "
13
12
NAND IMPLEMENTATION OF EXPAND INPUT FOR 9 OR MORE INPUTS 10
9
OUTPUT FUNCTION OUTPUT BOOLEAN

FUNCTION NEEDED AT EXPRESSION
EXPAND INPUT V5S
NOR OR J-(A+B+C+D+E+F+G+H)+(EXP)
INPUT~O-t.
OR OR J=(A+B+C+D+E+F+G+H)+(EXP)
OUTPUT ~SO"
ANDIOR
AND
NAND
NAND
NAND
J=(ABCDEFGH)·(EXP)
J-(ABCDEFGH)·(~)
-'~PHL~ f
92CS-22264
OR/AND NOR J=(A+B+C+D)·(E+F+G+H)·(EXP)

OR/NAND NOR J=(A+B+C+D)·(E+F+G+H)·(r:5<P) Fig. 16- tpHL - AND.
AND/NOR AND J=(ABCD)+(EFGH)+(EXP)

AND/OR AND J=(ABCD)+(EFGH)+(EXP)
Note: (EXP) designates the EXPAND function (j.e .• X,+X2+ . .. XN).
ANDINOR ORINAND ORlAND
92CS-22252"
Fig. 14(c) Actual·dq;uit logic configurations.
Fig. 14- Expansion logic and truth table.
588
CD4048A Types
K.
". - -
r-------
B~ 3 CONFIGURATIONS
CI SAME AS FOR INPUT "A" I
a~ _ _ _ _ _ _ _ ...J
,..---_p---. Vaa
EXP--~~~~~--------------------i
Vss
E---j--------
•
I
F
~ ---L 4 CONFIGURATIONS
SAME AS FOR INPUT ~AH
---------
,~ ~-
Vss ~KO
"0---1--------- ~O
Kc ---1 '3 CONFIGURATIONS Kc
Kd--l SAME AS FOR "K~'INPUT ~~c
L _ _ _ _ - - - --J---L::~:
Transmission Gate Definition
TG = Transmission Gate
Input to Output is:
al A bidirectianallow impedance when
control input 1 is low and control
2 is high.
b) An open circuit when control input 1
is high and control input 2 is low.
t2CM-222!SIRI
FUNCTION TRUTH TABLE
OUTPUT UNUSED
BOOLEAN EXPRESSION Ka Kb Kc
FUNCTION INPUT*
NOR J=A+B+C+D+E+F+G+H 0 0 0 VSS
OR J=A+B+C+D+E+F+G+H 0 0 1 VSS
OR/AND J=(A+B+C+DI-(E+F+G+HI 0 1 0 VSS
OR/NAND J=(A+B+C+DI-(E+F+G+HI 0 1 1 Vss
AND J=ABCDEFGH 1 0 0 VDD
NAND J=ABCDEFGH 1 0 1 VDD
AND/NOR J-ABCD+EFGH 1 1 0 VDD
AND/OR J=ABCD+EFGH 1 1 1 VDD
Kd=l Normal Inverter Action
Kd=O High Impedance Output
EXPAND InjJut=O *See Figs. 1 and 7.
Fig. 17- Logic diagram and truth table.
589
CD4049A, CD40S0A Types
CMOS Hex Buffer/Converters
CD4049A-lnverting Type RECOMMENDED OPERATING CONDITIONS at TA=25 0 C, Except as Noted.
CD4050A-Non-1 nverting Type For maximum reliability, nominal operating conditions should be selected so that
The C04049A and CD4050A are inverting LIMITS
and .non-inverting hex buffers, respectively, CHARACTERISTIC UNITS
Min. Max.
and feature logic-level conversion using only
one supply voltage (VCC)- The input-signal Supply·Voltage Range (Vee) (For T A=Full Package·
3 12 V
high level (VIH) can exceed the VCC supply
voltage when these devices are used for logic-
level conversions. These devices are intended
Temperature Range)
Input Vol tage Range (V I) Vce
. 12 V
for use as CMOS to OTL/TTL converters "The CD4049 and CD4050 have high-to-Iow-Ievel voltage conversion capability but not
and can drive directly two OTL/TTL loads. low-to-high·level; therefore it is recommended that V I "? v ec .
(VCC=5 V, VOL ;;'0.4 V, and ION;;'3.2 mA.)
The CD4049A and C04050A are designated
as replacements for C04009A and C04010A, Limits at Indicated Temperatures (OC)
respectively. Because the C04049A and Characteristic Conditions D, F, K, H Packages E Package Units
C04050A require only one power supply, Vo VIN Vce -55 +25 +125 -40 +25 -+65
they are preferred over the C04009A and (VI (VI (VI Typ. Limit Typ. Limit
C04010A and should be used in place of the
C04009A and C04010A in all inverter, cur- Quiescent
rent driver, or logic-level conversion appli- Device
- - 5 0.3 0.01 0.3 20 3 0.03 3 42
cations. In these applications the C04049A Current,
- - 10 0.5 0.01 0.5 30 5 0.05 5 70 j.lA
and C04050A are pin compatible with the
'LMax.
- - 15 10 0.02 10 100 50 0.05 50 500
C04009A and C04010A respectively, and
can be substituted for these devices in Output
existing as well as in new designs. Terminal Voltage:
No. 16 is not connected internally on the
C04049A or CD4050A, therefore, connection
Low· Level, - 0,5 5 o Typ.; 0.05 Max.
to this terminal is of no consequence to cir- VOL - 0,10 10 o Typ.; 0.05 Max. V
cuit operation. For applications not re- High·Level, - 0,5 5 4.95 Min.; 5 Typ.
quiring high sink-current or voltage conver- VOH - 0,10 10 9.95 Min.; 10 Typ.
sion, the C04069 Hex Inverter is recom-
Noise
mended.
Immunity:
These types are supplied in l6-lead hermetic
suffixes), l6-lead dual-in-line plastic pack- VNL 7.2 - 10 3 Min.; 4.5 Typ.
age (E suffix), l6-lead ceramic flat packages CD4050A
(K suffix), and in chip form (H suffix). Inputs High, 1.4 - 5 1.5 Min.; 2.25 Typ.
Features: VNH 2.8 - 10 3 Min.; 4.5 Typ. V
• High sink current for driving 2 TTL loads All Types
•
•
High-ta-Iow level logic conversion
Quiescent current specified to 15 V
Inputs Low, 3.6 - 5 1 Min.; 1.5 Typ.
• Maximum input leakage of 1 j.lA at 15 V VNL 7.2 - 10 2 Min.; 3 Typ.
(full package-temperature range) CD4049A
Applications: Noise
• CMOS to DTL/TTL hex converter Margin:
• CMOS current ·slnk" or ·source" Inputs Low, 4.5 - 5 1 Min.
driver VNML Min. 9 - 10 1 Min.
• CMOS hlgh-ta-Iow logic-level C04050A
converter
-
~ ~ G-'
A G.i A VNMH Min. 1 10 1 Min. V
C04050A
e~ Hoe 8~HaB Output Dri ve
e
~ I=C C !{>-! I-e Current:
N·Channel 0.4 - 4.5 3.3 5.2 2.6 1.8 3.1 5.2 2.6 2.1
o~ JoB
~ J=D (Sink),
ION Min.
0.4
0.5
-
-
5
10
3.75
10
6
16
3
8
2.1
5.6
3.6
9.6
6
16
3
8
2.5
6.6
E ~- 1(0E
E~ "E
P·Channel 4.5 5 0.62 -1 -0.5 -0.35 -0.6 -1 -0.5 -0.4
rnA
F ~- L'F F~ L=F (Source), 2.5 - 5 -1.85 -2.5 -1.25 -0.9 -1.5 -2.5 -1.25 -1
vee_'_ vee_'_ lOP Min. 9.5 - 10 -1.85 -2.5 -1.25 -0.9 -1.5 -2.5 -1.25 -1
vss _8_ vss-8- Input
Ne -13 Ne "I!
Ne 016 Ne sl6
Leakage
CD4049A Current, Any Input 15 ±10-5 Typ., ±1 Max. j.lA
CD4050A
Fig. 1 - Functional diagrams. ilL,IIH
Max.
590
MAXIMUM RATINGS, Absolute·Maximum Values: AMBIENT TEMPERATURE ITA lo2S·C

SUPPl..Y VOLTAGE I Vccl· , v
STORAGE·TEMPERATURE RANGE (T stg )
OPERATlNG·TEMPERATURE .RANGE (T A ):
PACKAGE TYPES D, F, K, H ........... . -SS to +12SoC
DC SUPPLY·VOL TAGE RANGE. (V CC ) MINIMUM MAXIMUM
(Voltages referenced to VSS Termlnal)....... ......................... ...... -0.5 to +15 V
FOR T A = -40 to +60 0 C (PACKAGE TYPE E) SOOmW
FOR T A = +60 to +85 0 C (PACKAGE TYPE E ) Derate Linearly at 12 mW/oC to 200 mW
FOR T A = -55 to +100°(; (PACKAGE TYPES D, F, K) SOOmW
I 2 ,
FOR T A = +100 to +125°C (PACKAGE TYPES D, F, K). ..... Derate Lonearlv at 12 mW/oC to 200 mW INPUT VOLTAGE 1VIJ-V

FOR TA = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES). 100 mW Fig. 2-Minimum and maximum voltage
transfer characteristics for
INPUT VOL TAGE RANGE. ALL INPUTS. -0.5 to V DO +O.S V
CD4049A.
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1/16 ± 1/32 Inch 11.59 079 mml from case for 10 s max.
AMBIENT TEMPE.RATURE (TAJ-2S·C

SUPPL.Y VOLTAGE {lIccl.S II
•
>
I ,
~
w , MIN'MUM MAXIMUM
~~ 2
S
~ I
, 2 ,
INPUT VOLTAGE I \Ix I-V
INPUT VOLTAGE IVZI-V
Fig. 3-Minimum and maximum voltage Fig. 4-Minimum and maximum voltage Fig. 5-Minimum and maximum voltage
transfer characteristics for transfer characteristics for
transfer characteristics for
CD4049A. CD4050A.
CD4050A.
: :
: ISU~LYV?"'G"V".)-'0
I} t
:
,,,,,~. ".PERATURE IT, .~
I~ . ,,:.~'
IT 'v : ....
I~
,
I
INPUT VOLTAGE (VI J-V
'ICS-lO.8:S .2CS-20 .....
Fig. 6- Typical voltage transfer charac- Fig. 7-Typical voltage transfercharac- Fig. 8- Tvpical and minimum n-channel drain
teristics as a function of tempera- teristics as a function of tempera- characteristics as a function of gate-to-
ture for CD4049A. ture for CD4050A. source voltage IV GSI for CD4049A, CD4050A.
DRAIN-to-SOURCE VOLTAGE lVosI-V

LOAD CAPACITANCE ICLJ-pF ~2CS-20~2~
Fig. 9- Typical and minimum p-channel drain
characteristics as a function of gate-to-
Fig. 10- Typical high-to-Iow level propagation delay Fig. 11- Typical high-to-/ow level propagation delay
source voltage IVGSI for CD4049A,
time vs. CL for CD4049A. time vs. CL for CD4050A.
CD4050A.
591
DYNAMIC ELECTRICAL CHARACTERISTICS at T A=250 C; Input t r ,tr=20 ns,
CL =15 pF, R.:=200 kn
LIMITS
ALL PKGS.
VCC Typ. Max.

Low·to-High, tpLH
5 5 50 80
CD4049A
10 10 25 55
ns
5 5 75 140
CD4050A
10 10 35 85
High-to-Low. tpHL
Fig. 12- Typicallow-to-high level propagation delay
5 5 15 55 time .... CL for CD4049A.
CD4049A
10 10 10 30
ns
5 5 55 110
CD4050A
10 10 25 55
Transition Time:
5 5 50 100
Low-to-High, tTLH
10 10 30 60
ns
5 5 20 45
High-to-Low, tTHL
10 10 16 40
Input Capacitance, CI
CD4049A 15
pF
Fig. 13- Typicallow-to-high level propagation delay

time .... CL for CD4050A.
9ZCS-20526
Fig. 14- Typical high-to-Iow level transition time Fig. 15-Typicallow-to-high level transition time
vs_ CL for CD4049A. CD4050A. vs. CL for CD4049A, CD4050A.
~ 10' AMBIENT TEMPERATURE ITA 1- FULL "G. TlMP. ft.. IE •
~IO'
10 AMBIENT T£.MPERA1lJRE ITA I -FUI.L Pd. TEU " RANGE,=I=
I. ...
.,". '
4 • '10' 2 4 . 'It a 2
.
10 10
llo!! INPUT FREQUENCY Iff' kHz 9ICS-2~21"
~ ffi"~ ~~
+'
,,, ..... ' .,..,
~ 10" ~ ,,' [}f-~" " Fig. 16-Typical dissipation characteristics for
~ ~ m~
,.- ~~
~ 10'
~"~
,..' ~(l~
.:i.tc.,ft;
CD4049A, CD4050A.
~
! 10'
" . ~...~...
~
is
i
10
\~,,;\.,."l
. ~
.<$'
~ ~ ~ ~ ~
I
10 IO~ 10' 10. IO!l 10 . 10
, ..n.
10
a
INPUT RISE ANO FALL. TI"E It,.t, 1 INPUT RISE ANO FALL TIM' '1,,111
9lCS-Z04'JOA IN
Fig. 17-Typical power dissipation VB. transition Fig. 18-Typical power dissipation vs. transition
time per inverter CD4049A. time per inverter CD4050A. Vgo
~
,NPUTS
vDO
V
00
-V,
~H
~
INPUTOVDO
OUTPUTS
+
~
Yeo
~
INPuTS NOTE
MEASURE INPUTS
SEQUENTIALLY.
TOIOTHVOOINDYsS·
,.) VSS
(0)
Vss
V.:'l 1:
=
•
Vss
~ CONNECT ALLUNUS. .
NlUTS 1"0 EITHER Fig. 22 - (a)Schematic diagram of CD4049A, 1 of
Yoo ORVSS
NOT[: '!CS-I"r401 6 identical units.
TEST ANY ONE INPUT,
Vss WITH OTHER INPUTS AT (b) Schematic diagram of CD4050A, 1 of
92CS-27400 Yeo OR Vss· Yss 'ICS-Z7401 6 identical units.
Fig_ 19-Noise.immunitv test circuit. Fig. 20-lnput leakage current test circuit. Fig. 21~-ouiescent device current test circuit.
592
CD405 7 A Types
CMOS LSI 4-Bit Arithmetic Logic Unit

The RCA·CD4057A is a low·power arithme· Applications:
tic logic unit (AlU) designed for use in LSI RIGHT SERIAL
computers. An arithmetic system of virtually • Parallel Arithmetic UniU DATA LINE
any size can be constructed by wiring to· • Process Controllers FUNCTION 1.....- - - - - ,
SELECT - ,
gether a number of CD4057 A A lU's. The • Remote Data Sets
CD4057 A provides 4·bit arithmetic opera· • Graphic Display Terminals
tions, time sharing of data terminals, and full
functional decoding for all control lines. The
distributed control system of this device
provides great flexibility in system designs
by allowing hard·wired connection of N VOO' 26 TO UCS-202~eRZ
units in 4N unique ·combinations. Four Yss -25 REGISTER
control lines provide 16 instructions which detected and used to establish a conditional
Fig. 1 - Block diagram - CD4057A.
include Addition, Subtraction, Bidirectional operation. Predetermined operation of the
and Cycle Shifts, Up·Down Counting, AND, CD4057A on a conditional basis allows
OR, and Exclusive·OR logic operations. greater ALU flexibility. Although especially Features:
applicable as a parallel arithmetic unit. the
• LSI Complexity on a Single Chip
Two mode control lines allow the CD4057A CD4057 A also finds use in virtually any
to function as any 4·bit section of a larger application requiring one or more of its 16 • 16-lnstruction Capability
arithmetic unit by controlling the bidirec· basic instructions. The CD4057 A is supplied ·Add, Subtract, Count
·AND, OR, Exclusive·OR
•
tional serial transfer of data to adjacent in a hermetically sealed 2B-lead dual-in-line
arithmetic arrays. By means of three "Con' ceramic package (CD4057 AD). 2B-lead cer- ·Right, Left, or Cyclic ShifU
ditional Control" lines Overflow, All Zeros, amic flat package (CD4057AK). and in chip • Bidirectional Data Busses
and Negative State conditions may be form (CD4057AH). • Instruction Decoding on Chip
• Fully Static Operation
MAXIMUM RATINGS, Absolure·Maximum Values:
STORAGE·TEMPERATURE RANGE (T stg ) • Single·Phase Clocking
OPERATING·TEMPERATURE RANGE (T A ): • Easily Expandable to 8,12,16,.
PACKAGE TYPES D. K. H -55 to +125 o C ... Bit Operation
DC SUPPLY·VOL TAGE RANGE. (VOO' • low Quiescent Device Dissipation ..
(Voltages referenced to VSS Terminal)...................................... -0.5 to +15 V .... 10 pW (typ.)
POWER DISSIPATION PER PACKAGE (POl: • Conditional·Operation Controls on Chip
ForTA = -5510 +100·C (PACKAGE TYPES D. K) ..................................... 500mW • Add Time (Data In·To Sum Out)
For TA = +100 10 +125·C (PACKAGE TYPES D. K) ......... Derale Linearly al12 mwrc 10 200 mW =375 ns (typ) at 10V
DEVICE DISSIPATION PER OUTPUT TRANSISTOR • Quiescent current specified to 15 V
FOR T A = FULL PACKAGE·TEMPERATURE RANGE (ALL PACKAGE TYPES) . . . . . . . 100 mW
• Maximum input leakage current of 1 JlA
INPUT VOLTAGE RANGE. ALL INPUTS. -0.5 to V OD +0.5 V at 15 V (full package·temperature range)
At distance 1/16 ± 1/32 Inch (1.59 ± 0.79 mm) from case for 105 max. • l·V noise margin (full package·temperature
range)
tpo (01 - Col + 3 tpD leI - Col = 790 ns
For maximum reliability, nominal operating conditions should be selected' so that
VDD liMITS
I013-16
513-16
tpo (D:t - Col + 2 tpo reI - Col + tpo lei - Sol = 925 ns
CHARACTERISTIC (V) UNITS

Min. Max. tpo lot - Col + 2 tpD leI - Col'" 615 ns

Setup Time, ts 5
3
40
12
-
V
I09-12
59-12
,
tpo (01- Col + tpo leI - Col. tpo Ie] - Sol = 150 os
DATA 10 20 - ns
tpo (OJ: - Col t Ipo leI - Col" 440 ns
OPCODE -
5
10
5
4590
1320
1200
-
-
I.5-.
05·8 IpO (01 - Col + tpo leI - Sol = 575 ns
Clock Pulse Width, tw ns

10 375 - tpo U)x - Col· 2&5 01
Clock Input Frequency, fCL 5 0.13 -

Count Mode 10 0.46 - MHz
01.4
151·4
tpOID:t-SoI;315ns
Shift Mode 5 0.33 -

10 1.4 - Vss 92CS -2 1875
Clock Rise or Fall Time, trCl, tfCl

5 - 15
IJS
10 - 15
Fig. 2 - Typicsl.pStldch6fBCteriniCl ofs 16·bit ALU st VDD - 10 V.
593
CD405 7 A Types
Limits at Indicated Temperatures (oCI
CONDITIONS
.~D4057AD, CD4057AK, C.D~OS7AH
Vo VIN VDD -S5°C 2SoC 12SoC
(VI (VI (VI Min. Max Min. Typ. Max. Min. Max.
Quiescent Device
- - 5 - 5 - 0.5 5 - 150
Current IL - - 10 - 10 - 1 10 - 300 IJA
- - 15 - 50 - 1 50 - 2000 MiX. COUNTING flll£QUENCY " ..}-IIIHz IlQ-2IUO
Output Voltage; - 5 5 o Typ.; 0.05 Max. Fig. 3 - Maximum counting frequency

Low-Level ,VOL V VI.
- 10 10 o Typ.; 0.05 Max_ supplV voltage for a typical C04057A.
- 0 5 4.95 Min.; 5 Typ.

High Level, VOH V
- 0 10 9.95 Min.; 10 Typ.
Noise Immunity 0.8 - 5 1.5 Min.; 2.25 Typ.

(Allinputsl 1 - 10 3 Min.; 4.5 Typ.
VNL' VNH V
4.2 - 5 1.5 Min.; 2.25 Typ.
9 .- 10 3'Min.; 4.5 Typ.
Noise Margin: 1 Min.
Inputs Low,
4.5 - 5
VNML 9 - 10 1 Min.
V
Fig. 4 - Transition time VI. load capacitance
VNMH 1 - 10 1 Min. for data outputs (01-04).
Output Drive Current: 0.5 - 5 0.11 - 0.09 0.16 - 0.06 -
ION,IOP CLOCK PULSE RISE AHI) tALL TlMIES
Zero Indicator VDD

L
n·channel 0.5 - 10 0.12 - 0.10 0.16 - 0.07 -
p-channel 3 - 5 0.04 - 0.03 0.06 - 0.02 -
7 - 10 0.08 - 0_07 0.13 - 0.05 -
Negative Indicator 0.5 - 5 0.11 - 0.09 0.30 - 0.06 - Fig. 5 - Clock pulse rise and fall times.
n-channel 0.5 - 10 0.12 - 0.10 0.40 - 0.07 -
p-channel 4.5 - 5 0.07 - 0.06 0.19 - 0.04 -

9.5 - 10 0_12 - 0.10 0.30 - 0.07 - rnA
Overflow Indicator 0.5 - 5 0.25 - 0.20 0.50 - 0.14 -

n-channel 0.5 - 10 0.37 - 0.30 0.90 - 0.21 -
p-channel 4.5 - 5 0.08 - 0.07 0.21 - 0.05 -
Fig_ 6 - Oars setup time.
9.5 - 10 0.12 - 0.10 0.38 - 0.07 -
All Other Outputs 0.5 - 5 0.11 - 0.09 0.10 - 0.06 - ~---Voo
n-channel 0.5 - 10 0.06 - 0.05 0.12 - 0.03 -

Voo
p-channel 4.5 - 5 0.02 - 0.02 0.05 - 0.01 -
9.5 - 10 0.06 - 0.05 0.08 - 0.03 -
~nr~5
I nput Lea kage 92CS-2187"
Current -AT ± 10-5 Typ., ± 1 Max. IJA

IIL,IIH,
Fig_ 7 - Oars hold time.
594
CD4057 A Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C and CL = 15 pF, R L = 200 kil, LOGIC DESCRIPTION
tptf = 20 ns OPERATIONAL MODES
Typical Temperature Coefficient at all values of V DO =0.3%fC
The CD4057A arithmetic 10!lic unit operates
TEST LIMITS in one of four possible modes. These modes
CHARACTERISTICS CONDITIONS CD4057AD, CD4057AK control the transfer of information, either
UNITS serial data or arithmetic operation carries, to
VDD Min. Typ. Max. and from the serial-data lines. Fig. 8 shows
Propagation Delay Time: the manner in -which the four modes control
tpLH,tpHL 5 - 1430 3900
the data on the serial-data lines.
DATA IN-to- r--------,
SUM OUT 10 - 375 720
CARRY IN-to- 5 - 915 2550

LEFT 0
etJ: :
:'1S"...."M~OOE~Of-o.." "1':: .RIGHT
r:'J:
~
SUM OUT 10 - 310 840
L - ----lBYPASS _..J
,..----------,
~s: ~
DATA IN-to-
5 - 950 2580 ns
LEFT
DATA _
LINE
!~ ~~~DATA
_ _ _ _ _ _ _ _ _ _ J LINE
~
RIGHT
CARRY OUT 10 - 265 720 BYPASS

r---·-----..,
CARRY IN-to- 5 - 485 1320 LEFT :~RIGHT
DATA~~~OATA
CARRY OUT L.INE ~ _________ ~ LINE
10 - 175 480 BYPASS
5 - 1980 5400
ZI Input
10 - 750
~
-to- 2040 92C$-20252.RI
ZIOutput 5 - 265 720 Fig. 8 - Schematic of "Mode" concept.
10 - 110 300 In MODE 0, data can enter or leave from

either the left or the right
Transition Time: 5 - 3700 10350 serial-data line.
In MODE 1, data can enter or leave only on
tTLH,tTHL 10 - 1650 4500 the left serial-data line.
ZIOutput-
5 - 420 1140 In MODE 2, data can enter or leave only
on the right serial-data line.
10 - 220 600
ns
In MODE 3, serial data can neither enter
nor leave the register ,re!lardless
Negative Indicator and 5 - 300 825 of the nature of the operation.
Overflow Indicator 10 - 165 450 Furthermore, the register is
by-passed electrically, i.e.,
All Other 5 - 1000 2775 there is an electrical bidirec·
Outputs tional path between the right
10 - 475 1275
and left serial' data terminals.
ns
The two input lines labeled C1 and C2 in
Width,tW the terminal assignment diagram define one
10 - 125 375 pf four possible modes shown in Table I.
Through the use of mode control, individual
Clock Rise and Fall Time, 5 - - 15
arithmetic arrays can be cascaded to form
trCL,tfCL fJS
10 - - 15 one large processor or many processors of
various lengths_
Minimum Set Up Time: tSLH,tSHL 5 - 20 40
ns
DATA 10 - 10 20 TABLE I - MODE DEFINITION
OPCODE
5 - 1675 4590
ns C2 C1 MODE
10 - 485 1320 0 0 0
Minimum Data Hold Time, tHLH, tHHL

5 - 20 40
ns
0 1 1
1 0 2
10 - 10 20
1 1 3
Maximum Clock Frequency: fCL 5 0.13 0.36 -
Examples of how one .. hard·wired ..
Count Mode 10 0.46 1.35 - MHz combination of three ALU's can form (a) a
Shift Mode 5 0.33 0.90 - 12-bit parallel processor, (b) one 8-bit and
one 4-bit parallel processor, or (c) three
10 1.4 3.8 - 4·bit parallel processors. merely by changes
in the modes of each ALO are shown in
Input Capacitance, CI ANY INPUT - 5 - pF Fig. 10.
595
CD405 7 A Types
.
PARAlLEL DATA
INIOUT LINES e. Exclusive;OR - processes contents
of register with data on parallel-data
lines in a logical Exclusive·OR function.
f. IN -loads data on parallel-data lines
FUNCTION { : I into register.
SELECT * c 6
g. DATA OUT CONTROL - unloads
, 7
contents of register and overflow
flip-flop onto parallel data lines and
overflow 110 independent of all other
controls.
h. SUB:
CLOCK
In Mooe 0, adds to the contents of
A' the register the one's com·
*{
CONDITIONAL B
INPUTS plement of the data on the
C parallel-data lines. Carries
can enter on the right
serial data line and can
leave on the left serial
data line. The overflow
indicator does not change
state.
17 4
In Mode 1, adds to the contents of the
J3f
OVERFLOW OVERFLOW LEFT NEG ROTATE-2
110 INO SERIAL INO
DATA
(Roll register the two's comple-
LINE DD ment of the data on the
*ALL INPUTS PROTECTED BY
parallel-data lines. Gener-
COS/Mas PROTECTION NETWORK
ated carries can leave on
the left serial line. The
V55
CARRY IN is set to zero.
Fig. 9 - Simplified logic diagram. The overflow indicator
Data-flow interruptions are shown by shaded abc d does not change state.
areas. With these three ALU's and the four 0 0 0 0 NO·OP (Operational Inhibit) In Mode 2, same as Mode D, except
available modes, 61 more system combina- 0 0 0 1 AND carries cannot leave on the
tions can be formed. If 4 ALU's are used, 0 0 1 0 right serial-data line.The
Countdown
44 combinations (256) are possible. Fig.TT 0 0 1 1 absence or presence of an
shows a diagram of 4 CD4057 A's inter- Count up overflow is registered.
connected to form a 16-bit parallel processor. 0 1 0 0 Subtract Stored number In Mode 3, same as Mode 1, except
from zero (SMZ) carries· cannot leave on the
Subtract from parallel data left serial-date line. The
lines (SM) (stored number from absence or presence of an
parallel data lines) overflow is registered.
Add (AD) i. COUNT UP:
Subtract (SUB) (Parallel data In Mode D, adds to the contents of the
lines from stored number) register the data on the
Set to all ones (SET) right serial-data line and
,.~ Clear to all zeroes (CLEAR)
permits any resulting carry
to leave on the left serial-
Exclusive-OR data line. No data enters
Fig. TO - "Mode" connections for parallel OR the parallel-data lines.
processor: Input Data (From parallel In Mode 1, internally adds a one to
(a) T2-bit unit. data lines) the contents of the register
(b) one B·bit and one 4·bit unit Left shift and permits any resulting
(c) three 4·bit units. carry to leave on the left
Right shift
Rotate (cycle) right serial-data line. No data
NOTE: The BYPASS terminal of the "most
enters or leaves the right
significant" CD4057A is connected to the serial-data line.
bypass terminal of the "least significant" All instructions are executed on the positive
edge of the clock. In Mode 2, adds to the contents of the
CD4057 A. The bypass terminals on all other register the· data on the
CD4057A's are left floating. This inter- PARALLEL COMMANDS right serial-data line. No
connection is performed whenever more data enters or leaves the
than one CD4057 A are used to form a a. CLEAR - sets register to zero.
b. SET -sets register to all ones. left serial-data line.
processor. In Mode 3, internally adds a one to
INSTRUCTION REPERTOIRE c. OR -processes contents of register
the contents of the register
with value on parallel-data lines in
No data enters or leaves
a logical OR function. the register on any serial-
Four encoded lines are used to represent d. AND -processes contents of register
16 instructions. Encoded instructions are as data or parallel·data line.
with value on parallel·data lines in In all modes, with the
follows: .
a logical AND function. DATA OUT control high
596
CD4057 A Types
line. The overflow indi-
cator does not change
LEFT SERIAL RIGHT SERIAL
DATA LINE DATA LINE state. The CARRY-IN is
(CARRY OUT) (CARRY IH) set to zero.
In Mode 2, one's complements the
..,
ZERO IND
..,
ZEROIND ZERO IND ZERO IND
BYPASS BYPASS • BYPASS BYPASS contents of the register
.01 • Rol and adds the data on the
* R02 •• 2 • R02 •• 2 right serial-data line to the
contents of the register.
Carries cannot leave the
L--+_+__ VDD left serial data line. The
absence or presence of an
overflow alters the
VDD • TERMINAL INTENTIONALLY LEFT FLOATING VDD VS$
overflow indicator.
92CS- 202"
In Mode 3, two's complements the
Fig. 11 - Connection for 16-bir arirh!peric logic unit.
contents of the register.
Serial data can neither
the count is presented on open-circuited. The over- enter the right serial-
the parallel data lines (01- flow indicator does not data line nor leave the
04)_ change state. The CARRY- left serial-data line. The
i- COUNT DOWN: IN is set to zero. overflow indicator is at
In Mode 2, adds. the contents of the zero. The CARRY-IN is
In Mode 0, subtracts a one (2's comple- register to the data on the set to zero.
ment forml from the con- parallel data lines and the n. NO-OP - no operation takes place,
tents of the register and right serial-data line. Any The clock input is inhib-
adds to this result the data overflow sets the overflow ited and the state of all
on the right serial-data line indicator. The left serial- registers and indicators
and permits any resulting data line is open-circuited. remains unchanged.
carry to leave on the left The absence or presence of SERIAL-SHIFT OPERATIONS
serial-data line_ No data an overflow is registered. a_ ROTATE (cycle) RIGHT - This opera-
enter& on the parallel-data In Mode 3, adds contents of the register tion is internal. The contents of the
lines_ to the data on the parallel- register shift to the right, cyclic fashion
In Mode 1, internally subtracts a one with the leftmost stage accepting data
data lines. Any resulting
from the contents of the from the rightmost stage regardless of
carry sets the overflow indi-
register and permits any the mode. Data can leave the register
cator. The two serial-data
resulting carry to leave on serially on the right data line only while
lines are open circuited. The
the left serial-data line_ No
absence or presence of an the register is in Mode 1 or Mode O.
data enters or leaves the
overflow is registered. The Data can enter the left data line serially
right serial-data line_
CARRY-IN is set to zero. while the register is in Mode 1 or Mode
In Mode 2, subtracts a one from the
I. SM - same operation as AD except the O. The Rol terminal of the "Most
contents of the register and Significant" C04057 A must be connect-
contents of the register are two's comple-
adds to this result the data
mented during addition in Mode 1 and ed to the R02 terminal of the "Least
on the right serial-data line.
Mode 3. In Mode 0 or Mode 2, the con- Significant" C04057A. All other R01
No data enters or leaves on
tents of the register are one's comple- and R02 terminals must be left floating.
the left serial-data line.
mented and added to the data on the When only one CD4057A is used, R01
In Mode 3, internally subtracts a one
right serial-data line and the parallel- must be connected to R02.
from the contents of the
register. No data enters or data lines. Overflows occurring in Mode b_ RIGHT SHIFT - The contents of the
leaves on the serial-data 1 or Mode 0 do not alter the overflow register shift to the right and serial opera-
lines. indicator. The presence or absence of tions are as follows:
In all modes, with the DATA OUT control overflows is registered on the overflow In Mode 0, data can enter serially on
high the count is presented on the parallel indicator in Mode 2 or Mode 3_ the left data line, shift
data lines (01-041. m_ SMZ: through the register, and
In Mode 0, one's complements the leave on the 'right data
. k. ADD(AD): contents of the register line.
In Mode 0, adds the contents of the and adds the data on the In Mode 1, data can enter serially on
register to the data on the right serial-data line to the the left data line. The
parallel-data lines and the contents of the register_ right data line effectively
right serial-data line. Any Any resulting carry can is open - circuited.
resulting carry can leave on leave on the left serial- In Mode 2, data can leave serially on
the left serial-data line. The data line. The overflow the right data line. The left
overflow indicator does not indicator does not change data line effectively is open-
change state. state. circuited. Vacant spaces are
In Mode 1, adds the contents of the In Mode 1, two's complements the filled with zeros.
register to the data on the contents of the register In Mode 3, serial data can neither en-
parallel-data lines and allows and permits any carry to ter nor leave the register;
any resulting carry to leave leave on the left serial- however, the contents sh ift
on the left serial-data line. data line. No data can to the right and vacated
The right serial-data line is enter the right serial-data places are filled with zeros.
597
CD4057 A Types
In all modes, with the DATA OUT
, CLE" SET NO CLEM NO . LT SHlPT NO ,. RT_T ,. SIO III! ,. lOB
. ..
NO
~.=
control high the data is presented "'..--'" GO
""r--
l- I- '-- f-- f--
on the parallel data lines (01·04). , -
c. LEFT SHIFT - The contents of the 0 I-
register shift to the left and serial
operations are as follows;
,
0
I--- - '--
r--
I--
In Mode 0, data can enter the right ,-
I---
- I-f--
I-- r--
I---
-
data line, shift through the
rl- r
,'W- I---
I-
register, and leave on the
left data line. co
- rt-
In Mode 1, data can leave serially on
the left data line. The right ,
data line effectively is --, - ....- . r--
'n'-. f--
-- - -L
R: -t-j~ -
r-t-
open-circuited. All vacant
0A'lJ.1·
o L .
positions are filled with 'h r-- r- . --1.. - I-- 'L
-- ' -H - - --
zeros.
DATAZ-
o L_ ~ 'r--
In Mode 2, data can enter serially· on 'n•• r-- r-- ~- - r-- -L
the right data line. The
DATA'·
o f-- -
--
left data line effectively is DATA'"
o'n r-- L_ r---
1----
L_
r-- .
- - f--
-L
open·circuited. ,
In Mode 3, data can neither enter nor ,
leave the register; however,
the contents sh ift to the
0
, r- L L -
left, and vacated places
are filled with zeros.
ZEROIND
~~
, h- I I-h
In all modes, with the DATA OUT
control high the data is presented on
NEG.IND
r -, r -,
,
the parallel data lines (01·04). CN£RFL.OW
IND. r h
Because the "DATA OUT" control instruc-
tion is independent of the other 16 instruc·
O\'t"F~
110
,
or---. ' - - .. _-- -- . .. .. ,-
---
tions, care must be taken not to activate
thil control when date are to be loaded into
CL
~LrLs s ...U LrL U-LrL ...r LJ Lr lsl Lr LJ " - -
:u: CONNECTED TO \'mo.
MOTU: Itol COMNECT£O TO Ral; BY 'PASS IS (PEN; ' '!OIST£II'' IIIODt: 5.
the processor. This instruction should only .~~~~~EfIM:~S '::::T~-rO~-?S":'GM~ WHEN "DATA our- IS L.OII; DAIHrO LIN(
be activated when the processor il executing
a NO·OP, any SHIFT, SMZ, COUNT UP or
DOWN, CLEAR, or SET. NEGATIVE·NUMBER DETECTION
If a data line, serial or parallel, is used as an
input and the logic state of that line is not
The NEG IND terminal of the CD4057A is
connected to the output of the flip-flop -
--
defined (i.e., the line is an open circuitl,then
that is in the mOlt significant bit position.
the result of any operation using that line is
undefined.
A "1" on the NEG IND terminal indicates INI'IIT •
-
a negative number is in the register. This
detection is also independent of modes.
IMtUT d
OPERATIONAL SEQUENCE FOR
ARITHMETIC ADD CYCLE ZERO DETECTION
I"'"""
h-
CLOCK
- I-- ~
~
1. Apply IN Instruction and Word A on
Parallel Data Lines (01-041.
The condition of "all zeros" is indicated
by a "1" on the Zero Indicator terminal DATA f
---L
of the "Most Significant" CD4057A.
2. Apply CLOCK to load Word A into
the register. As shown in Fig. 11, terminal ZI of the
DATA 2*
- ,
----
--~
3. Apply OP CODE Instruction and Word CD4057 A containing the least significant L-
B on Data Lines. set of bits is connected to VDO. Zero ,
4. Apply CLOCK to load resulting indication is independent of modes. '- ---
function of A and B into the register.
5. Apply "DATA OUT" control to COMPLEMENTING NUMBERS '---
present result to Parallel Data Lines.
OVERFLOW
1. One's complement of number in ALU INOICATOR
register. ~ -
al ALU must be in MODE 0 or MODE' 2.
HlGATIV!
INDICATOR - ~
bl Zero on Rt. Data Line.

• SOLID L.INE REPRESENTS INPUT
c) Execute an SMZ instruction.
NOTE: Transitions of Step 2 and Step 3 i5E~sW!~~ir':~:
our- IS HIGH
may occur almost simultaneously; i.e.
separated by only one data-hold time. (Continued) Fig. 13 - Add cycle waveforms.
598
CD4057 A Types
2. One's complement of number to be Division Algorithm TABLE 11- CONDITIONAL-INPUTS

loaded into ALU register. TRUTH TABLE
a) If zero indicator output is low,
execute a CLEAR instruction, and A B C OPERATION
PERMITTED
make Rt. Data Line = O.
b) ALU must be in MODE 0 or MODE 2. 0 X X Yes
A sa1 ... aN_l aN" a2N-l 1 0 0 Yes
__________- , ____________J
\
~
c) Execute an SUB instruction. 1 0 1 No
3. Two's complement of number in ALU Dividend 1 1 0 No
register.
a) ALU must be in MODE 1 or MODE 3. 1 1 1 Yes
b) Execute an SMZ instruction. x = don't care
4. Two's complement of number to be Two examples of how the conditional
loaded into ALU register. operation can be used are as follows:
a) If zero indicator output is low, 1) For the Multiplication Algorithm
execute a CLEAR instruction, I
and make Rt. Data Line = O. A = 1, for step 7 (1)
Divisor
b) ALU must be in MODE 1 or MODE 3. A = 0, for step 7 (2)
c) Execute an SUB instruction. B=l
The following algorithms are given as a C = negative Indicator
generar guideline to demonstrate some of 2) For the Division Algorithm
the capabilities of the CD4057 A. A = 1, for step 7 (1)
1. Store As (j) Bs in External Flip-Flop. A = 0, for step 7 (2)
2.lf As = 1, complement ALU 1 and ALU 2. B=l
C = Co (left data line)
MULTIPLICATION OF 3. If Bs = 1, complement Register A.
4. Check for Divisor = 0 OVERFLOW DETECTION
TWO N-BIT NUMBERS
a) If Divisor = 0; stop, indicates The CD4057 A is capable of detecting and
division by O. indicating the presence or absence of an
b) If Divisor *0; continue. arithmetic !Wo's-complement overflow. A
5. Apply SUB instruction to ALU 1 !Wo's-complement overflow is defined as
and the contents of Register A to having occurred if the signs of the two initial
ALU 1 data lines.
00 ... 0/00 .. 0
,O...O/As • al' ..aN-l
I
6. Put a zero on RT data line of ALU
2 and shift ALU 1 & ALU 2 left 1
words are the same and the sign of the result
is different while performing a carry-gener-
Multiplier ating instruction.
bit.
7. Do "N" times. 0.Q11
(1) Apply a sub instruction to ALU 1 For example: (+) 0.110
and the contents of Register A to 1.001
the ALU 1 data lines.
Overflows can be detected and indicated
a) If Co = 1, then clock ALU 1, and
only during operation in Mode 2 or Mode 3
put a 1 on right data line of ALU 2.
I and can occur for only four instructions
b) If Co = 0, then do not clock, and put
Multiplicand a 0 on right data line of ALU 2. (AD, SMZ, SM, and SUB). If an overflow is
(2) Shift left 1 bit . detected and stored in the overflow flip-flop,
• As and Bs are sign bits S. If sign Flip Flop = 1, complement anyone of the five instructions AD, SMZ,
ALU 2. SM, SUB, or IN can change the overflow
9. Answer i.n ALU 2. indicator.
Multiplication Algorithm When any of the three subtraction instruc-
1. Clear ALU to Zero tions is used, the sign bit of the data being
2. Store As (j) Bs in External Flip-Flop. subtracted. is complemented and this value
3. If As = 1, Complement Register 1. is used as one· of the !WO initial signs to
4. If Bs = 1, Complement Register 2. detect overflows. If an overflow has occur-
5. Load Register 2 into ALU. red, the final sign of the sum or difference is
6. Do shift Left on ALU N Times one's complemented and stored in the most-
(N = number of bits). CONDITIONAL OPERATION significant-bit position of the register.
7. Do N Times: Inhibition of the clock pulse can be accom- The overflow flip-flop is updated at the same
(1) plished with a programmed NO-OP instruc- time the new result is stored in the
a) If MSB of ALU = 1 tion or through conditional input terminals CD4057 A. Whenever data on the parallel-
(Negative Indicator = High). A,B,and C.ln a system of many CD4057A's, data lines are loaded into the CD4057 A,
Then shift ALU left 1 bit; each CD4057A can be made to automati- whatever is on the Overflow I/O line is
add Register 1 to ALU. cally control its own operation or the loaded into the overflow flip-flop. Also,
b) If MSB of ALU = 0 operation of any other CD4057 A in the whenever data are dumped on the parallel
(Negative Indicator = Low) system in conjunction with the Overflow, data lines from the CD4057 A, the contents
Then shift ALU left 1 bit. Zero, or Negative (Number) indicators. of the overflow flip-flop are dumped on the
S. If As (j) Bs = 1, then Complement Table II, the conditional inputs, truth Overflow I/O line. Thus overflows may be
ALU. table, defines the interactions among A,B, stored elsewhere and then fed into the
9. Answer in ALU. and C. cn4057A at another time.
599
CD4057 A Types
OPERATIONAL SEQUENCE 2. CARRY IN-to-CARRY OUT and CARRY
AND WAVEFORMS FOR IN-to-SUM OUT
PROPAGATION·DELAY MEASUREMENTS INPUTOVCDOUTPUTS
A. Apply Word A and IN instruction VDD-VNH
1. DATA·IN·to·CARRY OUT and DATA B. Apply Clock to load word A into ........ ~
IN·to-SUM OUT register V:L 1
A. Apply Word A and IN instruction C. Apply AD instruction NOTE:
TEST ANY ONE INPUT,
B. Apply Clock to load word A into D. Apply Word B VSS WITH OTHER INPUTS AT
E. Apply CARRY IN (carry in) 92tS~27400
register Voo OR Vss'
C. Apply AD instruction F. Apply Clock to load result

D. Apply Word B (data in) (sum out) Fig. 15 - Noire-immunity tBlt clmult.
E. Apply Clock to load result G. Apply DATA OUT CONTROL
(sum out) to look at result
F. Apply DATA OUT CONTROL
to look at result
.
V50
INPUTS
INPUT a INPUT G
INPUT b INPUT b
INPUT Ie -+-t--I
V50
INPUT 0 -+-t--t-+-t--+--- INPUT d -+-t---+-t-H---
OATA OUT toNTROL Fig. 16 - QuiBICsnt-davice-current
DATA ,. DATA ,* tart .imult
DATA 'I!' DATA 2·
.'----- DATA 3·-i=:j::==~

DATA
CLOCK
4·'--+-+-11--1
CLOCK
V~NP(JU'
'. : :
~YOOT-+-t--t-~ Vss TO BOTH VDD ANOVss'
CONNECT ALL UNUSED
CD DATA IN INPUTS 10 EITHER
CD CARRY OUT CARR' OUT --+-+---+-l-H-+---- VDD ORVSS ·
(i) IUM OUT Vss
<D-@ OATA IN ToeARR'!' OUT
<D - ® OATA IN TO SUM OUT
<D CARRY IN
@ CARRY OUT
@SUMOUT .. SOUO LINE REPRESENTS INPUT
<D_@CMRtINTOCARRYOUT ~~: ~~p;~~c:.umH=~~HES

R[PRESENT OUTPUT WHEN "DATA
<D _@CMRYIN TO SUM out our" IS HIGH
Fig. 17 - Input-#ssksge-currsnt
felt .'mu't.
Fig. 14(a} - DATA IN·ta-CARRY OUT and Fig. 14(b} - CARRY IN-ta-CARRYOUTand
DA TA IN·ta-5UM OUT. CARRY IN-ta-5UM OUT.
TYPICAL APPLICATION
The CD4057A has been designed for use as a connections and data busing are primary
parallel processor in flexible, programmable, design goals. The block diagram of Fig. 18
easily expandable, special or general purpose is an example of a computer that processes
computers, where minimization of external 8 bits in parallel.
11l~j;;;;;lilill~~~~~i[::~C~O~40~'~4~~:::J~1 INPUT-OUTPUT
REGISTER
EXTERNAL
DATA
SERIAL
OATA
LINES
Fig. 18 - Example of computer organization using CD4057A.
600
CD4059A Types
CMOS Programmable CL voo

Divide-by-"N" Counter JI
23
22
OUT
J5
Standard "Au -Series Types (3-to-15-Volt Rating) J2 4 21 J6
J3 20 J7
J4 19 Ja
RCA-CD4059 standard "A "-Series types are Counter Range of Table 1. Control inputs
JI6 la J9
divide-by-N down-counters that can be pro- Kb and Kc can be used to initiate and lock
JI5 17 JlO
grammed to divide an input frequency by the counter in the "master preset" state.
J14 9 16 JII
any number "N" from 3 to 15,999. The out- I n this condition the flip-flops in the counter
JI3-IO 15 JI2
put signal is a pulse one clock·cycle wide are preset in accordance with the jam in-
occurring at a rate equal to the input fre- Kc II I' Ka
puts and the counter remains in that state
LI_2~T~0~P~V~IE~W~~
quency divided by N. This single output has 13 Kb
as long as Kb and Kc both remain low. The VSS
TIL drive capability. The down-counter is counter begins to count down from the
92CS- 22212RI
preset by means of 16 jam inputs. preset state when a counting mode other
TERMINAL DIAGRAM
The three Mode-Select Inputs Ka, Kb, and than the master preset mode is selected.
Kc determine the modulus ("divide-by" The counter should always be put in the
number) of the first and last counting sec- Operational and Performance Features:
master preset mode before the +5 mode is
tions in accordance with the truth table • Synchronous Programmable + N Counter:
shown in Table I. Every time the first selected. N = 3 to 9999 or 15,999
(fastest) counting section goes through one Whenever the master preset mode is used, • Presettable down-counter
cycle, it reduces by 1 the number that has control signals Kb;O and Kc;O must be • Fully static operation
been preset (jammed) into the three decades applied for at least 3 full clock pulses. • Mode-select control of initial decade
of the intermediate counting section and into counting function (+ 10,8,5,4,2)
the last counting section, which consists of After the Master Preset Mode inputs have • T2L drive capability
flip-flops that are not needed for operating been changed to one of the + modes, the • Master preset initialization
the first counting section. For example, in next positive·going clock transition changes
• Latchable + N output
the + 2 mode, only one flip-flop is needed an internal flip-flop so that the countdown
in the first counting sectidn. Therefore can begin at the second positive-going clock • Quiescent current specified to 15 volts
the last counting section has three flip-flops transition. Thus, after an MP (Master Preset) • Max. input leakage current of 1 /lA at 15
that can be preset to a maximum count of mode, there is always one extra count before volts,full package-temperature range
seven with a place value of thousands. If the output goes high. Fig.l illustrates a • 1 volt noise margin, full package-
+ lOis desired for the first section, Ka is total count of 3 (7 8 mode). If the Master temperature ranga
set to 1, Kb to 1, and Kc to O. Jam Inputs Preset mode is started two clock cycles or • 5-V and 10-V parametric ratings
J1, J2, J3, and J4 are used to preset the less before an output pulse, the output pulse Applications
first counting section and there is no last will appear at the time due. If the Master
counting section. The intermediate counting • Communications digital frequency
Preset Mode is not used the counter jumps synthesizers: VHF, UHF, FM, AM,etc.
section consists of three cascaded BCD de- back to the "JAM" count when the output
cade (+ 10) counters presettable by means • Fixed or programmable frequency
pulse appears. division
of Jam Inputs J5 through J16.
• "Time out" timer for consumer-appli-
The Mode-Select Inputs permit frequency- cation industrial controls
synthesizer channel separations of 10, 12.5, • Companion Application Note,ICAN-6374,
20, 25, or 50 parts. These inputs set the "Application 01 the CMOS CD4059A
maximum value of N at 9999 (when the Programmable Divide-by-N Counter in
first counting section divides by 5 or 10) or Fig. , - Total count of 3. FM and Citizens Band Transceiver
15,999 (when the first counting section Digital· Tuners"
divides by 8, 4, or 2). A "1" on the Latch Enable input will cause
The three decades of the intermediate count- the counter output to remain high once an
Ing section can be preset to a binary 15 in- output pulse occurs, and to remain in the The C04059A series types are available in a
stead of a binary 9, while their place values high state until the latch input returns to 24-lead ceramic dual-in-line package (0
are still 1, 10, and 100, multiplied by the "0". If the Latch Enable is "0", the output and F suffixes). 24-lead dual-in-line plastic
number of the + N mode. For example, in pulse will remain high for only 1 cycle of package (E suffix), 24-lead ceramic flat
the + 8 mode, the number from which count- the clock·input signal. package (K suffix), and in chip form (H
ing-down begins can be preset to: suffix).
As illustrated in the sample applications, this
3rd decade: 1500 device is particularly advantageous in com-
2nd decade: 150 munication digital frequency synthesis (VHF,
1st decade: 15 UHF, FM, AM, etc.) where programmable
Last counting section 1000 divide·by-"N" counters are an integral part
of the synthesizer phase-locked-loop sub-
The total of these numbers (2665) times system. The C04059A can also be used to
8 equals 21,320. The first counting section perform the synthesizer "Fixed Oivide-by-R"
can be preset to 7. Therefore, 21,327 is the counting function. It is also useful in general-
maximum possible count in the + 8 mode. purpose counters for instrumentation func·
The highest count of the various modes is tions such as totalizers, production counters,
shown in the column entitled Extended and "time out" timers.
601
CD4059A Types
MAXIMUM RATINGS, Absolute-Maximum Valufl8: OPERATING CONDITIONS AT TA = 25°C
DC SUPPLV-VOLTAGE RANGE, (VDD) (Unless otherwise specified)
(Vollag'es referenced 10 VSS Terminal) .... " ... , .... , .. , .......................... ' -0.510 +15 V For maximum reliability, nominal operating condi-
INPUT VOLTAGE RANGE, ALL INPUTS ......... , .... ,., ..... , ................. -O.Slo VDD +0.5 V tions should be selected so that operation is always
POWER DISSIPATION PER PACKAGE (PO): within the following rangss.
ForTA = -4010 +6O"C (PACKAGE TYPE E) ............................................. SOOmW
For TA = +60 10 +8S'C (PACKAGE TYPE E) ..... , ...................... Derale Unearly 10200 mW Characteristic VDD Min. Max. Units
ForTA = -5510 +IOO'C (PACKAGE TVPES0, K, H) ...................................... 500 mW Supply Voltage
For TA = +100 10 +12S'C (PACKAGE TVPES 0, K, H) .•..••.•...•..•.••• Derale Unearly 10100 mW Range - 3 12 V
DEVICE DISSIPATION PER OUTPUT TRANSISTOR (over full temp.
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................. 100 mW range)
OPERATING-TEMPERATURE RANGE (TA): Clock Pulse 5 200 - ns
PACKAGE TYPES 0, K, H ....................................................... -5Slo +12S'C
PACKAGE TYPE E ............................................................... -40 10 +85° C
Width 10 100 -
STORAGE TEMPERATURE RANGE (Tslg) ..... .. .. .. . . . . .. . . . .. .. . .. • .. .. . .. .. . . .. -85 to +150" C
Clock Input 5 - 1.5
MHz
Frequency 10 - 3
AI distance 1/16± 1/32 inch (I.S9± 0.79 mm) from case for las max....................... +26S'C Clock Input Rise 5 - 15
and Fall Time 10 - 5 Ils
tI AMBIENT TEMPERATURE ITA 1~25·C

.
STATIC ,ELECTRICAL CHARACTERISTICS
i 60 200-mW CONSTANT
a POWER LOCUS
Conditions
Limits .
!:!50
ffi
Valu...t-55"C.+25 0 C.+725"C Apply to D, K, H, Packag... ~40
Vo VIN VDD Values at -4lJOC. +250 C. +850 C Apply to E Packages Units
Characteristic u
. (V) (V) (V) +25 0 Z 30
_550 -400 +850 +1250
Min. Typ. Max. ~
~ 20
Quiescent Device 5 10 10 700 300 - 0.02 10
Current.
IL Max.
10
15
20
-
20
-
200
-
400
-
-
-
0.02
-
20
500
IJ.A 1 10
2345678
Output Voltage: DRAIN-TO-SOURCE VOLTAGE{VOS'-V
Low Level, 05 5 0.05 - 0 0.05

VOL Max. 0,10 10 0.05 - 0 0.05 Fig.2 - Minimum output n-channel
V drain characteristics.
High Level, 0,5 5 4.95 4.95 5 -
VOH Min. 0,10 10 9.95 9.95 10 -
,"v
Noise Immunity:
Inputs Low, 5 1.5 1.5 2.25 -
VNL Min. 10 3 3 4.5 -
V
Inputs High, 5 1.5 1 2.25 - 1
ZOO-mW CONSTANT
VNH Min. 10 3 3 4.5 - POWER LOCUS
Noise Margin: Z 30
Inputs Low, 4.5 5 1 ~
VNML Min. 9 10 1 ~20 GATE-TO- SOURCE
V VOL~AGE ~VGSI~ 5 v
Inputs High; 0.5 5 1 ~ 10
VNMH Min. 1 10 1 5
1234567
Output Qrive ORAIN-TO-SOURCE VOLTAGE (VOS'-V
Current:
N·Channel Fig.3 - Typical output n-channel
(Sink)
0.4 5 2.5 2.3 1.6 1.4 2 4 - drain characteristics.
0.5 10 5 4.7 3.3 2.8 4 9 -
ION Min.
rnA DRAIN-TO -SOURCE VOLTAGE (Vosl- V
P·Ch"nnel 2.5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - -1$ -10
(Source)
lOP Min.
4.6
9.5
5
10
-0.5 -0.45 -0.36 0.3
-1.1 -1
0.4 0.8
-0.75 -0.65 -0.9 -1.8 -
AMBIENT TEMPERATURE (TAl' 25-C
.
i
GATE-TO-SOURC£ VOLTAGE (VGSl:- 5 V
I nput Lea kage -5 t!

Current:* 15 ±1 ±10· 5 ±1 IJ.A lOY
IlL, IIH Max.
* Any Input
-15V
Fig.4 - Minimum output p-channel

602
CD4059A Types
CRAIN-TO-SOURCE VOLTAcr C\losl-V
OYNAMIC ELECTRICAL CHARACTERISTICSATTA = 25 0 C.CL =50 pF.lnputtr.tf=20 ns.
~L =200len r----~
AMBIENT TEMPERATURE ITA
-I
,oz,·c
.,
GATE-TO-SOURCE VOLTAGE tvGS'o., \I ., t

CONOI·
LIMITS
t
-10.t!
TlONS
CHARACTERISTIC
VDD
(V)
ALL PACKAGES
Min. TVp. Max.
UNITS
200-0IIW CONSTANT
-lOY
-., ia
POWER LOCUS z
-204
Propagation Delay Time; tpHL. tpLH
5 - 180 360 ~
ns
10 - 90 180
Transition Time:
5 - 35 70
tTHL
10 - 20 40
ns
5 - 100 200
tTLH 10 - 50 100 Fig.6 - Typical output p-channel
Maximum Clock Input Frequency, ICL
5 1.5 3 - MHz
10 3 6 -
Average Input Capacitance, CI AMBIENT TEMPERATURf(TA)-2S"C
I t · ~ , ••• -....
1: i,.;,!~)lrq~:
~ ri '
(anv input) - - 5 - pF
1"""
~iltiij: :::;:I;::;lii1; !,:,'~_~j, ii,':,',:,-

+U·~H+""IIfI;n ···;H-t.. :!
PROGRAM JAM INPUTS (BCD)
-;-'
w w ~ ~ 00 ~ ro 00 00 ~
Fig.7 - Typicallow·to·high propagation delay

time VI. load capacitance.
~
;:
AMBIENT TEMPERATURE eTA ).a25·C·· .(.1+
; II
~ "..
,.~
Q 250
fFtt= fiFO
z
0 • :±t r-rtt
.j.;.. ,r ~t- ji,t
ii SUPPLY VOLTAGE (VDDl-'"1
is • +1#11
Ii!.!.,
0,,,
+h- Hn,i}
... lHt
,IllHi
Ttn t; ;j.::
~J ~
IOV '
t
~ .0
h=TT ITt ln' tnr ,ltt tT.
If-H H+ +Ftt
,~# , If i1tt
"
'" " :J:t:I=I= r;t l-Ht
a 0 30 40 5a 60 70 80 00 10
92CM-t2213RI
Voo
~
Fig.S - Typical high-to-Iow propagation delay
time VI. load capacitance.
ALL INPUTS (TERMS. 1-11, 13-22) PROTECTED

BY CMOS PROTECTION NETWORK
Fig.S - Functional block diagram.

vss
LOAD CAPACITANCE 1Cl.J-pF

!U:CS-24)2'2ftl
Fig.9 - Typicallow-to-high transition time

w. load capacitance.
603
CD4059A Types
TABLE I
MODE COUNTER
FIRST COUNTING LAST COUNTING
SELECT RANGE
SECTION SECTION
INPUT DESIGN EXTENDED
Can be Can be
MODE MODE
Ka Kb Kc
---
Di-
preset
to a Jam·
---
Di-
preset
to a Jam-'- Max. Max.
~ 10 vides max inputs vides max inputs
6 by: of: used: by: of: used:
'" 0
~ ro ~ ~ 00 ~ ro 00 ~ ~ 1 1 1 2 1 J1 8 7 J2,J3,J4 15,999 17,331
0 1 1 4 3 J1,J2 4 3 J3,J4 15,999 18,663
Fig. TO - Typical high-to%~~w transition time
VI. load capacitance.
1 0 1 5# 4 J1,J2,J3 2 1 J4 9,999 13,329
0 0 1 8 7 Jl,J2,J3 2 1 J4 15,999 21,327
1 1 0 10 9 J1,J2,J3,J4 1 0 - 9,999 16,659
X 0 0 MASTER PRESET MASTER PRESET - -
X = Don't Care #Operation in the -Hi mode (1 st counting section) requires
• Jl = Least significant bit. going through the Master Preset mode prior to going into
J4 = Most significant bit. the"'5 mode. At power turn·on, kc must be a 10gic'''O''
for a period of 3· input clock pulses after VDD reaches
a minimum of 3 volts. See Fig. 21 for a suggested external
preset circuit.
HOW TO PRESET THE CD4059A TO OESIRED'" N
10 15 20
SUPPLY VOLTAGE (vool-V
The value N is determined as follows:

Fig. II - Typical max. clock frequency N = [MODE") [1000 x Decade 5 Preset + 100X Decade 4
VS. supply voltage. (1 )
Preset + lOX Decade 3 Preset + 1 X Decade 2 Preset) + Decade 1 Preset
6 AMBIENT TEMPERATURE (TA )-2S-C MODE= First counting section divider (10, 8, 5,4 or 2)
4
2 II To calculate preset values for any N count, divide the N count by the Mode.
~I05 The resultant is the corresponding preset values of the 5th through 2nd
I R
":t .. ... decade with the remainder being equal to the 1st decade value.
, ,.,0
;;
5.
:iQ
10 \
.,
4 ~cY..~f
-:><Il
"..... N
Preset Value = Mode
(2)
G::
~
103
t
.. ,p
",< -.-CL-SO" Examples:
..
---CL-'!5pF A) N = 8479, Mode = 5
0
MODE SELECT = 5
/ I mill
1695~ Preset Values
10" , 4 •• 2
A
4 •• 2 4 G. , III
.. 681 2 4 .a
\0 102
INPUT FREQUENCY (n-kHz
10' 104 10' !5184~9 Ka Kb Kc
Mode N o
Fig. 72 - Typical power dissipation vs.
input frequency.
PROGRAM JAM INPUTS (BCD)

4
~
5
~
9 .
6
,
Jl J2 J3 J4 J5 J6 J7 J8 J9 Jl0 Jl1 J12 J13 J14 J15 J16
0 0 0 0 0 0 1 0 0
To verify the results use equation 1 :

N = 5 (1000X 1 + 100 X 6 + 10 X 9 + 1 X 5) + 4
N = 8479
MODE SELECT = 8
B) N = 12382, Mode = 8
2 .. 68'02 .. 6TcI 2 .. &'0' 2 .. 6T0 4 2 .. 6~0' 1547 + 6 Ka Kb Kc
CLOCK INPUT FREQUENCY(f CL1-KHr
8 I
12382 o 0
Fig. 13 - Typical power dissipation
VI. clock input frequency.
604
CD4059A Types
PROGRAM JAM INPUTS "CASCADING" VIA OTHER COUNTERS
6 7 4 5
~ ~
Fig. 14 shows a BCD'switch compatible ar·
Jl J2 J3 J4 J5 J6 J7 J8 J9 Jl0 Jll J12 J13 J14 J15 J16 rangement· suitable for 7 8 and 7 5 modes,
which can be adapted, with sl ight changes,
0 0 0 0 0 0 0 to the other divide-by-modes. In order to be
able to preset to any number from three to
To verify: about 256,000, while preserving the BCD-
N = 8 (1000 Xl + 100 X 5 + 10 X 4 + 1 X 71 + 6 switch compatible character of the jam in-
puts, a rather complex cascading scheme is
N = 12382
required. Such a cascading scheme is neces-
MODE SELECT = 10 sary because the CD4059A can never be pre-
set to a count less than 3 and logic is needed
CI N = 8479, Mode = 10 to detect the condition that one of the num-
0847 + 9 Ka Kb Kc bers to be preset in the CD4059A is rather
small. In order to simplify the detection
10 18479 o logic, only that condition is de

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Copyright 1983 by RCA Corporation

Printed in USA 8-83

Data Data Data Data

Number Title Page

MUL TIPLEXERS/ PHASE- QUAD INTER-

CD4006B CD4076Bt CD40105B CD4020B CD4017B CD4016B 6. CD4046B CD4016B+ CD4009UB

ARITHMETIC CIRCUITS DISPLAY DRIVERS TELECOMMUNICATION

Gates Gates (cont'd)

Flip-Flops Binary Ripple

Function I Type No. I No. of

Arithmetic Circuits (Cont'd)

CMOS LSI Products

CMOS Logic TTL Logic

CMOS Logic TTL Logic

Note: Add package suffix code to part number on all orders.

Welded-8eaI14,16,24, 18, 22, 24, 40-Lead

8,14,16,18,22,24, and 40-lead Versions

F'Suffix K Suffix T Suffix

Voo PAR. IN. Voo

voo PAR. IN.

40l> "- _4-

CD4045A (Page 571) CD4046A (Page 574)

ALL INPUTS PROTECTED BY

Triple 2·Channel 4·Segment Liquid·Crystal

92CS- 20092RI ALL INPUTS PROTECTED BY 92CS-Z009IR2

BCD-to-7·Segment Decoder/Driver BCD-to-7 -Segment Decoder/Driver

200-Stage Dynamic Quad Bilateral Switch 16-Channel

J 'A(±)B M'G(±)H VOO'14

4-Bit D-Type Register Quad Exclusive-NOR Gate a-Input NOR/OR Gate

INHIBIT/EXP .::IO~_ _ _ _ _ _---,

J .INH + ENABLE +AB+CO+EF+GH 92C5- 2 38 70RI

C04097B (Page 231) C040988 (Page 286) C04099B (Page 291)

Strobed Hex Inverter/Buffer Hex Buffer Dual 4-Bit Latch

BCD Presettable Up/Down BCD-to-7-Segment

4-Bit Latch/4-to-16 Binary Presettable Up/Down

Programmable Timer Dual Precision Monostable Programmable Timer

(Page 360) CD4555B (Page 366)

CD4556B (Page 366) CD4585B (Page 371) CD4724B (Page 375)

4-by-4 Crosspoint Switch 4-by-4-by-2 Crosspoi nt Switch

CD22103 (Page 649) CD22104 (Page 656) CD22104A (Page 656)

Hexadecimal Display Decimal Display

CD22105 (Page 661)

CD22105A (Page 661)

CD22301 (Page 666)

B~H"i II'I~ i'.. 1f---"9 DO 19

Hex Schmitt Trigger Dual 2-lnpul NAND 4-by-4 Multiporl Register

CLOC)!; DOWN I "l':':':=='-'-'-="-'

CMOS/TTL Level Converter CMOS/TTL Level Converter

Quad "D"-Type Flip-Flop 4-Bit Arithmetic Logic Unit

CD40175B (Page 449) Active-Low Data Active-High Data

CD40192B (Page 464) 4-Bit Universal Bidirectional Shift

CD40257B (Page 474)

8-BII FI••h AID Converter 8-BII FI..h AID Converter

CA3300 (Page 620) CA3308 (Page 831)

RCA RCA RCA

CD4000CN CD4000AE CD4010MJ CD4010AF CD4017BMD CD4017BD

CD4025BCJ CD4025BF CD4046BCN CD4046BE CD4073BCJ CD4073BF

CD4518BCN CD4518BE CD40175BCN CD40175BE F4021BDM CD4021BF

F4046BPC CD4046BE F4081BDC CD4081BF F4556BDM CD4556BF

HCF4011BF CD4011BF HCF4030BD CD4030BD HCF4052BE CD4052BE

HCF4078BF CD4078BF HCF4515BD CD4515BD HEF4015B CD4015BE

HEF4515B CD4515BE MC14010BCP CD4010BE MC14025UBAL CD4025UBF

MC14060BCL CD4060BF MC14161BCP CD40161BE MC14517BCL CD4517BF