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library
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity Nexys2_top_shell is
end Nexys2_top_shell;
------------------------------------------------------------------------
---------------
------------------------------------------------------------------------
---------------
COMPONENT nibble_to_sseg
PORT(
);
END COMPONENT;
------------------------------------------------------------------------
---------------------
--This component manages the logic for displaying values on the NEXYS 2
7-segment displays
------------------------------------------------------------------------
---------------------
COMPONENT nexys2_sseg
PORT(
clk : IN std_logic;
reset : IN std_logic;
);
END COMPONENT;
------------------------------------------------------------------------
-------------
--This component divides the system clock into a bunch of slower clock
speeds
------------------------------------------------------------------------
-------------
COMPONENT Clock_Divider
PORT(
clk : IN std_logic;
);
END COMPONENT;
------------------------------------------------------------------------
-------------
--Below are declarations for signals that wire-up this top-level module.
------------------------------------------------------------------------
-------------
------------------------------------------------------------------------
--------------
COMPONENT MealyElevatorController_Shell
PORT(
clk : IN std_logic;
reset : IN std_logic;
stop : IN std_logic;
up_down : IN std_logic;
);
END COMPONENT;
------------------------------------------------------------------------
--------------
------------------------------------------------------------------------
--------------
----------------------------
----------------------------
------------------------------------------------------------------------
--------------------
--This code instantiates the Clock Divider. Reference the Clock Divider
Module for more info
------------------------------------------------------------------------
--------------------
);
------------------------------------------------------------------------
--------------
------------------------------------------------------------------------
--------------
);
);
);
);
nexys2_sseg_label: nexys2_sseg
PORT MAP(
);
------------------------------------------------------------------------
-----
--Instantiate the design you with to implement below and start wiring it
up!:
------------------------------------------------------------------------
-----
-- C3C Hunter helped me with the syntax of the below port map
);
end Behavioral;
PROB 4
PROB3
.
PROB5
PROB2