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Once the number of states is at a minimum, then a judicious assignment of states may
further reduce the cost of the next state equations and/or the cost of the output equations.
A set of heuristic rules is proposed where each rule is directed toward the reduction of the
combinational logic in the finite state machine design.
As opposed to compact state assignments, one may propose a one-hot state assignment.
One-hot is a set of state assignments in which a unique bit is one in the assignment for
each state. This often leads to a reduction in the logic cost for the outputs, because in one
and only one state a given output is asserted.
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Digital System Design Using VHDL, Charles H. Roth, Jr., PWS Publishing Company, 1998, pp 25-27
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N1
Si Z1 = λ1(Si,X)
X
N2 Z2 = λ2(Sj,X)
Sj
A more practical way to determine state equivalence uses the state equivalence theorem:
Si = Sj if and only if for every single input X, the outputs are the same and the next states
are equivalent. When using the definition of equivalence, we must consider all input
sequences, but we do not need any information about the internal state of the system.
When using the state equivalence theorem, we must look at both the output and next state,
but we need to consider only single inputs rather than input sequences
The table of Figure 2 can be reduced by eliminating equivalent states. First, observe that
states a and h have the same next states and outputs when X = 0 and also when X = 1.
Therefore, a = h so we can eliminate row h and replace h with a in the table. To
determine if any of the remaining states are equivalent, we will use the state equivalence
theorem. From the table, since the outputs for states a and b are the same, a = b if and
only if c = d and e = f. We say that c-d and e-f are implied pairs for a-b. To keep track
of the implied pairs, we make an implication chart, as shown in Figure 3. We place c-d
and e-f in the square at the intersection of row a and column b to indicate the
implication. Since states d and e have different outputs, we place an x in the d-e square
to indicate that d ≠ e. After completing the implication chart in this way, we make
another pass through the chart. The e-g square contains c-e and b-g. Since the c-e
square has an X, c - e, which implies e - g, so we X out the e - g square. Similarly, since,
we x-out the f-g square. On the next pass through the chart, we X out all the squares that
contain e-f or f-g as implied pairs (shown on the chart with dashed xs). In the next pass,
no additional squares are X-ed out, so the process terminates. Since all the squares
corresponding to non-equivalent states have been X-ed out, the coordinates of the
remaining squares indicate equivalent state pairs. From the first column, a = b; from
third column, c = d; and from the fifth column, e = f.
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states are the same (or if i-j implies only itself), place a check (√) in square i-j to
indicate that i = j.
3. Go through the table square by square. If square i-j contains the implied pair m-
n, and square m-n contains an x, then i ≠ j, and an X should be placed in square
i-j.
4. If any Xs were added in step 3, repeat step 3 until no more Xs are added.
5. For each square i-j that does not contain an X, i = j.
If desired, row matching can be used to partially reduce the state table before
constructing the implication table. Although we have illustrated this procedure for a
Mealy table, the same procedure applies to a Moore table.
Two sequential networks are said to be equivalent if every state in the first network has
an equivalent state in the second network, and vice versa.
Present Next State Present Output
State X=0 X=1 X=0 X=1
a c f 0 0
b d e 0 0
c ha g 0 0
d b g 0 0
e e b 0 1
f f a 0 1
g c g 0 1
h c f 0 0
Figure 2 State Table Reduction by Row Matching
c-d
b
e-f
a-d
c f-g
e-g
b-c
d e-g a-b
f-g
e X X X X
f X X X X a-b
c-e e-f
g X X X X b-g a-g
a b c d e f
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c-d
b
e-f
a-d
c f-g
e-g
b-c
d e-g a-b
f-g
e X X X X
f X X X X a-b
c-e e-f
g X X X X b-g a-g
a b c d e f
Figure 4After Second and Third Pass
Present Next State Present Output
State X=0 X=1 X=0 X=1
a c E 0 0
c A g 0 0
e e A 0 1
g c g 0 1
Figure 5 Final Reduced Table
Key Terms
Equivalent States Two states in a sequential network are said to be equivalent if we
cannot tell them apart by observing input and output sequences.
Implication Chart A tabular method for finding equivalent states based upon
outputs and the implication made by next states.
Reduced State Table A state table in which all but one the equivalent states has
been removed.
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Digital Systems Design Using VHDL, Charles H. Roth, Jr, PWS Publishing Company, 1999, pp 19-20
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In order to reduce the amount of logic required, we will make a state assignment using
the following guidelines (see Fundamentals of Logic Design, p. 412):
I. States that have the same next state (NS) for a given input should be given adjacent
assignments (look at the columns of the state table).
II. States that are the next states of the same state should be given adjacent
assignments (look at the rows).
III. States that have the same output for a given input should be given adjacent
assignments.
NS Z
PS X=0 X=1 X=0 X=1
S0 S1 S2 1 0
S1 S3 S4 1 0
S2 S4 S4 0 1
S3 S5 S5 0 1
S4 S5 S6 1 0
S5 S0 S0 0 1
S6 S0 -- 1 --
Figure 6 State Table for Code Converter
Using these guidelines tends to clump 1s together on the Karnaugh maps for the next
state and output functions. The guidelines indicate that the following states should be
given adjacent assignments for the state table of Figure 6 :
I. (1, 2), (3, 4), (5, 6) (in the X = 1 column, Sl and S2 both
have NS S4; in the X = O column, S3
and S4 have NS Ss' and Ss and S6 have
NS So)
II. (1.2). (3.4). (5.6) (Sl and S2 are NS of So; S3 and S4 are
NS ofS1; and Ss and S6 are NS of S4)
III. (0, 1,4,6), (2,3,5)
Figure 7gives an assignment map, which satisfies the guidelines, and the corresponding
transition table. Since state 001 is not used, the next state and outputs for this state are
don't cares.
Q1
Q2Q3 0 1
00 S0 S1
01 S2
11 S5 S3
10 S6 S4
Figure 7 Assignment Map
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The one-hot assignment uses one flip-flop for each state, so a state machine with N states
requires N flip-flops. Exactly one flip-flop is set to 1 in each state. For example, a system
with four states (TO, T1, T2, and T3) could use four flip-flops (Q0, Q1, Q2, and Q3) with the
following state assignment:
We can write next-state and output equations by inspection of the state graph or by
tracing link paths on an SM chart. Consider the partial state graph given in Figure 8.
The next-state equation for flip-flop Q3 could be written as
Q3+ = X1 Q0 + X2 Q1 + X3 Q2 + X4 Q3
Note that each term contains exactly one state variable. Similarly, each term in each
output equation contains exactly one state variable:
Z1 = X1 QO + X3 Q2, Z2 = X2 Q1 + X4 Q3
When a one-hot assignment is used, the next-state equation for each flip-flop will contain
one term for each arc leading into the corresponding state ( or for each link path leading
into the state). In general, each term in every next -state equation and in every output
equation will contain exactly one state variable. The one-hot state assignment for
asynchronous networks is similar to that described above, but a "holding term" is
required for each next-state equation (see Fundamentals of Logic Design, p. 644).
3
Digital Systems Design Using VHDL, Charles H. Roth, Jr, PWS Publishing Company, 1999, pp 229-230
4
Programmable Gate Array
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T0 T1
X3/Z1 T2
X2/Z2
X1/Z1
T3
X4/Z2
When a one-hot assignment is used, resetting the system requires that one flip-flop be set
to 1 instead of resetting a11 flip-flops to 0. If the flip-flops used do not have a preset
input (as is the case for the Xilinx 3000 series), then we can modify the one-hot
assignment by replacing Q0 with Q0' throughout. For the preceding assignment, the
modification is
Another way to solve the reset problem without modifying the one-hot assignment is
to add an extra term to the equation for the flip-flop, which should be 1 in the starting
state. As an example, we use the one-hot assignment given in (6-6) for the main dice
game control of Figure 5-32(a). The next state equation for QO is
If the system is reset to state 0000 after power-up, we can add the term QO'Ql'Q2'Q3'to the
equation for QO+ . Then, after the first clock the state will change from 0000 to 1000
(TO), which is the correct starting state.
In general, both an assignment with a minimum number of state variables and a one-hot
assignment should be tried to see which one leads to a design with the smallest number of
logic cells. Alternatively, if speed of operation is important, the design that leads to the
fastest logic should be chosen. When a one-hot assignment is used, more next -state
equations are required, but in general both the next-state and output equations will
contain fewer variables. An equation with fewer variables generally requires fewer logic
cells-to realize. Equations with five or fewer variables require a single cell. As seen in
Figure 6-19, an equation with six variables may require cascading two cells, an equation
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Switching and Logic Spring 2007 jeg
with seven variables may require cascading three cells, etc. The more cells cascaded, the
longer the propagation delay, and the slower the operation.
Key Terms
State Assignment Rules A set of heuristic6 rules that attempts to reduce the cost of
the combinational logic in a finite state machine
One-Hot State Assignments State assignments uses one flip-flop for each state, so
a state machine with N states requires N flip-flops.
Problems5
1. Reduce the following state table to the minimum number of states using successive
partitioning method.
NS Z
PS X=0 X=1 X=0 X=1
A A E 1 0
B C F 0 0
C B H 0 0
D E F 0 0
E D A 0 1
F B F 1 1
G D H 0 1
H H G 1 0
2. Reduce the following state table to the minimum number of states using implication
chart method..
NS
PS X=0 X=1 Z
a e e 1
b c e 1
c i h 0
d h a 1
e i f 0
f e g 0
g h b 1
h c d 0
i f b 1
5
Fundamental of Logic Design, 5th Edition, Charles H. Roth, Jr. Thomson/Brooks/Cole, 2003
6
Heruistic -- of or relating to or using a general formulation that serves to guide investigation -
WordNet® 3.0, © 2006 by Princeton University
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3. Use the heuristic rule on page 4 to make compact state assignments. Assign state A
to "000".
NS Z
PS X=0 X=1 X=0 X=1
A A E 1 0
B C F 0 0
C B H 0 0
D E F 0 0
E D A 0 1
F B F 1 1
G D H 0 1
H H G 1 0
4. Implement the following state table using D-flip-flops and gates. Use a one-hot
assignment and write down the logic equations by inspecting the state table. Let S0 =
0012, S1 = 0102, and S2 = 1002.
7. Implement the state table of problem 3 using one-hot state assignments. Assume A =
000000012, B = 000000102, through H = 100000002.