Synchronous Rectification For Forward Converters PDF

Synchronous Rectification for Forward
Converters
Steve Mappus
www.fairchildsemi.com
1
Agenda
• Synchronous Rectifier (SR) Characteristics
• Forward Converter Transformer Reset Techniques
• Forward Converter SR Gate Drive

• Self-Driven
Self Driven
• Hybrid Self-Driven
• Control-Driven
• SR Timing Issues
• Primary-Side Trigger + Linear Predict Control (LPC)

• Application Example
• Measured Data
2 www.fairchildsemi.com
Synchronous Rectification (SR)
D1 L
Reset NP NS
Circuit D2 CO
CIN
Q1
Rectifier Diode Efficiency

y What is Synchronous
y Rectification?
(All Converter Losses Neglected)
• Replacing secondary side rectifiers (D1, D2)
ency, ηRECT (%)
100%
with MOSFETs (Q2, Q3)
90% Benefits of SR
80% • Higher Efficiency
Rectifier Efficie
VF=0.35V
70% VF=0.65V
• Lower output voltage and higher
VF=1V current applications benefit most
60%
• Parallel MOSFETs for higher current
50%
1 2 3 4 5 6 7 8 9 10 11 12 SR Nomenclature
Output Voltage (V) • Q2→control SR
• Q3→freewheeling SR
PO VO × I O 1
η= = =
PIN VO × I O + VF × I O V
1+ F
VO
Parallel MOSFETs
Diode Thermal Characteristic
• Negative temperature coefficient
• Tempp increase = VF decrease
• Not easily paralleled
SR Thermal Characteristic
• Positive
P iti temperature
t t coefficient
ffi i t
• Temp increase = RDS(ON) increase
• T↑, RDS(ON)↑, ID↓, T↓
• Automatic current sharing
• MOSFETs easily paralleled
Diode vs.
vs MOSFET Thermal II-V
V Characteristics
n = Number parallel MOSFETs
Rectifier I-V Characteristics
Rectifier efficiency
PO VO × I O 1
η= = =
PIN VO × I O + VF × I O V
1+ F
VO
Schottky Rectifier (MBR4035PT, 35V, 40A)
• Operates in first quadrant (Q1) only
η=86.84%, (VF=0.5V, VO=3.3V)
SR MOSFET (FDMS8670S,
(FDMS8670S 30V,
30V 42A)
η=97.06%, (VF=0.1V, VO=3.3V)
• >10% improvement, BUT…

RDS(ON) • Considers RDS(ON) conduction loss only!
VF
VF
• Operates in third quadrant (Q3)
IF IF
(a) SR MOSFET (b) Schottky Rectifier
SR I-V Characteristics
ID(A)
Q1
Ohmic VGS4 D ID
Region
VGS3
VDS
VGS2 G
VGS
VGS1 S
VF(BD)
BVDSS
VGS=0V VDS(V)
(Body-Diode)
D VGS1
VGS2
SR Operates in Third Quadrant
VDS • Low current
G VGS3
SR RDS(Q1)=RDS(Q3)
VGS Ohmic
S ID
VGS4 Region • High current, SR body-diode will conduct if:
I D × RDS (ON ) ≥ VF ( BD )
Q3
• For VGS=0V, negative current flows through SR
body-diode
body diode
CCM Buck, Diode Rectification
VGS(Q1)
VIN+VF
VIN-VO
VDS(Q1)
VIN
VD1
VIN-VO VF
VL
-V
VO
CCM
CCM ILO
VO
=D PD1 = VF × I O × (1 − D)
VIN IDS(Q1)
ID1
t0 t1 t2
CCM Buck Operational Waveforms
• D1 operates
p in first qquadrant onlyy – operation
p similar to SR
• Lower voltage converters can not tolerate losses associated with diode rectification
DCM Buck, Diode Rectification
DCM and CCM Voltage Gain
1
k=0.01
0.8
VO
k=0.1 =D
VIN
Volttage Gain
0.6
k≥1
kk=0
0.5
5
0.4
0.2
0 0.2 0.4 0.6 0.8 1
Duty Cycle
DCM
DCM Buck Operational Waveforms
VO 2
= where, 2× L
VIN 4× k k=
1+ 1+ 2 RO × T
D
• D1 operates in first quadrant only – no negative current flow during DCM

• Gain is non-linear during DCM operation
Non-Isolated Synchronous Buck
SR Dominant Losses:
• Channel conduction
PSR(CH) = I O2 × RDS (ON ) × (1 − D)
• Body-Diode conduction
Dedicated Controller or Driver PSR ( BD ) = V F × I O × t BD × Fs
• Minimize dead time
Where : t BD = (t1 − t 0 ) + (t 3 − t 2 )
• Anti cross-conduction protection
• Reverse Recovery
• Optimized gate drive current
• Emulate asynchronous operation PSR ( RR ) = QRR × VIN × FS
• Reduce body-diode conduction
SR Body-Diode Reverse Recovery
D IF
-dIF
CGD dt
G CDS
VF
RG CGS t
t0→t1 RDRV IF
D VR
CGD (a) Ideal Diode – No Reverse Recovery

G CDS
IF tRR
RG CGS (ISD)
tA tB
t1→t2 RDRV IDS -dIF
dt
VF
S QA QB t
QA=IFxtA IRR
D IDS
QB=IFxtB
CGD Softness=tA/tB
G CDS
VR
RG CGS
t0 t1 t2 t3
t2→t3 RDRV
(b) SR Body-Diode
Body Diode – “Ideal”
Ideal Reverse Recovery Characteristic
IG IS(CGS) IS(QRR) IS(CDS)
S
SR body-diode has high VF and long tRR!

Parallel SR Schottky Diode
Parasitic Inductance Limitation

di VSR ( BD ) − VF
=
dt LP1 + LP 2
• Typical example:
di 1.2V − 0.5V A
= = 70
dt 2 × 5nH µs SyncFET™ with Monolithic Schottky
• A
Assume 115A
A lload
d current • Minimal parasitic inductance
• Low VF
15 A × µs
dt = = 215ns • Using same example parameters:
70 A
di A 15 A × µs
• Current commutation time can exceed = 600 (measured ) dt = = 25ns
dt µs 600 A
body-diode conduction time
• Order of magnitude improvement
SyncFET™ Reverse Recovery
FDMS7670 vs FDMS7670S SyncFET™

• SyncFET™ QRR improvement of ~10%
• Previous generation trench technology would show improvement closer to ~50%
• FDMS7670S, SyncFET™ VF=0.43V, FDMS7670 VF=0.7V
Forward Converter SR
∝
(a) Forward Converter SR (b) Single-Ended Transformer Hysteresis
Forward Converter with SR

• Q2, Q3 gate drive challenges similar to synchronous buck
• Pi
Primary to
t secondary
d isolation
i l ti adds dd additional
dditi l timing
ti i requirement
i t
• Single-ended converter topology requires transformer reset
• Optimal SR timing is related to transformer reset method
Transformer Reset Techniques
Active Clamp
Reset
RCD Reset Resonant
Reset CCL
NP NS
NP NS NP NS
Q2
VIN
0
VIN VIN
-VR
0 Q1 0
Q1 -VR -VR Q1
Reset Winding RCD Reset Resonant Reset Active Clamp Reset

+ Reset Energy Recycled + Inexpensive Off-Line Solution + Reset Energy Recycled + High Efficiency (ZVT)
+ Simple Off-Line Solution + >50% Duty cycle Possible + Fewest Components + Higher Frequency Operation
- 50% Duty Cycle Limit (1:1) - Reset Energy Dissipated + Simple Telecom Solution + Lowest Vds Stress
- Possible Core Saturation - Q1 Hard Switched - Repeatable Design Difficult + Off-Line and Telecom
- Transformer Structure - High VDS Stress + SR Gate Drive
- Q1 Hard Switched - Not for Off-Line Power - Q1, Q2 Gate Drive
- Not
N t Suitable
S it bl for
f Self-Driven
S lf D i SR - Higher
Hi h Cost
C t
- Q1 Hard Switched - Limited PWM and/or Driver
Choices
Reset Method Impacts Self-Driven SR Gate Drive
SR Gate Drive Methods
1. Self-Driven
2. Hybrid Self-Driven
3. Control-Driven
Self-Driven SR
Self-Driven SR
• SR gate drive derived from transformer
(as shown) or output inductor
• Advantages
Self-Driven RCD Reset Waveforms
• Simple – no timing issues!
• SR gate charge recycled to load
• High efficiency with minimal components
• Best applied to active clamp forward (D and 1-D)
Self-Driven SR (Continued)
Self-Driven SR
• Disadvantages RDS(ON) versus VGS for
FDMS7670AS, SyncFET™
• SR gate drive is not regulated
• Not compatible with all reset techniques
• Difficult to optimize VGS and RDS(ON)
( ) when VIN > 2:1
• RDS(ON) can vary by 10% or more
• No control of freewheeling SR during start-up or light load
DCM operation
Hybrid Self-Driven SR
LO
VC VS Q3 CO RO
CIN U1
VIN PBias FAN3100C
Q1
VDD OUT
1 5 Q2
GND
R1
2
SBias U2
IN+ IN- FAN3100C
PWM 3 4
D1 VDD OUT
1 5
GND
C1 2
RC1 IN+ IN-
R2
3 4
D2
C2 RC2
RCD Forward Converter
Hybrid Self
Self-Driven
Driven SR
• Forward converters with resonant reset signals (ie, RCD or Resonant Reset)
• Control SR (Q2) is self-driven
• Freewheeling SR (Q3) gate-drive derived from primary-side inverted PWM
• Q1 to Q3, primary to secondary timing is critical
• Q2 to Q3 timing issues similar to non-isolated synchronous buck
Hybrid Self-Driven SR Timing
RC1 RC2 LO
PWM Q3
VC VS CO RO
CIN U1
VIN PBias FAN3100C
PWM Q1
VDD OUT
1 5 Q2
GND
2
SBias U2
R1 IN-
PWM 3
IN+
4 FAN3100C
PWM D1 VDD OUT
1 5
GND
C1 2
RC1 IN+ IN-
R2
3 4
VGS(Q1) D2
C2 RC2
VGS(Q2)
VGS(Q3)
VIN
VC Freewheeling SR Timing Adjustments
VDS(Q1)
• Split primary PWM signal
• Delay primary PWM rising edge,
edge t0→t2, tRC1
VS
• Delay and invert secondary-side Q3 gate drive
• Apply tRC2 so that Q3 turns on just after VS goes
VDS(Q2)
negative
• Adjust t0→t2 > t3→t4 so that Q2 is OFF prior to Q3 ON
VDS(Q3) (no cross-conduction for all line & load)
t0 t1 t2 t3 t4 t5
Hybrid Self-Driven SR
Advantages
• Improvement over self-driven SR
• Reduce body-diode conduction
• Regulate freewheeling SR gate drive
• Best applied to RCD or resonant reset forward converters
Disadvantages
• Non-adaptive to varying component or CCM/DCM mode change
• C t l SR gate
Control t drive
d i nott regulated
l t d (VGS proportional
ti l tot VIN)
• Timing adjustments dependant upon R and C tolerance and duty cycle, D
• Can not be used if primary PWM includes internal gate drive
• Can not control freewheelingg SR against
g negative
g current flow (DCM,
( , pre-biased
p loads))
Full control of both SR MOSFETs only achievable using Control-Driven

Control Driven SR
Control-Driven SR
LO
PBias U1
FAN3100C Q1a
Q3
VDD OUT
5
D2
1
VD VP CO RO
GND
2
IN+ IN-
IN D1
3 4
VIN Q1b
Q2
PWM
1 8
SBias
+
2 7
-
3 6
+
4 5
-
U2
FAN3225C
2 Switch Forward Converter (Delays Not Shown) 2 Switch Forward Desired SR Waveforms
• Both SR MOSFETs are controlled by primary-side

primary side PWM
• General purpose low-side gate drivers or “smart-drivers” often used
• Offers full SR control during start-up, light-load, OCP, pre-biased output
• SR g
gate drive is regulated
g and independent
p of transformer reset method
• Q3 timing adjustment similar to previous Hybrid Self-Driven example
• RC Delay also needed for Q2 SR
Control-Driven SR Timing Delays
Secondary-Side Control
SR secondary can be driven directly by PWM

Secondary
y to p
primary
yppower stage
g ppropagation
p g delay
y ((solid arrows))
• PWM to primary side gate drive and power transformer
Secondary to primary SR propagation delay (dashed arrows)
• Power stage and SR delay times are often not equal
• SR gate drive naturally leads primary MOSFET gate drive
• Timing delay normally added in this path
Control-Driven SR Timing Delays
Primary-Side Control
Primary to secondary power stage propagation delay (solid arrows)

• PWM to primary-side gate drive and power transformer
• Delay normally added in this path
Primary to secondary SR propagation delay (dashed arrows)
• PWM to pulse transformer and SR MOSFET gate driver
• Often need to advance the SR signal (impossible)
Optimal timing adjustment requires primary and secondary sensing

Control-Driven SR
Primary-Side Triggering
+
VIN LO
+
Q1a VO
R1
FAN6210
LM Q3 CO
DB D2
1 XP GND 8
D1 R2
2 XN SOUT 7
Q1b
3 SIN VDD 6
R3 Q2 R4
4 RDLY DET 5
DZ
FAN6206
1 LPC1 SR1 8
PWM
2 LPC2 GND 7
3 SN SR2 6
4 SP VDD 5
Primary Sensing
• Any single-ended
A i l d d PWM input
i t (SIN)
• Transformer reset voltage (DET)
Secondary Sensing
• Q2 drain
drain-source
so rce voltage
oltage (LPC1)
• Q3 drain-source voltage (LPC2)
Light Load (CCM)
FAN6210 Waveforms - Light Load (CCM), XP Triggered by DET
• XP rising edge triggers turn-on

turn on for each SR
• XN rising edge triggers turn-off for each SR
• XN triggered by PWM input (SIN) rising and falling edges
• XP control SR turn-on triggered
gg byy delayed
y PWM output
p (SOUT)
( )
• XP freewheeling SR turn-on normally triggered by DET (shown)
Full Load (CCM)
SIN
300ns 300ns
SOUT 100ns
Programmable delay 50ns Programmable delay
XP 700ns 700ns
50ns 50ns 50ns

300ns 300ns 300ns
XN
Gate drive for control SR Gate drive for Freewheeling SR
DET
FAN6210 Waveforms - Heavy Load (CCM), XP Triggered by XN
• XP rising edge triggers turn-on

turn on for each SR
• XN rising edge triggers turn-off for each SR
• XN triggered by PWM input (SIN) rising and falling edges
• XP control SR turn-on triggered
gg byy delayed
y PWM output
p (SOUT)
( )
• XP freewheeling SR turn-on normally triggered by DET or XN (shown)
• XP can never trigger while XN is HIGH – prevents SR cross-conduction
SR Negative Current Issues
LO
INEG
Q1
VIN PWM Q2 CO RO
CIN
IO
Forward SR Synchronous Buck

• Q2 blocks INEG when Q3 turns off (Q2 off) • Q1 drain clamped to DC source
• INEG charges SR COSS during Q3 off • Q2 VDS clamped to DC source through Q1
• BVDSS stress from switching INEG body-diode
• SR switching adjustment required (as shown) • Negative inductor current ok for VDS
Linear Predict Control (LPC)
LO
+
R1 VO
Power
Stage Q3 CO
((Primary)
y)
R2
R3 Q2 R4
FAN6206
1 LPC1 SR1 8
2 LPC2 GND 7
FAN6210 3 SN SR2 6
((XP, XN)) 4 SP VDD 5
1 1
< Ratio LPC 2 <
VO VO − 0.5V
• LPC Function is used to turn off Q3 before ILO<0A during DCM operation
• During CCM SR gate drive controlled by SP(XP) and SN(XN)
• SN signal follows PWM signal and can not turn off Q3 before ILO<0
• Both SR VDS monitored by resistor dividers
• Solves Problem of Negative SR Current
Primary-Side Triggering (DCM)
FAN6206 Waveforms - Light Load (DCM)
Advantages
• Easily implements correct primary to secondary SR timing for forward converters
• No RC timing adjustments required
• Compatible with all forward transformer reset techniques including 2 switch forward
• Can be used with any single-ended PWM controller
• G
Green mode
d ffunction
i didisables
bl ffreewheeling
h li SR gate drive
d i for
f D<10%
D 10%
• Operates in CCM and DCM
• Freewheeling SR control prevents negative current flow
Be Aware of
• SR Gate drive current limited to 0.7A/1A (source/sink)
• Use FAN3xxx series low-side ggate drivers for drivingg higher
g gate
g charge g
• Internal fixed delays result in longer body-diode conduction times at higher frequency
• For low output voltage converters SyncFET can help
Application Circuit Specifications
INPUT
I
Input
t Voltage
V lt 90VAC<V
VIN(AC)<264V
264VAC
Line Frequency 47Hz<FLINE<63Hz
PFC Output 310VDC<VBULK<380VDC
OUTPUT
Output Voltage 12VDC
Output Power 300W
Load Current 25A
Switching Frequency 65kHz
Intended Application: PC Power (Computing)
Why 65kHz Operation?
dBuV dBuV
100 100
Fundamental Fundamental
(66kHz) (100kHz)
90 90
80 80
2nd harmonic
(132kHz) 2nd harmonic
70 70 (200kHz)
60 60
EN 55022 QP
50 50
EN 55022 AV
40 40
30 30
20 20
10 10
100k 150k 200k 300k 500k 1M 100k 150k 200k 300k 500k 1M
Frequency spectrum with 66kHz operation Frequency spectrum with 100kHz operation
• Lower EMI
• Trade Off: EMI filter size versus transformer size
Application Validation Circuit
Measured Waveforms
Steady State and LPC Function
Control
SR Gate
Freewheeling
SR Gate
XP (SP)
XN (SN)
LPC
VDS Freewheeling SR
S and S
SP SN control S
SR switching
i i
LPC function during DCM operation
PWMIN
(SIN)
300ns
Freewheeling
SR G
Gate
XP, XN XP
XN
SOUT
SIN→SOUT, 300ns fixed turn-on delay SIN→SOUT, 100ns fixed turn-off delay
Measured Waveforms
SR Dead-Time, Load Transient
PWMIN
(SIN)
XP, XN XP
XN
Freewheeling 400ns
SR Gate
Control
SR Gate
FW SR↓→Control SR↑, 500ns dead-time FW SR↑→Control SR↓, 400ns dead-time
0A→10A load transient 10A→0A load transient

Measured Waveforms
Start-Up, OCP, Green Mode
SOUT
VOUT=8.8V
VOUT ZOOM
SOUT
Control SR
Freewheeling SR
SR control during start-up FW SR control during start-up
D=7.8%
PWMIN
(SIN)
XP, XN
VDS Freewheeling SR
VDS Control SR
10A→64A overload transient Green mode function enabled for D<10%

Measured Efficiency
Schottky vs SR
SR Efficiency Comparison
(115VAC Input, 12VDC Output, 300W, 12V/25A Output)
95%
Primary-Side Trigger Control-Driven SR
(FDP5800)
Schottky Rectifiers (FYP2006DN)
90%
Efficiency (%)
85%
80%
10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Output Power (%)
300W=100%
Summary
• Self-Driven SR
• Best for active clamp forward where IO(MIN) > ILO/2 (BCM)
• SR gate drive independent from primary control
• Hybrid Self-Driven SR
• Performance improvement over self
self-driven
driven SR
• Control Driven SR
• SR timing is critical
• Difficult to implement discretely
• FAN6210+FAN6206
• Simplifies SR timing
• Freewheeling SR control during DCM operation
Evaluate all SR solutions under steady state and dynamic test conditions!
Questions?
THANK YOU!
References
1. “FAN6210 — Primary-Side
y Synchronous
y Rectifier (SR)
( ) Trigger
gg Controller for Dual
Forward Converter”, Datasheet, Fairchild Semiconductor, March 2010.
2. “FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for
Dual-Forward Converter”, Datasheet, Fairchild Semiconductor, April 2010.
3 “AN
3. AN-6206
6206 — Primary-Side
Primary Side Synchronous Rectifier (SR) Trigger Solution for Dual-
Dual
Forward Converter”, Fairchild Semiconductor, April 2010.
Follow us on Twitter twitter.com/fairchildSemi
View product and company videos, listen to podcasts and comment on our blog @ www.fairchildsemi.com/engineeringconnections
Visit us on Facebook @ www.facebook.com/FairchildSemiconductor

Synchronous Rectification For Forward Converters PDF

Enviado por

Dados do documento

Título original

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

Synchronous Rectification For Forward Converters PDF

Enviado por

Direitos autorais:

Formatos disponíveis

Synchronous Rectification for Forward

• Synchronous Rectifier (SR) Characteristics

• Forward Converter Transformer Reset Techniques

• Forward Converter SR Gate Drive

• Primary-Side Trigger + Linear Predict Control (LPC)

Rectifier Diode Efficiency

n = Number parallel MOSFETs

• Operates in first quadrant (Q1) only

η=86.84%, (VF=0.5V, VO=3.3V)

η=97.06%, (VF=0.1V, VO=3.3V)

• >10% improvement, BUT…

(a) SR MOSFET (b) Schottky Rectifier

0 0.2 0.4 0.6 0.8 1

• D1 operates in first quadrant only – no negative current flow during DCM

CGD (a) Ideal Diode – No Reverse Recovery

SR body-diode has high VF and long tRR!

Parasitic Inductance Limitation

FDMS7670 vs FDMS7670S SyncFET™

(a) Forward Converter SR (b) Single-Ended Transformer Hysteresis

Forward Converter with SR

Reset Winding RCD Reset Resonant Reset Active Clamp Reset

Reset Method Impacts Self-Driven SR Gate Drive

RCD Forward Converter

Full control of both SR MOSFETs only achievable using Control-Driven

• Both SR MOSFETs are controlled by primary-side

SR secondary can be driven directly by PWM

Primary to secondary power stage propagation delay (solid arrows)

Optimal timing adjustment requires primary and secondary sensing

FAN6210 Waveforms - Light Load (CCM), XP Triggered by DET

• XP rising edge triggers turn-on

Programmable delay 50ns Programmable delay

50ns 50ns 50ns

Gate drive for control SR Gate drive for Freewheeling SR

FAN6210 Waveforms - Heavy Load (CCM), XP Triggered by XN

• XP rising edge triggers turn-on

Forward SR Synchronous Buck

FAN6206 Waveforms - Light Load (DCM)

Intended Application: PC Power (Computing)

LPC function during DCM operation

FW SR↓→Control SR↑, 500ns dead-time FW SR↑→Control SR↓, 400ns dead-time

0A→10A load transient 10A→0A load transient

SR control during start-up FW SR control during start-up

10A→64A overload transient Green mode function enabled for D<10%

Visit us on Facebook @ www.facebook.com/FairchildSemiconductor

Você também pode gostar