Bahcesehir University

CMPE2007 DIGITAL DESIGN LAB ASSIGNMENT 9

TITLE: Seconds Counter with Seven Segment Display

DESCRIPTION:
This week we are going to create a counter that will display on seven segment display. Each second counter will
go up by one until it hits 59. After one more second, it will reset to 0. To do this we are going to make use of
module we designed last week to display the digits of our counter on the seven segment display.

1. We may first start off with thinking what ports will be for our top-level module, because we won't probably
need any other module. Since we are going to design a sequential logic circuit, we will certainly need a clock
signal. We might want to reset our counter at any time, so we would need to get an input for it. The outputs are
seven segment related, remember, 8-bits sseg value and 4-bits anode. Let's call our module counter_with_sseg.

module counter_with_sseg(clk, rst, sseg, an);

input clk, rst;

output [7:0] sseg;
output [3:0] an;
….

endmodule

2. Just as we did in last two weeks, we need to do things periodically. Each second we should be able to change
the digits of our counter. Remember the clock frequency was 100MHz, so if we count 100x106 clocks, we would
effectively be waiting for 1 second. Our counter needs to be able to count up to 100,000,00010 = 101 1111
0101 1110 0001 0000 00002, so we need 27-bits register for it .

….
reg [29:0] inc_counter;

parameter COUNTER_MAX = 100000000; //100x10^6 clocks = 1second (f = 100MHz)

….
3. This week we will approach the problem differently by separating waiting code from state switching. To do
this we will have a 1-bit register to tell when to switch state and there will be an always block sensitive to it in
which we will change the state. That register will be set in another always block that is sensitive to clock signal
which is responsible from counting clocks.

….
reg increment;
….

always@ (posedge clk) begin

if (inc_counter == COUNTER_MAX) begin

inc_counter = 1;

increment = 1;

end

else begin

inc_counter = inc_counter + 1;

increment = 0;

end

end

….
4. Let's not use the design we used to divide a number into its base 10 digits. Instead, we can define digits
separately by defining different 4-bits registers. Then we can come up with a code to increment it. Once we
have the digits separately, we can just feed them into sseg_disp module to obtain sseg and an outputs. To
increment the counter, we will write an always block sensitive to rising edge of increment register value, in that
code, we first need to check the boundary cases. Ones digit should not be more than 9, so if it is 9, instead of
incrementing it, we need to reset it to 0 and try to increment tens digit. But since the ones digit has also a
boundary (5), if it is hit we need to reset it too.

….

reg [3:0] cdigit1, cdigit0;

sseg_disp(clk, 1, 0, 0, cdigit1, cdigit0, sseg, an);

initial begin
inc_counter = 0;

increment = 0;

cdigit0 = 0;

cdigit1 = 0;

end

always@ (posedge increment) begin

if (cdigit0 == 9) begin

if (cdigit1 == 5) begin

cdigit1 = 0;

end

else begin

cdigit1 = cdigit1 + 1;

end

cdigit0 = 0;

end

else begin

cdigit0 = cdigit0 + 1;

end

end

….
APPENDIX

You can find the contents ucf file (counter_with_sseg.ucf) necessary for counter_with_sseg module:

NET "rst" LOC = "T5";

NET "an[3]" LOC = "P17";

NET "an[2]" LOC = "P18";
NET "an[1]" LOC = "N15";
NET "an[0]" LOC = "N16";

NET "sseg[7]" LOC = "T17";

NET "sseg[6]" LOC = "T18";
NET "sseg[5]" LOC = "U17";
NET "sseg[4]" LOC = "U18";
NET "sseg[3]" LOC = "M14";
NET "sseg[2]" LOC = "N14";
NET "sseg[1]" LOC = "L14";
NET "sseg[0]" LOC = "M13";

NET "clk" LOC = "V10";