Code: 9A04306 SS

B.Tech II Year II Semester (R09) Supplementary Examinations January/February 2014

DIGITAL LOGIC DESIGN
(Computer Science and Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE questions
All questions carry equal marks

*****
1 (a) Add the following using the 2’s complement method:
(i) and
(ii) and
(b) Write a short note on weighted and non-weighted codes.
(c) Express 324 in gray code form.

2 (a) If , then prove that .

(b) Find the complement of the expression
(c) Obtain the canonical product of sum expression of

3 (a) Obtain minimal sop expression for the function:

(b) Realize the following function using multilevel NAND-NAND network:

.

4 (a) Draw the logic diagram of 4-bit carry look ahead adder and explain.
(b) What is meant by a decoder? Explain BCD to decimal decoder.

5 (a) Explain the operation of a master - slave flip flop and show how the race around
condition is eliminated in it.
(b) Differentiate combinational and sequential circuits.
(c) What do you understand by state assignment?

6 (a) What is a ripple counter? Draw the logic diagram of a 4-bit binary ripple counter using
flip flops that trigger on the positive edge transition. Explain.
(b) What is a shift register? Name and explain different types of shift registers.

7 (a) Draw the basic circuit of a ROM cell and explain its working.
(b) What is a PLD? What are the steps used for implementing combinational circuit using
PLA?

8 (a) Design an asynchronous sequential circuit that has two inputs and one output .
The output if changes from 0 to 1, if changes from 0 to 1, and
otherwise. Realize the circuit using D flip flops.
(b) Explain the method to eliminate static hazard in an asynchronous circuit with an
example.

*****