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Design of Low-Voltage Low-Dropout Regulator with Wide-Band High-PSR

Characteristic

Conference Paper · November 2006

DOI: 10.1109/ICSICT.2006.306415 · Source: IEEE Xplore

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 Design of Low-Voltage Low-Dropout Regulator with
Wide-Band High-PSR Characteristic
Liang-Guo Shen, Zu-Shu Yan*, Xing Zhang, Member, IEEE, Yuan-Fu Zhao*, Senior Member, IEEE, and Tie-Jun Lu*
Institute of Microelectronics, Peking University, Shenzhen Graduate School, China
*Beijing Microelectronics Technology Institute, Beijing, China
E-mail: slg@ime.pku.edu.cn and *yanzushu@yahoo.com.cn

Abstract—Utilizing a novel unit-gain compensation cell

(UGCC) to perform frequency compensation and power
supply rejection (PSR) enhancement, a low-voltage high-
PSR low-dropout regulator(LDO) is presented in this paper.
The proposed UGCC, consisting of a 1pF on-chip capacitor
and six transistors, effectively overcomes the drawbacks
that exist in the conventional compensation schemes by
generating an internal low-frequency zero. A LDO that
adopts this new structure is implemented and simulated
using a standard 0.18-μm CMOS process. Simulation
results show that the circuit can work properly when the
supply voltage is as low as 1.2V. The PSR over the
frequency range of dc to 1GHz is better than -40dB in all
cases at 1.2V supply voltage. The dropout voltage is 200mV
when the load current is 100mA. Therefore, it is well suited Fig. 1. The structure of the proposed UGCC
for low-voltage ripple-sensitive applications.

1. Introduction
Low-dropout regulators (LDOs) are widely used in RF
communication systems and battery-powered equipments
[1]-[5]. One of the issues in LDO design is to maintain
the system stability. As the supply voltage shrinks, the
stability problem of LDOs becomes more challenging.
In the conventional equivalent series resistance (ESR)
compensation technique, an off-chip capacitor with high
ESR is needed to generate a low-frequency zero [1]. This
scheme introduces large overshoots and restricts the Fig. 2 The structure of the proposed LDO with UGCC
usage of ceramic capacitors.
An internal zero was introduced in [2]. Using the A common practice of improving the PSR is to place
cascode current mirror stages in implementing Gm(s), the RC filter between the supply and the LDO, while
this compensation method is not suitable for low voltage using two linear regulators in series is another solution
applications. A pole-zero pair with the frequency of the [5]. They will consume extra power and require more
zero lower than that of the pole was added in [3]. voltage headroom. The method that cascode the NMOS
Unfortunately, the requirements of this scheme can device to the linear regulator was presented in [6], [7].
hardly be fulfilled under the low voltage environment. However, the charge pump, low-pass RC filter with large
A compensation scheme that can be used in low resistor and capacitor are needed. Therefore, the circuit
voltage LDO design was presented [4]. However, the complexity, chip area and power consumption increase.
Miller compensation technique used in this system is not Aiming at solving the problems that exist in the
effective for LDO design. low-voltage high-PSR LDO design, a novel topology
Powering the RF circuits, the output voltages of the based on the unit-gain compensation cell (UGCC) is
LDOs must be especially clean. The supply that powers presented in this paper.
LDOs usually includes wideband ac ripple superimposed
on the dc value, which makes the design of LDOs that 2. The proposed UGCC and LDO
have high power-supply rejection (PSR) over a wide
frequency range extremely critical for high system The structures of the proposed UGCC and LDO are
performance [5]-[6]. given by Fig.1, Fig.2, respectively. The whole system

1-4244-0161-5/06/$20.00 ©2006 IEEE

contains the PMOS pass transistor, the UGCC, the
feedback resistors Rf1 and Rf2, the off-chip capacitor
and the error amplifier. In order to obtain high dc gain
and low output impedance under low-voltage condition,
the error amplifier consists of gm1 and gm2 gain stage.
The transfer function derived from the Fig.1 can be
expressed by
vo (s) gm R par 1 RCCC s 

vi (s) § § R ·
¨ ¨ 1 C ¸C
·
¸ (1)
¨ ¨ R par ¸ C RCCCC par ¸
1 gmRpar 
¨ 1 ©
gm
¹ s
gm
s ¸
2
¨ ¸
¨¨ ¸¸
© ¹ Fig. 3 The circuit implementation of the proposed UGCC

In deriving (1), the approximation of CC >> Cpar has

been made. The Rpar and Cpar are parasitic elements exist
in the UGCC. The low-frequency zero is given by
Z ZC 1 / RC CC (2)
while the dc gain of the UGCC is A0 = gmRpar /(1+gmRpar).
In general, gmRpar>>1, therefore the dc gain is close to 1,
which gives the name of UGCC.
If the condition of (1+RC/Rpar)2CC >> gmRCCpar can be
fulfilled, the two poles ȦPC1 and ȦPC2 of the transfer
function are widely separated and given by
gm (3)
Z PC1
¨1  RC ¸CC
§ ·
¨ R ¸ Fig. 4 The circuit diagram of the proposed LDO with UGCC
© par ¹

¨1  RC ¸
§ · pole ȦPC1 and zero ȦESR. Note that ȦP3 is function as the
¨ R ¸ dominate pole of the LDO.
Z PC 2 © par ¹
(4) The pole ȦPC1 usually occurs at the frequency of
RC C par
several megahertz, which means that, the off-chip
The pole ȦPC2can be ignored because it is located at a capacitor with much smaller ESR can be used to generate
much higher frequency than the unit-gain frequency the high-frequency zero ȦESR. The low ESR value, not
(UGF). Therefore, the proposed LDO has four poles and only reduces the overshoots and undershoots during load
two zeros that need to be considered during frequency transient response greatly, but also facilitates the usage
compensation. Besides the zero ȦZC and pole ȦPC1 of the ceramic capacitors, which are compact and cheap
mentioned above, the others are given by compared with the tantalum alternatives.
Z P1 1 / R1C1 (5) The pole ȦP1 should be taken into consideration during
Z P 2 1 / R2C 2 (6) stability analysis. If the desired phase margin is 60o, the
frequency of the pole ȦP1 should be twice as high as the
Z P 3 1 / R3COUT (7) UGF. Consisting of two gain stages, the error amplifier
Z ESR 1 / RESR COUT (8) can place ȦP1 at a high enough frequency. Thus, the loop
where R(1-2), C(1-2) are the output resistance and the stability can be maintained even in the worst case (the
lumped parasitic capacitance of the first and second gain supply voltage and load current are at their maximum
stages, respectively, while R3 is the lumped resistance of values, the pass transistor operates from linear region to
the output node, including the output resistance rds of the saturation region).
pass device, the feedback resistances Rf1, Rf2, and the The UGCC, functioning as a lead phase compensation
load impedance RL. module, has the ability of enhancing the PSR over
In the proposed compensation scheme, two pole-zero wide-spectrum, especially at the frequency around the
cancellations exist: the first cancellation is achieved by UGF. In addition, the high dc open-loop gain and UGF,
the low-frequency zero ȦZC and pole ȦP2, while the besides the low ESR off-chip capacitor, also play a role
second cancellation is realized by the high-frequency in improving the PSR characteristic of the whole system.
 3. Circuit implementation and simulation results
Fig. 3 presents the circuit diagram of the UGCC. It is
composed of a differential pair (M1 and M2) with active
load (M3 and M4), the compensation capacitor CC (with
the value of 1pF) and the transistor M5. Note that in
order to reduce chip area and noise, RC is replaced by
active device M5, which operates in deep triode region.
The circuit implementation of the LDO is illustrated in
Fig.4. The error amplifier, with the gain of the second
stage higher than that of the first stage, consists of
transistors M10-M14 and M20-M21. In addition, a
sub1-V CMOS bandgap voltage reference is used [8].
The LDO was simulated using HSPICE and a standard
BSIM3V3.2 0.18μm CMOS model from Semiconductor
Manufacturing International Corporation (SMIC). The
designed output voltage is 1.0V, Vref = 0.6V. This LDO
is capable of operating from 1.2V to 1.8V. The dropout
voltage of 200mV is achieved at the 100mA maximum
load current. The COUT and the RESR are 10μF and 10mȍ,
respectively. The ground current consumed by the LDO
is 20.5μA, in which 4μA is consumed by UGCC.
The load transient response and PSR characteristics of
the proposed LDO are compared with the ESR compen-
sation LDO, in which the UGCC is removed, and the
RESR is increased from 10mȍ to 200mȍ.
Fig. 5. Frequency responses of the proposed LDO at Vdd = 1.2V.
The load current is 1, 34, 67 and 100 mA, respectively.
Fig. 6. Comparison of PSR between LDOs with and without UGCC
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A. Frequency response
Fig. 5 demonstrates the frequency response curves of
the proposed LDO at Vdd = 1.2V. The results show that
the UGF is in the range of 0.43 ~ 3.77MHz, which is
much higher than the conventional LDO, while the phase
margin is better than 60o for all cases.
B. Load transient response
When the load current is changed between 0mA and
100mA in 0.1μs, there is significant overshoots (12.4mV)
and undershoots (14mV) in the ESR compensation LDO,
while the corresponding values in the proposed LDO are
1.2mV and 0.6mV, respectively.
C. PSR performance
The PSR characteristics of the proposed LDO and the
ESR compensation LDO (without UGCC) are given by
Fig. 6. The high PSR performance of the proposed LDO
is retained up to 1GHz. Moreover, compared with the
LDO without UGCC, a remarkable PSR improvement of
20dB at the frequency above several hundred kilohertz
can be seen clearly in the curves of the proposed LDO.
4. Conclusions
This paper presents a novel structure that can be used
in low-voltage high-PSR LDO design. This structure
bases on the proposed UGCC. The detailed description
of the UGCC and the LDO has been given. The circuit
realization and simulation results show that this LDO can
realize low-voltage operation and reduce the overshoots
and undershoots that occur in the ESR compensation
LDO efficiently. It should be spoken with emphasis that
this LDO achieves super PSR characteristic, which is
better than -40dB from dc to 1GHz in all cases when the
supply voltage is 1.2V. Therefore, the proposed structure
offers a good choice for the design of high performance
power supply circuitry.
References
[1] G. A. Rincon-Mora and P. E. Allen, IEEE J. Solid-
State Circuits, 33, p.36 (1998)
[2] C. K. Chava and J. Silva-Martinez, IEEE Trans.
Circuit and Systems I, 51, p.1041 (2004)
[3] C. D. Stanescu and R. H. Iacob, U.S. Patent 6518
737, (2003)
[4] K. N. Leung and P. K. T. Mok, IEEE J. Solid-State
Circuits, 38, p.1691 (2003)
[5] Dallas Semiconductor/Maxim, Appl. Note 883,
http://www.maxim-ic.com/appnotes.cfm/appnote_nu
mber/883
[6] V. Gupta and G. A. Rincon-Mora, IEEE Internation-
al Symposium on Circuits and Systems, p.4245
(2005).
[7] C. Lee, K. McClellan and J. Choma Jr., IEEE J.
Solid-State Circuits, 36, p.1453 (2001)
[8] K. N. Leung and P. K. T. Mok, IEEE J. Solid-State
Circuits, 37, p.526 (2002)