How to predict stability in linear regulators

Sudhansu Sekhar Mishra, Tarun Rehani, and Nishant Thakur - November 20, 2012

A regulator is a closed-loop feedback system. For the LDO to be stable, the phase margin must be
positive. In other words, at unity gain crossover frequency of the gain curve, the phase of the system
should be positive. This can be measured using a vector network analyzer. Many voltage regulators
are of the fixed output variety and include the voltage divider internal to the regulator. There are
definite advantages to this approach, which allows active voltage trimming and also minimizes the
physical space required. A disadvantage to this approach is that the voltage divider is not available
for gain-phase or “Bode” measurement. This leads many to believe that it is not possible (or even
necessary) to evaluate the stability of such a regulator. This is simply not true.

An empirical observation can be made to understand the relative stability of the feedback system
and leverage that understanding to monitor low voltage detects and the transient performance of the
system. It is important to keep the voltage regulator stable in order to make sure that the output
voltage of the regulator does not go above and below specified limits and does not break into
oscillations. SPICE simulation can be used to easily predict stability of the voltage regulator in both
the time and frequency domains, but it is rather difficult to predict post-silicon on a validation board
where only transient simulations can be done. Is it not possible to know exactly how much phase
margin a voltage regulator loop has by merely looking at transient responses. However, the
transient response can still be used to test whether the regulator is stable or not by observing
ringing behavior at its output for a transient load current. It is necessary to pay attention and plan
for necessary pins and circuit elements on board in order to apply different transient load currents
at the regulator output to test its stability.

Types of regulators
Regulators can be built on the premise of a linear or non-linear regulator, depending on the
underlying principles on which they work. The basic types are linear regulators (low drop-out
regulators; LDOs) and non-linear regulators (also known as switching regulators, or switch-mode
power supplies; SMPS). LDOs are used extensively because of their design simplicity, low footprint
on a silicon wafer, and low noise whereas SMPS cater to higher current needs and higher efficiency.
 Figure 1. LDO block diagram

Figure 2. LDO block diagram(simplified diagram using a SPICE simulator)

The principle of an LDO is simple. A part of the output is fed back to the error amplifier through a
resistor divider network, which makes the regulator function in a closed loop. That fraction of the
output is compared with the reference voltage from the band gap reference generator. By
controlling the current through the pass transistor, the output voltage is controlled. Hence, a steady
voltage is attained at VOUT. The bypass capacitor ensures that if any fast transients are seen on the
load, it is able to supply the same until the feedback loop compensates. This ensures there are no
ripples in the load transients.

Stability in the frequency domain

A regulator is a closed-loop feedback system. So, for the LDO to be stable, the phase margin must be
positive. In other words, at unity gain crossover frequency of the gain curve, the phase of the system
should be positive, non regenerative i.e. neither 0 nor multiple of 360. The LDO could be modeled as
a control system with the error amplifier, pass transistor, and feedback resistor forming a closed-
loop system. The output impedance model of the LDO depends on the bypass capacitor, bulk/stability
capacitor, the equivalent series resistance (ESR) of the bulk capacitor, output impedance of the
error amplifier, and parasitic capacitance of the trace to the base of the pass transistor. This model
forms three poles and one zero. The location of poles and zeros can be calculated as shown below.
(The Laplace transform could be used for calculations, and the following impedances will be in
parallel.)

A typical pole zero location plot is shown in Figure 3. P1 is dominant pole and it depends on load
current values (rout =1/(K*Drain current) where K is channel length modulation parameter. As load
current increases, Rout reduces and the pole moves to higher frequencies. The relative location of
P1, P2, and Z2 determines the phase margin of the system. P3 is usually at very high frequency
outside the unity-gain bandwidth of the system. A high value of RESR helps to bring Z1 near P2 and
hence improves phase margin while also degrading the transient response (as explained in next
section).

Figure 3 Gain Plot of arbitrary LDO depicting the position of poles and zeros
>>Stability concept in time domain Title-1
Stability concept in time domain
The presence of the bulk capacitor and bypass capacitor is essential for the transient response
stabilization of the LDO. There may be sharp changes in the load current, and these capacitors
ensure that the regulator’s output has minimal undershoots and overshoots. The voltage dips are
caused by a sudden load switch from minimum to maximum. The bulk capacitor and bypass
capacitor provide the transient charge (as it has a higher capacitance) to ward off this undershoot.

If a high transient load current step Δi is applied, the pass transistor will take some time (dependent
on system bandwidth) before responding to it. So, in the meantime, current is supplied by the bulk
capacitor. Hence a voltage drop will appear as given by

Transient voltage drop= Δi*RESR

A bypass capacitor can be used to reduce the effect of this IR drop. Because the bypass capacitor
supplies the majority of fast transient current, the IR drop can be reduced.

The stability is affected by the magnitudes of the bulk capacitor and bypass capacitor. The bypass
capacitance should be much smaller than the bulk capacitance. For example, in Figure 3, the bypass
capacitance is 7uF and bulk capacitance is 10uF. Ringing can be observed as the phase margin is
around 25o. In Figure 4, the bypass capacitance has been changed to 700nF and the phase margin
improved to 45o. There is less ringing observed on the regulator’s output waveform.

Figure 4: Unstable LDO ringing observed on LDO out

 Figure 5: Stable LDO no ringing observed on LDO out

Figure 6: Ringing as a function of Phase Margin

Figure 5 depicts the ringing observed due to load transients as a function of phase margin. As the
phase margin increases, the number of bumps introduced due to sudden load transients is decreased
and vanishes for PM greater than 54o. This is an arbitrary response for a simulated LDO and
responses to load transient stimuli may change from design to design. The relation between the PM
and quality factor (indicative of ringing) is empirically given as
 Phase Margin = 50.36 X Q -0.907
Hence, if an LDO’s output response shows oscillations, it indicates that the quality factor is high and
phase margin is low, and vice versa.

Stability tests in lab

The stability testing can be done in many different ways, such as using a network analyzer for the
phase margin measurements, but we would limit our focus to measuring the relative stability using
load switching. This means we would need to have a switch connected to the regulator’s output that
would change the load current from minimum to maximum (and vice versa) based on some control
signal and enable us to record the regulator’s output on the DPO. If we fail to notice any
undershoots and overshoots on the regulator’s output during the load transitions, we could be
reasonably satisfied that the phase margin is high. The load transitions should be fast in the range of
nanoseconds.

Figure 7: Schematic diagram for LDO stability tests

Board Design
The following are board design considerations for regulators:

1. The stability capacitors should have small ESRs that give the best compromise between phase
margin and transient IR drop. Tantalum capacitors are well suited for use as stability caps as they
have small ESR.
2. The stability caps should be placed as close to the pass transistor end of device as possible and
the routing resistance should be minimal.
3. The decoupling (this is the same as bypass cap) capacitors should be of MLCC type as they have
high tolerance and voltage ratings.
4. The bypass capacitors should be placed as close to the load end as possible to provide a low-
impedance path for high frequency noise isolation between the different loads derived from the
same source.

Related Content

● Fundamentals of Linear Regulators

● Overview of LDO Linear Regulators
● Taming Linear Regulator Inrush Currents
About the Authors
Sudhansu Sekhar Mishra
Sudhansu is a analog validation engineer at Freescale Semiconductors India Pvt. Ltd. He has
characterized power management units and data converters in various automotive and industrial
SOCs.

Tarun Rehani
Tarun Rehani is a staff analog validation engineer in Freescale Semiconductor Pvt. Ltd., India. He
has 9 +years of analog validation for automotive and consumer products. He has worked on various
type of ADCs(sigma-delta, SAR, time interleaved, Cyclic ADCs), power management unit (LDOs and
SMPS), CMOS crystal oscillators, etc. He has various articles published on regulators on various
technical sites.

Nishant Thakur
Nishant is a design engineer at Freescale Semiconductors India Pvt. Ltd. He has worked on design
of various LDOs and other analog blocks.