A fully-differential Operational Amplifier using a
new Chopping Technique and Low-Voltage Input
Devices
Timo Mai∗ , Konstantin Schmid† , Jürgen Röber† , Amelie Hagelauer∗ and Robert Weigel∗
∗ Lehrstuhl für Technische Elektronik, Cauerstr. 9, 91058 Erlangen,
Friedrich-Alexander University, Germany, Email: timo.mai@fau.de
† eesy-ic GmbH, Frauenweiherstraße 15, 91058 Erlangen, Germany
Abstract—A fully differential CMOS operational amplifier is
presented. It uses a new chopping technique that works without
the use of switching transistors in the high gain path, resulting
in high noise performance and low offset. It is designed in a
low-cost 180 nm process with a 5 V supply voltage. In critical
places, such as the differential pair, 1.8 V-devices are used, as
they provide much better matching and noise performance, and
at the same time have lower parasitics. They are protected from
breakdown conditions by several circuit techniques. Some of
them are described below. The operational amplifier is used in a
differential programmable gain amplifier for processing signals
of up to 50 kHz bandwith with a SINAD > 100 dB, making it
suitable as a preamplifier for 18-Bit ADCs.
Index Terms—chopping, operational amplifier, gain boosting,
1/f-noise, offset, programmable gain amplifier.
I. I NTRODUCTION
Every precision analog-to-digital converter has two differ-
ential input pins, because differential signals are more robust
against supply voltage noise and have a higher signal swing
than single-ended ones. Many applications use single-ended
signal processing for simplicity, or because the used sensor
has only a single-ended output. In this case, a single-ended-
to-differential conversion should be done to drive an ADC
with differential input. This can be achieved with a typical
differential amplifier, as seen in Fig.1, where the negative
input is tied to ground. To achieve a reasonable performance,
R2
R1
Vinn − Vop
+
Vout,cm
−
Vinp + Von
R1
R2
Fig. 1. Typical differential amplifier
the inherent imperfections of the opamp, especially offset and
noise, must be supressed, e.g. by chopping. Usually this is
implemented with CMOS switches [6], [2]. In this work, an
alternative approach is presented, that works without the use
of additional transistors in the high gain path.
978-1-5386-1911-7/17/$31.00 ©2017 IEEE
The paper is organized as follows: in the second section
the overall structure of the Opamp and the chopping scheme
are explained. The third section addresses the input stage and
the circuit techniques, which protect the low-voltage input
transistors. In the fourth section the high gain folded cascode
stage is shown, which utilizes the new chopping technique. In
section V some simulation results are shown, discussed and
compared to similar works. Finally, a conclusion is drawn.
II. O PAMP STRUCTURE AND CHOPPING SCHEME
The Opamp’s structure is shown in Fig. 2. The two input
voltages Vin1 and Vin2 pass a clocked analog multiplexer and
thus are mixed to the chopping frequency. The result is routed
to the input gm stage, which transforms the input voltage
difference into a current difference. The two currents form
the input signal for the two high gain stages which convert
them back into the voltage domain. The output of each gain
stage is alternately connected to one of the output stages. Thus
the signal is mixed down, and the 1/f -noise is mixed up to
the chopping frequency.
There are two typical ways to implement this, they are
shown in Fig. 3. In the voltage mode realization, the gate
of the output device is connected over a switch to one of
the high-impedance nodes. The switches can be very small,
as they don’t need to carry much current. On the downside,
the voltages on the two high-impedance nodes are typically
different, so after switching there will occur large spikes from
the settling of the two nodes. In the current mode realization,
the currents from the two current sources are alternately
connected to the two cascodes. The two operating points
differ significantly less from each other than in the voltage
mode realization. Also, the charge injection spikes occur at
a low impedance node and hence should settle faster. The
main drawback is the additional transistor in the signal path,
increasing parasitics and routing effort and decreasing voltage
headroom due to its parasitic on-resistance. In this paper, a
new current mode realization is shown, that does not need
additional transistors in the signal path. It is described in
section IV.
74
 Vin1 Vin2

out1 out1
Class out2 high input high out2 Class
AB gain gm gain AB
Vout1 stage 2 out3 stage 2 stage stage 1 out3 stage 1 Vout2
out4 out4

Fig. 2. Block diagramm of the Opamp. Each high gain stage controls Class-AB stage 1 and 2 alternately

input pair [8],[1]. Thus, a large transconductance is needed.

To obtain this at a reasonable power consumption, the W L -ratio
must be large.
On the other hand, huge input devices have a huge input
capacitance. In Fig. 1, this parasitic input capacitance occurs
at the operational amplifier’s input, forming a parasitic pole,
or low-pass filter, in the feedback loop with R2 . This parasitic
pole must be located well beyond the closed-loop bandwidth,
otherwise it will noticeably decrease the overall phase margin.
Fig. 3. The two typical ways to realize chopping: current mode (left) and
This builds a constraint for the product R2 · Cg,in .
voltage mode chopping (right). The cascodes in the current mode approach As lowering the value of R2 considerably increases power
are not absolutely necessary [4],[5],[7]. consumption, it is necessary to push the input capacitance
below a certain level while keeping the WL -ratio above a certain
Is1 level. This way, a minimum of distortion and maximum noise
performance can be achieved for a given current consumption.
Typically, this problem is addressed by using capacitors in
Ib Rb
parallel to R2 [9]. Then the circuit acts like an integrator,
Vcs or low-pass filter, for higher frequencies. This has a positive
Min1 Min2
Vin1 Vin2 effect on stability, because a low-pass filter has a slow step
Vin2 Vin1 response, and the parasitic pole simply does not occur at those
Rds lower frequencies. On the downside, the slower overall oper-
ation of the circuit causes higher distortions when processing
Is2
to gain stage 1 to gain stage 2
fast signals.
Next, the operation of the input stage is explained. Vcs is
Mb1 Mb2 roughly one threshold voltage above the input common mode
Vf Vf p level. The current Is1 flows through the resistor Rds , creating a
constant voltage drop and Vf is following Vcs . The transistors
1 1
2 Ib Is1 + Is2 2 Ib Mb1 and Mb2 have the same current densities and thus the
same gate-source voltage. Therefore, Vf p follows the input
voltage keeping the drain-source voltage of the input devices
Fig. 4. Schematic of the input stage with regulation of the drain-source voltage constant at
of the differential pair. The folding point Vf p follows the input voltage.
Vds = Rds Is1 − Vgs,b1 + Vgs,b2 ≈ Rds Is1 . (1)
III. I NPUT S TAGE WITH FOLDED CASCODE
Fig. 4 shows the schematic of the input stage. The short- Vf p will be at the lowest possible level for the minimum input
channel low-voltage devices Min1 and Min2 form the differen- voltage (0 V). To ensure proper functionality, it still must be
tial pair. At first it is explained why they should be low-voltage high enough to keep the current sources 12 Ib in saturation.
devices. Vgs,M in mainly depends on Vth,M in , which is increased by
In simplified terms, an opamp’s overall noise contribution is utilizing the body effect, keeping the bulk-source voltage
roughly inversely proportional to the transconductance of the constant at Rb Is1 .

75
 The presented input stage is capable of protecting high- Vdd
performance low-voltage devices, as every voltage at their Mp1
Mp3
pins is regulated relatively to the input voltage. Every process
with devices for different supply voltages can benefit from this φp2 Mp9
approach and optimize the ratio transconductance/bandwidth
to power consumtion. Vreg1

IV. HIGH GAIN STAGE φp1 Mp8

The structure of the high gain stage can be seen in Fig. 5.

φp2
It works as follows. The current signal from the input stage
controls the current source Mp3 . The output pins out1 and −
Vgb V1
out3 are connected to one of the output stages, the pins out2 A1 Mp4
Mp5
+
and out4 to the other one. The second gain stage is connected
the other way around, out2 and out4 are connected to the first Mp7 V2
Mp2
Mp6
output stage and out1 and out3 to the second one. Considering Vb1
the chopping control signals φp1 and φn1 at Vdd , and φp2 and φp1
φn2 at ground, the amplifier A1 regulates the cascode Mp4 , out1 out2

while Mp6 is shut off. At the same time the amplifier A2

out3 out4
regulates the cascode Mn1 , while Mn2 is shut off. Thus, the

f rom input stage

φn2
first gain stage drives the first output stage through out1 and
+
out3, and the second gain stage drives the second output stage Vb2
V3
through out1 and out3. In the other chopping state, the input A2
− Mn4 Mn2
switches in Fig. 4 are toggled, and the cascodes Mp6 and Mn2
are regulated by A1 /A2 . Then the first gain stage drives the
Mn3 V4
second output stage, and the second gain stage drives the first Mn1
output stage.
In summary, the output of the current sources Mp3 and φn1
Ib
2 gets alternately routed to one of the two output stages φn2 Mn5
using two gain boosted cascodes each. One of them is always
Vreg2
switched off. That way, no additional switching transistor is
necessary.
Ib
φn1 Mn6 2
common−
mode
V. S IMULATION R ESULTS f eedback
In this section, some simulation results are presented and
discussed. The opamp is connected as shown in Fig. 1, thereby Fig. 5. Schematic of the high gain stage. Two instances of this circuit are
the differential gain is set to unity, which is the most critical connected to the input stage.
case for stability. The amplifier’s input-referred offset voltage
is artificially set to 10 mV, the chopping frequency is set to caused by the cascodes gate capacitance, which needs to be
500 kHz. charged from Vdd to Vgb .
The first simulation result can be seen in Fig. 6. A constant The second simulation result is shown in Fig. 7. It shows
input signal of ΔVin = 1 V is applied. In the ideal case, this two simulations of the output noise spectral density, with
should also be seen at the output, as the differential gain is and without chopping. The 1/f-noise, and thus the offset, is
set to one. The actual output signal ΔVout alternates between modulated to the chopping frequency fchop . On the other hand,
0.98 V and 1.02 V. At first this might seem suspicious, as the the white noise is modulated to DC and the frequency range
offset voltage is only 10 mV. Assume the inputs in Fig. 1 of interest. A very small amount of 1/f-noise is generated in
are both at 0 V. Caused by the opamp, which has an offset the output stages and added to the white noise, because the
of 10 mV, it forces the voltage difference at its inputs to be output stages are not chopped. Note that a significant part of
10 mV. If R1 and R2 have the same value, the output voltage the output noise is generated by the feedback resistors.
difference must be 20 mV. The output signal is filtered by The third simulation result is shown in Fig. 8. It shows the
a first-order low-pass filter with 100 kHz cutoff frequency frequency response of the Opamp and the gain plots of the
(ΔVout,lpf ). two gain boost amplifiers A1 and A2 (Fig. 5). It can be seen
The voltages in the upper plot refer to Fig. 5. It shows that, for the nominal case, the DC gain of the Opamp exeeds
the transient behavior of the gain booster’s output voltage and 140 dB, while the phase margin is 86◦ at 72 MHz. Also, the
those at the gates of the cascodes Mp4 and Mp6 . It shows the GBW of the gain boost amplifiers is higher than the Opamp’s,
gate voltages being alternately switched between Vdd and Vgb . which is essential for a good exponential settling, especially
The spikes in Vgb , that occur at every switching operation, are in unity-gain feedback.

76
 V TABLE I
T HE OPAMP ’ S SIMULATED WORST- CASE PARAMETER IN COMPARISON TO
5 V1 SIMILAR WORKS
V2
parameter this work [2] [3] [10] @5 V
Vgb
t.-range / ◦ C -40 - 125 -40 - 125 -40 - 125 -40 - 85
4.5 Vdd / V 5 ± 10% 2.1 - 5.5 1.8 - 5.5 4.5-12
Isupply / mA 7 1.4 0.017 17
Vin / V 0. . . Vdd -1 0-Vdd 0-Vdd 1.15-3.85
4
Vcm,out / V 0.8 . . . 2.7 s.-ended s.-ended 0.55. . .Vdd -1.3
DC gain / dB 106 136 172 68
94 94.5 95 95.5 96 96.5 97
GBW / MHz 43 4 0.35 135
1.02 ΔVin phase margin 60◦ 63◦ ≈ 60◦ -/-
ΔVout noise / √nV 3.5 5.6 55 4.5
Hz
ΔVout,lpf
1
Since any offset will be cancelled by the chopping, the
results of Monte-carlo analysis play a minor part in relation to
the worst-case process corners and operating conditions. Table
0.98 I shows the simulated operating range, lists the resulting worst-
94 94.5 95 95.5 96 96.5 97 case parameters and compares them to recent works on this
time in μs field.
Fig. 6. Transient response. The upper plot shows the signals in the high gain VI. C ONCLUSION
stage (Fig. 5), the lower plot shows overall behavior of the circuit.
A new chopping technique for Operational Amplifiers is
presented. It gets by without the use of additional transistors
Hz

without chopping in the high gain path. A fully-differential opamp that uses
noise power density in √V

with chopping this approach is shown. The input stage uses low-voltage
10−6 devices for higher performance and lower parasitics. Some
of the circuit techniques used to protect them, such as the
fchop = 500 kHz folded cascode with regulated folding point, are described. The
10−7 shown techniques are verified by different simulation results,
that prove their functionality.
R EFERENCES
−8
10 [1] B. Razavi, Design of Analog
√ Integrated Circuits, McGraw-Hill, 2001.
[2] Y. Kusuda, A 5.6 nV/ Hz Chopper Operational Amplifier Achieving a
100 101 102 103 104 105 106 107 108 0.5 μV Maximum Offset Over Rail-to-Rail Input Range with Adaptive
Clock Boosting Technique, in IEEE Journal of Solid-State Circuits, Vol.
frequency in Hz 51, No. 9, SEPTEMBER 2016
[3] Rod Burt and Joy Zhang, A Micropower Chopper-Stabilized Operational
Fig. 7. Simulated output noise with and without chopping Amplifier Using a SC Notch Filter With Synchronous Integration Inside
the Continous-Time Signal Path, in IEEE Journal of Solid-State Circuits,
Vol. 41, No. 12, December 2006
◦

[4] R. Wu, K. A. A. Makinwa and Johan H. Huijsing, A Chopper Current-

150
loop gain in dB / phase in

Feedback Instrumentation Amplifier With a 1 mHz 1/f Noise Corner and

an AC-Coupled Ripple Reduction Loop, in IEEE Journal of Solid-State
Circuits, Vol. 44, No. 12, December 2009
72 MHz / 86◦ [5] H. W. Klein and W. L. Engl, Design Techniques for Low Noise CMOS
100 Operational Amplifiers, in Tenth European Solid-State Circuits Confer-
ence, 1984
[6] Christian C. Enz and Gabor C. Temes, Circuit Techniques for Reducing
the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double
50 Sampling, and Chopper Stabilization, in Proceedings of the IEEE, Vol.
84, No. 11, November 1996
[7] M. Dessouky and A. Kaiser, Very low-voltage fully differential amplifier
for switched-capacitor applications, in IEEE International Symposium on
0 Circuits and Systems, May 2000
100 101 102 103 104 105 106 107 108 [8] Gaurav Kumar Sharma, D. Kumar and A. Kumar, Design of 3 Stage
frequency in Hz Low Noise Operational Amplifier, in 2015 International Conference on
Communication, Control and Intelligent Systems
[9] THS413x Datasheet, revised August 2015, www.ti.com.
Fig. 8. Simulated frequency response of the Opamp (blue, dashed) and gain [10] THS4552 Datasheet, revised July 2017, www.ti.com.
plot of the gain boost amplifiers A1 and A2 (Fig. 5)

77