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APPLICATION NOTE

AN046
Rev 1.00
Building a Battery Operated Auto Ranging DVM with the ICL7106 1999

Introduction Input Divider Network


In the field of DVM design, three areas are being addressed A simplified drawing of the divider network is shown in
with vigor: size, power dissipation, and novelty. The Figure 2. This configuration was chosen for simplicity and
handheld portable multimeter has gained in popularity since implementation using analog switches. The low leakage
low power dissipation devices enabled battery operation, LSI ID101s are used for input protection, and the second set of
A/D converters reduced IC count, and novelties such as switches to IN LO reduces the net error due to switch
conductance, automatic range scaling, and calculating were resistance. This can be seen calculating IN HI and IN LO
included to entice the user. voltages for the two equivalent circuits.

This application note describes a technique for auto-ranging For equivalent circuit A,
a battery operated DVM suitable for panel meter  RS + R  K 
applications. Also, circuit ideas will be presented for V MEAS = V IN HI =  ------------------------------------- V IN (EQ. 1)
 R S + R + R  K
conductance and resistance measurement, 9V battery and
5V supply operations, and current measurement. where RS = switch resistance, R = input resistance (1M),
and 1 + K is the desired divider ratio.
Auto Ranging Circuitry
Ideally VINHI should be
The control signals necessary for auto-ranging are over-
RK 1
range, under-range, and clock. The over-range and under- V IDEAL =  ----------------------- V IN =  ------------- V IN (EQ. 2)
 R  K + R  1 + K
range inputs control the direction of a scale shift, becoming
active at the completion of an invalid conversion and
Therefore the percent error is:
remaining active until a valid conversion occurs. The clock
input controls the timing of a scale shift. This signal should Ideal – Actual
--------------------------------------- 100, (EQ. 3)
Ideal
occur only once per conversion cycle, during a time window
which will not upset an ongoing conversion and must be
disabled after valid conversions.  R S + R/K 
or  1 –  1 + K  ----------------------------------- 100 (EQ. 4)
 R S + R/K + R
In the circuit of Figure 1, inverted over-range (O/R) and
under-range (U/R) are generated by detecting the display The worst case error occurs at (1+K) = 1000. For this
reading. The ICL7106 turns the most significant digit on and example, the error due to a 1kW switch resistance is 99.7%.
blanks the rest to indicate an over-range. An under-range IN HI for equivalent circuit B is the same as Equation 1.
occurs if the display reads less than 0100. R1C1 and R2C2 However, IN LO for circuit B is:
are required to deglitch O/R and U/R. RS
 
 ------------------------------------- V IN , (EQ. 5)
The next step in the logic disables O/R and U/R prior to  R S + R + R  K
shifting into nonexistent ranges. O/R is disabled when in the
200V range, while U/R is disabled when in the 200mV range. and combining Equations (1) and (5)
RK
The next level of gating disables the clock if the conditions V MEAS = V INHI – V INLO =  ------------------------------------- V IN (EQ. 6)
 R + R + R  K
S
are as described above and a valid conversion state exists.
Clock is enabled only when a range shift is called for and The percent error is equal to:
there exists a valid range to shift into.
R/K
 1 –  1 + K  ----------------------------------
The CD4029 is a four bit up/down counter, used as a register - 100 (EQ. 7)
 R + R + R/K S
to hold the present state and as a counter to shift the scale
as directed by the control inputs. The CD4028 is a BCD to
Using the same values for RS, (1+K), and R, the worst case
decimal decoder interfacing the CD4029 and ladder
error is 0.1%. This error can be further improved if lower
switches. An additional exclusive OR gate package is added
rDS(ON) switches are used. From the results calculated
to drive the appropriate decimal point.
above, the worst case conversion error due to switch
resistance will be one count of the least significant digit for a
full scale input, and a slight adjustment to R itself will correct
the remaining error on all scales.

AN046 Rev 1.00 Page 1 of 7


1999
1999
AN046 Rev 1.00

Building a Battery Operated Auto Ranging DVM with the ICL7106


V+
CREF
1 V+ OSC 1 40
100k
2 D1 OSC 2 39
100pF
V+ 3 C1 OSC 3 38
CLOCK A/Z
4 B1 TEST 37 DIG GND

5 A1 REF HI 36

6 F1 REF LO 35 1k
1F
7 G1 CREF 34
24k C3
20k
8 E1 CREF 33 5.1k 0.1F
ICL7106 PIN26
V- 9 D2 COMMON 32 S 22k
47M D1
10 C2 IN HI 31 Q2 2N3702
0.01F D Q3
R8 D
11 B2 IN LO 30 Q1 100k
0.47F
12 A2 A-Z 29 S
47k 3N169
13 F2 BUFF 28 N CH. 1M D2
14 E2 INT 27
O/RANGE 0.22F
D 2 15 D3 V- 26 V- TEST
3 3
3 2 10k 6
1
4 16 B3 G2 25
1 4023
R1 11 4
C1 4023 5 10 5 17 F3 C3 24
10 8 12
0.005F
9 74C32 TEST 13
6
18 E3 A3 23
O/RANGE 1
4011 8
4011 5 10k 2 10 19 AB4 G3 22
3 1 4 9
2 6 R2 9 8 20 POL BP 21
13 A C2 0.005F 4023
12 12
11
TEST 13
4011 VIN
4011
11

C
ID101
TEST V+ V+ R1 R2 R3 R6
VIN
1 PE V+ 16 1 V+ 16 D 1.001k 1M
13, 5 3
2 CLK 15 2 2 3 15 4
B 8 CD4016 9 R4
3 14 3 1 14
O A
10.1k
4 13 4 B 13 10
CD4029BC CD402T 11
5 12 6, 12
C1 5 C 12 TEST R5
1 2
6 Q1 Q7 11 6 D 11 111.1k
A B C A OR D 3
7 UP/DOWN 10 7 A 10 4
1 2 5 6 8 9 12 13 5, 13
BINARY CD4016 10
8 V 9 12 OPEN
DECODE 8 V 9 11
Page 2 of 7

TEST OPEN
9
BACK
8
UP/DOWN PLANE
COUNTER DECODER ARROW 6

FIGURE 1. AUTO RANGING CIRCUITRY


Building a Battery Operated Auto Ranging DVM
with the ICL7106

IN HI
+
ID101
VIN R/999 R/99.01 R/9

IN LO

SWITCH CONTROL
LINES

200V 20V 2V 200mV

FIGURE 2A.

+ +

R R

TO IN HI
TO IN HI

VIN VIN R/K VMEAS


R/K
VMEAS TO IN LO

R SWITCH
R SWITCH

- TO IN LO -

FIGURE 2B. EQUIVALENT CIRCUIT A FIGURE 2C. EQUIVALENT CIRCUIT B


(SWITCHES TO IN LO REMOVED) (SWITCHES TO IN LO INCLUDED)
FIGURE 2. INPUT DIVIDER NETWORK

Ranging Clock Circuit delay the clock, eliminating disparity with O/R and U/R (see
Figure 4 for timing diagram).
Two N-Channel MOSFETs, a PNP transistor and a handful of
passive components combine to generate the clock signal
used to gate the auto-ranging logic. A closer look at the inner
workings of the ICL7106 will help clarify the discussion of this
circuit. The analog section of the ICL7106 is shown in Figure 3.

It can be shown that CREF low (pin 33 of ICL7106) will sit at -


VREF for DE+ and at common for DE-, with DE+ designating
the deintegrate phase for a positive input signal and DE-
referring to a negative input signal. During the auto-zero
phase, CREF low is tied to an external reference through pin
35, which in Figure 1 is VREF below the positive supply. The
net result is that CREF low is above COMMON during auto-
zero, is left to float during signal integrate, and is at or below
COMMON during deintegrate. R8 and D1 are added externally
to pull CREF to COMMON during integrate, with Q2 and R1
included to speed this action. The signal at CREF low is now a
square wave that is high during auto-zero and low at all other
times. Q1 and Q3 amplify and level shift this waveform for logic
level compatibility. This clock signal is gated through D2 and
controls the timing of the auto-ranging circuitry. C3 is added to

AN046 Rev 1.00 Page 3 of 7


1999
Building a Battery Operated Auto Ranging DVM
with the ICL7106

CREF
RINT CAZ CINT
CREF+ REF HI REF LO CREF - BUFFER V+ A-Z INT
34 36 35 33 28 1 29 27
V+

A-Z A-Z - INTEGRATOR


+
10A TO
- - DIGITAL
+ +
31 2.8V SECTION
IN HI
INT DE- DE+ INPUT 6.2V A-Z
HIGH

A-Z
COMPARATOR
N -
+
DE+ DE-
32
COMMON
INPUT
INT A-Z AND DE LOW
30
IN LO
26

V-
FIGURE 3. ANALOG SECTION OF ICL7106

INTEGRATOR
A/Z A/Z A/Z
OVER-RANGE VALID
CONVERSION CONVERSION

CREF LOW
(PIN 33)

CLOCK

O/R, U/R

FIGURE 4. TIMING DIAGRAM

Supply Requirements limited to approximately 2V, if COMMON is disconnected from


-VIN.
The circuit of Figure 1 operates on a standard 9V transistor
battery. CMOS logic and a CMOS A/D converter (ICL7106) are
used to extend battery life; the approximate power drain for this
circuit is 8mW. The circuit in Figure 5 can also be added to
detect low supply voltage.

The circuit of Figure 6 can be used to generate 5V from a


single 5V supply. The ICL7660 is a voltage converter which
takes a 5V input and produces a -5V output. With respect to
common mode signals, the circuit of Figure 1 will have infinite
common mode handling capability if operated from a floating
9V battery. However, if powered by a fixed supply such as in
Figure 6, the common mode capability of the converter will be

AN046 Rev 1.00 Page 4 of 7


1999
Building a Battery Operated Auto Ranging DVM
with the ICL7106

For transconductance measurement, merely switch RSTD and


RX. This scheme makes the measurement of large resistors, in
1M conductance form, convenient and easy. This is also
1 8
convenient for leakage measurements.
2 ICL8211 7
A simple current meter can be built using the circuit of Figure 8.
3 6 1M The low leakage of the ICL7106 (10pA/max) makes possible
4 FIG 7 5 the measurement of currents in the mid pico-Amp range.
180K However, the switch leakage current will limit the accuracy of
TO DISPLAY the resistor network and may degrade converter resolution.
INDICATOR
BACKPLANE
TEST

FIGURE 5. LOW VOLTAGE DETECTOR


900R

+5V IN HI
NC 1 8 90R

2 7 NC IIN ICL7106
AUTO-RANGING
+ ICL7660 9R
DVM CIRCUIT
10F 3 6 NC
- IN LO
4 5
10F -5V R

FIGURE 6. GENERATING 5V FROM +5V


FIGURE 8. CURRENT METER
Resistance, Transconductance and
Current Circuits Using the ICL7126 and ICL7107
The purpose of this section is to show the simplicity of With a few modifications, the circuit of Figure 1 can easily be
measuring transconductance (1/R) and resistance with the adapted for use with either the low power ICL7126 or the
ICL7106. The circuit of Figure 7 requires only one precision ICL7107. Using the ICL7126 simply requires a change in the
resistor per decade range of interest. The conversion output is values of the integrating and auto-zero components. Refer to
described by the formula: the ICL7126 data sheet for details.

 RX  The ICL7107 is an LED version of the ICL7106, and is a bit


 --------------- 1000 (EQ. 8)
 R STD trickier to use in this application. First the over-range/under-
range logic must be changed slightly. Simply replace the quad
exclusive-NOR with an LM339; connect the outputs, as before,
V+
to the CD4023 triple 3-input NAND. Second, the ICL7107
requires +5V and -5V rather than the +9V battery used in
REF HI Figure 1. If battery operation is desired, the negative supply
RSTD can be derived from 4 Ni-Cad cells in series and an ICL7660
REF LO (see Figure 9). Note that both supplies float with respect to the
X4 ICL7106 input terminals. (Logic supplies are V+ and DIG. GND.)
IN914 or
IN4148 IN HI
RX
IN LO

COMMON

FIGURE 7. TRANSCONDUCTANCE AND RESISTANCE


MEASUREMENT

AN046 Rev 1.00 Page 5 of 7


1999
Building a Battery Operated Auto Ranging DVM
with the ICL7106

ICL7107

+5V 1 V3 OSC 1 40
ICL7660 2 D1 OSC 2 39

1 8 3 C1 OSC 3 38
4 B1 TEST 37
2 7
+ 5 A1 REF HI 36
10F 3 6
- 6 F1 REF LO 35
4 5 -5V 7 G1 CREF 34
- 12k
10F 8 E1 CREF 33
+
9 D2 COMMON 32
10 C2 IN HI 31
11 B2 IN LO 30
12 A2 A-Z 29
13 F2 BUFF 28
14 E2 INT 27
+
O /RANGE -
15 D3 V- 26 -5V
16 B3 G2 25
+
- 17 F3 C3 24
18 E3 A3 23
-
U /RANGE +
19 AB4 G3 22
20 POL GND 21 NEGATIVE (0V)
LOGIC SUPPLY
-
+
CD4023 OR
74C10 LM339 33k

FIGURE 9. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL7107 OUTPUTS. THE LM339 IS
REQUIRED TO ENSURE LOGIC COMPATIBILITY WITH HEAVY DISPLAY LOADING

AN046 Rev 1.00 Page 6 of 7


1999
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