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Eliyahu Zamir
ECE1388F - Final Project Report Manuel Saldaña
1. Functional Specification
This project focuses on the full-custom design of a 200MHz 6-bit Flash ADC converter implemented
using the TSMC 0.35µm process technology [1]. It uses separate analog and digital power rails (VDD =
3.3V), and encodes a single-ended analog input between 0V and VDD. A more complete set of
specifications can be found in the datasheet in the Appendix.
2. Chip Design
This section describes the chip in terms of the modular structure shown in the top-level architecture
diagram (Figure 1) in the Appendix. The entire chip layout diagram (Figure 2) is also available in the
Appendix.
To ensure excellent matching between components, the resistors used in the comparator ladder were
surrounded with dummy resistors. The preamplifiers and latched comparators were laid out using inter-
digitated fingers for the same reason. A 50µm separation region was inserted between the latched
comparators and the CML-to-CMOS converters to shield the analog section of the chip from the noise-
inducing digital section. Numerous N-Well diffusion contacts connected to VDD were inserted within
this isolation region to improve the shielding. Figure 3 illustrates the layout of the block.
Since only one output will be active at a given point in time, this block greatly simplifies the
implementation of the following Priority to Binary conversion block. It also improves robustness in the
case where one of the latched comparators were to fail: the missed code in the thermometer output does
not affect the priority-encoded output for the remainder of the latches. Figure 4 illustrates the layout.
The pad frame was laid out using CMC guidelines with a pad pitch of 150µm. All input and output pads
were surrounded by VDD and ground pads to prevent cross-talk. This also prevents ground bounce by
reducing the overall supply pin inductance, and avoids excessive current flow through a single pin.
3. Division of Labour
Arun Patel
Initial research and simulation of folding quantizer design, research and development of priority encoder
circuit (schematics and layout), top-level architecture design and modeling, chip-level simulation, clock
management design (schematics), global layout, and preparation of reports and presentation slides.
Eliyahu Zamir
Initial research into high-speed comparator design, analog circuit design (schematics and layout of pre-
amplifiers, resistor ladders, latched comparators, biasing networks, and CML-to-CMOS conversion
logic), interfacing and isolation of analog and digital circuitry, pad-frame design (schematics and layout,
including ESD protection), and global layout.
Manuel Saldaña
Market surveys of analog-to-digital topologies, research into dynamic logic design, implementation of
64-to-6-bit binary encoder circuit based on dynamic logic (schematics and layout), implementation of 6-
bit D-type output register (schematics and layout), clock management cell layout, and global layout.
4. Appendices
4.1 Figures
layout schematic
instances
un-matched 0 0
rewired 0 0
size errors 0 0
pruned 0 0
active 15199 3040
total 15199 3040
nets
un-matched 0 0
merged 0 0
pruned 0 0
active 1618 1618
total 1618 1618
terminals
devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:
devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:
4.4 Schematics
The following section illustrates the schematics of key components within our design. For further
information, please consult the “Schematics Slides” or “Top-Level Slides” referenced from the project
web-page.
4.5 Simulations
The following section contains simulation results for the key components within our design. Further
details regarding the simulations can be found in the Appendix section of the project web-page.
[2] Kun, C., and Mason, A., A Power-Optimized 64-bit Priority Encoder Utilizing Parallel Priority
Look-Ahead, IEEE International Symposium on Circuits and Systems 2004, vol. II, pp. 753-756.