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# BJT Small Signal Analysis

## Lec. Mian Hammad Nazir

Department of Electrical Engineering
The re Transistor MODEL for CE
configuration
 The re model employs a diode and controlled current source to
duplicate the behavior of a transistor in the region of interest
controlled-
Input output current source
terminal terminal

Zi
For Input Impedence (Zi) :
 The base and collector currents are related by the following
equation:
 The voltage Vbe is across the diode resistance.

 .

 .
For Output Impedence :
Role of r0 :
 The steeper the slope, the less the level of output impedance (Zo).

## Slope of the curves increases with

increase in collector current

## lesser the level of output impedance the

higher the value of IC
 For determining Z0,

Thus,
Ic=0 Amp

## Thus from figure,

 But if there is no r0 in the circuit i.e,
The contribution due to ro is ignored as in the re model
Than,

Z0= V0/I0
 ForVoltage Gain (Av) Here the role of r0
is ignored
 For current gain (Ai):
Various type of BJT Configurations
 Common-Emitter Fixed-Bias Configuration

##  Common Emitter VOLTAGE-DIVIDER BIAS Configuration

 CE Emitter-Bias Configuration

QUESTION

## Why capacitor allows to pass AC and not

allow for DC?
 Capacitive reactance -- the "resistance" of a capacitor to current
flow
is found by 1/(2*pi*f*C). For high frequencies, this "resistance" is
low, allowing current flow. The lower the frequency, the higher
this "resistance" is.

## DC or direct current is consider "zero" Hertz frequency and the

capacitive reactance ("resistance") at this point is infinite, allowing
no current flow at all. So, the higher the frequency, the easier it is
for the signal to pass through the capacitor; the lower the
frequency, the more difficult it is for current to pass and
impossible for DC.
Common-Emitter Fixed-Bias
Configuration
 The input signal Vi is applied to the base of the transistor
while the output Vo is off the collector.
 The small-signal ac analysis begins by removing the dc effects
of VCC and replacing the dc blocking capacitors C1 and C2
by short-circuit equivalents

After

AC Analysis
e
Example
Common Emitter VOLTAGE-DIVIDER
BIAS Configuration
 Substituting the re equivalent circuit will result in the
network

## Absence of RE due to the low-impedance shorting

effect of the bypass capacitor, CE.That is, at the
frequency (or frequencies) of operation, the
reactance of the capacitor is so small compared
to RE that it is treated as a short circuit across RE
 The parallel combination of R1 and R2 is defined by

 .

 .
CE Emitter-Bias Configuration
 Un-bi-passed circuit (removing r0 , and RE is not removed)
 Applying Kirchhoff’s voltage law to the input side

##  The input impedance looking into the network to the right of RB is

Study Assignment
What will be over all effect if we include r0 in the re
circuit configuration ?
Collector Feed-Back Configuration
Study Assignment
What will be over all effect if we include r0 in the re circuit
configuration of collector feed back configuration ?
Collector DC Feed back Configuration
%

##  The total gain of the system is then determined by the

product of the individual gains as follows.

##  and the total current gain by

Two cascaded CE stages
Approximate HYBRID Equivalent
Circuit
Relation between re and Hybrid equivalent
model

## hfe  lower case (h) denotes Hybrid equivalent circuit

fe denotes forward current gain in Common emitter config
Fixed-Bias Configuration