//module: chia tan so CLK

//input: xung Clk 40Mhz cua FPGA, tin hieu Reset tích cuc muc thap

//output: xung Clk 1Hz, tin hieu rst tich cuc muc cao

module clk(

Clk40M, //xung clock vao 40MHz

Reset, //Reset dau vao tich cuc muc thap

Clk1, //xung clock 1Hz

rst //Reset ra tich cuc muc cao

);

input Clk40M,Reset;

output Clk1,rst;

reg Clk1;

reg [27:0] count1;

assign rst=~Reset; //Reset in active-low, rst out active-higt

always@(posedge Clk40M or negedge Reset)

begin

if(!Reset) count1<=28'b0;

else if(count1==19999999)

begin

Clk1<=1'b1;

count1<=count1+1'b1;

end

else if (count1==39999999)

begin

Clk1<=1'b0;

count1<=28'b0;

end

else count1<=count1+1'b1;
//counter.v

// h2h1 : m2m1 : s2s1

module Counter(clk, rst, s1, s2, m1, m2, h1, h2);

input clk, rst;

input s1, s2, m1, m2, h1, h2;

reg [7:0] s1, s2, m1, m2, h1, h2;

always @ (posedge clk or posedge rst)

begin

if (rst)

begin

s1 <= 0; s2 <= 0; m1 <= 0; m2 <= 0; h1 <= 0; h2 <= 0;

end

else

begin

// giay

s1 = s1 + 1;

if (s1 > 9) begin

s1 = 0;

s2 = s2 + 1;

end

//phut

if (s2 > 5) begin

s2 = 0;

m1 = m1 + 1;
 end

if (m1 > 9) begin

m1 = 0;

m2 = m2 + 1;

end

//gio

if (m2 > 5) begin

m2 = 0;

h1 = h1 + 1;

end

if (h1 > 9) begin

h1 = 0;

h2 = h2 + 1;

end

if ((h2 == 2) && (h1 > 3)) begin

h1 = 0;

h2 = 0;

end

end

endmodule
//led 7seg

// anode chung

module Led7seg (bcd, seg);

input bcd;

output seg;

reg [6:0] seg;

always @ (bcd)

begin

case(bcd)

0: seg <= 7'b0000001;

1: seg <= 7'b1001111;

2: seg <= 7'b0010010;

3: seg <= 7'b0000110;

4: seg <= 7'b1001100;

5: seg <= 7'b0100100;

6: seg <= 7'b0100000;

7: seg <= 7'b0001111;

8: seg <= 7'b0000000;

9: seg <= 7'b0000100;

default: seg <= 7'b0000001;

endcase

end

endmodule
//bai3.v

module bai3 (Clk40M, Reset, 7segS1, 7segS2, 7segM1, 7segM2, 7segH1, 7segH2);

input Clk40M, Reset;

output 7segS1, 7segS2, 7segM1, 7segM2, 7segH1, 7segH2;

wire clk1, rst, s1, s2, m1, m2, h1, h2;

clk Clk1Hz (.Clk40M(Clk40M), .Reset(Reset), .Clk1(clk1), .rst(rst));

Counter C (.clk(clk1), .rst(rst), .s1(s1), .s2(s2), .m1(m1), .m2(m2), .h1(h1), .h2(h2));

// H2H1 : M2M1 : S2S1

//gio

Led7seg H2 (.bcd(h2), .seg(7segH2));

Led7seg H1 (.bcd(h1), .seg(7segH1));

// phut

Led7seg M2 (.bcd(m2), .seg(7segM2));

Led7seg M1 (.bcd(m1), .seg(7segM1));

// giay

Led7seg S2 (.bcd(s2), .seg(7segS2));

Led7seg S1 (.bcd(s1), .seg(7segS1));

Endmodule
/clk.tv=b

`timescale 1 ns / 100 ps

module clk_tb ();

reg Clk40M, Reset;

wire 7segS1, 7segS2, 7segM1, 7segM2, 7segH1, 7segH2;

bai3 U1 (.Clk40M, .Reset(Reset), .7segS1(7segS1), .7segS2(7segS2), .7segM1(7segM1),

.7segM2(7segM2), .7segH1(7segH1), .7segH2(7segH2));

//generate clock

always

begin

clk40M <= 0;

#12.5;

clk40M <= 1;

#12.5;

end

initial

begin

Reset <= 0; // start

#12.5;

Reset <= 1; // case 1

end

endmodule
Vẽ sơ đồ trạng thái Mealy và mô tả sơ đồ bằng verilog cho trường hợp sau :
Đầu ra Y = 1 khi tổng các số bit 1 nhận được chia cho 4 dư 3 ( biết các bit nhận được
theo thứ tự LSB vào trước //bai4.v
module countBit(clk,Out,newNum,count);

input clk;

output Out,newNum,count;

reg[4:0] Num;

reg[4:0] newNum;

reg Out;

reg[4:0] count;

integer index;

initial

begin

Num = 15;

count = 0;

end

always @(posedge clk) begin

if((Num & 1) == 1) begin

newNum[index] = 1;

count = count + 1;

end

else newNum[index] = 0;

Num = Num >> 1;

if(count%4 ==3) Out =1;

else Out = 0;

end endmodule
/bai4_tb.v

`timescale 1ns/1ps

module countBit_tb();

wire Out;

wire [4:0] newNum;

wire [4:0] count;

reg clk;

countBit CB (.clk(clk), .Out(Out), .newNum(newNum), .count(count));

always

begin

#10 clk = 0;

#10 clk = 1;

end

endmodule