DE LA SALLE LIPA

COLLEGE OF INFORMATION TECHNOLOGY AND ENGINEERING

ELECTRONICS ENGINEERING
LOGIC CIRCUITS AND SWITCHING THEORY

LMS ACTIVITY

Submitted by:
Atienza, Marvin James A.

Submitted to:
Engr. Aileen F. Villamonte, ECE

November 14, 2018

Activity:
A 3-input Majority Gate is a digital circuit whose output is equal to 0 if majority of the
inputs are 1’s.

A. With X, Y, and Z as the inputs and F as the output, generate the Truth Table.
X Y Z F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

B. By means of Truth Table, find the following Boolean function of a 3-input Majority
Gate
1. canonical SOP
F(x,y,z) = x’y’z’ + x’y’z + x’yz’ + xy’z’
2. canonical POS
F(x,y,z) = (x+y’+z’)(x’+y+z’)(x’+y’+z)(x’+y’+z’)

C. simplify the Boolean function using

1. K-Map
  Canonical SOP
F(x,y,z) = x’y’z’ + x’y’z + x’yz’ + xy’z’

x 0 1
yz
F(x,y,z)= x’z’ + x’y’ + y’z’
00 1 1
01 1  Canonical POS
11 F(x,y,z) = (x+y’+z’)(x’+y+z’)
10 1 (x’+y’+z)(x’+y’+z’)

yz 0 1
x

00
01 0
11 0 0
10 0 0

F(x,y,z) = (y’+z’)(x’+y’)(x’+z’)

2. Tabulation (Quine-McClusky) Grou Dec xyz method

p
 Canonical SOP
0 0 000 ✔
Dec xyz 1 1 001 ✔
0 000 2 010 ✔
1 001 4 100 ✔
2 010
4 100

xyz
0,1 00_ *
0,2 0_0 *
0,4 _00 *
 Prime Implicant Table
0 1 2 4
0,1 x’y’ x x
0,2 x’z’ x x
0,4 y’z’ x x

F(x,y,z) = x’y’ + x’z’ + y’z’

 Canonical POS
Dec xyz Grou Dec xyz
3 011 p
5 101 2 3 011 ✔
6 110 5 101 ✔
7 111 6 110 ✔
3 7 111 ✔
xyz
3,7 _11 *
5,7 1_1 *
6,7 11_ *

Prime Implicant Table

 3 5 6 7
3,7 y’+z’ x x
5,7 x’+z’ x x
6,7 x’+y’ x x

F(x,y,z) = (x’+y’)(x’+z’)(y’+z’)

D. Generate and compile the VHDL code of your design using quartus II and give the
following:
SOP
1. VHDL code
library ieee;
use ieee.std_logic_1164.all;

entity LMS is

port( x: IN std_logic;
y: IN std_logic;
z: IN std_logic;
F : OUT std_logic);
end LMS;

architecture simplify of LMS is

begin
F <= not ((x and y) or (y and z) or ( x and z));

end simplify;

2. Summary Report

3. RTL view
POS

1. VHDL code

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LMS_POS is

port( x: IN std_logic;
y: IN std_logic;
z: IN std_logic;
F : OUT std_logic);
end LMS_POS;

architecture LMS of LMS_POS is

begin
F <= not ((y or z) and (x or z) and (x or y));

end LMS;

2. Summary Report

3. RTL view