SLDS031A – APRIL 1985 – REVISED APRIL 1993

Each Device Drives 32 Electrodes SN75555 . . . N PACKAGE

(TOP VIEW)
90-V Output Voltage Swing Capability
Using Ramped Supply
Q17 1 40 Q18
15-mA Output Source and Sink Current Q16 2 39 Q19
Capability Q15 3 38 Q20
High-Speed Serially-Shifted Data Input Q14 4 37 Q21
Totem-Pole Outputs Q13 5 36 Q22
Latches on All Driver Outputs Q12 6 35 Q23
Q11 7 34 Q24
description Q10 8 33 Q25
Q9 9 32 Q26
The SN65555, SN75555, SN65556, and Q8 10 31 Q27
SN75556 are monolithic BIDFET† integrated Q7 11 30 Q28
circuits designed to drive the column electrodes of Q6 12 29 Q29
an electroluminescent display. The SN65556 and Q5 13 28 Q30
SN75556 output sequence is reversed from the Q4 14 27 Q31
SN65555 and SN75555 for ease in printed-circuit- Q3 15 26 Q32
board layout. 16 25
Q2 OUTPUT ENABLE
The devices consist of a 32-bit shift register, 32 Q1 17 24 DATA IN
latches, and 32 output AND gates. Serial data is SERIAL OUT 18 23 LATCH ENABLE
entered into the shift register on the low-to-high CLOCK 19 22 VCC1
transition of CLOCK. When high, LATCH ENABLE GND 20 21 VCC2
transfers the shift register contents to the outputs
of the 32 latches. When OUTPUT ENABLE is SN65555, SN75555 . . . FN PACKAGE
high, all Q outputs are enabled. Data must be (TOP VIEW)
loaded into the latches and OUTPUT ENABLE
Q12
Q13
Q14
Q15
Q16
Q17
Q18
Q19
Q20
Q21
Q22
must be high before supply voltage VCC2 is
ramped up.
6 5 4 3 2 1 44 43 42 41 40
Q11 7 39 Q23
Serial data output from the shift register can be
used to cascade shift registers. This output is not Q10 8 38 Q24
affected by LATCH ENABLE or OUTPUT Q9 9 37 Q25
ENABLE. Q8 10 36 Q26
Q7 11 35 Q27
The SN65555 and SN65556 are characterized for Q6 12 34 Q28
operation from – 40 C to 85 C. The SN75555 and Q5 13 33 Q29
SN75556 are characterized for operation from 14 32 Q30
Q4
0 C to 70 C. 15 31 Q31
Q3
Q2 16 30 Q32
Q1 17 29 NC
18 19 20 21 22 23 24 25 26 27 28
VCC1
SERIAL OUT

LATCH ENABLE

OUTPUT ENABLE
NC
NC
NC
CLOCK
GND

DATA IN
VCC2

NC – No internal connection

† BIDFET – Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.

Copyright 1993, Texas Instruments Incorporated

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SLDS031A – APRIL 1985 – REVISED APRIL 1993

SN65556, SN75556 SN65556, SN75556

N PACKAGE FN PACKAGE
(TOP VIEW) (TOP VIEW)

Q21
Q20
Q19
Q18
Q17
Q16
Q15
Q14
Q13
Q12
Q11
Q16 1 40 Q15
Q17 2 39 Q14
6 5 4 3 2 1 44 43 42 41 40
Q18 3 38 Q13 Q22 7 Q10
39
Q19 4 37 Q12 Q23 8 38 Q9
Q20 5 36 Q11 Q24 9 37 Q8
Q21 6 35 Q10 Q25 10 36 Q7
Q22 7 34 Q9 Q26 11 35 Q6
Q23 8 33 Q8 Q27 12 34 Q5
Q24 9 32 Q7 13 33 Q4
Q28
Q25 10 31 Q6 Q29 14 32 Q3
Q26 11 30 Q5 15
Q30 31 Q2
Q27 12 29 Q4 16
Q31 30 Q1
Q28 13 28 Q3 17 29
Q32 NC
Q29 14 27 Q2 18 19 20 21 22 23 24 25 26 27 28
Q30 15 26 Q1

VCC1
SERIAL OUT

LATCH ENABLE
DATA ENABLE
OUTPUT ENABLE
NC
NC
NC
CLOCK
GND
VCC2
Q31 16 25 OUTPUT ENABLE
Q32 17 24 DATA IN
SERIAL OUT 18 23 LATCH ENABLE
CLOCK 19 22 VCC1
GND 20 21 VCC2

NC – No internal connection

logic symbols†
SN65555, SN75555 SN65556, SN75556
CMOS/EL DISP CMOS/EL DISP
VCC2 21 [PWR Q1-32] V CC2 21 [PWR Q1-32]
OUTPUT ENABLE 25 EN3 OUTPUT ENABLE
25
EN3
LATCH ENABLE 23 C2 LATCH ENABLE
23
C2

19 SRG 32 19 SRG 32
CLOCK C1/ CLOCK C1/

DATA IN 24 1D 2D 3
17
Q1 DATA IN
24
1D 2D 3
26 Q1
2D 16 2D 27 Q2
3 Q2 3

1 40 Q15
2D 3 Q17 2D 3
2D 40 Q18 2D 1 Q16
3 3

2D 27 Q31 2D 16
3 3 Q31
26 Q32 17 Q32
2D 3 2D 3
18 SERIAL OUT 18 SERIAL OUT

† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for N packages.

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 SLDS031A – APRIL 1985 – REVISED APRIL 1993

logic diagram (positive logic)

V CC2
OUTPUT
ENABLE Output
LATCH Buffers
ENABLE
Shift
Register Latches

DATA IN 1D C2 LC1 Q1
R1
CLOCK C1 2D

1D C2 LC2 Q2
R2
C1 2D

28 Stages
(Q3 thru Q30)
Not Shown

1D C2 LC31 Q31
R31
C1 2D

1D C2 LC32 Q32
R32
C1 2D

SERIAL OUT

FUNCTION TABLE
CONTROL INPUTS OUTPUTS
SHIFT REGISTER LATCHES
FUNCTION LATCH OUTPUT
CLOCK R1 THRU R32 LC1 THRU LC32 SERIAL Q1 THRU Q32
ENABLE ENABLE
X X Load and shift† Determined by R32
Load Determined by OUTPUT ENABLE
No X X No change LATCH ENABLE‡ R32
X L X Stored data
Latch As determined above R32 Determined by OUTPUT ENABLE
X H X New data
Output X X L Determined by R32 All L
As determined above
Enable X X H LATCH ENABLE‡ R32 LC1 thru LC21, respectively
H = high level, L = low level, X = irrelevant, = low-to-high-level transition.
† R32 and the serial output take on the state of R31, R31 takes on the state of R30,. . .R2 takes on the state of R1, and R1 takes on the state of
the data input.
‡ New data enter the latches while LATCH ENABLE is high. These data are stored while LATCH ENABLE is low.

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SLDS031A – APRIL 1985 – REVISED APRIL 1993

typical operating sequence

CLOCK

DATA IN Valid Irrelevant

Invalid Valid
SR Contents

LATCH ENABLE

Latch Previously Stored Data New Data Valid

Contents

OUTPUT
ENABLE

VCC2

Q Outputs Valid

schematic of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL Q OUTPUTS TYPICAL OF SERIAL OUTPUT

VCC1 VCC2 VCC1

Output
Input
Output

GND GND GND

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 SLDS031A – APRIL 1985 – REVISED APRIL 1993

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Supply voltage, VCC2 (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC1 + 0.3 V
Ground current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: SN65555, SN65556 . . . . . . . . . . . . . . . . . . . . . . . – 40 C to 85 C
SN75555, SN75556 . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65 C to 150 C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260 C
NOTES: 1. Voltage values are with respect to network GND.
2. These devices have been designed to be used in applications in which the high-voltage supply, V CC2, is switched to GND before
changing the state of the outputs.

DISSIPATION RATING TABLE

TA 25 C DERATING FACTOR TA = 70 C TA = 85 C
PACKAGE
POWER RATING ABOVE TA = 25 C POWER RATING POWER RATING
FN 1700 mW 13.6 mW/ C 1088 mW 884 mW
N 1250 mW 10.0 mW/ C 800 mW 650 mW

recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, VCC1 10.8 12 15 V
Supply voltage, VCC2 0 80 V
VCC1 = 10.8 V 8.1 11.1
High level input voltage
High-level voltage, V IH (see Figure 1) V
VCC1 = 15 V 11.25 15.3
VCC1 = 10.8 V – 0.3† 2.7
Low level input voltage
Low-level voltage, V IL (see Figure 1) V
VCC1 = 15 V – 0.3† 3.75
High-level output current, IOH – 15 mA
Low-level output current, IOL 15 mA
Output clamp current, IOK 20 mA
Clock frequency, fclock 0 6.25 MHz
Pulse duration, CLOCK high or low, tw(CLK) (see Figure 2) 80 ns
Pulse duration, LATCH ENABLE, tw(LE) 80 ns
DATA IN before CLOCK (see Figure 2) 20
Setup time,
time tsu ns
OUTPUT ENABLE before VCC2 (see Figure 4) 500
DATA IN after CLOCK (see Figure 2) 80
Hold time,
time th ns
OUTPUT ENABLE after VCC2 (see Figure 4) 100
Rate of rise for V CC2, dv/dt 80 V/ s
SN65555, SN65556 – 40 85
Operating free-air
free air temperature,
temperature TA C
SN75555, SN75556 0 85
† The algebraic convention, in which the least positive (most negative) value is designated as minimum, is used in this data sheet for logic voltage
levels.

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SLDS031A – APRIL 1985 – REVISED APRIL 1993

electrical characteristics over recommended operating free-air temperature range, VCC1 = 12 V,

VCC2 = 80 V
PARAMETER TEST CONDITIONS MIN MAX UNIT
Q outputs IO = – 15 mA 77
V OH High level output voltage
High-level V
SERIAL OUT IO = – 100 A 10.5
Q outputs IOL = 15 mA 8
V OL Low level output voltage
Low-level V
SERIAL OUT IOL = 100 A 1
IIH High-level input current V I = 12 V 1 A
IIL Low-level input current VI = 0 –1 A
ICC1 Supply current from VCC1 2 mA
ICC2 Supply current from VCC2 5 mA

switching characteristics, VCC1 = 12 V, TA = 25 C

PARAMETER TEST CONDITIONS MIN MAX UNIT
Propagation delay time, high-to-low-level,
tPHL 140 ns
SERIAL OUT from CLOCK CL = 20 pF to GND,, V CC2 = 0,,
Propagation delay time, low-to-high level, See Figure 3
tPLH 140 ns
SERIAL OUT from CLOCK
td Delay time, VCC2 to Q outputs dv/dt = 80 V/ s, See Figure 4 100 ns

RECOMMENDED OPERATING CONDITIONS

INPUT VOLTAGE LOGIC-LEVEL LIMITS
vs
SUPPLY VOLTAGE VCC1

12
TA = Full Range

10

Minimum VIH
VVII – Input Voltage – V

Maximum V IL
2

2
10 11 12 13 14 15
V CC1 – Supply Voltage – V

Figure 1

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 SLDS031A – APRIL 1985 – REVISED APRIL 1993

PARAMETER MEASUREMENT INFORMATION

tw(CLK)

VIH
CLOCK
50% 50% 50%

VIL
tw(CLK)
tsu th

VIH
DATA IN Valid
VIL

Figure 2. Input Timing Voltage Waveforms

VIH
CLOCK 50%
VIL
t PLH

VOH
SERIAL OUT 50%
VOL
t PHL
VOH
SERIAL OUT 50%
VOL

Figure 3. Voltage Waveforms for Propagation Delay Time, CLOCK to SERIAL OUT

VIH
OUTPUT 50% 50%
ENABLE
VIL

tsu 80 V
th
VCC2
10% 10%
0V

td
VOH
Valid
Q Output
10%
VOL

Figure 4. Voltage Waveforms for Delay Times, VCC2 to Q Outputs

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