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A low-power digital PWM DC/DC converter based on passive sigma-delta

modulator

Conference Paper · January 2005

DOI: 10.1109/ISCAS.2005.1465476 · Source: DBLP

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S.K.  Hoon,  F.  Maloberti,  J.  Chen:  "A  low-­power  digital  PWM  DC/DC  converter  
based   on   passive   Sigma-­Delta   modulator";   Proc.   of   the   IEEE   International  
Symposium   on   Circuits   and   Systems,   ISCAS   2005,   Kobe,   23-­‐26   May,   Vol.   4,   pp.  
3873-­‐3876.  
 
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 A Low-Power Digital PWM DC/DC Converter
based on Passive Sigma-Delta Modulator

Siew Kuok Hoon*, Franco Maloberti**, and Jun Chen***

*
Wireless Analog Technology Center, Texas Instruments Inc., Dallas, USA, siewkh@ti.com
**
Department of Electronics, University of Pavia, Pavia, Italy, franco.maloberti@unipv.it
***
Advanced Analogic Technologies, Dallas, USA, junchen@analogictech.com

Abstract— This paper describes a novel method to obtain a
digital control for PWM DC/DC switching regulator. A passive
sigma-delta modulator which output is suitably processed
obtains the PWM control and makes the control loop. The
output of the sigma-delta enables generating the discrete-time
PWM control. The proposed method has been extensively
simulated at the behavioral level. Results show that the method
can be effectively employed in low power DC/DC converters.
converter in conventional digital PWM controller. The
voltage ripple is low even with a relatively low over-
sampling. If higher accuracy is required the system can
conveniently increase the over-sampling rate of the sigma-
delta modulator instead of modifying the A/D converter
design and with a relatively small increase of power
consumption.

II. CONVENTIONAL TECHNIQUE

I. INTRODUCTION
A DC/DC buck converter system as illustrated in Fig.1
The scenario of portable power management system
can replace the analog controller with a digital controller.
changed recently because of the explosive demand in
The conventional analog loop including a filter, a comparator
portable devices such as cellular phone, PDA (personal
and ramp generator is replaced by a digital controller to
digital assistant) and digital camera. The DC/DC converter
produce the PWM signal. The only analog part is the A/D
plays a critical role in the power management system in
converter. The challenge is to design a low power, high
keeping long battery life while providing stable supply and
immunity to noise and process variation, low complexity
noise isolation [1]. The main requirements of DC/DC
A/D converter. The most common A/D converter used is a
converter are high efficiency, low cost and small solution
multi-bit flash A/D converter.
size. With the advancement of deep sub-micron technology,
DC/DC converter based on digital controller exploits the
advantage of the small digital system realization and offer as
an attractive solution especially for the Systems On Chip +
(SOC) implementations. Moreover, digital controller poses VS
-
the advantages of less sensitive to noise, process parameters,
and low quiescent current [2]. Another feature is also the
flexibility to modify control and stability compensation
scheme corresponding to a change in external components, CMP -
+
which can be critical to product cycle time in today’s + VREF
-
competitive market environment. On the other hand, digital RAMP
controller for DC/DC converter suffers DC accuracy issue (from OSC)

due to the finite signal resolution processed by the A/D

converter and the time delays in the control loop due to the
computation of the A/D converter and control processor. digital controller A/D

This paper presents a digital PWM DC/DC converter

Figure 1. Proposed DC/DC Switching Regulator
using a passive sigma-delta modulator. The benefit of the
method is low power and less sensitive to mismatch as However, the flash architecture requires high power
compared to the use of flash A/D (analog-to-digital) consumption (an N-bit converter requires 2N comparators)

0-7803-8834-8/05/$20.00 ©2005 IEEE. 3873

and large silicon area. In [3], instead of using the flash A/D
converter a delayed-line A/D converter has been used. The
implementation of the delayed-line converter is purely
digital-type. However, the performances of the delayed-line
depend on the matching of threshold-voltages of the chain
inverters. The optimum solution is to have digital control and
at the same time flexible process portability and small in
area. Solutions described in [4],[5] use digital controller and
an analog section made by a window comparator with 2
decision levels. Here, the optimal window range is the
critical and difficult design parameter. Solutions in [6],[8]
use sigma-delta converters. The sigma-delta modulation is
used primarily in driving the power switches, thus reducing
EMI and switching noise. Using high variable frequency
switching can be problematic and PWM power switching
scheme becomes preferable. Finally, [9] uses a PWM
DC/DC converter based on a sigma-delta modulator but the
active implementation costs area and power.
III. PROPOSED TECHNIQUE
This switching regulator, with proportional control, uses
a passive first-order signal delta modulator [10] as input
stage of the control circuit. The output of the sigma delta is a
bit-stream at the main clock frequency, fCK. The processing
(PROC) block consists of an integrate-and-dump by N clock
periods and a digital to duty-cycle converter that produces a
PWM pulse at fCK/N. Fig. 2 shows the block diagram of the
system.
Figure 2. Proposed DC/DC Switching Regulator
A simple RC switched capacitor circuit replaces the
integrator normally used in a sigma-delta modulator.
Capacitor C1 is charged to the regulated voltage minus the
two-levels DAC output during phase 1 and during phase 2,
capacitor C1 is in parallel to C2 through Vset. Therefore, the z-
transfer function of the SC-RC is
C1z −1
VC (z) =
C1 + C2 − C2 z−1
[VDAC − Vreg + Vset ]
since
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Vc = Vε − VDAC
where Vε is the quantization error, it results
(Vreg − Vset )C1z −1 Vε (C1 + C − C2 z −1)
VDAC (z) = +
C1 + C2 − (C2 − C1)z −1 C1 + C2 − (C2 − C1 )z −1
Therefore, the sequence of the digital bit-stream driving
the digital-to-analog converter (DAC) depends on the term
(Vreg-Vset) and the quantization error of the modulator, Vε.
The noise shaping is modest and, actually, its effect is
causing an acceptable degradation of performances as
verified with behavioral level simulations.
The accumulation of the output bit-stream will lead to an
averaging operation: the term (Vreg-Vset) is preserved while
the quantization noise is reduced by N1/2. The amplitude at
the output of the accumulate-and-dump by N clock period is
used as input of a digital-to-duty cycle converter. The value
of the duty cycle is discrete and holds k/N, where k is the
number of 1 at the output of the sigma-delta in an N-clock
period. The generated pulse, decimated by N with respect to
fCK is used for the PWM control. Since the system requires a
sequence of PWM pulses with continuous-time duration, the
output of the system accomplishes the request by generating
a sigma-delta like modulation of the PWM duration by using
N+1 possible duty-cycles (k/N; k=0…N).
In addition to the above features the system can work
with very low power consumption. The power required by
the switched capacitor circuit is negligible being the
equivalent resistance of the SC structure very high. The
power required by the comparator can be in the µW range or
below for clock frequency as high as 16 MHz. With this
frequency, assuming C1=0.2pF the equivalent resistance
T/C1 is 312 KΩ. If the reference voltage used by the DAC is
0.1V the SC current is 0.3 µA.
IV. SIMULATION RESULTS
The proposed modulator has been simulated in the
Matlab-Simulink! environment. Fig. 3 shows the high-level
block diagram. Three blocks make the control loop. The
PWM control is monitored together with the regulated
voltage. The output to workspace enables post-processing.
Figure 3. Simulink block diagram of the DC/DC converter.
 Fig. 4 shows the used model for the buck regulator. The
schematic is the representation of the V-I equations of the
circuit elements used in the buck converter [11]. In addition,
the ESR resistance in series with the capacitance (in parallel
with the load K) is accounted for. The saturation block
ensures that the current in the inductor flows always in the
direction of the load.

Figure 6. Regulator output voltage and P control only

Figure 4. Behavioral model of the buck voltage regulator.

Fig. 5 shows the model of the passive sigma-delta

modulator. The values indicated in the diagram correspond
to C2/C1=4. A random number generator enables the
studying of a possible noise affecting the reference or the
input terminal. The descriprion of the processing block is not
given here being already discussed the digital functions.

Figure 7. Regulated voltage with PD control

between response improvement and complexity. PID is also

possible with additional passive SC filters before the sigma-
delta or with suitable processing in the digital domain.
Figure 5. Passive sigma-delta modulator.
The noise on the Vset is ± 2mV peak. Observe that, after a
transient the voltage settles around the set value 2.23V. The
The performance of the buck converter using only
duty cycle control varies between 6/16 and 9/16 as shown in
proportional control (P) and proportional-derivative (PD),
Fig. 8. The average duty cycle is 7.32 as required to achieve
based on the design parameters in Table I, are compared in
the value of the setting. Having discrete values for the duty
Fig.6 and Fig.7. It is apparent the derivative component is
cycle slightly affects the regulated voltage.
essential in damping the overshoot and providing stability
compensation. The damping comes from a proper trade-off

TABLE I.

Design Paramenters
Parameter Value Dimension
Main clock frequency 16 MHz

PWM frequency` 1 MHz

L 20 µH
C 40 µF
R in series with C 0.1 Ω
R_load 8 Ω
Figure 8. PWM duty cycle generated by the Σ∆_processor
V_set 2.23 ±0.02 V

3875

Figure 9. Expanded view of the regulared voltage
As shown in Fig. 9 there is some ringing in the crest
output value. The fluctuation is below 2mV. The effect of the
used control is also evident looking at the spectrum of the
regulated voltage after the transient. Fig. 10 compares the
spectrum at the output of a DC/DC regulator with digital
control and that of a conventional buck converter using the
same design parameters. The result is that the noise spectrum
with sigma-delta conversion is higher than the conventional
buck converter, but it has tones lower than -80dB. They are
at a lower level than the peak tones produced by the buck.
The obtained spectrum depends on the value of the regulated
voltage and the design parameters but the above features
remains.
Figure 10. Spectrum of the regulated voltage after the intitial transient.
V. CONCLUSION
This paper presented a new approach for obtaining a
digital-controlled switched-mode DC/DC regulator. The
proposed method utilized low power sigma-delta A/D
conversion. The PWM signal has a discrete duty cycle that
changes like the signal at the output of a multi-level sigma-
delta modulator. Simulated performances show limited
degradation with respect to a conventional buck converter.
However, the method brings about a number of advantages:
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the design is small and because of the passive
implementation of sigma-delta modulator, the overall power
consumption is very low. Design consideration such as
mismatch requirement can be less stringent due to the
oversampling scheme.
In addition, PID control is made possible in the analog or
in the digital domain making the design flexible. The PWM
power-switching scheme makes the design suitable for the
wireless portable power management application. The
proposed solution uses a fixed PWM frequency (fck/N).
However, it is also possible using a time-varying decimation
factor, N, thus permitting a modulation of the frequency used
in the PWM.
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