WCLK

DOUT

BCLK
DIN
4 5 2 3
TLV320AIC3104 Functional Block Diagram with Registers
All Output gains
All Output Volume gains HPLOUT Volume Are Positive in 1 dB steps
Sample Rate Select : (R2)
are in 0.5dB steps (0 to -78dB)
Codec Data Path Setup: (R7)
Audio Serial Data Interface Ctrl: (R8-R10 DAC_L1 Gain:
(R47) 0 to 9 dB
DAC_R1 (R50)
PGA_L (R46)
+
To enable Record-Only Digital Audio Processing PGA_R (R49) 19 HPLOUT
(shown with SW-Dx): DAC_L2 (R51)
1. Power Down Both DACs* (R37) All Register Numbers are in Decimal
Audio Serial Bus Interface and in Page 0 Unless Otherwise Noted
Left AGC control:
2. Enable ADC Digital Processing (R107)
(R26-R28, R32, R34, 3. 3-D Processing is not available in Record Mode
R103-R104) *DACs must be powered down in order to use ADC processing HPLCO M Volume

DOUTR
MIC2L

DOUTL
MIC2L/LINE2L/MICDET 14 (R37) Gain:
(0 to -78dB) HPLCOM

DINR

DINL
Gain: (R17, 0 to 9 dB
0 to -12 dB R18) DAC_L1 Drive Ctrl
(R54)
(R107-D3) (R43) DAC_R1 (R37)
1.5dB steps AGC (R57)
Gain: PGA_L (R53) + 20 HPLCOM
Volume PGA_R (R58)
0 to -63.5 dB (R56)
SW-D2 Control VCM
0.5dB steps
Bypass (R12-D3) Bypass (R12-D2)
(R8-D2) DAC_L1
PGA 1st 0 DAC (R37)
MIC1LP / LINE1LP 10 1st Ord DAC_L2 HPRCOM Volume Gain:
MIC1L + 0/59.5dB ADC Order 1 LB1 LB2 deemp
0 (0 to -78dB) 0 to 9 dB HPRCOM
MIC1LM / LINE1LM 11 L DAC_L3
Gain: (R19, 0.5dB steps L HP
SW-D1
1
DAC_L1 (R68) VCM Drive Ctrl
0 to -12 dB R24) Filter P1:R1-R6, P1:R7-R12,
(P1:R16-R21) (R41) DAC_R1 (R71) (R38)
R13-R16 R17-R20
1.5dB steps
(R15) (R12, D6-7) (R8-D2) PGA_L (R67) + 22 HPRCOM
(R107,D7) Normal Left Channel Processing PGA_R
(R70) (R72)
(P1:R65-R70)
PGA_L

Normal Processing and 3-D Processing are

HPROUT Volume
Left ADC PWR Mutually Exclusive. (R8-D2, 3-D Control)
(0 to -78dB)
Ctrl : (R19-D2)
DAC_L1 Gain:
(R61)
DAC_R1 0 to 9 dB
(R64)
Status Registers: L Ch + 1st
PGA_L (R60)
+
1. SC, BP, AGC, etc.(Sticky Int) – R96 (P1:R53-R54)
+ LB2
Ord DAC PGA_R (R63) 23 HPROUT
2. SC, BP, AGC, etc.(Realtime Int) – R97 + + PWR (R37)
3. ADC Flags – R36 + LB1 Atten DAC_R2 (R65)
- - DAC Current
1st
+ RB2
Ord CTL (R109) High Power
R Ch + Output Stage Ctrl SW-L2
Right AGC control: (R40) LINE2LP
(R29-R31, R33, R35,
SW-L1
R105-R106) 3-D Digital Audio Processing LINE1LP
DAC_L3
LEFT_LOP/M Gain:
0 to 9 dB SW-L0
(R107-D3) Volume
AGC (0 to -78dB) 27 LEFT_LOP
DAC_L1 (R82) SW-L3
SW-D4 DAC_R1 (R85) 28 LEFT_LOM
Bypass (R12-D3) Bypass (R12-D2)
(R41) PGA_L
(R81) + (R86)
SW-L4
DAC_R1 PGA_R (R84)
LINE1LM
PGA 1st 1 1 DAC DAC_R2
MIC1RP / LINE1RP 12 LINE1R
+ ADC Order 0 1st Ord R
0/59.5dB HP RB1 RB2 deemp
0 DAC_R3
MIC1RM / LINE1RM 13 (R21, R SW-D3
Gain: 0.5dB steps Filter (R8-D2)
0 to -12 dB R22) P1:R1-R6, P1:R7-R12, (R8-D2) Gain:
(P1:R16-R21) Volume
1.5dB steps (R12, D4-5) R13-R16 R17-R20 0 to -63.5 dB SW-Lx and SW-Rx switches
(R16) Control are programmed in R108
(R107,D6) Normal Left Channel Processing 0.5dB steps
(P1:R71-R76)
(R44)
PGA_R
SW-R2
RIGHT_LOP/M LINE2RP
Right ADC PWR
Ctrl : (R22-D2)
Relevant App notes: Volume
SW-R1
MIC2R/LINE2R 16 LINE2R 1. TLV320AIC3104 Programming Made Easy (SLAA403) (0 to -78dB)
LINE1RP
(R17, 2. Common Noise issues in audio Codecs (SLAA749) DAC_L1 (R89)
Gain:
R18) DAC_R1 (R92)
0 to -12 dB 3. The Built-In AGC Function (SLAA260) PGA_L + SW-R0
1.5dB steps (R88) 29
4. Out-of-Band Noise measurement Issues for Audio Codecs (SLAA313) PGA_R (R91)
SW-R3
5. The Built-In AGC Function (SLAA260)
30
6. Using AIC3x with TDM support (SLAA311) DAC_R3
(R93)
SW-R4
LINE1RM

PLL Regs : (R3-R6)

CODEC_CLKIN : (R101)
MICBIAS Ctrl: CLKDIV_IN/PLLCLK_IN Software Reset (R1)
(R25) Select : R102 I2C Status (R107)

Bias/ Audio Clock I2C Serial

Voltage Supplies Reference Generation Control Bus

BCLK
17 26 25 18 24 21 32 7 6 15 1 31 8 9
IOVDD

MICBIAS
DRVDD

DRVDD

Reset
MCLK
DVDD
AVSS1

AVSS2

SCL

SDA
DRVSS
AVDD

DVSS