PART-B - 6 QUESTIONS(13 MARKS)

Reg. No. 2 1 2 0 1 7 1 0 6
21. Explain the dynamic behavior of MOSFET with neat diagram? (A/M 2018) (UNIT I)
SKR ENGINEERING COLLEGE, CHENNAI - 600123. 22. Derive VI characteristics of NMOS transistor with neat diagram.(N/D 2016) (UNIT I)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING 23. Derive VTC of CMOS Inverter with neat diagram.(N/D 2016) (UNIT I)
INTERNAL TEST 1-QUESTION BANK 24. (i).Explain in detail about scaling principles briefly. (N/D 2017) (UNIT I)
(ii).Derive the noise margin of CMOS INVERTER. (A/M 2018) (UNIT I)
Subject code: EC6601 Date:28 /01/19
25. (i).Explain briefly about NP CMOS logic. (UNIT II)
Subject Title: VLSI DESIGN Time : 9.30 -11.30
(ii). Write short notes on Ratioed logic. (N/D 2016) (UNIT II)
Branch / Year: ECE / III Max. Marks: 65
QP CODE:61063 26. (i).Design MUX using transmission gate. (UNIT II)
PART-A (20×2 = 40 Marks) (ii). Write short notes on Dynamic circuits. (N/D 2016) (UNIT II)
1. What is velocity saturation effect? (A/M 2018)(UNIT I)
2. What is meant by channel length modulation in NMOS transistor? (A/M 2017) (UNIT PART-C - 3 QUESTIONS( 15 MARKS)
I) 27. Estimate the least delay and determine the input capacitance of each stage for the
3. Define propagation delay of CMOS inverter? (A/M 2017) (UNIT I) logic network shown in fig. which may represent the critical path of a more logical
4. Draw stick diagram and layout diagram of CMOS inverter. (N/D 2016) (UNIT I) complex circuits. The output of a is loaded network with a capacitance which is 5 times
6. What is the value of Vout for the fig below. Where Vtn is threshold voltage of larger than the input capacitance of the first gate, which is minimum sized transistor.
transistor? (N/D 2016) (UNIT II) (N/D 2017)
7. What is latch up? How to prevent latch up? (A/M 2016) (UNIT I)
8. Why PMOS transistor is used as a pull up transistor? (UNIT II) (page 2 of 3)
9. What are the types of layout design rules? (UNIT I)
10. Design using PTL. (UNIT II)(PROBLEM) 28. Implement the equation X XXXXXXX XXXXXX using complementary CMOS. Size
11. Why dynamic gates are not to be cascaded? (UNIT II) the devices so that the output resistance is the same as that of an inverter with an NMOS
12. What are the operating mode of transistor? (UNIT II) W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best
13. problem on VI CHARACTERISTICS. equivalent pull-up or pull-down resistance? (UNIT II) (N/D 2018)
14. Design OR/NOR gate using DCVSL? (UNIT II) 29. Consider the circuit of Figure below (UNIT II) (N/D 2018)
15. What is meant by HOT CARRIER effect? (UNIT I)
16. What is Substrate bias? Write the expression for threshold voltage. (N/D 2016) a. What is the logic function implemented by the CMOS transistor network? Size the
(UNIT I) NMOS and PMOS devices so that the output resistance is the same as that of an
17. Mention the advantage of Domino logic. (UNIT II) inverter with an NMOS W/L = 4 and PMOS W/L = 8.
18. What is the advantage of Ratioed logic? (UNIT II)
19. Draw 3 input NAND gate using Pseudo NMOS logic. (A/M 2016)
20. Define Noise margin. (UNIT I)
b. What are the input patterns that give the worst case tpHL and tpLH. State clearly what
are the initial input patterns and which input(s) has to make a transition in order to
achieve this maximum propagation delay.
c. If P(A=1)=0.5, P(B=1)=0.2, P(C=1)=0.3 and P(D=1)=1, determine the power
dissipation in the logic gate. Assume VDD=2.5V, Cout=30fF and fclk=250MHz