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Fast Delayed Signal Cancellation based PLL for Unbalanced Grid Conditions
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Abstract—Frequency identification is one of the most critical becomes deficient due to the presence of a negative sequence
issues for grid-connected power converters, especially when the component of the grid voltage. Therefore, different PLL
grid is unbalanced or distorted. Therefore, this paper proposes structures incorporate negative and positive sequence compo-
a novel frequency estimator with fast convergence for balance
and unbalanced grid-voltage faults. The proposed algorithm is nents separation. Typical examples are the Dual Synchronous
based on a Phase Locked Loop (PLL), enhanced with a fast Reference Frame (DSFR) PLL [10], the Dual Second Order
positive and negative sequence detector. Delayed Signal Cancel- Generalised Integrator (DSOGI) PLL [2], and the Delayed
lation methodology with fast convergence is investigated under Signal Cancellation (DSC) PLL [11]. The main disadvantage
single-phase and two-phase voltage dip. The effectiveness of the of using DSRF-PLL, DSOGI-PLL and DSC-PLL is that at
proposed PLL is validated using simulations and experimental
results. least, a significant delay T /4 (5 ms for 50 Hz) is introduced
in the positive and negative sequence components, affecting
Keywords—Phase Locked Loop, Double Synchronous Ref-
the frequency estimation. In digital implementations, the ratio
erence Frame, Double Second Order Generalized Integrator,
Delayed Signal Cancellation. T /4Ts (where Ts is the sample time) must be an integer,
which is not always feasible [12]. In this context, this paper
proposes a novel PLL structure equipped with a Fast Delayed
I. I NTRODUCTION
Signal Cancellation (FDSC) algorithm. Using the proposed
Proper synchronisation is one of the most critical control FDSC-PLL the delay of T /4 can be significantly reduced
tasks for grid-connected power electronics, especially in the and, therefore, the frequency estimation is enhanced. The
connection of distributed generators which need information effectiveness of the proposed PLL is validated using sim-
of the amplitude, phase and frequency of the grid-voltages ulations and experimental results. The rest of this paper is
[1]. As the amount of distributed generation connected to the organised as follows: Section II first provides an overview of
grid increases, grid code and standards have become stricter the conventional PLL systems Then Section III presents the
to prevent grid instability [2], [3]. Therefore, fast and accurate proposed FDSC-PLL structure. Simulations results are shown
detection of the grid-frequency is necessary to fulfil grid codes in Section IV and experimental results in Section V. Finally,
[4], [5]. To achieve grid-frequency and grid synchronisation, Section VI presents conclusions.
many different techniques can be employed. The first one is the
zero-crossing method that finds the zero-crossing points of the
II. OVERVIEW OF PLL STRUCTURE FOR UNBALANCE
grid-voltage to calculate the phase and frequency. However,
GRID - VOLTAGE CONDITIONS
this method can only detect the phase information at each
half cycle, which reduces its performance [6]. The angle and In this section the most used PLL structure for unbalance
frequency of the grid-voltage can be obtained using filtering grid conditions are briefly described.
methods implemented in αβ or dq frames, considering that
the filter has to be appropriately designed to avoid undesired A. Double Synchronous Reference Frame PLL
delays and oscillations [7], [8]. This method was introduced as an improvement of the SRF-
The most commonly used grid-frequency estimator are PLL [10]. The main limitations of SRF-PLLs lie in the poor
PLLs implemented in Synchronous Reference Frame (SRF) performance when the grid-voltage is unbalanced, or it has
[9]. In this case, the grid-voltages are transformed to a dq harmonic contamination. In these cases, low bandwidth filters
reference frame controlling the angular position of this ref- are used to reject the effects of the harmonics at the output of
erence frame. A feedback control loop regulates the quadra- the PLL. However, the use of filters slow-down the dynamic
ture component to zero, and then the direct component will response of the PLL.
depict the same phase and frequency than the grid voltage. The DSRF-PLL identifies the positive and negative se-
SRFPLLs yield to an effective frequency and phase estimation quence components. Additionally, it has a decoupling network
under balanced grid conditions [1]. However, when the grid that allows cancelling the double frequency oscillations that
voltage presents harmonic distortion or unbalances, SRF-PLLs are generated in the quadrature voltage vq due to the negative
D. Guajardo, C. Contreras, M. Diaz, and F. Rojas are with the Department sequence voltage [10]. Therefore, the bandwidth of the PLL
of Electrical Engineering, University of Santiago of Chile is not reduced which results in a more accurate identification
M. Espinoza is with the Department of Electrical Engineering, University of the frequency and most suitable instantaneous phase angle
of Costa Rica.
R. Cardenas is with the Department of Electrical Engineering, University estimation. In fig. 1, a diagram of DSRF-PLL method is
of Chile. shown.
Fig. 3: DSC-PLL.
Voltage
100
(6)
(V)
− e−jθd [vgp ej(wt−θd ) +vgn e−j(wt−θd ) ] 0
-100
By simple inspection of (6) it is concluded that the negative
-200
sequence: (a)
200
p vs
Voltage
v̂gαβ = 100
[1 − e−j2θd ]
(V)
0
(7)
p [vg (wt) − e−jθd vg (wt − θd )](1 − ej2θd ) -100
v̂gαβ =
2[1 − cos(2θd )] -200
p (b)
where v̂gαβ .The negative sequence component is cancelled, 200
obtaining the following expression:
Voltage
100
(V)
0
n [vg (wt) − ejθd vg (wt − θd )](1 − e−j2θd ) -100
v̂gαβ = (8)
2[1 − cos(2θd )] -200
0.9 1.0 1.1 1.2 1.3
It can be shown that (7) and (8) are equivalent to (1)and (2) (c)
when θd → 0. The time delay of NTs seconds corresponds
Time(s)
to a delay angle of θd rads. For instance, the delay is T4 56
Frequency
for the conventional DSC which correspond to delay angle
of θd = ω ∗ T /4 = π/2. Notice that the use of θd > π2 is also
(HZ)
50
possible. Using (7) and (8) and separating by αβ-components,
the following expressions are obtained:
44
k1 − k1 cos(2θd ) + k2 sin(2θd ) 0.970 0.980 0.990 1.000 1.010 1.020 1.030
v̂αp = (9) (d)
2[1 − cos(2θd )]
Time (s)
k2 − k2 cos(2θd ) − k1 sin(2θd )
v̂βp = (10) Fig. 4: Response during 50% single phase voltage dip: a)
2[1 − cos(2θd )]
Voltages ABC , b)Voltage αβ+, c)Voltage αβ-, d) Frequency
k3 − k3 cos(2θd ) + k4 sin(2θd ) PLLs
v̂αn = (11) 200
2[1 − cos(2θd )]
100
Voltage
k4 − k4 cos(2θd ) − k3 sin(2θd )
(V)
v̂βn = (12) 0
2[1 − cos(2θd )]
-100
where k1 , k2 , k3 , and k4 stand for: -200
0.9 1.0 1.1 1.2 1.3
θd θd
k1 = vgα − vgα cos(θd ) − vgβ sin(θd ) (13) (a)
Time (s)
θd θd 56
Frequency
50 DSC-PLL
θd θd DSOGI-PLL
k3 = vgα − vgα cos(θd ) + vgβ sin(θd ) (15)
44
0.970 0.980 0.990 1.000 1.010 1.020 1.030
θd θd
k4 = vgβ − vgβ cos(θd ) − vgα sin(θd ) (16) (b)
Time (s)
IV. S IMULATION RESULTS
Fig. 5: Response during 50% two-phase voltage dip: a) Voltage
Three PLL are implemented in PLECS for an unbalance ABC, b)Frequency PLLs
three phase circuit, which has the same parameters than the
experimental setup (see Fig. X). The source feed three methods
V. E XPERIMENTAL I MPLEMENTATION
for component sequences separation DSOGI-PLL, DSC-PLL
and FastDSC-PLL. In this case, a single-phase and two-phase The experimental setup is presented in Fig. 7, and it
voltage dip is tested for 200 ms. The voltages αβ+,αβ− comprises a control platform and a power stage. The control
and frequencies for 50% single phase voltage dip is presented platform is composed of a Texas-Instrument Digital Signal
in Fig. (4). The responses of frequencies for 50% two-phase Processor (DSP) connected to an Actel Field Programmable
voltage dip is presented in Fig. (5). Gate Array (FPGA) board. The DSP board used in this
Fig. 6: Proposed FDSC-PLL.
application is based on a TMS320C67 processor. For data that the overshot obtained with θd = T /20 (FDSC-PLL) is
acquisition purposes, a ten analogue-digital channels board is higher than θd = T /4 (DSC-PLL), but FDSC-PLL is faster
incorporated in the FPGA board. A sampling frequency of than DSC-PLL.
10 kHz is used. Hall-Effect transducers are used to measure
the voltages and currents. The power stage is composed of
a three-phase voltage source connected to an RL load. The
voltage source is emulated using an AC programmable power
source used to generate single and two phases voltage dips.
In the experimental implementation, three methods have been
considered: DSOGI-PLL, DSC-PLL, and FDSC-PLL. The
implementations of the FDSC-PLL method was programmed
with delays of T /4 (conventional DSC) and T /20.
In the experimental implementation, the same faults than in
simulation were tested, as shown in Fig. 8(a) and Fig. 9(a)
In this case, the tests were performed with the same failure
times than the used for the simulation results, where a single-
phase fault is observed in Fig. 8, and a two-phase fault are
illustrated Fig. 9.
𝑇𝑟𝑎𝑛𝑠𝑑𝑢𝑐𝑒𝑟𝑠
𝐻𝑎𝑙𝑙 − 𝐸𝑓𝑒𝑐𝑡
𝑯𝒐𝒔𝒕 𝑷𝑪
𝑪𝒐𝒏𝒕𝒓𝒐𝒍 𝑺𝒚𝒔𝒕𝒆𝒎
Fig. 7: Diagram of the experimental implementation. Fig. 8: Experimental Results for 50% single-phase voltage
dip: a) Voltages ABC , b)Voltage αβ+, c)Voltage αβ-, d)
The experimental results presented in Fig.8 show that the Frequency PLLs
overshot is increased as the delay is reduced. This is due to the
derivative implicit in (7)-(8) [12]. For example, Fig.8 shows
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Signal Cancellation Method for Sequence Component Separation,” IEEE
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been proposed as a frequency estimator for unbalance grid- 2015. [Online]. Available: http://ieeexplore.ieee.org/document/6963423/
voltage conditions. The proposed FDSC-PLL has been tested
for single-phase and two-phase grid-voltage faults, and it
has been compared with state-of-the-art algorithms such as
DSOGI-PLL and DSC-PLL, with good performance and faster
convergence. However, as anticipated by smaller values of
θd imply more noise and overshoot. Therefore, a trade-off
between noise, overshoot and delay should be considered
according to the application.
ACKNOWLEDGMENT
The support of University of Santiago of Chile through
DICYT Projects 091813DD and 091813DD-RED is kindly
acknowledged. The support provided by Fondecyt Project
1180879 and Basal Project F B0008 is kindly acknowledged.
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