A High-Speed Low-Power D Flip-Flop

Rajasekaran Chandrasekaran" 2, Yong Lian1'2, Ram Singh Rana'

lInstitute of Microelectronics, Singapore. ramrana@ime.a-star.edu.sg
2Department of ECE, National University of Singapore. Singapore {g030579 1, eleliany } (nus.edu.sg

Abstract - This paper proposes a new D flip-flop configuration consists of both the true and complement forms. The
based on Differential Cascode Voltage Switch with Pass-Gate sampling operation is usually done by a stack of transistors
Logic. The circuit is able to reduce the transition time from the forming a pull-down and gated by the D input and the clock.
input to output. The flip-flop was implemented in 0.18 ftm
CMOS technology. The flip-flop was simulated using HSPICE
to assess the performance and was further evaluated by
measurements on a test chip. The maximum operating
frequency of the flip-flop is 5 GHz according to simulation. The
test chip operates correctly at 3 GHz. This performance makes
it one of the fastest flip-flops with a rail-to-rail input and voltage
swing.

I. Introduction
Fig 1 Multiplexer Based Flip-Flop
Flip-flops are an integral part of digital systems as they
form the core of the timing circuits. The system clock
controls the rhythm of the chip. The high density of modem Some variations involve pre-charge and evaluation phases,
digital processors increases the clock load. With increasing wherein the outputs are pulled usually to the high state during
requirement for high-speed and low power, flip-flops with the pre-charge phase and during the evaluation phase, the
fewer transistors are preferred for their low power inputs are sampled and the output changed accordingly [2].
consumption and small area occupation. The proliferation of One such implementation is shown in Fig. 2.
logic circuits with very small propagation delay also forces
the flip-flops to have very small latency as otherwise the
flip-flop delay occupies a larger part of the clock cycle.
Many schemes have been proposed in the literature [1-5]
for flip-flops with very few transistors. Most of them use
either transmission gates or multiplexers in order to reduce
the latency of the flip-flop. The latching of the input is
usually done using a sense amplifier. Other implementations
employ a differential latch type configuration either with or
without a pre-charge and evaluation cycles.
Multiplexer based implementations normally implement
the latches using multiplexers [2]. The flip-flop is constructed
as a cascade of two latches triggered by opposite phases of
the clock. Their efficiency is dependent on the fast operation Fig 2 Differential Flip-Flop
ofthe multiplexers and the ability of the multiplexer circuit to
function as a latch. A multiplexer based flip-flop is shown in The flip-flops discussed above sample the input at either
Fig. 1. This implementation can employ very few transistors the rising or the falling edge of the clock. This necessitates
depending on the multiplexer. The main drawback is that the that the clock be at a higher frequency than the data rate.
latching operation can be weak reducing the ability of the Double edge triggered flip-flops [6, 7] sample the input at
flip-flop to drive large loads. both the edges of the clock thereby allowing twice the data
rate at the same clock frequency. These usually include a
Another implementation uses cross-coupled pMOS multiplexer functionality built into them. WVhen one of the
transistors or sense-amplifiers to perform the latching latches is in the hold state, the other latch samples the input
operation [2-4]. This requires that the input to the flip-flop data. In this way, data is transferred at both the edges of a

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clock cycle. The implementation is shown in Fig. 3. logic is of use in minimizing the transistor count. The
feedback connection of the pMOS transistors serves to latch
the output. The addition of a clock function makes these
circuits function as a flip-flop with added logic.
An implementation of the flip-flop using DCVSPG [9] is
shown in Fig. 5. The circuit uses two latches, one using
nMOS transistors and one using pMOS transistors. The use
of complementary latches eliminates the need for two clock
signals as the latches are operated by the opposite phases of a
single clock.
out
+
_1r- +
r
Fig 3 DET Flip-Flop L.
+ L-+
In applications where the transistor count is required to be
low, due to area or power considerations, flip-flops can be Fig 5 DCVSPG Flip-Flop using complementary latches
implemented using transmission gates and inverters as shown
in Fig 4. [1] The transmission gates serve to transmit the input The use of the pMOS latch severely undermines the
during the sample phase and the inverter sense-amplifiers performance of the flip-flop as the delay of the latch in
hold the output value in the latch phase. The feedback transferring the input depends on the pMOS input transistors.
inverters need to be of smaller size than those of the forward The presence of transistors in series also contributes to an
path to reduce the power consumption and the transfer delay increase in delay.
that is dependent on the transmission-gate inverter series
path.
III. Proposed D Flip-Flop Circuit
A new D-latch circuit is presented in Fig. 6. The output
expressions of a D-latch with differential inputs can be given
as

Fig 4 Transmission Gate Flip-Flop Q=D-CLK+Q-CLK (1)

In this paper, we present a new D Flip-Flop circuit based
on the principle of Differential Cascode Voltage Switch with
Pass-Gate (DCVSPG) [7]. The proposed D Flip-Flop is able
to operate at very high speed while the power consumption is
kept low. The paper is organized as follows. Section II
explains the functioning of the DCVSPG flip-flop followed
by the discussion of the proposed flip-flop circuit in Section
III. In Section IV, the simulation and measurement results are
presented. Section V concludes the paper with a summary.
II. DCVSPG Logic and Flip-Flop
Differential Cascode Voltage Switch with Pass-Gate
(DCVSPG) Logic [8] is derived from Differential Cascode
Voltage Switch (DCVS) Logic and Pass transistor logic
combining the advantages of both. The combination of the
two makes the implementation of the logic ratio-free. This
translates to the optimization of the individual transistors for
high performance. The high logic functionality of Pass gate
Q=D-CLK+Q.CLK
The above expressions express the sample and latching
operations. When CLK goes high, the pass transistors are
switched on and the input is is transferred to the output. The
complementary inputs pull one of the outputs down and the
other output is pulled up by the latching action of the
cross-connected pMOS transistors. The latch remains out of
operation as the transistor controlling it is switched off by the
low CLK . The use of pass transistor helps reduce the delay of
passing the data to the output as the delay depends entirely on
a single transistor. Another factor contributing to the fast
transfer of the input to the output is that the pull-up of the
output need not be done for the whole logic level. The input
pass transistor passes a weak high logic, which aids the
pull-up thereby reducing the transfer delay.
When CLK goes low and CLK is high, the latch is

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activated and it holds the value until CLK goes high again.
The control of the regeneration circuit by the CLK signal
reduces the possibility of the latching wrong data due to
spurious inputs. The transfer delay of the flip-flop is also
influenced by the size of the latching transistor pair, as the
input pass transistor is loaded by the latch. A very small
latching transistor leads to a fast transfer of the input to the
output but the regenerative gain of the latch becomes too low
to hold the transferred value. A large transistor increases the
load on the input leading to a reduction in the operating speed
of the circuit. Hence, the latch sizing is a trade-off between
speed and regenerative gain. The transistors used in the
proposed D-latch circuit all have minimum length. The
widths of the transistors have been optimized for high-speed
operation.
functionality of the flip-flop is tested using input at half the
rate of the clock signal. The resulting output follows the input
and the maximum operating frequency can be easily verified.
The results of simulation for a clock frequency of 5 GHz and
input data rate of 2.5 Gbps is shown in Fig. 8. The power
consumed at 5 GHz by the flip-flop was found to be 2 mW.
The flip-flop was implemented in a test chip with the
inputs driven by buffers. The complementary D inputs
required by the full adder were generated using inverters in
the chip. The performance was tested by applying sinusoidal
signals to the inputs. The complementary clock inputs
required by the flip-flop were fed from outside the chip. To
generate the complementary inputs without any skew, the
CLK and CLK inputs were connected via a 1800 power
splitter with added DC bias to ensure voltage swing from
0-1.8 V.

Do

-Q
Q 'QB CLI D
Flip-Flop _-QB
CLK
C LKB 4>0
Fig 7 Test Circuit for Simulation

CL
D DB

CLKB

Fig 6 Proposed D Latch circuit

The flip-flop is formed by cascading two latch circuits in a

master-slave configuration. Since both the latches are
required to work at the same speed, separate sizing for the
slave latch is not necessary.

IV. Simulation, Measurement and Results

The layout of the D flip-flop is developed using Cadence.
The post-layout simulations have been done using HSPICE
for a 0.18 pim/1.8 V CMOS technology. All the transistors
have minimum channel length. Since flip-flops are normally
used in cascade with other such cells, their inputs may not be Fig 8 D Flip-Flop simulation results for a clock frequency of 5 GHz
ideal. To simulate the actual operating conditions, as closely and input of 2.5 GHz
as possible, the setup shown in Fig. 7 is used. The

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 The input D was fed from another signal source with a DC
bias. The outputs at 1.5 Gbps corresponding to an input of 1.5
GHz and clock of 3 GHz are shown in Fig. 9. The power
consumption of the flip-flop core could not be measures as
the power supply was shared by the buffers driving the output.
The total power consumption including the buffers was
measured to be 20 mW as compared to 12 mW when the test
set-up was simulated using HSPICE.
Volume: 35, Issue: 6 , June 2000, Page(s):876 - 884.
[4] Jimenez R., Parra P., Sanmartin P., Acosta A.,
"High-performance edge-triggered flip-flops using
weak-branch differential latch," Electronics Letters
Volume 38, Issue 21, 10 Oct. 2002 Page(s):1243 - 1244
[5] Jian Zhou, Jin Liu, and Dian Zhou, "Reduced setup time
static D flip-flop," Electronics Letters, Volume 37, Issue
5, 1 Mar 2001, Page(s):279 - 280.
[6] Pedram. M, Qing Wu, and Xunwei Wu, "A new design
of double edge triggered flip-flops," Proceedings of the
ASP-DAC 1998. 10-13 Feb. 1998, Page(s):417 - 421.
[7] Johnson T.A., Kourtev I.S., "A single latch, high speed
double-edge triggered flip-flop (DETFF),"
The 8th IEEE Intemational Conference on Electronics,
Circuits and Systems, Volume 1, 2-5 Sept. 2001,
Page(s): 189 - 192 vol.1
[8] Fang-Shi Lai, and Wei Hwang, "Design and
implementation of differential cascode voltage switch
with pass-gate (DCVSPG) logic for high-performance
digital systems," IEEE Joumal of Solid-State Circuits,
Vol. 32, Issue 4, April 1997, Page(s):563 - 573.
[9] Afghahi, M., "A robust single phase clocking for low
power, high-speed VLSI applications,"- IEEE Journal of
Solid-State Circuits, Volume 31, Issue 2, Feb. 1996,
Page(s):247 - 254.

Fig 9 Test results for clock of 3 GHz and D input of 1.5 GHz

V. Conclusions
A D flip-flop circuit has been introduced which offers
high-speed consuming less power. It uses a pass transistor
implementation to sample the input and a DCVSPG style
latching stage. It overcomes the threshold voltage problem
associated with pass transistor circuits and produces full
voltage swing at the output. This circuit has a very small
latency and can be used for high-speed applications.

References
[1] Uming Ko, and Balsara P.T., "High-performance
energy-efficient D-flip-flop circuits," IEEE Transactions
on Very Large Scale Integration Systems, Vol. 8, Issue
1, Feb. 2000, Page(s):94 - 98.
[2] Li Ding; Mazumder, and P.; Srinivas, N., "A dual-rail
static edge-triggered latch," The 2001 IEEE
International Symposium on Circuits and Systems,
Volume: 2, 6-9 May 2001 Page(s):645 - 648 vol. 2.
[3] Nikolic B., Oklobdzija V.G., Stojanovic. V., Wenyan Jia,
James Kar-Shing Chiu, Ming-Tak Leung, M., "Improved
sense-amplifier-based flip-flop: design and
measurements," IEEE Journal of Solid-State Circuits,

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