Roll No.

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DEPARTMENT OF ELECTRONICS & INSTRUMENTATION ENGINEERING

KAKATIYA INSTITUTE OF TECHNOLOGY & SCIENCE:: WARANGAL – 15
(An Autonomous Institute under Kakatiya University, Warangal)
M.Tech (VLSI & Embedded Systems) II Semester I-Mid Examinations
P14VE205A ASIC DESIGN

Time: 2 Hours
Date of Examination: 12.03.2016 Max. Marks: 25

Note: Question No.1 Compulsory.

1 a) List out the information associated with a cell in a cell library. [2]
b) What are the advantages of programmable ASIC. [1½]
c) Illustrate the operation of anti-fuses. [2]
d) State the difference between the logic synthesis & simulation. [1½]

2 a) With a neat diagram, explain in detail ASIC Design flow. [3]

b) Compare EPROM &EEPROM technologies with respect to erasing mechanism. [3]

(OR)
c) Explain the configurable logic block of Xilinx XC 4000. [3]
d) Explain about transistor parasitic capacitance. [3]

3 a) Explain the different types ASIC with neat diagrams. [6]

(OR)
b) Explain the ACTEL ACT1 logic module. [3]

c) What are the logic expanders? How are they used to implement the logic design? [3]

4 a) Describe the salient features of Xilinx LCA interconnect architecture. [3]

b) Explain about SRAM. [3]
(OR)
c) Explain about metal-metal anti-fuse. [3]
d) Explain the configurable logic block of Xilinx XC 5200. [3]

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Paper set by
G. Raju,
Asst. Professor