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PART-B ( 8X10=80)
1. Draw the CMOS logic circuit for the Boolean expression Z=[A(B+C)+DE]’ an explain
2. Explain the basic principle of transmission gate in CMOS design
3. Explain the domino logic with neat diagram
4. Discuss the low power design principle in detail
5. Write short notes on Ratioed circuits
6. Discuss about dynamic CMOS circuits
7. Explain the dynamic power dissipation in CMOS circuits with necessary diagrams and
expression
8. Estimate least delay and determine input capacitance of each stages for the logic
network shown in fig , which may be represent the critical path of a more complex logic
block this output of the network is loaded with capacitance which is 5 time larger than
the input capacitance of the first stage which is a minimum sized inverter
THIRUVALLUVAR COLLEGE OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
EC 6601-VLSI DESIGN
ASSESMENT TEST – II
PART-B ( 8X10=80)
9. Draw the CMOS logic circuit for the Boolean expression Z=[A(B+C)+DE]’ an explain
10. Explain the basic principle of transmission gate in CMOS design
11. Explain the domino logic with neat diagram
12. Discuss the low power design principle in detail
13. Write short notes on Ratioed circuits
14. Discuss about dynamic CMOS circuits
15. Explain the dynamic power dissipation in CMOS circuits with necessary diagrams
and expression
16. Estimate least delay and determine input capacitance of each stages for the logic
network shown in fig , which may be represent the critical path of a more complex logic
block this output of the network is loaded with capacitance which is 5 time larger than
the input capacitance of the first stage which is a minimum sized inverter