DESIGINE AND IMPLIMENTATION OF APPLICATION SPECIFIC

LOW POWER MULTIPLIERS

1.INTRODUCTION
Multipliers play a critical part in recent digitalized life. In this advanced sphere, many
investigation are going to propose multipliers with high speed rate, less power utilization or
periodic arrangement and small size. Integration of them in a single multiplier allows to use
for applications with less competence, high speed rate and dense VLSI application. The
common multiplication method is "add and shift" algorithm. In this paper various low power
multiplier design techniques are analysed which includes selective activation approach, DCT
flow graph algorithm, multiplier less design in FPGA, 2-signed 2 dimensional bypassing
array multiplier, column bypassing multiplier and so on. Energy consumption and power
dissipation issues become increasingly important due to the proliferation of portable devices
and their requirement for extended battery life, the wide-spread use of very high density
circuits and the related heat management issues, as well as the need for the reduction of the
operation cost of green server farms. Over the last decades, a huge research effort has been
devoted to reduce power consumed by digital processing circuits. Starting from transistor-
level techniques up to algorithm selection and system-level optimization, remarkable
progress has been achieved. Substantial power reduction in a contemporary system can be
achieved at the algorithmic and system level; however such techniques can be combined with
the optimization of basic hardware processing units, further reducing power and energy
requirements. Total power utilization of a digital system is the sum of three terms, namely
dynamic power, static or power leakage, and closed-circuit power.

TITLE: DESIGNE AND IMPLIMENTATION OF LOW POWER MULTIPLIERS Page 1

2.LITERATURE SURVEY

1. Nan-Ying Shen et al (2002) presented Low-power 2's complement multipliers are

developed through minimizing switching activities of partial products using the radix-4
Booth algorithm. Before computation, the input datum with the smaller effective dynamic
range is processed to generate Booth codes, thereby increasing probabilities of partial
products being zero. By employing the dynamic-range determination units to control input
data paths, the proposed 16×16-bit multipliers based on the Yu, Goldovsky, and Mahant-
Shetti's low-power approaches are individually implemented. It illustrates the proposed
multiplier having low-power dissipation; the theoretical analyses of switching activities of
partial products are derived. Compared to the power consumed by the conventional
multipliers. The proposed multipliers conserve more than 14%, 30% and 31% of power,
respectively.

2. More & Kshirsagar (2011) presented low power Column bypass multiplier design
methodology that inserts more number of zeros in the multiplicand thereby reducing the
number of switching activities as well as power consumption. The switching activity of the
component used in the design depends on the input bit coefficient. This means if the input bit
coefficient is zero, corresponding row or column of adders need not be activated. If
multiplicand contains more zeros, higher power reduction can be achieved. To reduce the
switching activity is to shut down the idle part of the circuit, which is not in operating
condition. Use of look up table is an added feature to this design. Further, low power adder
structure reduces the switching activity. Flexibility is another critical requirement that
mandates the use of programmable components like FPGAs in such devices.

TITLE: DESIGNE AND IMPLIMENTATION OF LOW POWER MULTIPLIERS Page 2

3.PROPOSED WORK

we propose two architectures for two-input signed multipliers, namely selective activation
multiplier and partitioned multiplier. Multipliers play a critical part in recent digitalized life.
In this advanced sphere, many investigation are going to propose multipliers with high speed
rate, less power utilization or periodic arrangement and small size. Integration of them in a
single multiplier allows to use for applications with less competence, high speed rate and
dense VLSI application. The common multiplication method is "add and shift" algorithm. In
this paper various low power multiplier design techniques are analyzed which includes
selective activation approach, DCT flow graph algorithm, multiplier less design in FPGA, 2-
signed 2 dimensional bypassing array multiplier, column bypassing multiplier and so on.

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3(a).PROBLEM DEFENATION
The problem definition in the existing system is “Reduce power by minimizing the
switching activity of partial products using the selective activation multipliers algorithm
along with a DRD (Dynamic Range Determination) and the partitioned method multipliers”.

TITLE: DESIGNE AND IMPLIMENTATION OF LOW POWER MULTIPLIERS Page 3

3(b).BLOCK DIAGRAM

An earlier version of the architecture presented here is reported. Here we introduce

optimizations to further decrease power consumption. The main idea of the proposed
selective-activation multipliers is that the architecture provides two paths, one for small-
number and one for large-number multiplications.

Figure 3.1
When a value is within a predefined range then the path for small-number multiplication is
utilized while the other part remains inactive. When a value is outside of the predefined range
then the path for large-number multiplication is used. The proposed system is shown in Fig.1.
On left side large no of multiplication is shown while small-number multiplication is
implemented on right side
.

TITLE: DESIGNE AND IMPLIMENTATION OF LOW POWER MULTIPLIERS Page 4

A partitioned multiplier circuit which is designed for high speed operations. The multiplier of
the present invention can perform one 32x32 bit multiplication, two 16x16 bit multiplications
(simultaneously) or four 8x8 bit multiplications (simultaneously) depending on input
partitioning signals. The time required to perform either the 32x32 bit or the 16x16 bit or the
8x8 bit multiplications is constant. Therefore, multiplication results are available with a
constant latency regardless of operand bit-size. In one embodiment, the latency is two clock
cycles but the multiplier circuit has a throughput of one clock cycle due to pipelining. The

Figure 3.2

The hardware is partitioned without any significant increase in the delay or area and the
multiplier can provide six different modes of operation. In one embodiment, Booth encoding
is used for the generation of 17 partial products which are compressed using a compression
tree into two 64-bit values. This is performed in the first pipeline stage to generate a sum and
a carry vector. These values are then added, in the second pipestage, using a carry propagate
adder circuit to provide a single 64-bit result. In the case of 16x16 bit multiplication, the 64-
bit result contains two 32-bit results. In the case of 8x8 bit multiplication, the 64-bit result

TITLE: DESIGNE AND IMPLIMENTATION OF LOW POWER MULTIPLIERS Page 5

contains four 16-bit results. Due to its high operating speed, the multiplier circuit is
advantageous for use in multi-media applications, such as audio/visual rendering and
playback

3(c).HARDWARE & SOFTWARE

HARDWARE REQUIREMENT
FPGA

Field Programmable Gate Arrays (FPGAs) are programmable semiconductor devices

that are based around a matrix of Configurable Logic Blocks (CLBs) connected through
programmable interconnects. As opposed to Application Specific Integrated Circuits
(ASICs), where the device is custom built for the particular design, FPGAs can be
programmed to the desired application or functionality requirements and One-Time
Programmable (OTP) FPGAs are available. In our project we are using Spartan 3 FPGA kit.

SPARTAN 6

The Spartan 3 trainer xc3s400 pq208 is useful to realize and verify digital designs. User
can construct Verilog /VHDL code and verify the results by implementing physically into the
target device (FPGA). With the help of this kit user can simulate/observe various input and
output conditions to verify the implemented design.

SOFTWARE REQUIREMENT
MODELSIM 6.4C
Modelsim is a simulation tool for hardware design which provides behavioral simulation
of a number of languages, Verilog, VHDL, and System C. Verilog HDL is an industry
standard language used to create analog, digital, and mixed-signal circuits. HDL’s are
languages which are used to describe the functionality of a piece of hardware as opposed to
the execution of sequential instructions like that in a regular software application.

XILINX 9.1/13.2

Xilinx Tools is a synthesize tools used for the design of digital circuits implemented using
Xilinx Field Programmable Gate Array (FPGA). Digital designs can be entered in various
ways using the above CAD tools: using a schematic entry tool, using a hardware description
language (HDL) – Verilog or VHDL or a combination of both..

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4.CONCLUSION
Digital multipliers are one among critical arithmetic units. Power utilization is the crucial
factor to be considered in recent decades, many researches are focusing on low power
architectures. The multiplier architectures presented in this paper can be used as general-
purpose multipliers. Extensive power consumption simulations show that by taking
advantage of the characteristics of the input data and the processing algorithm, the proposed
architectures reduce power consumption. The above surveyed papers present the low power
design along with other features such as lifetime enhancement, low area complexity

5.REFERENCES

[1]A. Kishore Kumar, D. Somasundareswari, V. Duraisamy, and M. Pradeepkumar,

“Low power multiplier design using complementary pass-transistor asynchronous
adiabatic logic,” International Journal on Computer Science and Engineering, vol.
2, no. 7, pp. 2291–2297, 2010.

[2]V. S. K. Bhaaskaran, S. Salivahanan, and D. S. Emmanuel, “Semi-custom design

of adiabatic adder circuits,” in Proceedings of the 19th International Conference on
VLSI Design Held Jointly with 5th International Conference on Embedded
Systems Design, pp. 745–748, January 2006.

[3] Vijayprasath S, Palanivel Rajan S, Performance Investigation of an Implicit

Instrumentation Tool for Deadened Patients Using Common Eye Developments as a
Paradigm, International Journal of Applied Engineering Research, 10 (1), 2015, 925-929.

[4]S. K. Mangal and R. M. Badghare, “FPGA Implementation of Low Power Parallel

Multiplier”, 20th International Conference on VLSI Design, IEEE, 2007

[5] Palanivel Rajan S, Sukanesh R, Experimental Studies on Intelligent, Wearable and

Automated Wireless Mobile TeleAlert System for Continuous Cardiac Surveillance, Journal
of Applied Research and Technology, 11 (1), 2013, 133 - 143.

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