Application-Specific Low-

Power Multipliers
ABSTRACT

In these paper multipliers is mainly focusing for low power. Here we propose two
architectures for two inputs signed multipliers namely selective activation multiplier and
partitioned multiplier. The proposed technique is mainly applied in DCT and DWT Application.
The propose technique Power is reduced up to 20.7%. The proposed multiplier is applied to all
low power techniques with moderate area and time overhead.
 CHAPTER 1

1.INTRODUCTION

1.1 GENERAL

Energy consumption and power dissipation issues become increasingly important due to
the proliferation of portable devices and their requirement for extended battery life, the wide-
spread use of very high density circuits and the related heat management issues, as well as the need
for the reduction of the operation cost of green server farms. Over the last decades, a huge research
effort has been devoted to reduce power consumed by digital processing circuits. Starting from
transistor-level techniques upto algorithm selection and system-level optimization, remarkable
progress has been achieved. Substantial power reduction in a contemporary system can be
achieved at the algorithmic and system level; however such techniques can be combined with the
optimization of basic hardware processing units, further reducing power and energy requirements.

Total power consumption of a digital circuit is the sum of three terms, namely dynamic
power, static or leakage power, and short-circuit power; i.e.,

(1)

Leakage power has emerged as an important component with shrinking technology. The
dynamic power dissipation of a system composed of N components, each operating at voltage V(i)

with clock frequency f(i) and effective capacitance Ceff(i) with i = 1, . . . ,N is given by

(2)

Dynamic power consumption minimization can be achieved by minimizing each term of

(2). Flynn et al. review some of the most widely spread techniques for power reduction. Parhi
illustrates the fundamental design methods based on architectural and data flow graph (DFG)
transformations to reduce power , including retiming, use of parallelism, and pipelining.
 There are several information-theoretic approaches that suggest methods to reduce energy
computation cost. Ramprasad et al. derive bounds of signal transition activity following an
information-theoretic approach . The optimization of quantization on both input and output of a
system is another aspect to be taken into account when minimizing power since it affects both the
amount of data and their characteristics. Xanthopoulos and Chandrakasan present DCT cores and
pinpoint that there is no need to calculate data not required in subsequent steps. This can be done
by masking the clock and, along with other introduced techniques, minimize the power
consumption of DCT cores. Also show that the switching activity of circuits can be dynamically
minimized by designing algorithms that exploit signal statistics. Concerning power consumption
at the architecture level, Landman and Rabaey introduce a strategy for generating accurate black-
box models . They introduce a way to characterize the power consumption based on the switching
activity derived through the exploitation of signals statistics. Among the various approaches to
reduce power dissipation, performance optimization techniques have been employed exploiting
power-delay-area trade-offs.

Several authors have introduced techniques that minimize the contribution of the various
terms in (2). One of the investigated techniques is the reduction of the switching activity. Chen et
al. reduce power by minimizing the switching activity of partial products using the radix-4 Booth
algorithm along with a DRD (Dynamic Range Determination) unit.

Furthermore, several authors have introduced architectural approaches to reduce power

consumption. Following the Baugh-Wooley multiplier, the authors have previously proposed a
technique based on selective activation. Ohban et al. use a method to reduce energy needs by
bypassing the partial products. Park et al. present a multiplier architecture which utilizes the
dynamic operand interchange technique. Kim and Papaefthymiou propose a reconfigurable
pipelined multiplier to achieve high performance and low energy dissipation by adapting its
structure to computation demands over time, targeted for image processing applications. The
basics of multiplier partitioning are highlighted in, where Krithivasan and Schulte introduce
multipliers that support sub-word parallelism and addition features. The goal is to enhance the
performance while keeping the area overhead low. Following, Lin introduces a multiplier matrix
decomposition method to reduce power consumption while keeping high performance.
1.2 OBJECTIVE

Focusing on more complex circuits, several authors combine a multiplier and an adder to
form one component (MAC - Multiplier Accumulator unit) due to area, time and power benefits.
In Chen et al., along with other techniques, emphasize the benefits of a DRD unit in order to
decrease power requirements. The basic idea of partitioning is adopted in where, Han et al. take
into consideration the high spatial redundancy of the input data and they use a cache to store the
values of higher order bits in a partitioned-based multiplier. In addition, they use the Digital
Coefficient Method (DCM), which exploits the high correlation of the data applied in FIR filter.

The multipliers proposed in this paper target application domains where the input data have
specific characteristics similar to Common in such applications are discrete transforms such as
DWT (Discrete Wavelet Transformation) and DCT (Discrete Cosine Transformation) applied to
images, video and audio data. A detailed hardware implementation of DCT is presented the
fundamentals of which are used here. DCT-specific architectures such as replace the multiplier
with a minimum number of additions and shifts in order to decrease power dissipation. However
the particular architecture is dedicated to the specific computation and cannot be used in a more
general context within the application or in similar applications with different coefficients. As a
second test case we study the impact of the proposed multiplier on DWT implementation. A
detailed architecture implementing DWT is presented.

In this article, some techniques for the reduction of power consumed by multipliers are
proposed. The proposed architectures reduce power by exploiting the statistics of the input data.
Benefits are achieved for specific applications. Increased circuit complexity means more static
power dissipation and may increase the overall power needs. There is a trade-off between the
amount of energy that can be saved by circuits that employ DRD (Dynamic Range Determination)
and the energy consumed by the additional circuitry required to implement such processes. Clearly,
if the amount of power saved is less than the power consumed by additional introduced circuitry,
the total power would increase instead of decreasing. Motivated by this observation, we minimize
any additional circuitry required by the proposed method.
1.3 EXISTING SYSTEM

Reduce power by minimizing the switching activity of partial products using the radix-4
Booth algorithm along with a DRD (Dynamic Range Determination) unit Park et al. present a
multiplier architecture which utilizes the dynamic operand interchange technique.

1.4 LITERATURE SURVEY

1. LOW POWER METHODOLOGY MANUAL: FOR SYSTEM-ON-CHIP DESIGN

2. ENERGY REDUCTION IN VLSI COMPUTATION MODULES: AN INFORMATION

THEORETIC APPROACH

3. ARCHITECTURAL POWER ANALYSIS: THE DUAL BIT TYPE METHOD

4. HIGH-SPEED ARITHMETIC IN BINARY COMPUTERS

5. ENERGY DELAY ANALYSIS OF PARTIAL PRODUCT REDUCTION METHODS

FOR PARALLEL MULTIPLIER IMPLEMENTATION