B.

Tech VLSI 2018-2019 Projects

Front End Design(VHDL/Verilog HDL)

S.No Project Name IEEE Year

1 VLSI Design Of Low-Cost And High-Precision Fixed-Point Reconfigurable 2018
FFT Processors
2 Unbiased Rounding for HUB Floating-point Addition 2018
3 A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier 2018
Design
4 Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error 2018
Correction
5 A Low-Power Yet High-Speed Configurable Adder for Approximate Computing 2018
6 The Design and Implementation of Multi – Precision Floating Point Arithmetic 2018
Unit Based on FPGA
7 Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact 2018
Multipliers
8 Efficient Modular Adders based on Reversible Circuits 2018
9 Low-Complexity VLSI Design of Large Integer Multipliers for Fully 2018
Homomorphic Encryption
10 Design of 5 port router for network on chip using FPGA 2018
11 Design And Implementation Of A Novel PRPG for Low Power Applications 2017
12 Design of MAC Unit For DSP Applications Using Verilog HDL 2017
13 Floating-Point Butterfly Architecture Based On Multi Operand Adders 2017
14 VLSI Architecture For Montgomery Modular Multiplication Algorithm By 2017
Using Pasta Adder
15 Pre encoded Multiplier Architecture Based On NR4SD Encoding Technique For 2017
DSP Applications
16 Design And Implementation Of High Speed Accelerator Using Carry Save 2017
Adder
17 A Transparent Test Technique For Detection Of Faults In FIFO Buffers Of NOC 2017
Routers
18 Design Of 16-Bit Multiplier Using Modified Gate Diffusion Input Logic 2017
19 An Optimized Implementation Of IEEE-754 Floating Point Multiplier For DSP 2017
Applications
20 Efficient Architecture For Processing Of Two Independent Data Streams Using 2017
Radix-2 FFT
21 High Throughput DA-Based Fir Filter For FPGA Implementation 2017
22 Low Power And Area Efficient Carry Select Adder With Binary To Excess-1 2016
Converter
23 VLSI Design Of High Speed Vedic Multiplier For FPGA Implementation 2016
Head Office:Flat No 202, 2nd Floor, Pancom Business Center, Beside Opp: Chennai Shopping
Mall, Ameerpet, Hyderabad.Ph: 040-4443 3434, Dilsukhnagar: 9000404181, Warangal: 9000739460,
Vijayawada: 9000404182,
24 A Review On Power Optimized TPG Using LP-LFSR For Low Power BIST 2016
25 FPGA Based Hardware Implementation Of AES Rijndael Algorithm For 2016
Encryption And Decryption.
26 A Modified Partial Product Generator For Redundant Binary Multipliers 2016
27 Pipeline And Parallel Processor Architecture For Fast Computation Of 3D-DWT 2016
Using Modified Lifting Scheme
28 Hybrid LUT/Multiplexer FPGA Logic Architectures 2016
29 A Synergetic Use Of Bloom Filters For Error Detection And Correction 2015
30 Fault Tolerant Parallel Filters Based On Error Correction Codes 2015
31 High-Throughput Finite Field Multipliers Using Redundant Basis For FPGA 2015
And ASIC Implementations
32 Recursive Approach To The Design of a Parallel Self-Timed Adder 2015
33 Low Delay Single Symbol Error Correction Codes Based On Reed Solomon 2015
Codes
Back End Design
34 Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates 2018
35 Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized 2018
Full Adder
36 Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line 2017
Decoders.
37 Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver 2017
Design.
38 A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell. 2017
39 Low power 6T SRAM design 2016
40 Algorithm And Architecture For A Low-Power Content-Addressable Memory 2015
Based On Sparse Clustered Networks

Head Office:Flat No 202, 2nd Floor, Pancom Business Center, Beside Opp: Chennai Shopping
Mall, Ameerpet, Hyderabad.Ph: 040-4443 3434, Dilsukhnagar: 9000404181, Warangal: 9000739460,
Vijayawada: 9000404182,