A Transformer-less Partial Power Boost Converter for
PV Applications Using a Three-Level Switching Cell
Mohammed Agamy Maja Harfman-Todorovic, Ahmed Elasser &
School of Engineering General Electric Global Research Center
The University of British Columbia General Electric Co.
Kelowna, BC, Canada Niskayuna, NY, USA
Abstract— Photovoltaic architectures with distributed power
electronics provide many advantages in terms of energy yield as
well as system level optimization. As the power level of the solar
farm increases it becomes more beneficial to increase the dc
collection network voltage, which requires the use of power
devices with higher voltage ratings, and thus making the design
of efficient, low cost, distributed power converters more
challenging. In this paper a simple partial power converter
topology is proposed. The topology is implemented using a
three-level switching cell, which allows the use of semi-
conductor devices with lower voltage rating; thus improving
design and performance and reducing converter cost. This
makes the converters suitable for use for medium to high power
applications where dc-link voltages of 600V~1k kV may be needed
without the need for high voltage devices. Converter operation
and experimental results are presented for two partial power
circuit variants using three-level switching cells.
I. INTRODUCTION
For medium to large-scale commercial and utility
photovoltaic (PV) systems, a string/multi-string level MPPT
distribution, shown in Fig. 1, provides the best
cost/performance operating point [1-3]. For string dc-dc
converters rated at (1.5kW~6kW), the estimated gains in
energy yield are in the range of 3%~9% over a standard
central inverter systems [3]. However, the implementation of
such distributed system requires high performance, high
efficiency dc-dc converters [4-6]. A simple approach to
achieve this high efficiency is to use partial power processing
converters. These converters process only paart of the input PV
power to generate the voltage differential between the PV
string voltage input to the converter and the output dc-link
voltage of the dc collection network, while the rest of the
power is directly fed forward to the output [7-11]. Most
standard partial power processing converters include high
frequency transformers in their design. However, in [12, 13] a
transformer-less partial power converter was presented, which
achieved high efficiency at a much lower cost and higher
reliability due to lower part count.
Designing solar converters for medium to large scale
applications requires the use of dc-bus voltages close to or
above 600V in order to get better system efficiency.
Therefore, these converters require the use of devices with
voltage ratings of at least 1200V. Commercially available
978-1-4673-4355-8/13/$31.00 ©2013 IEEE 2934
Somasundaram Essakiappan
Dept. of Electrical and Computer Eng.
Texas A&M University
College Station, TX, USA
devices at this rating are either IGBTs, which limits the
switching frequency of the converter thus leading to large
passive component sizes or 1200V SiC MOSFETs which
perform well in high frequency applications but have a higher
cost compared to Si IGBTs. Therefore, three-level solutions
allow the use of devices with lower voltage rating (<= 600V)
for commercial applications, where relatively low cost
CoolMOS devices can be used and achieve high efficiency at
high switching frequency or if used at the same switching
frequency as the IGBTs will provide higher conversion
efficiency [14-18]. For applications where higher voltage
(>=1kV) is required the same concept applies as lower voltage
devices can be selected and the overall cost and power density
of the converter can be improved.
This paper presents a partial power converter with a three-
level switching cell, which is suitable for applications with a
high dc-link voltage. The use of devices with lower voltage
rating helps achieve high efficiency because of their lower
conduction losses compared to devices with double the
voltage rating. Efficiency is further improved as the proposed
converter is designed with one device soft-switching under all
operating conditions while the other achieves soft turn-on at
light loads, which helps flatten the efficiency curve across the
converter range of operation. The paper is organized as
follows: in section II the proposed topology is presented.
Circuit operation and some design considerations as well as
variants of the proposed topology, are discussed in section III.
In section IV experimental results are presented for a 1.75kW
proof of concept prototype along with efficiency comparison
between the proposed converter and its two-level counterpart
using IGBTs or SiC MOSFETs to show the potential and
applicability of the proposed method.
Fig. 1. Distributed PV architecture with string/multi-string dc-dc converters.
 II. CONVERTER TOPOLOGY 2
2 1 (3)
A transformer-less partial power dc-dc converter was
developed for solar medium to large scale distributed PV where, τloop is the loop time constant.
applications [12, 13]. The power circuit is simple, has low part
count, as shown in Fig. 2, and achieves high conversion Stage 3 (t2<t<t3): At the beginning of this interval the inner
efficiency due to the fact that at normal operation a high MOSFET Qin is softly turned OFF at zero voltage and zero
percentage of the input power is directly fed forward to the current. The inductor current continues to discharge and
output, while only a fraction of the input PV power, sufficient reaches its minimum value in continuous conduction mode
to generate the voltage differential between the input and (CCM) operation and reaches zero in case of discontinuous
output across the capacitor Cs, is processed through the conduction mode (DCM) of operation.
converter. The fraction of power being processed by the Stage 4 (t3<t<t4): This stage represents the beginning of a
converter depends on the ratio between the input voltage Vin new cycle. The inner switch Qin is turned ON softly at zero
and the output capacitor Vs: current. The input inductor remains in discharge mode in case
of CCM or is at zero current in DCM.
(1) Stage 5 (t4<t<t0): The outer switch Qout is turned ON. In case
of DCM it is turned ON at zero current, which improves the
light load efficiency.
However, one issue with designing a high power density The output of the converter is a fixed dc voltage regulated by
topology is that the switching device is required to block the the grid tied dc-ac inverter stage, and the duty ratio of the
full dc-link voltage, which necessitates the use of SiC devices converter is set such that the input voltage is regulated to
if high power density is a design requirement. Furthermore, achieve maximum power point tracking. Since the output
operating at a high dc-link voltage to reduce losses on the dc voltage is held constant, the output current can thus be used
collection network requires the use of IGBTs with higher
directly as a measure of the output power. Maximum power
voltage ratings and thus forcing a much lower power density
in order to maintain good performance. Therefore, multi-level tracking control can therefore be achieved without the need
versions of this topology are proposed to alleviate these for online power calculation, but rather by only using the
problems, since they can allow the use of devices with lower output current feedback, which significantly simplifies the
voltage ratings that are capable of operating at higher tracking control computations.
switching frequencies as well as providing an alternative for Voltage balance between the two switches and the flying
the use of high cost devices. The proposed topology is shown capacitor is very sensitive to the device output capacitance,
in Fig. 3. The circuit is a three-level partial power processing which in turn is affected by the device voltage. Therefore, the
converter in which the voltage stress across the devices is half dead time determined by equation (3) has to be dynamically
that of the dc-link voltage (Vout). Maintaining voltage balance adjusted by means of the MOSFET voltage feedback signal.
depends on the value of the flying capacitor (Cf) and also Fig. 6 shows a simplified block diagram of the system control
requires properly regulating dead time between turn -offof the algorithm.
two devices. To further improve the efficiency, which is
required by solar converters, SiC Schottky diodes are used to
eliminate reverse recovery losses.
III. CONVERTER OPERATION
The stages of operation of the proposed converter can best
be described using the timing diagram in Fig. 4 and the
topology stages shown in Fig. 5, and are summarized as
follows:
Stage 1 (t0<t<t1): Both inner and outer switches (Qin and Qout,
respectively) are ON and the current through the input
Fig. 2 Baseline Partial Power Boost Converter [12, 13]
inductor Lin ramps up. This period where both switches are
conducting represents the effective duty ratio (Deff) of the
Cs
converter. The top capacitor Cs supplies energy to the load.
Stage 2 (t1<t<t2): The outer switch (Qout) is turned OFF.
The input inductor current is diverted to the top diodes to
charge the output capacitor and the voltage across Qout builds
up such that at the end of this period
(2)
The duration of this interval highly affects the voltage
balance between the two switches and it is actively controlled
during closed loop operation. In order to achieve perfect Fig. 3 The Proposed Three-Level Partial Power Processing topology
voltage balance the duration of this interval is given by:

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 CCM

DCM

CCM

DCM
t4 t0 t1 t 2 t3

Fig. 4 Timing diagram for converter shown in fig. 3 Fig. 6 Controller functional block diagram.

The relationship between the output capacitor voltage (Vs) and

the input PV voltage (Vin) is given by equation (4) for the case
of CCM and given by equation (5) in the case of DCM

(4)
1

1 2
2
1 1 (5)

where, Deff is the effective duty ratio, fsw is the switching

Fig. 5 Stages of operation for converter shown in fig. 3
frequency, Lin is the input inductance and Rload is the
equivalent load resistance.
Since high voltage (up to 1700V) wide bandgap (SiC)
diode technology is quite mature, a variant of this topology
where, one high voltage diode can be used with a three-level
switching cell is shown in Fig. 7; leading to a reduced part
count and better efficiency due to lower conduction losses in
the diode with only one being used in the conduction path.
The stages of operation of this converter are similar to those
of the converter in Fig. 5. The value of Cf is chosen to be
close to the value of the drain source capacitance of the
MOSFETs or otherwise any snubber capacitors in parallel
with the two switching devices. It should be noted that the
capacitor Cf should be rated at the full dc-link voltage in this
case and not half the voltage as for the converter in Fig. 3,
since the flying capacitors is directly connected across the
output when the lower device is turned ON. For high voltage,
high frequency applications, and with the maturation of SiC
diode technology, SiC Schottky diodes can be used as the top
freewheeling diode (D) with a single device instead of
multiple diodes as in the first configuration in Fig. 3.

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 the baseline IGBT based topology, as it achieved a weighted
Cs efficiency of 98.4% vs. 98% for the IGBT topology.

Fig. 7 Variant topology with high voltage diode and a three-level switching
(a)
cell
IV. EXPERIMENTAL RESULTS
A 1.75kW converter prototype was built and tested at a
switching frequency of 30kHz, with a rated input voltage of
400V and rated output voltage of 600V. The two diode
converter ofFig. 3 and the single diode converter of Fig. 7
were tested. The three level switching cell, with two 800V
CoolMOS devices, performance was first tested and then
replaced by a single 1200V IGBT and later replaced by a
1200V SiC MOSFET. For the three-level cell, the MOSFET
voltage sharing and flying capacitor voltages are shown in Fig.
8. In Fig. 8a, the flying capacitor voltage is limited to half the (b)
output voltage (chosen as 500V in this test) for the two diode Fig. 8 Switch and flying capacitor voltage waveforms for (a) two diode
circuit and (b) one diode circuit. Ch1 (yellow): Inner switch drain-source
converter of Fig. 3 and in Fig. 8b, it reaches the full output voltage (100V/div), Ch2 (blue): Outer switch drain-source voltage
voltage for the single diode converter of Fig. 7. In Fig. 9, (100V/div) and Ch3 (magenta): Flying capacitor voltage (a:100V/div, b:
MOSFET voltages are shown along with switch current, both 200V/div)
in CCM in fig. 9a and in DCM in fig. 9b. In DCM, the device
capacitance resonates with the converter inductor to cause the
oscillation in the device drain-source voltage. Fig. 10 shows
the turn-on and turn-offtransitions with the associated delays
constituting the dead times between switching transitions.
In Fig. 11, the efficiency of the single diode three-level
topology compared to a topology with a single 1200V IGBT
switch at a 300V input and 500V output is shown. Since the
lower voltage CoolMOS devices have superior conduction
characteristics, the efficiency of the three-level topology is
higher by about 0.4% than the IGBT based topology across
the converter power range. Efficiency was measured over the (a)
entire converter power range with three input voltages (200V,
300V, and 400V) with a 500V output voltage and a weighted
efficiency was calculated based on the California Energy
Commission (CEC) formula:
0.04 % 0.05 % 0.12 %
0.21 % 0.53 % 0.05 %
(6)
Fig. 12 shows a comparison of the measured weighted
efficiency for the proposed three-level converter versus a high
voltage IGBT based converter and a high voltage SiC
MOSFET based converter all operating at a switching
frequency of 30kHz. SiC MOSFETs show a clear efficiency (b)
advantage (99%) over the Si IGBTs and CoolMOS due to the Fig. 9 Switch and flying capacitor voltages and switch current waveforms for
significantly lower switching losses (primarily turn-off losses), (a) CCM operation and (b) DCM operation. Ch1 (yellow): Inner switch
the three-level topology has a higher weighted efficiency than drain-source voltage (100V/div), Ch2 (blue): Outer switch drain-source
voltage (100V/div), Ch3 (magenta): outer device current (5A/div) and Ch4
(green): Flying capacitor voltage (200V/div)

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(a)
(b)
Fig. 10 Switching transitions (a) Turn-on transition and (b) Turn-off
transition. Ch1 (yellow): Inner switch drain-source voltage (100V/div), Ch2
(blue): Outer switch drain-source voltage (100V/div) and Ch3 (magenta):
Flying capacitor voltage (100V/div)
Fig. 11 Efficiency of three-level converter with one diode (Top-Blue) and a
converter with a 1200V IGBT (Lower-Red)
Fig. 12 Comparison of weighted CEC efficiency at 30kHz for (i) converter
with single 1200V IGBT, (ii) converter with single 1200V SiC MOSFET and
(iii) converter with 3-level switching cell containing two 800V CoolMOS
devices
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V. CONCLUSIONS
A three-level based topology is proposed for distributed
PV dc-dc converters. The topology allows the use of
switching devices with lower voltage rating and thus helps
improve cost as well as performance compared to standard
high voltage Si IGBT based topologies. The inner switch is
always soft switched (at zero current) at turn-on and turn-off,
while the outer switch can achieve soft turn-on in some
operating conditions based on the converter design and
component values. This topology concept is readily
expandable to medium voltage PV architectures (~1kV+ dc-
link voltages), where higher power density and more efficient
and cost effective converters can be designed. Experimental
results show a better efficiency for the three-level topology
compared to a high voltage Si IGBT topology at the same
switching frequency. However, online tuning of the dead time
between ON and OFF switching transitions of the inner and
outer switches requires an additional feedback signal and
complicates the controller design compared to two-level
topologies.
Overall, three-level variants of the transformer-less partial
power converters provide a good topology candidate for high
voltage high power density solar power converters.
ACKNOWLEDGMENT
This material is based upon work supported by the
Department of Energy-Golden Field Office under Award DE-
EE0000572.
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