Microelectronics: Devices to Circuits

Instructor Name: Prof.Sudeb Dasgupta ( IIT Roorkee - Electrical Engineering )

COURSE DURATION: Jul-Oct 2019 CORE / ELECTIVE: Core_Elective UG / PG: Both
PRE-REQUISITES: First course on linear circuit analysis, A basic course on Semiconductor Devices and Digital Electronics. A
course on Computer Organization will be also helpful (though not strictly required).
INTENDED AUDIENCE: NA
INDUSTRIES APPLICABLE TO: Cadence; Synopsys; ST Microelectronics; NXP Semiconductors; Semiconductor Complex
Limited, Chandigarh; Design House in general
COURSE OUTLINE: This course is intended for the core courses in Electronics Circuits taught to undergraduates in Electrical and Computer
Engineering. The objective of this course is to develop the ability to analyse and design electronic circuits both analog and digital, discrete and
integrated. The course starts with the basics of the device most seldom encountered in mixed designs and then go on to do circuit analysis in the
later parts.

ABOUT INSTRUCTOR: S. Dasgupta,is presently working as an Associate Professor, in Microelectronics and VLSI Group of the Department of
Electronics and Communication Engineering at Indian Institute of Technology, Roorkee. He received his PhD degree in Electronics Engineering
from Institute of Technology-Banaras Hindu University (currently IIT-BHU), Varanasi in 2000. During his PhD work, he carried out research in
the area of effects of ionizing radiation on MOSFET. Subsequently, he was member of faculty of Department of Electronics Engg.,at Indian School
of Mines, Dhanbad (currently IIT-Dhanbad). In 2006, he joined as an Assistant Professor in the Department of Electronics and Communication
Engineering at Indian Institute of Technology, Roorkee. He is currently the Chairman, Faculty Search Committee of the Department. He has
authored/co-authored more than 200 research papers in peer reviewed international journals and conferences.

COURSE PLAN
Week 1: Bipolar Junction Transistor; L1: Physical Structure and Modes of operation L2: Operation in Active Mode, circuit symbols and
conventions, L3: BJT as an Amplifier, small circuit model, L4: BJT as a switch and Ebers Moll Model, L5: Simple BJT inverter and Second Order
Effects.

Week 2: L1: MOS Transistor Basic-I; L2: MOS Transistor Basic-I; L3: MOS Transistor Basic-II; L4: MOS Parasitic & SPICE Model; L5: CMOS
Inverter Basics-I

Week 3: L1: CMOS Inverter Basics-II; L2: CMOS Inverter Basics-III; L3: Power Analysis-I; L4: Power Analysis-II; L5: SPICE Simulation-I

Week 4: L1: Biasing of MOS Amplifier and its behavior as an analog switch, L2: CMOS CS/CG/SF Amplifier Configuration, L3: Internal cap
models and high frequency modelling, L5: JFET, structure and operation.

Week 5: L1: Multistage and Differential Amplifier, L2: Small Signal Operation and Differential Amplifier, L3: MOS Differential Amplier, L4:
BiCMOS Amplifier with Active Load, L5: Multistage Amplifier with SPICE Simulation

Week 6: L1: s-domain analysis, transfer function, poles and zeros, L2: High Frequency Response of CS and CE Amplifier, L3: Frequency
Response of CC and SF Configuration, L4: Frequency Response of the Differential Amplifier, L5: Cascode Connection and its Operation

Week 7: L1: General Feedback structure and properties of negative feedback, L2: Basic Feedback Topologies, L3: Design of Feedback Amplifier
for all configuration, L4: Stability and Amplifier poles, L5: Bode Plots and Frequency Compensation

Week 8: L1: Ideal Operational Amplifier and its terminals, L2: Inverting and Non- Inverting Configuration, L3: As an integrator and
Differentiator, L4: Introduction to Analog Computer, L5: Large Signal Operation of Op-Amp and Second order offsets.

Week 9: L1: Butterworth and Chebyshev Filters, L2: First and Second Order Filter Functions, L3: Switched Capacitor based filters, L4:
Single-Amplifier Biquadratic Filters, L5: Second Order LCR Resonator.

Week 10: L1: Combinational Logic Design-I; L3: Combinational Logic Design-II; L4: Combinational Logic Design-III; L5: Combinational Logic
Design-IV
Week 11: L1: Sequential Logic Design-I, L2: Sequential Logic Design-II; L3: Sequential Logic Design-III; L4: Sequential Logic Design-IV; L5:
Sequential Logic Design-V

Week 12: L1: Clock Strategies for Sequential Design-IV; L2: Sequential Logic Design-IX; L3: Clock Strategies for Sequential Design-V; L4:
Concept of Memory & its Designing-I; L5: Concept of Memory & its Designing-II