IECON2015-Yokohama
November 9-12, 2015
Comparative of Modulation Techniques for Modular
Multilevel Converter
M. Moranchel, I. Sanz, E. J. Bueno, F. J. Rodriguez
Department of Electronics, Alcala University, Alcalá de Henares, Spain
miguel.moranchel@depeca.uah.es
Abstract— The modulation technique chosen for use in the
power converter largely defines the harmonics generated,
consequently it is a fundamental part that must be studied. In
this paper it’s shown a comparative between different
modulations techniques applied to a modular multilevel
converter. Sinusoidal Pulse Width Modulation, Space-Vector
Modulation and Nearest Level Modulation are studied. The
whole techniques are explained and finally are implemented in a
hardware platform and tested in a real high-power six-level
modular multilevel converter.
Keywords—Modulation techiniques; Modular Multilevel
Converter; Nearest Level Modulation; Space Vector Modulation;
Sinusoidal PWM.
I. INTRODUCTION
High Voltage Direct Current (HVDC) transmission using
voltage source converter (VSC) has been accepted as a feasible
solution to connect distantly located renewable sources to large
AC network[1][2]. To achieve high voltage and high power
conversion, conventional VSC-HVDC system are usually
based on two-level or three-level converter with series-
connected IGBTs, which suffers from the disadvantages of
voltage sharing across each IGBT and low power quality.
The research on the multilevel inverter has been receiving
wide attention mainly due to its capability of high voltage
operation without switching devices connected in series.
A very promising topology, which is already commercially
available for HVDC, is the Modular Multilevel Converter
(MMC)[3][4]. This topology can be adapted to a wide range of
voltage and power with minimum changes[5].
Along with the evolution of the topologies, many pulse
width modulation (PWM) techniques have been developed for
multilevel converters. The complexity of the switching
decisions and the implementation in real time is one of the
hindrances of the multilevel converters. As the number of level
increases, the complexity of the switching algorithms
increases.
The most common modulation technique in multilevel
converters is the Sinusoidal pulse-width modulation (SPWM)
due to ease of switching algorithm implementation[6]. The
drawback of this modulation technique is that requires a carrier
wave for each output level is required. Moreover, in large
multilevel converters the phase displacement existing between
978-1-4799-1762-4/15/$31.00 ©2015 IEEE 003875
carrier waves is very little so the accuracy in the carrier wave
generation must be very high.
Space vector modulations (SVPWM) works with line-to-
line voltages, as long as SPWM works with phase-voltages.
SVPWM attracts much attention because it provides significant
flexibility to optimize switching waveforms, and is suitable for
implementation in digital signal processors [7]. The flexibility
in selecting redundant vectors can be used to provide better DC
bus voltage utilization or to reduce the common-mode voltage.
SVPWM techniques for multilevel converter have been
developed by several authors [8]-[10].
Nearest Level Modulation (NLM) avoids the use of any
triangular carrier wave, by directly computing the switching
states and duty cycles for each phase of the converter. The
NLM brings more flexibility and easy digital implementation
when the level number of the converters is large.
This paper is organized as follows. Section II presents the
MMC topology. Sinusoidal pulse-width modulation is shown
in Section III, followed by the Space-vector modulation
explained in Section IV. Nearest Level Modulation is shown in
Section V. Finally, Section VI shows the experimental results
and the MMC prototype where the modulations are validated.
This paper summarizes its conclusions in Section VI.
II. MODULAR MULTILEVEL CONVERTER
Fig. 1 shows the structure of a three phase Modular
Multilevel Converter, which is composed of six arms. Each
arm consist of n/2 series-connected submodules (SM) and an
arm inductor LMMC. The submodule is a half H-bridge that
contains two insulated-gate bipolar transistors (IGBT), two
reversing diodes and a dc storage capacitor. The two switches
(S and ܵҧ) in each SM are controlled with complementary
signals and produce two active switching states. Each
submodule added to the arm, increase in two voltage steps the
output voltage. Different topologies have been proposed for
the MMC submodules that provide more output levels, e.g.
Neutral Point Clamped (NPC) or Flying Capacitor (FC) [11].
The advantage of the MMC is that it can be adapted
perfectly to any power and to any voltage. To increase the
power, just select properly the IGBT, the inductance and the
capacitor. In case to increase the voltage, just only increase the
number of SM connected in series, additionally the voltage
steps are increased and therefore the output current quality is
better. The MMC provides n +1 voltage steps, where n is the vref
vc1 vc5 vc3 vc4 vc2
number of submodules of one phase.
ʘt

v1
ʘt
v2
ʘt
ܵ
v3
ʘt
ܵ v4
ʘt
v5
ʘt
vo

ʘt

Fig. 1. a) Modular Multilevel Converter diagram, b) Sumodule diagram Fig. 2. SPWM output waveform generation.

III. SINUSOIDAL MODULATION IV. SPACE VECTOR MODULATION

The sinusoidal PWM modulation is the most used
modulation in power converters. The modulation consists of The obstacle for applying SVM to multilevel converters is
compare the reference signal, which is also called modulation the difficulty caused by the largely increased number of
wave with a triangular signal, also called carrier wave. When switching states and switching sequences that accompany the
the modulation wave is greater than the carrier wave, the output higher number of levels. Generally, for a three- phase n-level
is on, else the output is off. converter, there are ݊ଷ switching states and ͸ሺ݊ െ ͳሻଶ
triangles in the space vector diagram[12]. Fig. 4 shows the
ܱܰǡ ܸ௥௘௙ ൒ ܸ௖௥
݂ሺ‫ݔ‬ሻ ൌ ൜ (1) space vector diagram of a six-level converter.
ܱ‫ܨܨ‬ǡ ܸ௥௘௙ ൏ ܸ௖௥
The space-vector modulation algorithm chosen in this paper
The fundamental-frequency component in the converter is based on [13]. In this paper it’s shown a fast space-vector
output voltage can be controlled by the amplitude modulation algorithm for multilevel converters that can be used in any n-
index: level multilevel converter with minimum changes. This
෡ೝ೐೑
௏ algorithm avoids the use of coordination transformations. The
݉௔ ൌ ෡೎ೝ
௏
(2) algorithm is explained below.

Where ܸ෠௥௘௙ and ܸ෠௖௥ are the peak values of the modulation The first step is to normalize the reference voltage vectors
dividing by ୡ .
and carrier waves, respectively. Moreover, there is another
parameter which is the frequency modulation index that ܸ௜
determines the relationship between the frequencies of the ܸ௜‫ כ‬ൌ (4)
ܸ௖
modulation and carrier waves, respectively.
௙ೝ೐೑ where ܸ௜ are ܸ௔௕ ǡ ܸ௕௖ ܸܽ݊݀௖௔ .
݉௙ ൌ (3)
௙೎ೝ
The next step is to obtain the four vectors nearest to the
Fig. 2 shows the waveform obtained using five carrier reference voltages, as shows Fig. 3. They can be identified
waves. The output waveform is formed by the sum of all using upper and lower rounded integer values from the
‫כ‬ ‫כ‬
signals. normalized ܸ௔௕ and ܸ௕௖ voltages.
‫כ ܸڿ‬
ܸ௨௟ ൌ ൤ ௔௕‫ כ‬൨ (5)
‫ܸہ‬௕௖
‫ܸہ‬ ‫כ‬
ܸ௟௨ ൌ ൤ ௔௕‫ כ‬൨ (6)
‫ܸڿ‬௕௖

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 ‫כ ܸڿ‬ If the third vector is ܸ௨௨ the duty cycles are:
ܸ௨௨ ൌ ൤ ௔௕ ‫ כ‬൨ (7)
‫ܸڿ‬௕௖ ‫כ‬
‫כ‬ ݀௨௟ ൌ ܸ௔௕ െ ܸ௟௟௔௕ (10)
‫ܸہ‬
ܸ௟௟ ൌ ൤ ௔௕‫ כ‬൨ (8) ‫כ‬
݀௟௨ ൌ ܸ௕௖ െ ܸ௟௟௕௖ (11)
‫ܸہ‬௕௖
݀௟௟ ൌ ͳ െ ݀௨௟ െ ݀௟௨ (12)
Vectors ܸ௨௟ and ܸ௟௨ are always two of the three nearest
vectors, the third vector is chosen by evaluation the sign of the In the case of ܸ௟௟ is the third vector, the duty cycles are:
following expression:
‫כ‬
െܸ௖௔‫ כ‬െ ሺܸ௨௟௔௕ ൅ ܸ௨௟௕௖ ሻ (9) ݀௨௟ ൌ െሺܸ௕௖ െ ܸ௨௨௕௖ ሻ (13)
‫כ‬
݀௨௟ ൌ െሺܸ௔௕ െ ܸ௨௨௔௕ ሻ (14)
If the sign of (9) is positive, ܸ௨௨ is the third nearest vector, ݀௨௨ ൌ ͳ െ ݀௨௟ െ ݀௟௨ (15)
otherwise, ܸ௟௟ is the third nearest vector.
ܸ݈‫ݑ‬ ܸ‫ݑݑ‬ To obtain the available switching states, (16) is used.

݇
ܸ‫݂݁ݎ‬ ቎ ݇ െ ܸ݆ܾܽ ቏ (16)
ܱ ݇ െ ܸ݆ܾܽ െ ܸ݆ܾܿ
ܸ݈݈ ܸ‫݈ݑ‬

Fig. 3. Normalized reference voltage vectors and the four nearest vectors.
The duty cycles of the vectors are obtained using the
equation shown below.
Where ݆ is the three nearest vectors ܸ௨௟ , ܸ௟௨ and ܸ௟௟ or ܸ௨௟ ,
ܸ௟௨ and ܸ௨௨ , depends on the results of (9).
Using (16) some invalid states will appear and need to be
eliminated. All the switching states that are out of range 0 to 5
are invalid.

Fig. 4. Six-level converter space vector diagram.

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 V. NEAREST LEVEL MODULATION
The nearest level modulation (NLM) is a very interesting
modulation technique to use when the number of submodules
is quite high. The advantage of the NLM is that is not
necessary the use of carrier signals. In the MMC topology n/2
carrier signals are needed, where n is number of submodules of
each phase. Nowadays there are MMC which easily exceed
200 submodules [14], resulting in more than 100 carrier
signals. Therefore, the phase-shifted must be very accurate.
The principle of the modulation is based on approximate
the reference voltage using two voltage levels. Appling each
voltage level during a certain period of time is possible to
generate a signal which mean value is the desired value. This is
the basic principle of the DC/DC converter. The higher the
frequency, the better the approximation to the reference signal
is. Fig. 5 shows the operating principle.
The number of voltage steps in which the signal can be
divided depends on the number of submodules. Each
submodule adds one voltage step.
ܸ௥௘௙ ൌ ܰ ȉ ݀ ൅ ሺܰ െ ͳሻሺͳ െ ݀ሻ (17)
The input signal of the modulator is the voltage reference
signal obtained from the current controller and normalized with
the dc-bus voltage.
‫כ‬
௏ೝ೐೑
ܸ௥௘௙ ൌ (18)
௏೏೎
VI. EXPERIMENTAL RESULTS
The three modulations are been implemented in a real
hardware platform designed to control large multilevel
converters.
The used hardware platform consists of two boards
interconnected. The core of the control system is the ZC702
evaluation board manufactured from Xilinx that is based on a
Z-7020 System-On-Chip (SoC). The other board is a custom
interface board. Fig. 6 shows the hardware platform.
The entire modulations have been implemented in the SoC
Programmable Logic (PL). The FPGA family is the Artix-7
and the resources available are 85K Logic Cells, 53,200 Look-
Up Tables (LUTs) and 106,400 Flip-Flops. Table I shows the
FPGA resources used by each modulation technique.
The modulations have been implemented as IP peripheral
cores. These cores are connected to the FPGA AXI-bus where
receive the voltage references. The advantage of use IP
peripherals is that they can be exported to other devices
without changes, reducing the development time.
SVPWM is the modulation that consumes more resources
followed by NLM and by SPWM. However, the resources
used difference is very small compared with the high amount
of resources available in the platform.

ܸ௥௘௙ varies between ±1 if there is not overmodulation. This

range is not valid for the modulator, therefore a signal scaling
is made to change the range from 0 to n, where n is the number
of submodules of one arm.
௏ೝ೐೑ ାଵ
ܸ௛‫ כ‬ൌ ݊ (19)
ଶ

The switching states and duty cycles of each phase are

obtained as:

‫ܭ‬௛ ൌ ݅݊‫ݐ‬ሺܸ௛‫ כ‬ሻ (20)

‫ܦ‬௛ ൌ ܸ௛‫כ‬ െ ‫ܭ‬௛ (21)

where ݅݊‫ݐ‬ሺ‫ݔ‬ሻ means the integer part of ‫ݔ‬. Now, ܸ௛‫ כ‬can be
expressed as:
ܸ௛‫ כ‬ൌ ሺ‫ܭ‬௛ ൅ ͳሻ‫ܦ‬௛ ൅ ‫ܭ‬௛ ሺͳ െ ‫ܦ‬௛ ሻ (22)
Fig. 6. Hardware platform.

TABLE I
FPGA RESOURCES

MODULATION TECHNIQUE RESOURCES USED

LUTs Flip-Flops

SPWM 315 0.59% 94 0.08%

SVPWM 992 1.86% 482 0.45%

NLM 762 1.43% 349 0.32%

Fig. 5. Nearest Level Modulation operating principle.

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 The modulations have been tested in a real prototype Fig.8, Fig. 9 and Fig 10 show the output waveform obtained
ensuring that the implementation is made properly. The using the SPWM, SVPWM and NLM respectively. The figures
prototype is shown in Fig. 7 and the parameters are presented show that the output voltage waveforms are generated
in Table II. properly. The main difference between the figures is the
commutation frequency used in each modulation.
The SPWM uses a 2500 Hz carrier signal. The SVPWM
and the NLM calculates the duty cycle at a 5000Hz frequency.
The signals analyzed are the output voltage and the output
current. Two experimental tests have been done. The first test
consists of measure the output voltage without loads
connected. The objective of this test is to measure the voltage
output without the influence of the inductances since they filter
the harmonics. The results are shown below.
The second test consists of measure the output current and
analyzes the harmonics. To carry out this test a 2 kW load is
connected to the converter output. The results are shown
below. The output current THD of each modulation techinque
is shown in Table III.

Fig. 8. SPWM output waveform

Fig. 7. Modular Multilevel Converter Prototype

TABLE II
MMC PROTOTYPE PARAMETERS

PARAMETER VALUE

Nominal Power 25 kVA Fig. 9. SVPWM output waveform

Nominal Voltage 400 V
Nº submodules 10
Submodule Capacitor 2200 μF
IGBT SKM145GB066D
IGBT Driver Skyper 32 R UL
DC-BUS Voltage 1200 V
MMC inductor 0.5 mH
Grid inductor 5 mH

TABLE III
EXPERIMENTAL RESULTS
MODULATION THD WTHD
SPWM 1.55% 0.39%
SVPWM 1.5% 0.39%
NLM 2.72% 0.41% Fig. 10. NLM output waveform

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 shown have been: Nearest Level Modulation, Space Vector
Modulation and Sinusoidal PWM. Each modulation has both
advantages and disadvantages. All modulations have been
implemented in a hardware platform and have been tested in a
real six-level Modular Multilevel Converter. Finally, the
experimental results have been shown. The results have been
shown that the three modulation techniques work properly and
can generate the reference voltages.

a)
ACKNOWLEDGMENT
This work has been supported by the Autonomous
Community of Madrid under the PRICAM project (S2013-
ICE-2933), and the Spanish Ministry of Economy and
Competitiveness under the CONPOSITE project (ENE2014-
57760-C2-2-R).
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