EL2002 Digital System

Sequential Logic (CH8 – Analysis SM)

The Sequential Circuit Model
x1 z1
 Sequential Circuit has
Combinational
xn logic zm memory elements
(a)  It remembers the
x1 z1 present state (y1..yr)
xn
Combinational
zm
 Uses the present state
logic
to determine the next
y1 yr Yr Y1 state (Y1..Yr)
 A state transition is
Memory defined as
(b)
 Y = h(x, y)
 The output is definedas
 Z = g(x, y)
The Synchronous Sequential Circuit Model

x1 z1

...

...
xn Combinational zm
logic

y1 ... yr Yr ... Y1

Memory

Clock

 Transition depends on Clock

General Architecture of Synchronous
State Machines
 “Moore machine” – outputs depend only on the state
 “Mealy machine” – outputs depend on the state and the
current inputs

M P
W Combinational N Combinational
Z
circuit : circuit

next state output logic

(excitation) logic N Flip-flops
Clock “state”
Moore Machine Model

0
1
w/0
W/0 X/1

0 0
1 1
Y/0

(a)

Present Input x
state 0 1 Outputs
W Y X 0
X X Y 1 z = f(y)
Y X W 0

(b)
Moore Machine Timing Diagram
0
1
W/0 X/1

0 0
1 1
Y/0

(a)

Present Input x
state 0 1 Outputs
W Y X 0
X X Y 1
Y X W 0

(b)
Mealy Machine Model

A
1/1 1/0
0/1
0/0 0/0 1/0
B C
X/Z
(a)

Present Input x
state 0 1
A B/1 C/0
B B/0 A/1
C A/0 C/0 z = f(x,y)
Next state/output
(b)
Mealy Machine Timing Diagram
A
1/1 1/0
0/1
0/0 0/0 1/0
B C
X/Z
(a)

Present Input x
state 0 1
A B/1 C/0
B B/0 A/1
C A/0 C/0
Next state/output
(b)
State Machine Analysis Steps
1. Determine excitation eqns for flip-flop inputs
2. Substitute excitation eqns into flip-flop Characteristic
Equations
characteristic eqns to obtain transition eqns
3. Use transition eqns to create a transition table SR flip-flop
Q* = S + R’Q
4. Determine output eqns
5. Add output values to the transition table for D flip-flop
each state (Moore) or state/input combination Q* = D
(Mealy) T flip-flop
6. Name the states, create a state/output table Q* = T·Q’ + T’·Q
7. Draw a state diagram JK flip-flop
Q* = J·Q’ + K’·Q
SR Master-Slave Flip-Flop Characteristics
S R Q C Q*
0 0 0 0 No change
0d SR d0
0 0 1 1
0 1 0 0 Reset 10
0 1 1 0 0 1
1 0 0 1 Set 01
1 0 1 1
State Diagram
1 1 0 x Not allowed
1 1 1 x

Excitation Table
Characteristic Equation
Q* = S + RQ
The same as SR Latch but changes only takes
effect during clock pulse
Master-Slave D Flip-Flop Characteristics
D Q C Q*
0 0 0 Store 0
0 D 1
0 1 0
1 0 1 Store 1 1
1 1 1 0 1

Excitation Table 0
State Diagram
Characteristic Equation
Q* = D
Enabled: M S M S M S M S M

QM

Q = QS

Timing Diagram
Pulse-Triggered JK Flip-Flop Characteristics
0d JK d0
1d
0 1
d1
State Diagram

Excitation Table

Characteristic Equation
Q* = KQ + JQ
Example 1
Example 1 (continued)

1. Excitation equations for flip-flop inputs:

D 1 = w y1’ + w y 2
D2 = w y1 + w y2

2. Transition equations:
Y1 = w y1’ + w y2 Present Next State
State w=0 w=1
Y2 = w y1 + w y 2
y2 y1 Y2 Y1 Y2 Y1
0 0 0 0 0 1
3. Transitiontable:
0 1 0 0 1 0
1 0 0 0 1 1
1 1 0 0 1 1
 Example 1 (continued)
Present Next State
4. Output equations: State w=0 w=1
Output
z = y1 y2
y2 y1 Y2 Y1 Y2 Y1 Z
0 0 0 0 0 1 0
5. Transition/output table: 0 1 0 0 1 0 0
1 0 0 0 1 1 0

6. Name states: 1 1 0 0 1 1 1

y2 y1 State
0 0 A
0 1 B
1 0 C
1 1 D
 Example 1 (continued)
Present Next State Output
 State/output table: State w=0 w=1 Z
A A B 0
B A C 0
C A D 0
D A D 1
 Statediagram:

w=0 w=1
w=1

w=1 w=1 D
A w=0 B C
(z=1)
w=0 w=0
Timing Diagram
Example 2
Example 2 (continued)
Present Next State
1. Excitation equations for flip-flop State x=0 x=1
inputs: D1= y’1+ y2 y2 y1 Y2 Y1 Y2 Y1
D2= xy’2 0 0 0 1 1 1
2. Transition equations: 0 1 0 0 1 0
Y1= y’1+ y2 1 0 0 1 0 1
Y2= xy’2 1 1 0 1 0 1
3. Transition table:
Present Next State
Output
State x=0 x=1
4. Output equations: y2 y1 Y2 Y1 Y2 Y1 z
z = y1+y’2 0 0 0 1 1 1 1
5. Transition/output table: 0 1 0 0 1 0 1
1 0 0 1 0 1 0
1 1 0 1 0 1 1
Example 2 (continued)
Present Next State Output
6. Define states, create State x=0 x=1 z
state/output table A B D 1
B A C 1
C B B 0
D B B 1
7. State diagram
Timing diagram for Example 2
Example 3
Combinational logic
Dt
z

D
x

C

Q
y Y
Q D
Q
y
Q C Clock 0 1 2 3 4 t/Dt
(b)
Memory
(a)
Example 3 (continued)
Present Next State
1. Excitation equations for flip-flop State x=0 x=1
inputs: D = xy’ + x’y y Y Y
0 0 1
2. Transition equations: 1 1 0
Y = xy’+ x’y

3. Transition table: Next

Present State/Output
State
4. Output equations: x=0 x=1
z = xy y Y Y
0 0/0 1/0
5. Transition/output table:
1 1/0 0/1
Timing Diagram
Example 4

Q1Q2 Q1
T1
T Q
z
Q1Q2
Clock Q

X
XQ2 T2 Q2
T Q

Clock Q Q* = T Q’ + T’ Q
Example 4 (continued)
 Excitation equations for flip-flop inputs:
 T1 = Q1’Q2
 T2 = X Q2’

 Transition equations:
 For a T F/F: Q* = T Q’ + T’ Q
 Q1* = T1 Q1’ + T1’ Q1
 = (Q1’ Q2) Q1’ + (Q1’ Q2)’ Q1 = Q1’ Q2 + (Q1 + Q2’) Q1
 = Q1’ Q2 + Q1
 = Q1 + Q2
 Q2* = T2 Q2’ + T2’ Q2
 = X Q2’ Q2’ + (X Q2’)’ Q2 = X Q2’ + (X’ + Q2) Q2 = X Q2’ + Q2
 = X + Q2
Example 4 (continued) Next State
Present
 Transition table: State x=0 x=1
Q2 Q1 Q*2 Q*1 Q*2 Q*1
0 0 0 0 1 0
0 1 0 1 1 1
1 0 1 1 1 1
1 1 1 1 1 1

 Output equations: Z = Q1 Q2
Present Next State
Output
State x=0 x=1
 Transition/output table:
Q2 Q1 Q*2 Q*1 Q*2 Q*1 z
0 0 0 0 1 0 0
0 1 0 1 1 1 0
1 0 1 1 1 1 0
1 1 1 1 1 1 1
Example 4 (continued)
Present Next State Output
6. Define states, create State x=0 x=1 Z
state/output table S0 S0 S2 0
S1 S1 S3 0
S2 S3 S3 0
S3 S3 S3 1
7. State diagram
reset

X’ X 1 S3 X
S0 S2 z=1
S1 X’

1
Can’t ever get
This machine waits until a 1 is input … it then to state S1
waits one cycle and then outputs a 1 forever
Example 5
Mealy Machine
X

Y T Q T Q
Q1 Q2
z
Q Q

Clk z  XQ2
T1 Y Q*  YQ YQ
1 1 1
T2  XYQ1 Q  XYQ Q  (XYQ )Q
*
2 1 2 1 2

Q*  TQ  TQ
Example 5
Present Next State Q*2Q*1,z
State XY
Q2 Q1 00 01 10 11
0 0 00,1 01,1 00,0 01,0
0 1 11,1 00,1 01,0 00,0
1 0 10,0 11,0 10,0 11,0
1 1 01,0 10,0 11,0 10,0

Present Next State Q*2Q*1,z

State XY
00 01 10 11
A A,1 B,1 A,0 B,0
B D,1 A,1 B,0 A,0
C C,0 D,0 C,0 D,0
D B,0 C,0 D,0 C,0
Example 5
Example 6

Q0
D Q D0 = Q2’ D1 = Q0 D2 = Q1
Since Q* = D for a D flip-flop, we get
Clk Q Q0* = Q2’ Q1* = Q0 Q2* = Q1

Q1
D Q

Clk Q

Q2
D Q

Clk Q
Example 6
reset

000

100 001

110 011

111
“Johnson” counter

010 101

should never get into these states

State Machines in VHDL
 No special method to describe state machines in VHDL
 Instead, declare a
signal vector to represent state value
 Then use CASE statement to assign nextstate
Example 1 (fig 8.3)
Reset

w=1
w=0 Az=0 Bz=0

w=0

w=0 w=1

C  z =1

LIBRARY ieee ; w=1

USE ieee.std_logic_1164.all ;

ENTITY simple IS Present Next state Output

PORT ( Clock, Resetn, w : IN STD_LOGIC ; state w = 0 w = 1 z
z : OUT STD_LOGIC );
END simple ; A A B 0
B A C 0
C A C 1
Example 2 (fig 8.23)

Reset
w = 1  z =0

w = 0  z =0 A B w = 1  z =1

w = 0  z =0

Present Next state Output z

state w= 0 w=1 w= 0 w=1
LIBRARY ieee ;
USE ieee.std_logic_1164.all ; A A B 0 0
B A B 0 1
ENTITY mealy IS
PORT ( Clock, Resetn, w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;
END mealy ;
ARCHITECTURE Behavior OF mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
y <= A;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN A=>
IF w = '0' THEN y <= A;
ELSE y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN y <= A;
ELSE y <= B ;
END IF ; Present Next state Output z
END CASE ; state w= 0 w=1 w= 0 w=1
END IF ;
END PROCESS ; A A B 0 0
B A B 0 1
PROCESS ( y, w )
BEGIN
CASE y IS
WHEN A=> For Mealy machine,
z <= '0' ;
WHEN B => outputs may change
z <= w ;
END CASE ;
whenever inputs (w) or
END PROCESS ;
END Behavior ;
state (y) changes
Example 3 (fig 8.91)

State/output table
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY sequence IS
PORT ( Clock, Resetn, w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;
END sequence ;

ARCHITECTURE Behavior OF sequence IS

TYPE State_type IS (A, B, C, D, E) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN A=>
IF w = '0' THEN y <= B ;
ELSE y <= D ;
END IF ;

-- skip some for brevity

WHEN E =>
IF w = '0' THEN y <= B ;
ELSE y <= E ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
z <= '1' WHEN (y = C OR y = E) ELSE '0' ;
END Behavior ;
Example 4 (fig 8.96)

w
State
machine z

Clock

Resetn

State/output table
Example 4 (fig 8.96)

w
State
machine z

Clock

Resetn

State/output table
 State/output table
ARCHITECTURE Behavior OF seqmealy IS
TYPE State_type IS (A, B, C) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN y <= A;
ELSIF (Clock'EVENT AND Clock = '1')THEN
CASE y IS
WHEN A=>
IF w = '0' THEN y <= B ;
ELSE y <= C ;
END IF ;
WHEN B => PROCESS ( y, w )
IF w = '0' THEN y <= B ; BEGIN
ELSE y <= C ; CASE y IS
END IF ; WHEN A=>
WHEN C => z <= '0' ;
IF w = '0' THEN y <= B ; WHEN B =>
ELSE y <= C ; z <= NOT w ;
END IF ; WHEN C =>
END CASE ; z <= w ;
END IF ; END CASE ;
END PROCESS ; END PROCESS ;
END Behavior ;