IMPLEMENTATION OF HIGH
PERFORMANCE VLSI ARCHITECTURE FOR
ADVANCED ENCRYPTION STANDARD
REENA.D
M.E.,Communication Systems
Dept.of. ECE, Dr. MCET
Pollachi, Tamilnadu, India
reena37.d@gmail.com
Abstract—Data security is highly needed for protecting data.
Advanced encryption standard (AES) algorithm has been widely
used in cryptographic applications. In this work, pipelining is
combined with merging of two modules, Substitute Byte and
Shift Rows. This process provides high throughput.The
proposed work shows higher efficiency with increased power
consumption.VHDLsoftware is used forimplementation
andsimulation and synthesis are done using Xilinx.14.3 and
Modelsim.6.6d.
Index Terms--Advanced encryption standard (AES) algorithm;
VLSI architecture; High Throughput.
I. INTRODUCTION
In recent years, there is a growing requirement to
implement cryptographic algorithms in network applications.
Encryption is the process of encoding information so that
unauthorized persons cannot identify the information. All the
encryption algorithms convert the available information into
an unreadable secured form, referred to as cipher-text. The
authorized person will be able to decode the progress of so-
called decryption. AES is an iterative and symmetric block
cipher with the steps such as add round key, substitute bytes,
shift rows and mix columns for encryption and inverse of
these steps for decryption. It is very important to optimize the
parameters such as area, latency, and power. The main aim is
to develop an architecture of AES with higher throughput and
to have better performance efficiency.
II. LITERATURE SURVEY
The literature survey focuses its attention towards AES,
particularly to utilize under low power consumption, high
security, better performance and improved efficiency is also
studied and analyzed in depth.
Jason Van Dyken, et.al.,[1][3] presented for maintaining the
speed of encryption, the pipelining technology is applied and
the mode of data transmission is modified in this design so
that the chip size can be reduced. AES encryption can be
mainly divided into two parts: key schedule and round
transformation.
Dr. K. Sumathi
Associate professor
Dept.of.ECE, Dr. MCET
Pollachi, Tamilnadu, India
sumathimin@gmail.com
Pravin.B.Tewari & Jaymala.K.Patil.,[2] discussed that
concurrent implementation requires less time but the area is
large with high power consumption. The transformations used
in different rounds are same so, algorithm can be used
repeatedly and area and power can save with the
improvement in speed.
T.Hoang, et al.,[4][5][6] proposed the system aims at reduced
hardware structure. Compared with the pipeline structure, it
has less hardware resources and high cost-effective. And this
system has high security and reliability. This AES system can
be widely used in the terminal equipments. AES encryption
algorithm includes key expansion process and encryption
process . The advantage of this design is the fact that we do
not need to store the round key since they are currently
calculated.This system has the significant features such as
less hardware resources, high speed, high reliability, high
cost-effective.
K.Gaj, et al., [11][12] presents to improve the safety of in
data transmission. The mathematic principle, encryption
process and logic structure of AES algorithm are introduced.
So as to reach the propose of improving the system
computing speed, the pipelining and parallel processing
methods were used. In order to accomplish an encryption
process, ten times of round must be iterative . This paper
gives a design of AES encryption algorithm using pipeline
structure and parallel processing.
I. M. Verbauwhede,et al.,[14]suggested that hardware
implementation can be done through different architectures
trading throughput with area and power consumption. The
design optimization can be done by replacing conventional
modules in AES architecture with a module which best suits
for the area and latency reduction details.
III. OVERVIEW OF AES DESIGN
A. Introduction:
Advanced Encryption Standard (AES) NIST (2001), is an
algorithm used for data encryption. One key of length 128,
192 or 256 is used for encryption and decryption. In this
paper, we are working with 128-bit key. This algorithm can
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be divided into three parts as shown in Fig.1, according to
Daemen and Rijmen: initial part (Key Expansion,
AddRoundKey), iteration part – so-called round (SubBytes,
ShiftRows, MixColumns, AddRoundKey), final part
(SubBytes, ShiftRows an AddRoundKey).

Figure.3.ShiftRow

Figure.1. AES block_diagram
B. Key Expansion
The expansion of the key is performed at the beginning of
each encryption.The original input key is used for the
initiation part, the newly calculate keys are used for another
ten rounds. The number of rounds depends on the length of
the key
E. MixColumn
This operation processes in Fig.4each column
separately. It is substitution which works in the Galois Field
polynomial g(x) = 𝑥 8 + 𝑥 4 + 𝑥 3 + 𝑥 2 + 𝑥 1 .Matrix from the
previous step 2.3 ShiftRows is multiplied by so-called
Mixing matrix, which is listed in the Table and that is the
basis of MixColumns transformation. The column of the
original matrix is multiplied by mixing matrix, and this will
create a new column of the transformed matrix.

C. Substitute Byte
It is a simple substitution shown in Fig.2, where to every
input byte a predefined value of output byte is assigned.Each
Figure.4.MixColumn
byte is divided into two hexadecimal digits. The row in the
table is determined by the first digit and the column by using
the second digit. The substitution table consists of all 256
possible combinations of an input byte. If the input data block F. Add Round Key
is 16 bytes, each byte is replaced with a new value specified The last transformation is the addition of the round key. A
according to the substitution table. subsequent operation of addition between the matrix and the
key is made using logical operation XOR as shown in Fig.5.
The input data block is the same size as the encryption key,
therefore it is 128bits. Both of these values are known, so we
D. ShiftRow
can immediately perform a logical XOR operation.
When rows are rotated, the individual rows of the matrix
are adjusted as follows.There will be no change in the first
row of the matrix. Each byte of these row is shifted by one
byte to the left. Similarly, the third row is shifted by offsets of
two and the fourth rowis shifted by three bytes. This shifting
process is shown in Fig.3.

Figure.5.AddRoundKey

Figure.2.SubByte

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 1V. PROPOSED METHOD
A Exclusion of Shift Row
The operation of the AES algorithm can be little
modified by exclusion of shift rows as shown in
Fig.6. While substitution the element is replaced in
shifted matrix element place. This is performed
through calling required shifted element from the
data matrix, (instead of calling element one by one
sequentially orderly from the data matrix). Thus
merging of the two steps SUB-BYTE and SHIFT
ROWS reduces to one step.
Figure.6.Merging of two modules
B Pipelining
The pipelined architecture in Fig.7 is just a
modification of the iterative looping architecture
except that in between two rounds a register is
included. These registers help us in achieving the
pipelining of the AES. Basically pipelining means to
process the data that is given as input in a continuous
manner without having to wait for the current process
to get over. Instead of passing the output of each
round to the next round directly we use a register
which would act as a bypass or an internal register.
Since the current rounds’ value is storedin the
register the next input to the current round can be
given as soon as the current output is obtained. And
the input to the next round is given from the register
thus avoiding direct contact between the two round.
Figure.7.Pipeline process
V. SIMULATION RESULTS
It is very clear that, as the number of inputs is
greater than 4 there will be a progressive decrease in
the time at which the output is obtained when
compared to the AES iterative looping structure. Thus
by using the AES pipelined architecture we have seen
an increase in the throughput whose proportions
increases as the size of data increases. Invariably, the
size of inputs is going to be high in real time
application as large volumes of data are fragmented
into 128 bits each and fed as input. But the hardware
utilization is higher than that of the iterative looping
architecture. But this is a trade-off that needs to be
done in order to achieve high speed in encryption.
In figure.8, the text given has to be encrypted is
shown. These text and key of size 128-bit are
converted into hexadecimal form and pass it to the
algorithm. Consider a text and its hexadecimal
representation.
For encryption, the input text along with key is
given, this performs Add Round Key(Key generation),
merging of Substitute Byte & Shift Rows, and Mixed
columns. All these modules for 10 rounds are
integrated and resulted as cipher text.
In decryption part, these cipher text along with key
generated (symmetric key) is decrypted i.e., inverse of
all modules and these are combined together to
produce the plain text.
INPUT:Glad to Meet You KEY: How are You
47 6C 61 64 48 65 6C 6C
20 6C 6F 20 6F 20 48 6F
4D 65 65 74 77 20 61 72
20 59 6F 75 65 20 59 6F
Figure.8.Text to be cryptograph
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 Table 1. Comparison of Obtained results

TITLE WITHOUT WITH

PIPELINING PIPELINING

Number used 4480 out of 311 out of 19200

as Logic 19200 23%
Number of 4608 out of 311 out of 19200
Slice (LUT) 19200 24%
Number of Flip 311 5760
Flops
Number of IOs 258 258
Efficiency 17.5 28.1

Throughput 25 77.2
Figure.9.Simulation results of proposed AES algorithm
Number of 3 16
GCLKs
Max Frequency 515 412

Dynamic 4656 1528

Current &
Voltage
Dynamic 14650.51 28155.4
Power
Delay 944 141 9%

Figure.10.Analyzed final output values of proposed AES

In figure.8, the text that is to be encrypted is shown.
Theses texts are converted into hexadecimal form and pass it
to the algorithm. it is shown that the simulation results of
merging and pipelined waveform by integrating all the blocks
and modules for both encryption as well as decryption. And
the analyzed output values is also determined, figure.9. As a
result, the objective in increasing the throughput which in
tends increase the efficiency is clearly made using this
propose methodology. And Figure.10, shows the RTL
Schematic representation for 128-bit size in which this work
is done.
Figure.10. RTL Schematic of AES
In the table given above Table.1, It is said that the area
and delay tends to decrease with greater throughput. But the
power consumption is comparatively higher, since area and
power is always a trade-off. Hence, for the applications like
higher throughput and less latency, we go for this pipelining
method.
VI. CONCLUSION
Advanced Encryption Standard offers a high level of
security with a strong key system. Here the use of Pipelining
and Merging of two modules can be increases the efficiency
and throughput, but the computational power is high since it
requires registers to store and so called memory bases. This
increases the area but by the proposed method of merging two
modules, the area can be minimized. Integrated circuit space is
limited for a smart card, wireless devices. Hence the
development of this standards and proposed method is suitable
for the use of a cryptosystem. This proposed method of AES
can be applied for wireless communication devices like PDA's
multimedia cellular phones which requires less space. This also
have high computational efficiency, so as to be usable in high-
speed applications such as broadband links. Therefore, for any
kind of applications like where security is needed for current
cryptosystem and the limited space requirements, this above
proposed method cab be used.

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 VII. REFERENCES 13. A. Dandalis, V.K. Prasanna, and J.D.P. Rolim, “A
Comparative Study of Performance of AES Final
1. Jason Van Dyken, Jose G. Delgado-Frias, “FPGA Candidates Using FPGAs,” Proc. Third Advanced
schemes for minimizing the power-throughput trade- Encryption Standard (AES) Candidate Conf., Apr.
off in executing the Advanced Encryption Standard 2016.
algorithm" Journal of Systems Architecture pp. 116– 14. I. M. Verbauwhede, P.R. Schaumont, and, H. Kuo,
123,2010. "Design and Performance Testing of a 2.29 Gb/s
2. PRAVIN B. TEWARI, MRS. JAYMALA K. Rijndael Processor, "IEEE J. of Solid State-Circuit,
PATIL,AMIT B. CHOUGULE, “Efficient Hardware Vol.38, No. 3, March 2003, pp. 569 – 572,2017.
Design and Implementation of AES Cryptosystem”, 15. Xilinx, Inc., "Virtex 2.5 V Field Programmable Gate
International Journal of Engineering Science and Arrays," http://www. xilinx.com.
Technology Vol. 2(3), 2010.
3. O.S. Gomes, R.L. Moreno, and T.C. Piment, “A fast
cryptography pipelined hardware developed in
FPGA with VHDL", in Ultra Modern
Telecommunications and Control Systems and
Workshops(ICUMT), 2011 3rd International
Congress,pp.1-6, IEEE,2011.
4. T. Hoang et al, “An efficient FPGA implementation
of the AES algorithm" in computing and
communication technologies, research, innovation
and vision for the future(RIVF), IEEE
Conference,pp.1-4,2012.
5. P.N. Khose and V.G. Raut, “Implementation of AES
algorithm in FPGA for low area consumption", in
ICPC, International Conference,pp.1-4, IEEE,2015.
6. O.S. Dhede and S. Shah, “A review: Hardware
implementation of AES algorithm using minimal
resources on FPGA", in ICPC, International
Conference,pp.1-4, IEEE,2015.
7. Nation Institute of Standards and Technology
(NIST), Data Encryption Standard (DES), National
Technical Information Service, Springfield, VA
22161, Oct. 2015.
8. J. Daemen and V. Rijmen, “AES Proposal:
Rijndael”, AES Algorithm Submission, September
3, 2015.
9. J. Nechvatal et. al., Report on the development of
Advanced Encryption Standard, NIST publication,
Oct 2, 2016.
10. FIPS 197, “Advanced Encryption Standard (AES)”,
November 26, 2016.
11. K. Gaj and P. Chodowiec, Comparison of the
hardware performance of the AES candidates using
reconfigurable hardware, in The Third AES
Candidates Conference, printed by the National
Institute of Standards and Technology.
12. K. Gaj and P. Chodowiec, Comparison of the
hardware performance of the AES candidates using
reconfigurable hardware, in the Third AES
Candidates Conference, printed by the National
Institute of Standards and Technology,2016.