Scribd Logo
Fazer o upload

Bem-vindo(a) ao Scribd!

  • Digital Systems Design Using VHDL

    Enviado por

    K Praveen Kumar
    22 visualizações1 página
    This document appears to be an exam for a course on CPLD and FPGA architectures and applications. It contains 8 questions related to topics like designing a 4-bit majority function generator, explaining blocks of an Altera FPGA, behavioral modeling of FPGA logic blocks, and implementing a 4x4 array multiplier using FPGA logic cells. The questions cover concepts like macro cell architecture, FPGA architecture, behavioral modeling, and logic partitioning for implementation in FPGA resources.

    Descrição original:

    old paper

    Direitos autorais

    © © All Rights Reserved

    Formatos disponíveis

    PDF, TXT ou leia online no Scribd

    Você considera este documento útil?

    Este conteúdo é inapropriado?

    Denunciar este documento
    This document appears to be an exam for a course on CPLD and FPGA architectures and applications. It contains 8 questions related to topics like designing a 4-bit majority function generator, explaining blocks of an Altera FPGA, behavioral modeling of FPGA logic blocks, and implementing a 4x4 array multiplier using FPGA logic cells. The questions cover concepts like macro cell architecture, FPGA architecture, behavioral modeling, and logic partitioning for implementation in FPGA resources.

    Direitos autorais:

    © All Rights Reserved
    Baixe no formato PDF, TXT ou leia online no Scribd
    Sinalizar o conteúdo como inadequado
    22 visualizações1 página

    Digital Systems Design Using VHDL

    Enviado por

    K Praveen Kumar
    This document appears to be an exam for a course on CPLD and FPGA architectures and applications. It contains 8 questions related to topics like designing a 4-bit majority function generator, explaining blocks of an Altera FPGA, behavioral modeling of FPGA logic blocks, and implementing a 4x4 array multiplier using FPGA logic cells. The questions cover concepts like macro cell architecture, FPGA architecture, behavioral modeling, and logic partitioning for implementation in FPGA resources.

    Direitos autorais:

    © All Rights Reserved
    Baixe no formato PDF, TXT ou leia online no Scribd
    Sinalizar o conteúdo como inadequado
    de 1

    Q6 Q6

    www.jntuworld.com Q6 Q6 Q6
    www.android.jntuworld.com Q6 Q6 Q6
    www.jwjobs.net

    Code No: D5504


    R09
    Q6 Q6 Q6 Q6 Q6
    JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
    M.Tech II SEMESTER EXAMINATIONS, APRIL/MAY-2013
    Q6 Q6 Q6
    CPLD AND FPGA ARCHITECTURES AND APPLICATIONS
    (EMBEDDED SYSTEMS)
    Time: 3hours Max.Marks:60
    Answer any five questions
    Q6 Q6 Q6 Q6 Q6
    All questions carry equal marks
    ---
    Q6 Q6 Q6
    1. Design a 4-bit Majority function generator and implement it with a suitable PAL.

    2. With block diagram explain the Macro Cell of Altera 7000 CPLD.
    Q6 Q6
    3.
    Q6 Q6 Q6
    Explain, in detail, every block of FLEX 10000 Device.
    Q6 Q6 Q6

    Q6
    4.

    5.
    Q6
    Write down the behavioural model for XC4000 CLB

    Q6 Q6 Q6 Q6 L D
    Explain the alternative realizations for SM charts using microprogramming with
    Q6 Q6
    R
    suitable examples.

    O
    6. Demonstrate the one-hot state assignment and discuss its advantages using an
    example.

    Q6 7.
    Q6
    8.
    Q6 Q6

    U W
    Discuss the features of Mentor Graphics EDA tool.
    Q6 Q6
    A 4×4 array multiplier is to be implemented using an XC4000 family FPGA.
    Q6
    Without using the built-in-carry logic, partition the logic so that it fits in a
    Q6

    Q6 Q6 Q6
    required.

    N T
    minimum number of logic cells. Draw loops around each set of components that
    will fit in a single logic cell. Find the total number of F and G function generators
    Q6 Q6 Q6 Q6 Q6
    J *****

    Q6 Q6 Q6 Q6 Q6 Q6 Q6 Q6

    Q6 Q6 Q6 Q6 Q6 Q6 Q6 Q6

    Q6 Q6 Q6 Q6 Q6 Q6 Q6 Q6

    www.jntuworld.com

    Você também pode gostar